Deprecate wait() in favour of acquire(), try_acquire(),
try_acquire_for() and try_acquire_until().
Brings Semaphore more into line with CMSIS-RTOS 2 (which uses "acquire"),
itself (as it has "release"), and other classes having "try", "try for"
and "try until".
Also steps away from vague "wait" term - the primary operation here is
to acquire the semaphore, and this will of course sleep.
Fix WATCHDOG_STATUS_INVALID_ARGUMENT for timeout values from 1 ms to
407 ms (fix inability to set prescaler bits to zero).
Fix timeout <-> IWDG registers conversions.
Fix read & write access to IWDG_PR and IWDG_RLR registers.
Fix LSI RC frequency setting.
Limit MAX_TIMEOUT_MS to UINT32_MAX.
- Fix typo in module comment
- Redefine the default system behaviour in sleep mode
- Guard K64F enableWait flag
- Remove bit shifts from reset reason enum
- Add preprocessor guard to watchdog api that errors if the reset reason api is not also implemented
- Add RESET_REASON and WATCHDOG to K64F targets.json
- Add watchdog reference implementation
* The following v14.2 files are removed from nrfx/legacy:
nrf_drv_clock.h
nrf_drv_common.h
nrf_drv_gpiote.h
nrf_drv_spi.h
nrf_drv_twi.h
nrf_drv_uarth.h
* Remove unneeded references to "nrfx_glue.h" and "nrf_drv_common.h"
* Remove the definition of PACKED from app_util_platform.h (already defined
in mbed_toolchain.h)
* Update all scatterfiles to define MBED_RAM_START and MBED_RAM_SIZE. These
get defined in mbed_lib.json when building with a SoftDevice but were missing
when no SoftDevice is brought in.
* Remove SDK 14.2 SoftDevice files.
* Add missing header file to qspi_api.c.
- Adjust memory for SoftDevice
- Enable PRIO=5 for interrupt priority check
- Change NRF_SD_BLE_API_VERSION to 6
- Add handle and buffer for advertising and scanning
- Remove guard for phy update
- Change scatter files and mbed_lib.json for PR #8607
* Update TARGET_NRF5x/README.md to improve "Changing SoftDevice" section
and added section on NRF52840 CryptoCell310 Support
* Update the file list in TARGET_SDK_15_0/TARGET_SOFTDEVICE_COMMON/README.md
* Add missing CR-LF to Nordic-provided SDK file
* Rename a header file in the TARGET_SOFTDEVICE_S112 tree
This reverts commit 3d2fa535a71b7bad08c6a91a31d74f4492c8948c.
This was a breaking change for the "MBR" and "NONE" builds.
After testing it was also determined that copying the vector
table a second time wasn't required for the "FULL" build.
- Add MBR, NONE and OTA SoftDevice build options for S132 and S140
- Add S112 SoftDevice (single build option)
- Some folder restructuring in TARGET_SOFTDEVICE_COMMON was required
The 15.0 SDK doesn't support the nRF51 so it must continue to use the legacy
NRF drivers. Thus the original common_rtc.c, gpio_api.c and us_ticker.c are
restored and placed under TARGET_NRF5x/TARGET_NRF51.
Likewise the modified common_rtc.c, gpio_api.c and us_ticker.c are moved to
TARGET_NRF5x/TARGET_NRF52 so they are excluded from nRF51 builds.
Ensure that vector table gets initialized properly. The table that we
initialize in startup_nrf52840.S gets wiped out as the section is
declared as noinit. Fix this by implementing the weak function mbed_sdk_init
that inits the vector table.
When the SoftDevice (SD) is enabled we need to set the app_offset
to 0x26000 to make room for the SoftDevice. If we let the build
tools self-manage this, MBED_APP_START is coming out at 0x25000
which is not correct for the Nordic 15.0 SDK.
The app_offset value is translated to MBED_APP_START by the build
infrastructure. We were hard coding MBED_APP_START in the scatter
and ld files as a temporary measure while testing. This now sets
it properly if the SD is being brought in.
- Added legacy nrf_drv_rng.c as there is no merit in fully adopting nrfx_rng.c
- Added nrf_queue library component
- Removed apply_old_config.h (unused for some time now)
- Updated sdk_config.h for queue and RNG support for nRF52832
- Brought back RNG into targets.json for nRF52832
Note: nRF52840 still uses CryptoCell 310 for TRNG
- Use new NRFX header file
- Fix nRF52832 linker script/ld files (hardcoded addresses for now)
- Temporarily remove DEVICE_TRNG for nRF52832 (which broke the build)
- Improve serial_putc() fix so we don't rely on "extra" functions
- Missed some NRFX defines that needed to changed
- Set PWM base clock to 125kHz (needs to be reverted back to 1 MHz)
- Updated sdk_config.h for nRF52_DK builds
- Brought in updates from PR7779 (fix for nRF52 PWM issues)
Also addressed:
- removed dependency on legacy config (excluded apply_old_config.h)
- removed legacy pwm and saadc headers
- Arm Compiler 5 linking issue (a band-aid for now... needs to
be properly addressed for peripheral sharing)
- added missing header in SoftDevice file
- top level files ported from TARGET_NORDIC/TARGET_NRF5x/
Also addressed:
- fixed linking issue for gcc
- added support for nRF52-DK builds, but reverted to using nRF52840 sdk_config.h (must be updated)
- introduced "RTC" to targets.json (might need to be removed eventually)
Imports working McuBoot for reset.
Updates microsec ticker driver.
Default baudrate is set to 115200 to see TF-M boot messages.
Stack top is set to scatter file dependent and not hard-coded.
Musca-A1 is a Cortex-M33 based target with security extension enabled.
- ARM_MUSCA_A1 is the non-secure target running mbed-os.
- ARM_MUSCA_A1_S is the secure target running TF-M.
- TF-M sources were imported and patched in previous commits.
- TF-M secure bootloader (McuBoot) for MUSCA_A1 is submitted by a pre-built binary.
- A post-build hook concatenates The secure and non-secure binaries,
signs it and then concatenates the bootloader with the signed binary.
due to partial implementation. Having FUTURE_SEQUANA_M0 and
FUTURE_SEQUANA PSA targets is misleading.
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
In M2351 SPDMC (SMCC) test, it boots from secure code to non-secure bootloader, and finally
to non-secure test code itself. The boot sequence will takes longer than usual. In test
initiation, host will send sync signal 1s after reset device. But due to the longer boot
sequence, test code in device can miss the signal. We enlarge the reset idle time to fix
the issue.
On ARMC6 with optimization level "-Os", the two functions NVIC_SetVector/NVIC_GetVector
will be translated to illegal instruction for trapping due to NVIC_FLASH_VECTOR_ADDRESS
defined as direct 0. Fixed by defining NVIC_FLASH_VECTOR_ADDRESS as a symbol instead to
avoid such optimization error.
By default, FLASH_SIZE should be read from HW.
In case this is not the case, we define it here, as the size of FLASH
that is available to the application running on M4.
the flash is shared and split between cortex-M4 that
runs (mbed-os) application and the cortex-M0+ that
runs the BLE firmware.
The 512K allocated to the application was a
conservative that can now be updated.
With recent up-to-date BLE firmware flashed @ 0x080CB000,
there should be 812K available to application.
But there are boards out there that don't have an up-to-date
firmware, so we're keeping an intermediate, safer,
application size of 768K.
Change the heuristic for selection of CMSE in the tools python, so that
a non-TrustZone ARMv8 build can happen.
Ideally we would have more direct flagging in the targets, but this
refines the heuristic so the necessary behaviour can be easily
achieved.
* DOMAIN_NS=1 is based purely on the `-NS` suffix on the core name.
* Enabling CMSE in the compiler and outputting a secure import library
is now enabled when the core doesn't have an `-NS` suffix by either
the target label `TFM` being present or the flag `trustzone` being set.
This covers the existing ARMv8-M behaviour - TF-M builds have the TFM
label, as per its documentation; M2351 secure builds have no explicit
flagging, so we ensure that the M2351_NS target has the trustzone flag
set, and the out-of-tree secure target inherits that.
Some Nuvoton targets support DEVICE_FLASH but their corresponding COMPONENT_FLASHIAP
supports are not enabled. Enable them:
NUMAKER_PFM_M453
NUMAKER_PFM_M2351
Reimplement atomic code in inline assembly. This can improve
optimisation, and avoids potential architectural problems with using
LDREX/STREX intrinsics.
API further extended:
* Bitwise operations (fetch_and/fetch_or/fetch_xor)
* fetch_add and fetch_sub (like incr/decr, but returning old value -
aligning with C++11)
* compare_exchange_weak
* Explicit memory order specification
* Basic freestanding template overloads for C++
This gives our existing C implementation essentially all the functionality
needed by C++11.
An actual Atomic<T> template based upon these C functions could follow.
Purposes:
* Remove MbedOS-specific code from system_psoc6_{cm4,cm0plus}.c
to simplify updates to new PDL version (startup code is part of PDL).
* Unify mbed_sdk_init initialization sequence for both CPU cores.
This change is non-functional, sequence itself is not changed for any
of the PSoC 6 M4/M0 PSA/non-PSA targets.
According to their cmsis.h, FPU is present, so change targets.json to
use it.
* ARM_MPS2_M4: already was Cortex-M4F
* ARM_MPS2_M7: Cortex-M7 -> M7FD
* FVP_MPS2_M4: Cortex-M4 -> M4F
* FVP_MPS2_M7: Cortex-M7 -> M7FD
If they do not in fact have FPU, then cmsis.h should be modified to set
`__FPU_PRESENT` to 0. This will currently cause compilation problems
with ARMC6, but I'll be submitting a fix for that.
On NUC472, on wake-up from power-down mode, we may meet hard fault or some other
unknown error. Before its cause is found, we enter idle mode instead for a workaround.
To simulate power-down mode with idle mode, we also disable us_ticker during
power-down period.
PDL Flash API requires that the data buffer is 32-bit aligned, otherwise
programming can hung. Buffer declared as uint8_t array is not always
properly aligned, e.g. with gcc 6 when -Os option is used.
Flash driver 3.30:
Moved ipcWaitMessageStc structure to the RAM section called ".cy_sharedmem"
Added support Secure Boot devices
Moved CY_FLASH_EFFECTIVE_PAGE_SIZE to flash_api.c (the macro is Mbed specific).
GeneratedSource folders are BSP specific. No parts of the kit BSP can be reused
as generic chip support package. Remove TARGET_CY8C62XX directory,
and use flat BSP inheritance model:
MCU_PSOC6 -> MCU_PSOC6_M4 -> CY8CKIT_062_WIFI_BT
MCU_PSOC6 -> MCU_PSOC6_M0 -> CY8CKIT_062_WIFI_BT_M0
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN382(ARM_MPS2_M0). Add "IAR" to supported_toolchain list.
Change-Id: I2b2ad7645166c4f973a8baa9c394521514183767
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN383(ARM_MPS2_M0P). Add "IAR" to supported_toolchain list.
Change-Id: Ib2278d34e265e53ad070aecd318ed4e6a355e3c0
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN382(ARM_MPS2_M0). Add "GCC_ARM" to supported_toolchains list.
Change-Id: I7046b698834c82e94015e51eef9a0f5e1315ddaa
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN383(ARM_MPS2_M0P). Add "GCC_ARM" to supported_toolchains list.
Change-Id: I48020b4f0f1b6e0aef3c53f5a3586bc9e9fca9c9
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN385(ARM_MPS2_M3). Add "IAR" to supported_toolchain list.
Change-Id: I038b05b8b21bd146a1568de897ed030ccd52ab79
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN386(ARM_MPS2_M4). Add "IAR" to supported_toolchain list.
Change-Id: I4f43617c870197b9d39a4d4c9c12456adcc6f96f
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN500(ARM_MPS2_M7). Add "IAR" to supported_toolchain list.
Change-Id: I0b8f018fc937727382b27ea0669940ae6675c834
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN385(ARM_MPS2_M3). Add "GCC_ARM" to supported_toolchains list.
Change-Id: I3110d4ab37a3294488a80a8dc1c929bfd87ce989
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN386(ARM_MPS2_M4). Add "GCC_ARM" to supported_toolchains list.
Change-Id: Ib8cea952e1ce0a5ef11ab623cca6f3786eab56f5
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN500(ARM_MPS2_M7). Add "GCC_ARM" to supported_toolchains list.
Change-Id: Ife109e9e1f2ec8e075e566f9d5c2ec7e3c5067f2
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
These file changes provide small fixes for various targets
on MPS2 platform in order to work properly and pass all
Greentea test cases. The __initial_sp has been explicitly set
in the targets' startup files, and also INITIAL_SP has been
given a different value. The values have been extracted from
the specific targets' Application Note documentation.
Affected targets are: ARM_MPS2_M0, ARM_MPS2_M0P, ARM_MPS2_M3,
ARM_MPS2_M4 and ARM_MPS2_M7.
Change-Id: I3d5d0e1ae386cdcc3ba5eb63be929267a257b139
Signed-off-by: Bence Kaposzta <bence.kaposzta@arm.com>
Spotted in compiler warnings - code was trying to access a non-existent
second security control block, rather than access the settings for the
second APB bridge in the first and only security control block.
The hal code for this target uses "const volatile" types inside of
structs, which are non-trivially copyable in clang (used by ARMC6). This
causes the build to fail.
Here's the commit that changed this in clang:
a3d727ba77
It seems this was reverteed some time ago in clang, but ARMC6 may not
be up to date.
To have the flexibilty in application; to use any of the section
(data/bss/heap) without updating linker script in every use case,
following decisions are made:
1. Fixed size and small sections moved to SRAM2 (32K)
Vectors
Crash data
Remaining section - RW / ZI
2. Large memory space should be used for variable sections
RW/ZI
Heap - (Minimum - 0x12000)
Stack - At bottom
Please note the heap address of the both the banks must not be contigious else
GCC considers it to be single memory bank and does allocation across the banks,
which might result into hard-fault
To have the flexibilty in application; to use any of the section
(data/bss/heap) without updating linker script in every use case,
following decisions are made:
1. Fixed size and small sections moved to SRAM2 (32K)
Vectors
Crash data
Stack
Remaining section - Heap memory
2. Large memory space should be used for variable sections
Data
BSS
Heap - Remaining section
Heap is moved to the end of both sections as GCC allocates till 4K boundary,
if end of heap is not aligned to 4K, that chunk of memory will go unutilized
Fixes test failure seen with tests-mbed_hal-stack_size_unification
under IAR and ARM toolchain
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This change moves all PDL drivers into common source and include
directories to alleviate issue with Windows version of GNU Make 4.x
maximum command line length limit.
New `target.console-uart` option added to indicate whether a target has
a console UART on STDIO_UART_TX/RX/RTS/CTS pins. (The existing option
`target.console-uart-flow-control` indicates whether RTS and or CTS is
available in addition to TX and RX).
The option defaults to true, and is currently true on all platforms. It
only applies if DEVICE_SERIAL is true, so no need to go through and mark
it false for non-SERIAL platforms.
An application can turn off target.console-uart to save ROM/power/etc if
they don't want to use the serial console. If this is turned off, the
console won't be activated for stdin/stdout, but the application is
still free to open `UARTSerial(STDIO_UART_TX, STDIO_UART_RX)`
themselves.
Since commit 12c6b1bd8, the i.MX RT1050 has effectively had its data
cache disabled, as the SDRAM was marked Shareable; for the Cortex-M7,
shareable memory is not cached.
This was done to make the Ethernet driver work without any cache
maintenance code. This commit adds cache maintenance and memory barriers
to the Ethernet driver, and removes the Shareable attribute from the
SDRAM, so the data cache is used again.
Cache code in the base fsl_enet.c driver has not been activated - the
bulk of it is in higher-level Read and Write calls that we're not using,
and there is one flawed invalidate in its initialisation. Instead
imx_emac.cpp takes full cache responsibility.
This commit also marks the SDRAM as read/write-allocate. As the
Cortex-M7 has its "Dynamic read allocate mode" to automatically switch
back to read-allocate in cases where write allocate is working poorly
(eg large memset), this should result in a performance boost with no
downside.
Activating write-allocate is also an attempt to provoke any flaws in
cache maintenance - the Ethernet transmit buffers for example will be
more likely to have a little data in the cache that needs cleaning.
Fixed interrupt vector settings on M0 core. Wrong vector settings prevented
LP_TICKER from working, resulting in deep sleep tests failing on M0
or PSA variant.
Internal channels use is enabling ADC "internal path" which needs
to be disabled after measurement.
Same applied here for WB family as was done for others in #10143.
Typically the RTC clock is configured by RTC driver itself.
RNG on the other hand is shared with M0+ core and it is expected that
M4 turns it on at boot time.
When doing so, do not disbale GPIO clocks as they may be used by other
drivers !
As a result, debug will be disabled by default, but can be enabled by
either modifying code or selecting MBED debug profile.
Review HSE clock initialization to match with latest CUBE firmware.
Also there is no need to set the full clock tree again after deep sleep exit.
With this change we get a stable deep sleep mode (when allowed by CORDIO stack).
Until the CMSIS pack device name is officially deployed.
then we'll the name as can be found in Keil CMSIS pack
<!-- ************************* Device 'STM32WB55RG' ***************************** -->
<device Dname="STM32WB55RGVx">
<memory id="IROM1" start="0x08000000" size="0x001000000" startup="1" default="1" />
<memory id="IRAM1" start="0x20000000" size="0x000040000" init="0" default="1" />
<algorithm name="CMSIS/Flash/STM32WB_M4.FLM" start="0x08000000" size="0x001000000" default="1" />
<feature type="QFP" n="68"/>
</device>
There is no need to add FIRST attribute to MAPPING_TABLE as the default
ordering is alphabetical order.
With this change, we don't have any warning with MBED2 and the sections
are properly ordered anyway in BLE cases.
In case of mbed2, BLE feature is not built.
As there is a MAPPING_TABLE in BLE feature which is not compiled in case
of mbed2, the linker reported the below error
[ERROR] "C:/Data/Workspace/mbed/BUILD/test/NUCLEO_WB55RG/ARM/MBED_2/
.link_script.sct", line 65 (column 6): Error: L6236E:
No section matches selector - no section to be FIRST/LAST.
Solution is to check whether BLE is enabled.
These files are not BLE specific, but also needed for some clock setting
for instance.
In order to compile an MBED2 application, we need to move the files.
- move hw_conf.h file to targets/TARGET_STM/TARGET_STM32WB directory as
this is used also out of BLE feature.
- create a dedicated hal_deepsleep function as the behavior in WB is a lot
different from other existing STM32 targets
- update clock tree configuration to directly clock the entire tree @ 32MHz
out of HSE. This is needed as we want to let the M0 core running without
any change on M0-side of clocks when M4 enters /exits deep sleep.
Needed for PSoC to deep-sleep for more than 2 seconds
Max sleep with 16 bit lp_ticker (before this change) : 2sec
Max sleep with 32 bit lp_ticker (after this change) : 36hours
The cache must be refreshed when we erase or program flash memory.
It fix 2 issues :
Fix#9934Fix#6380
This solution was initially proposed in #6380.
Signed-off-by: Vincent Veron <vincent.veron@st.com>
The OS timer of RZ/A1 uses P0 clock, so until now it has been set the value of P0 clock in SystemCoreClock.
Changed the system clock value to set to SystemCoreClock.
Changed to refer to P0 clock macro instead of SystemCoreClock in OS timer processing.
Nuvoton targets below don't provide SPI-bus SD on-board, identified by 'SD' in
target component list. Instead, these targets provide SD-bus SD on-board, identified
by unofficial 'NUSD', driver of which is provided outside mbed-os tree. So 'SD' must
be removed to reflect the truth.
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M487
- NUMAKER_IOT_M487
- NUMAKER_PFM_M2351
The flash driver for the LPC55S69 is different from
prior LPC family. Move the Flash HAL driver to SoC
specific folder
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This data, placed at physically not existing addresses (0x9xxxxxxx) was used
only by PSoC Programmer and KitProg2 and is no longer needed, but was causing
issues with standard hex file processing tools like srecord (srec_cat).
Old M2351 CMSIS pack reports single secure ROM/RAM spec. It is updated in new
version which reports secure/non-secure ROM/RAM spec. Override this memory spec
in targets.json regardless of CMSIS.
If the board-specific initialization code configures the serial port to
use an 8-bit divider, the serial_init_clock function would configure the
16-bit divider with the same index instead of the intended 8-bit
divider.
Added WiFi_Bt CM4 PSA target in mbedos json
Added SPE-NSPE mailbox initialization for CM4 SystemInit
Made similar to FUTURE_SEQUANA configurations
Copied FUTURE_SEQUANA CM0 SPM part for WiFi_Bt smoke test
Added CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Sorted files for new CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Copied files for CY8CKIT_062_WIFI_BT_M0_PSA from FUTURE_SEQUANA
Copied and updated cm0p start files
Corrected according to FUTURE_SEQUANA
Changes to M0 startup files to have SPM started
Fixed implicit declaration warning
Commented interrupts enabling according to FUTURE_SEQUANA flow
Updated prebuild spm_smore CM0 hex for CM4 target
Turned on greentea environment
Used special memory region for common CM0/CM4 data
Updated prebuild CM0 SPM hex
Placed shared memory region for flash operations into SPM shared memory region
Updated cyprotection code and configuration
Start address of protected regions is set by a defined number from target.json
Added masters pcMask configuration
Added support for PSA target to WIFI_BT board
Enabled resources protection for SPM
Aligned RAM usage according to Cypress FlashBoot and CyBootloader
alligned protection config
Added CYW943012P6EVB_01_M0 target
Enlarged heap size, remobed nv_seed
Added heap reservation in linker script from mbed-os
Removed heap size definition
turned on nv_seed config
Removed nv_seed macros
Enabled protection for PSoC6 CM0
Added PSoC6 CM0 PSA readme
Enabled mbed_hal-spm test
Enabled nv_seed and removed unneeded ipc config define
Added SPDX string to feature_ble cypress target files
Removed unneeded supported_toolchains lines for Cypress targets
Disabled protection settings
Corrected flash initialization for PSoC6 CM0 PSA
Changed PSoC6 IPC6 protection for flash
Enabled special flash initialization and enabled protection settings
Updated and added new prebuild PSoC6 CM0 PSA hex files
Disabled HW TRNG and CRC for PSoC6 CM4 PSA target
Added missing const to allow types to match
Updated PSoC6 WIFI_BT_PSA prebuilt directory
Moved PSoC6 shared section usage area definition to begin of ld
Added initial ARM_STD linker and startup files for PSoC6 CM0
Added initial IAR linker and startup files for PSoC6 CM0
Added defines to disable some SPM protection settings for PSoC64
Moved Flash function variables into separate memory region
Added defines for new Public area definition
Updated PSoC6 CM0_PSA hex-files
Page size in all PSOC6 boards is 512 bytes. This is very problematic in
all storage applications. This change reduces the page size (in flash_api's
flash_program_page API) to 32 by reading the original page, modifying it
with programmed data and programming it back. The number 32 for page size
conforms to the number of times (16) this action can be done.
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
Due to a bug the LPTIM peripheral can cause interrupts to fire at the
wrong time on the NUCLEO_L073RZ. This patch switches the backend
of the low power ticker to the RTC until this bug is addressed.
Nuvoton M2351 was including generic core_armv8mbl.h from CMSIS - we
need it to be more specific to identify the specific core for
wait_ns. Change to core_cm23.h.
I implemented USB Device feature for Renesas mbed boards.
The code referenced the following code as a starting point and is implemented it by inheritting USBPhy same as other boards.
(mbed-os\features\unsupported\USBDevice\targets\TARGET_RENESAS)
When activating an endpoint assign new data rather than ORing
data to it. This ensures that values set from the previous use
do not effect the current configuration.
Update the patch "Create HAL_PCD_EP_Abort" to fix bugs.
This patch adds the low level functions USB_EPStopXfer, USB_EPSetNak,
USB_EPClearNak and the high level function HAL_PCD_EP_Abort so that
transfers can be stopped.
The functions USB_EPSetNak and USB_EPClearNak allow nak to be enabled
or disabled for an endpoint, preventing or allowing further transfers.
The function USB_EPStopXfer stops pending reads and writes started by
USB_EPStartXfer along with clearing and masking any interrupts enabled
by USB_EPStartXfer.
The function HAL_PCD_EP_Abort aborts any transfers on the given
endpoint. When this function completes the transfer interrupt
is guarenteed not to fire for this endpoint. Furthermore, the size
of data transferred during an aborted read can be found by calling
the function HAL_PCD_EP_GetRxCount.
Other notes on this Change:
1.
Prior to this patch the interrupt USB_OTG_DOEPINT_EPDISD was not
handled. When an OUT endpoint was disabled this interrupt occurred
causing the CPU to get stuck repeatedly handling this interrupt. This
is because this interrupt was unmasked but nothing cleared this
interrupt. This patch also adds code to handle and clear this
interrupt to prevent a lockup.
2.
Stopping a transfer on an OUT endpoint requires global nak OUT to
be in effect. Even with this being done, having entries in the rx fifo
prevented an OUT endpoint from being disabled. This behavior is not
mentioned in the Reference Manual.
Take the code from
mbed-os\features\unsupported\USBDevice\targets\TARGET_STM
as a starting point and use it to fill in the USBPhy template for STM32
devices.
Move the USBPhy header files into usb/device/USBPhy. Also move hal
and target USB files since mbed 2 does not compile when these files
are present without the USBPhy headers.
Directory restructure summary:
platform/USBPhy*
to usb/device/USBPhy/USBPhy*
hal/*
to usb/device/hal/*
targets/TARGET_Freescale/usb/*
to usb/device/targets/TARGET_Freescale/*
targets/TARGET_NXP/TARGET_LPC176X/usb/*
to usb/device/targets/TARGET_NXP/*
Make the following changes to improve stability:
-When disconnecting set address to disabled to prevent nacks
-Clear EP_SLOW one and only once for every interrupt where it is set_address
-Disable and clear control endpoint interrupts when disconnecting
Even thought the USB phy is disabled during disconnect, endpoints
still nack packets sent. This patch disables all endpoints so after
disconnect no USB traffic will be sent. This allows brief disconnects
of ~200us (or more) to be reliably detected by the host PC.
Reverting this feature till IAR 8.x is stable and supported in Mbed OS
for few releases
1. Revert "Add Dynamic heap support to IAR"
This reverts commit 8ee29bbfa2.
2. Revert "Splited RAM section not compatible with dynamic HEAP."
This reverts commit a645bb2a6b.
3. Revert "Add Dynamic heap support to IAR"
This reverts commit 891e1f261b.
Two new block properties available in linker configuration files:
"expanding size" and "minimum size" for IAR 8.11.2 and above
Sample:
define block HEAP with expanding size, minimum size = 16K, alignment = 8 {};
This block will expand to consume all remaining available space in
the range where it is placed. If several such blocks end up in the same
range, they will share the remaining space.
Cannot place a block with expanding size inside another block with
expanding size, inside a block with maximum size, or inside an overlay.
Few targets have libraries compatible to IAR 7.x, which fail with
IAR 8.x, IAR support for them is removed till updated library is
added.
CI failure seen if IAR is not added as supported target, trying with
release_version as empty string
List of targets affected:
1. UBLOX_EVK_ODIN_W2
2. MTB_UBLOX_ODIN_W2
3. MBED_CONNECT_ODIN
4. MTB_MXCHIP_EMW3166
5. MTB_ADV_WISE_1530
6. MTB_USI_WM_BN_BM_22
7. REALTEK_RTL8195AM
RAM define/section if splited, IAR exanpding size considers just one
section while heap creation which results in smaller chunk for heap.
This commit is to unify the RAM section.
Two new block properties available in linker configuration files:
"expanding size" and "minimum size" for IAR 8.11.2 and above
Sample:
define block HEAP with expanding size, minimum size = 16K, alignment = 8 {};
This block will expand to consume all remaining available space in
the range where it is placed. If several such blocks end up in the same
range, they will share the remaining space.
Cannot place a block with expanding size inside another block with
expanding size, inside a block with maximum size, or inside an overlay.
The low power ticker wrapper layer adds a large amount of interrupt
latency. This can cause dropped bytes at a baud of 115200 on some
devices. To prevent this by default use the microsecond ticker for
tickless on devices which make use of the low power ticker wrapper.
Fix port_write API to correctly shift the passed value.
This allows the reference application provided in PortOut docs
to work corectly with arbitrary LED_MASK.
https://os.mbed.com/docs/mbed-os/v5.11/apis/portout.html
The fix applies to both PSOC6 and PSOC6_FUTURE HAL implementations.
Fix for issue #9450 by adding turning off the modem power at startup, so that modem is sure to be in the initial state.
Fix for wrong filename and classname.
// WIP
Main thread stack size is reduced for TARGET_STM32F070RB and TARGET_STM32F072RB,
in recent update to mbed_rtx.h the conditional check for main thread size update
was removed.
Memory model for RTOS and No RTOS was initially single stack and heap,
only few targets implemented 2-region RAM model.
2-region RAM model is applied for all toolchains and targets.
GCC: __wrap__sbrk was implemented for 2-region ram model, with switch to 2-region
for all targets, we do not need target specific implementation of this API
Also _sbrk is WEAK function, hence can be over written in target folder for
special cases
The NRF52_DK and DELTA_DFBM_NQ620 have the SWO pin (p0_18) mapped to
LED2. This means that on startup LED2 turns on after the ITM is
initialized which is confusing. Since most users want LED2 usage
instead of SWO we remove the ITM for these targets.
The nRF52 readme is updated to instruct users how to get SWO support
if they need it.
Use ModusToolbox Device Configurator 1.1.0.284 to generate the
BSP low-level initialization code. Compatible version of Device
Configurator to be released with ModusToolbox 1.1.
Notable changes:
* rename cycfg_connectivity -> cycfg_routing
* switch LF_CLK clock source from ILO to WCO on
CY8CPROTO-062-4343W and CYW943012P6EVB-01
An entropy source is required in order to use the PSA Crypto API. The
only devices Mbed OS knows are guaranteed by default to have an entropy
source are those devices with a TRNG. Don't enable the PSA Crypto API by
default for devices that Mbed OS can't know have an entropy source. This
avoids run-time errors when an entropy source is not present on these
targets.
Applications can add their own entropy source by place entropy into
their systems, implementing their own NV Seed read and write callbacks,
and then enabling the MBEDTLS_ENTROPY_NV_SEED configuration option to
notify the PSA Crypto implementation that an entropy source is present
and how to use it.
See https://os.mbed.com/docs/mbed-os/v5.11/porting/entropy-sources.html
for the background on why entropy is fundamental to system security and
how to inject entropy into systems that lack an on-board source of
entropy.
Enabled tickless mode for Sequana PSA M0 core code to allow it to enter
deep sleep mode. This fixes issue #9094 where tests were failing due to
M0 core not entering deep sleep mode, blocking the whole chip.
Fixed incorrect resource management on M0 core, which crashed tickless
mode.
Linker files for LPC11U68 and LPC1549 updated as Mbed OS memory model
1. LPC1549
Has multiple memory banks, 4K bank used for stack exclusively and 16K for Heap
Its is mbed 2 only target hence 4K for stack.
2. LPC11U68
Added Heap and Stack sections in linker files. Resolved build issues.
Port of NUC472/M487 crypto AC mgmt work to M2351:
1. Choose mutex to synchronize access to crypto non-SHA AC
2. Choose atomic flag to synchronize access to crypto SHA AC
1. Removed random i/o glitches occurring during device reconfiguration
2. Fixed hazardous reads occurring at the end of transfer resulting
in incorrect values being received
3. Added spi_free() function
4. Replaced default M0 image with a one ignoring i/o reservation. This is
a workaround for missing proper destructors in Mbed drivers and BlockDevice
tests failing on repeated initialization
Fixes issue #9620.
Add support for listing all the pins of one or more form factors.
This is in preparation for automated testing of the default form
factor.
This patch includes the following:
-A function to get a list of restricted pins which should not be
used for testing due to some caveat.
-The target config "default-form-factor" which can specify which form
factor should be tested
-Form factor information for the arduino form factor
Add the functions qspi_master_sclk_pinmap, qspi_master_ssel_pinmap and
qspi_master_data0_pinmap-qspi_master_data3_pinmap to all targets with
qspi support.
Add prebuilt WICED libraries for the PSoC 6 boards with WICED radios:
* TARGET_CY8CKIT_062_4343W
* TARGET_CY8CKIT_062_WIFI_BT
* TARGET_CY8CPROTO_062_4343W
* TARGET_CYW943012P6EVB_01
Add required extra labels to the PSoC 6 targets in targets.json:
(PSOC6_01/02 labels are used during the library compilation).
Add Cypress HCI driver implementation in TARGET_Cypress directory.
Update targets.json to enable CORDIO stack for Cypress PSoC 6 boards
with CYW43XXX radios with compatible HCI driver implementation:
CYW4343W and CYW43012.
Code generated for pioneer kits:
* CY8CKIT-062-4343W
* CY8CKIT-062-BLE
* CY8CKIT-WIFI-BT
Prototyping boards:
* CY8CPROTO-062-4343W
The source is generated with ModusToolbox Device Configurator.
The origin design.modus files used to produce the GeneratedSource
will be submitted in the consequent pull requests.
Copy the porting layer from TARGET_PSOC6_FUTURE to TARGET_PSOC6.
This commit is intended to make the history and changes applied easier
to follow.
ipcpipe_transport.c, ipcpipe_transport.h, rpc_api.h, rpc_defs.h
are excluded (not used by Cypress port).
PeripheralNames.h is moved to BSP layer introduced in subsequent
commits (the peripheral names and count are board-specific).
The targets/TARGET_Cypress/TARGET_PSOC6 is dedicated to the mbed-os HAL
and PSoC 6 MCU targets developed by Cypress Semiconductor. Move the
existing port developed by Future Electronics to TARGET_PSOC_FUTURE
and update the labels in targets.json appropriately.
Use new atomics (exchange, load, store and bool types) to simplify
and improve the atomics in the nRF52 serial HAL.
* Ensure mutexes are released last and atomically when done
done inside a critical section.
* Compare-and-swap is not required for the spinlock - exchange is
sufficient. (Not clear a spinlock is needed anyway, but left in).
* Remove unneeded volatile, and make mutexes bool.
* Remove unused Peripheral Pins definitions and add UART_1 TXD/RXD pins (fix#9026) for the Wio BG96 board
* Remove/Fix unused PinName definitions for the Wio BG96 board from the PinNames enum
* Remove unused Peripheral Pins definitions and add UART_1 TXD/RXD pins (fix#9026) for the Wio 3G board
* Remove/Fix unused PinName definitions for the Wio 3G board from the PinNames enum
Remove the ARDUINO form factor from the RBLAB_BLENANO2 since it
does not have D11, D12, D14, D15 defined and does not physically have
the arduino form factor.
Rename the existing PSoC-specific m0_core_img key in targets.json
as a more generic hex_filename key. Update makefile exporter to select
the subset of resources.hex_files matching the hex_filename value.
Without this fix, multiple prebuilt CM0+ hex files are found in the
target resources and erroneously passed to the srec_cat tool.
The fix is generic so other targets that need post-build hex merging
can use this key to pass the correct image to srecord tool.
The fix also removes sub_target key: instead, rely hex_filename json
key to detect if the hex image merging needs to be done.
The sub_target is not used in mbed-os codebase for anything else.
It is possible to override the hex file name in mbed_app.json:
{
"target_overrides": {
"*": {
"target.hex_filename": "my_custom_m0_image.hex"
}
}
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