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H7 ST CUBE V1.4.0

pull/10631/head
Vincent Veron 2019-05-23 10:06:19 +02:00
parent 3e1a24b3fe
commit 80b41f0276
114 changed files with 22371 additions and 5618 deletions
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1
targets/TARGET_STM/README.md
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@ -18,6 +18,7 @@ This table summarizes the STM32Cube versions currently used :
| F3 | 1.9.0 |
| F4 | 1.19.0 |
| F7 | 1.10.0 |
| H7 | 1.4.0 |
| L0 | 1.10.0 |
| L1 | 1.8.1 |
| L4 | 1.11.0 |

4
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32h743xx.S
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@ -14,8 +14,8 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the

4
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_ARM_STD/startup_stm32h743xx.S
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@ -14,8 +14,8 @@
;******************************************************************************
;* @attention
;*
;* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.</center></h2>
;* Copyright (c) 2017 STMicroelectronics.
;* All rights reserved.
;*
;* This software component is licensed by ST under BSD 3-Clause license,
;* the "License"; You may not use this file except in compliance with the

1
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/TOOLCHAIN_GCC_ARM/startup_stm32h743xx.S
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@ -292,7 +292,6 @@ g_pfnVectors:
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word 0 /* Reserved */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word 0 /* Reserved */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word SAI4_IRQHandler /* SAI4 global interrupt */
.word 0 /* Reserved */

376
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/stm32h743xx.h
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@ -59,7 +59,7 @@ typedef enum
PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
/****** STM32 specific Interrupt Numbers **********************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
@ -1047,12 +1047,14 @@ typedef struct
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
__IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */
__IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
__IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
__IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
uint32_t RESERVED3[62]; /*!< Reserved, 0x2C-0x120 */
__IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
__IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */
uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */
__IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
__IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
__IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
@ -1145,7 +1147,6 @@ typedef struct
} JPEG_TypeDef;
/**
* @brief LCD-TFT Display Controller
*/
@ -1194,7 +1195,6 @@ typedef struct
} LTDC_Layer_TypeDef;
/**
* @brief Power Control
*/
@ -1221,9 +1221,9 @@ typedef struct
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
__IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
__IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */
__IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
@ -1288,31 +1288,6 @@ typedef struct
} RCC_TypeDef;
typedef struct
{
__IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0x00 */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x04 */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x08 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x0C */
__IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x10 */
__IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x14 */
__IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0x18 */
__IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0x1C */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x20 */
__IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0x24 */
uint32_t RESERVED9; /*!< Reserved, Address offset: 0x28 */
__IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0x3C */
__IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x40 */
__IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x44 */
__IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x48 */
__IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x4C */
__IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x50 */
__IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x54 */
__IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x58 */
__IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x5C */
uint32_t RESERVED10[4]; /*!< Reserved, 0x60-0x6C Address offset: 0x60 */
} RCC_Core_TypeDef;
/**
* @brief Real-Time Clock
@ -2099,7 +2074,6 @@ typedef struct
#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
#define RCC_C1_BASE (RCC_BASE + 0x130UL)
#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
@ -2453,7 +2427,6 @@ typedef struct
#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
@ -2656,6 +2629,8 @@ typedef struct
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/******************************* ADC VERSION ********************************/
#define ADC_VER_V5_X
/******************** Bit definition for ADC_ISR register ********************/
#define ADC_ISR_ADRDY_Pos (0U)
#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
@ -2746,8 +2721,10 @@ typedef struct
#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
#define ADC_CR_BOOST_Pos (8U)
#define ADC_CR_BOOST_Msk (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
#define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
#define ADC_CR_ADCALLIN_Pos (16U)
#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
@ -12576,9 +12553,6 @@ typedef struct
#define I2C_CR1_ANFOFF_Pos (12U)
#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13U)
#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14U)
#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
@ -14253,59 +14227,35 @@ typedef struct
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
/******************** Bit definition for RCC_ICSCR register ***************/
/******************** Bit definition for RCC_HSICFGR register ***************/
/*!< HSICAL configuration */
#define RCC_ICSCR_HSICAL_Pos (0U)
#define RCC_ICSCR_HSICAL_Msk (0xFFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000FFF */
#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[11:0] bits */
#define RCC_ICSCR_HSICAL_0 (0x001UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000001 */
#define RCC_ICSCR_HSICAL_1 (0x002UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000002 */
#define RCC_ICSCR_HSICAL_2 (0x004UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000004 */
#define RCC_ICSCR_HSICAL_3 (0x008UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000008 */
#define RCC_ICSCR_HSICAL_4 (0x010UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000010 */
#define RCC_ICSCR_HSICAL_5 (0x020UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000020 */
#define RCC_ICSCR_HSICAL_6 (0x040UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000040 */
#define RCC_ICSCR_HSICAL_7 (0x080UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000080 */
#define RCC_ICSCR_HSICAL_8 (0x100UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000100 */
#define RCC_ICSCR_HSICAL_9 (0x200UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000200 */
#define RCC_ICSCR_HSICAL_10 (0x400UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000400 */
#define RCC_ICSCR_HSICAL_11 (0x800UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000800 */
#define RCC_HSICFGR_HSICAL_Pos (0U)
#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */
#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (12U)
#define RCC_ICSCR_HSITRIM_Msk (0x3FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x0003F000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[5:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00002000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00004000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00008000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00010000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00020000 */
/*!< CSICAL configuration */
#define RCC_ICSCR_CSICAL_Pos (18U)
#define RCC_ICSCR_CSICAL_Msk (0xFFUL << RCC_ICSCR_CSICAL_Pos) /*!< 0x03FC0000 */
#define RCC_ICSCR_CSICAL RCC_ICSCR_CSICAL_Msk /*!< CSICAL[7:0] bits */
#define RCC_ICSCR_CSICAL_0 (0x01UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x00040000 */
#define RCC_ICSCR_CSICAL_1 (0x02UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x00080000 */
#define RCC_ICSCR_CSICAL_2 (0x04UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x00100000 */
#define RCC_ICSCR_CSICAL_3 (0x08UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x00200000 */
#define RCC_ICSCR_CSICAL_4 (0x10UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x00400000 */
#define RCC_ICSCR_CSICAL_5 (0x20UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x00800000 */
#define RCC_ICSCR_CSICAL_6 (0x40UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_CSICAL_7 (0x80UL << RCC_ICSCR_CSICAL_Pos) /*!< 0x02000000 */
/*!< CSITRIM configuration */
#define RCC_ICSCR_CSITRIM_Pos (26U)
#define RCC_ICSCR_CSITRIM_Msk (0x1FUL << RCC_ICSCR_CSITRIM_Pos) /*!< 0x7C000000 */
#define RCC_ICSCR_CSITRIM RCC_ICSCR_CSITRIM_Msk /*!< CSITRIM[4:0] bits */
#define RCC_ICSCR_CSITRIM_0 (0x01UL << RCC_ICSCR_CSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_CSITRIM_1 (0x02UL << RCC_ICSCR_CSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_CSITRIM_2 (0x04UL << RCC_ICSCR_CSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_CSITRIM_3 (0x08UL << RCC_ICSCR_CSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_CSITRIM_4 (0x10UL << RCC_ICSCR_CSITRIM_Pos) /*!< 0x40000000 */
#define RCC_HSICFGR_HSITRIM_Pos (24U)
#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
/******************** Bit definition for RCC_CRRCR register *****************/
@ -14325,6 +14275,32 @@ typedef struct
#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
/******************** Bit definition for RCC_CSICFGR register *****************/
/*!< CSICAL configuration */
#define RCC_CSICFGR_CSICAL_Pos (0U)
#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */
#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
/*!< CSITRIM configuration */
#define RCC_CSICFGR_CSITRIM_Pos (24U)
#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */
#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U)
@ -15116,11 +15092,18 @@ typedef struct
#define RCC_AHB1ENR_USB2OTGFSEN_Pos (27U)
#define RCC_AHB1ENR_USB2OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos) /*!< 0x08000000 */
#define RCC_AHB1ENR_USB2OTGFSEN RCC_AHB1ENR_USB2OTGFSEN_Msk
#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos (28U)
#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */
#define RCC_AHB1ENR_USB2OTGFSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
/* Legacy define */
#define RCC_AHB1ENR_USB2OTGHSEN_Pos RCC_AHB1ENR_USB2OTGFSEN_Pos
#define RCC_AHB1ENR_USB2OTGHSEN_Msk RCC_AHB1ENR_USB2OTGFSEN_Msk
#define RCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGFSEN
#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
#define RCC_AHB1ENR_USB2OTGHSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_DCMIEN_Pos (0U)
@ -15203,7 +15186,6 @@ typedef struct
#define RCC_AHB4ENR_D3SRAM1EN RCC_AHB4ENR_D3SRAM1EN_Msk
/******************** Bit definition for RCC_APB3ENR register ******************/
#define RCC_APB3ENR_LTDCEN_Pos (3U)
#define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
#define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
@ -15503,7 +15485,6 @@ typedef struct
/******************** Bit definition for RCC_APB3RSTR register ******************/
#define RCC_APB3RSTR_LTDCRST_Pos (3U)
#define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
#define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
@ -15803,12 +15784,17 @@ typedef struct
#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos (27U)
#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */
#define RCC_AHB1LPENR_USB2OTGFSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos (28U)
#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */
#define RCC_AHB1LPENR_USB2OTGFSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
/* Legacy define */
#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
#define RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN
#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
#define RCC_AHB1LPENR_USB2OTGHSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN
/******************** Bit definition for RCC_AHB2LPENR register ***************/
#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
@ -15888,7 +15874,6 @@ typedef struct
#define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_D3SRAM1LPEN_Msk
/******************** Bit definition for RCC_APB3LPENR register ******************/
#define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
#define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
#define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
@ -17177,9 +17162,9 @@ typedef struct
#define SAI_xCR1_DMAEN_Pos (17U)
#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
#define SAI_xCR1_NOMCK_Pos (19U)
#define SAI_xCR1_NOMCK_Msk (0x1UL << SAI_xCR1_NOMCK_Pos) /*!< 0x00080000 */
#define SAI_xCR1_NOMCK SAI_xCR1_NOMCK_Msk /*!<No Divider Configuration */
#define SAI_xCR1_NODIV_Pos (19U)
#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV_Pos (20U)
#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
@ -17199,6 +17184,9 @@ typedef struct
#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<OverSampling Ratio for master clock */
/* Legacy define */
#define SAI_xCR1_NOMCK SAI_xCR1_NODIV
/******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH_Pos (0U)
#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
@ -18264,9 +18252,9 @@ typedef struct
#define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
/******************* Bit definition for SPI_RXCRC register ********************/
#define SPI_TXCRC_RXCRC_Pos (0U)
#define SPI_TXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
#define SPI_TXCRC_RXCRC SPI_TXCRC_RXCRC_Msk /* CRCRegister for receiver */
#define SPI_RXCRC_RXCRC_Pos (0U)
#define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
#define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
/******************* Bit definition for SPI_UDRDR register ********************/
#define SPI_UDRDR_UDRDR_Pos (0U)
@ -18352,10 +18340,10 @@ typedef struct
#define QUADSPI_CR_FTHRES_Pos (8U)
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
#define QUADSPI_CR_TEIE_Pos (16U)
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
@ -18380,14 +18368,14 @@ typedef struct
#define QUADSPI_CR_PRESCALER_Pos (24U)
#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
/***************** Bit definition for QUADSPI_DCR register ******************/
#define QUADSPI_DCR_CKMODE_Pos (0U)
@ -18396,17 +18384,17 @@ typedef struct
#define QUADSPI_DCR_CSHT_Pos (8U)
#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
#define QUADSPI_DCR_FSIZE_Pos (16U)
#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
/****************** Bit definition for QUADSPI_SR register *******************/
#define QUADSPI_SR_TEF_Pos (0U)
@ -18428,15 +18416,14 @@ typedef struct
#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
#define QUADSPI_SR_FLEVEL_Pos (8U)
#define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
#define QUADSPI_SR_FLEVEL_6 (0x30UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003000 */
#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
/****************** Bit definition for QUADSPI_FCR register ******************/
#define QUADSPI_FCR_CTEF_Pos (0U)
@ -18460,7 +18447,7 @@ typedef struct
/****************** Bit definition for QUADSPI_CCR register ******************/
#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
@ -18470,57 +18457,57 @@ typedef struct
#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
#define QUADSPI_CCR_IMODE_Pos (8U)
#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
#define QUADSPI_CCR_ADMODE_Pos (10U)
#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
#define QUADSPI_CCR_ADSIZE_Pos (12U)
#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
#define QUADSPI_CCR_ABMODE_Pos (14U)
#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
#define QUADSPI_CCR_ABSIZE_Pos (16U)
#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_CCR_DCYC_Pos (18U)
#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
#define QUADSPI_CCR_DMODE_Pos (24U)
#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
#define QUADSPI_CCR_FMODE_Pos (26U)
#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
#define QUADSPI_CCR_SIOO_Pos (28U)
#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
#define QUADSPI_CCR_DHHC_Pos (30U)
#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold half cycle */
#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold half cycle */
#define QUADSPI_CCR_DDRM_Pos (31U)
#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
/****************** Bit definition for QUADSPI_AR register *******************/
#define QUADSPI_AR_ADDRESS_Pos (0U)
@ -18591,6 +18578,7 @@ typedef struct
#define SYSCFG_PMCR_BOOSTEN_Pos (8U)
#define SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos) /*!< 0x00000100 */
#define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
#define SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U)
#define SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */
#define SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk /*!< Analog switch supply source selection : VDD/VDDA */
@ -18784,6 +18772,7 @@ typedef struct
#define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
/**
* @brief EXTI9 configuration
@ -18798,6 +18787,7 @@ typedef struct
#define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
/**
* @brief EXTI10 configuration
@ -18812,7 +18802,7 @@ typedef struct
#define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
/**
* @brief EXTI11 configuration
@ -18827,7 +18817,7 @@ typedef struct
#define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
@ -18855,6 +18845,7 @@ typedef struct
#define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
/**
* @brief EXTI13 configuration
*/
@ -18868,6 +18859,7 @@ typedef struct
#define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
/**
* @brief EXTI14 configuration
*/
@ -18881,6 +18873,7 @@ typedef struct
#define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
/**
* @brief EXTI15 configuration
*/
@ -18894,6 +18887,42 @@ typedef struct
#define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
/****************** Bit definition for SYSCFG_CFGR register ******************/
#define SYSCFG_CFGR_PVDL_Pos (2U)
#define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos) /*!< 0x00000004 */
#define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk /*!<PVD lock enable bit */
#define SYSCFG_CFGR_FLASHL_Pos (3U)
#define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos) /*!< 0x00000008 */
#define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk /*!<FLASH double ECC error lock bit */
#define SYSCFG_CFGR_CM7L_Pos (6U)
#define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos) /*!< 0x00000040 */
#define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
#define SYSCFG_CFGR_BKRAML_Pos (7U)
#define SYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos) /*!< 0x00000080 */
#define SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk /*!<Backup SRAM double ECC error lock bit */
#define SYSCFG_CFGR_SRAM4L_Pos (9U)
#define SYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos) /*!< 0x00000200 */
#define SYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk /*!<SRAM4 double ECC error lock bit */
#define SYSCFG_CFGR_SRAM3L_Pos (10U)
#define SYSCFG_CFGR_SRAM3L_Msk (0x1UL << SYSCFG_CFGR_SRAM3L_Pos) /*!< 0x00000400 */
#define SYSCFG_CFGR_SRAM3L SYSCFG_CFGR_SRAM3L_Msk /*!<SRAM3 double ECC error lock bit */
#define SYSCFG_CFGR_SRAM2L_Pos (11U)
#define SYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos) /*!< 0x00000800 */
#define SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk /*!<SRAM2 double ECC error lock bit */
#define SYSCFG_CFGR_SRAM1L_Pos (12U)
#define SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos) /*!< 0x00001000 */
#define SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk /*!<SRAM1 double ECC error lock bit */
#define SYSCFG_CFGR_DTCML_Pos (13U)
#define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos) /*!< 0x00002000 */
#define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk /*!<DTCM double ECC error lock bit */
#define SYSCFG_CFGR_ITCML_Pos (14U)
#define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos) /*!< 0x00004000 */
#define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk /*!<ITCM double ECC error lock bit */
#define SYSCFG_CFGR_AXISRAML_Pos (15U)
#define SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos) /*!< 0x00008000 */
#define SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk /*!<AXISRAM double ECC error lock bit */
/****************** Bit definition for SYSCFG_CCCSR register ******************/
#define SYSCFG_CCCSR_EN_Pos (0U)
@ -18924,6 +18953,10 @@ typedef struct
#define SYSCFG_CCCR_PCC_Pos (4U)
#define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos) /*!< 0x000000F0 */
#define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk /*!< PMOS compensation code */
/****************** Bit definition for SYSCFG_PWRCR register *******************/
#define SYSCFG_PWRCR_ODEN_Pos (0U)
#define SYSCFG_PWRCR_ODEN_Msk (0x1UL << SYSCFG_PWRCR_ODEN_Pos) /*!< 0x00000001 */
#define SYSCFG_PWRCR_ODEN SYSCFG_PWRCR_ODEN_Msk /*!< PWR overdrive enable */
/****************** Bit definition for SYSCFG_PKGR register *******************/
#define SYSCFG_PKGR_PKG_Pos (0U)
@ -26117,6 +26150,7 @@ typedef struct
#define FLASH_SIZE 0x200000UL /* 2 MB */
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */

29
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/device/stm32h7xx.h
View File

@ -58,17 +58,26 @@
application
*/
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx)
// MBED PATCH
#define STM32H743xx /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx)
/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
// MBED PATCH
#define STM32H743xx /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
/* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
/* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
#error "Dual core device, please select CORE_CM4 or CORE_CM7"
#endif
#if !defined (USE_HAL_DRIVER)
/**
@ -82,10 +91,10 @@
#define USE_FULL_LL_DRIVER // MBED PATCH
/**
* @brief CMSIS Device version number V1.4.0
* @brief CMSIS Device version number V1.5.0
*/
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
@ -107,6 +116,16 @@
#include "stm32h753xx.h"
#elif defined(STM32H750xx)
#include "stm32h750xx.h"
#elif defined(STM32H742xx)
#include "stm32h742xx.h"
#elif defined(STM32H745xx)
#include "stm32h745xx.h"
#elif defined(STM32H755xx)
#include "stm32h755xx.h"
#elif defined(STM32H747xx)
#include "stm32h747xx.h"
#elif defined(STM32H757xx)
#include "stm32h757xx.h"
#else
#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
#endif

102
targets/TARGET_STM/TARGET_STM32H7/device/stm32_hal_legacy.h
View File

@ -236,6 +236,11 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
/**
* @}
*/
@ -486,6 +491,7 @@
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
/**
* @}
*/
@ -599,6 +605,7 @@
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
/**
* @}
*/
@ -738,6 +745,12 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
/**
* @}
*/
@ -753,7 +766,6 @@
#define I2S_FLAG_TXE I2S_FLAG_TXP
#define I2S_FLAG_RXNE I2S_FLAG_RXP
#define I2S_FLAG_FRE I2S_FLAG_TIFRE
#endif
#if defined(STM32F7)
@ -971,6 +983,24 @@
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
#endif
#if defined(STM32H7)
#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
/**
* @}
*/
@ -1250,7 +1280,7 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32G0)
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
@ -1259,7 +1289,18 @@
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
#endif /* STM32H7 || STM32G0 */
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
#endif /* STM32F4 */
/**
* @}
*/
@ -1339,7 +1380,7 @@
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0)
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
@ -2235,6 +2276,20 @@
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
#if defined(STM32WB)
#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
#define QSPI_IRQHandler QUADSPI_IRQHandler
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
@ -2451,12 +2506,28 @@
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
#if defined(STM32H7)
#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
@ -2789,6 +2860,15 @@
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
#if defined(STM32L1)
#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
#endif /* STM32L1 */
#if defined(STM32F4)
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
@ -2905,7 +2985,7 @@
#if defined(STM32L4)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32G0)
#elif defined(STM32WB) || defined(STM32G0)
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
@ -3149,7 +3229,7 @@
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
@ -3408,6 +3488,16 @@
* @}
*/
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32L4)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif
/**
* @}
*/
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/

226
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.c
View File

@ -47,10 +47,10 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/**
* @brief STM32H7xx HAL Driver version number V1.4.0
* @brief STM32H7xx HAL Driver version number V1.5.0
*/
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x04UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x05UL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB2 (0x00UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
@ -128,6 +128,12 @@ HAL_StatusTypeDef HAL_Init(void)
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU);
/* Update the SystemD2Clock global variable */
SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
@ -229,11 +235,32 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
return HAL_ERROR;
}
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Cortex-M7 detected */
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
}
else
{
/* Cortex-M4 detected */
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
}
#else
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
#endif
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
@ -602,16 +629,92 @@ void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
if ( BootRegister == SYSCFG_BOOT_ADDR0 )
{
/* Configure CM7 BOOT ADD0 */
#if defined(DUAL_CORE)
MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BCM7_ADD0_Pos));
#else
MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((BootAddress >> 16) << SYSCFG_UR2_BOOT_ADD0_Pos));
#endif /*DUAL_CORE*/
}
else
{
/* Configure CM7 BOOT ADD1 */
#if defined(DUAL_CORE)
MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, (BootAddress >> 16));
#else
MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, (BootAddress >> 16));
#endif /*DUAL_CORE*/
}
}
#if defined(DUAL_CORE)
/**
* @brief BootCM4 address 0 configuration
* @param BootRegister :Specifies the Boot Address register (Address0 or Address1)
* This parameter can be one of the following values:
* @arg SYSCFG_BOOT_ADDR0 : Select the boot address0
* @arg SYSCFG_BOOT_ADDR1: Select the boot address1
* @param BootAddress :Specifies the CM4 Boot Address to be loaded in Address0 or Address1
* @retval None
*/
void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress)
{
/* Check the parameters */
assert_param(IS_SYSCFG_BOOT_REGISTER(BootRegister));
assert_param(IS_SYSCFG_BOOT_ADDRESS(BootAddress));
if ( BootRegister == SYSCFG_BOOT_ADDR0 )
{
/* Configure CM4 BOOT ADD0 */
MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((BootAddress >> 16)<< SYSCFG_UR3_BCM4_ADD0_Pos));
}
else
{
/* Configure CM4 BOOT ADD1 */
MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, (BootAddress >> 16));
}
}
/**
* @brief Enables the Cortex-M7 boot
* @retval None
*/
void HAL_SYSCFG_EnableCM7BOOT(void)
{
SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7);
}
/**
* @brief Disables the Cortex-M7 boot
* @note Disabling the boot will gate the CPU clock
* @retval None
*/
void HAL_SYSCFG_DisableCM7BOOT(void)
{
CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM7) ;
}
/**
* @brief Enables the Cortex-M4 boot
* @retval None
*/
void HAL_SYSCFG_EnableCM4BOOT(void)
{
SET_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
}
/**
* @brief Disables the Cortex-M4 boot
* @note Disabling the boot will gate the CPU clock
* @retval None
*/
void HAL_SYSCFG_DisableCM4BOOT(void)
{
CLEAR_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4);
}
#endif /*DUAL_CORE*/
/**
* @brief Enables the I/O Compensation Cell.
* @note The I/O compensation cell can be used only when the device supply
@ -747,6 +850,63 @@ void HAL_DisableDBGStandbyMode(void)
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);
}
#if defined(DUAL_CORE)
/**
* @brief Enable the Debug Module during Domain1 SLEEP mode
* @retval None
*/
void HAL_EnableDomain2DBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
}
/**
* @brief Disable the Debug Module during Domain2 SLEEP mode
* @retval None
*/
void HAL_DisableDomain2DBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);
}
/**
* @brief Enable the Debug Module during Domain2 STOP mode
* @retval None
*/
void HAL_EnableDomain2DBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
}
/**
* @brief Disable the Debug Module during Domain2 STOP mode
* @retval None
*/
void HAL_DisableDomain2DBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);
}
/**
* @brief Enable the Debug Module during Domain2 STANDBY mode
* @retval None
*/
void HAL_EnableDomain2DBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
}
/**
* @brief Disable the Debug Module during Domain2 STANDBY mode
* @retval None
*/
void HAL_DisableDomain2DBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);
}
#endif /*DUAL_CORE*/
/**
* @brief Enable the Debug Module during Domain3 STOP mode
* @retval None
@ -867,6 +1027,21 @@ void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line)
}
#if defined(DUAL_CORE)
/**
* @brief Clears the EXTI's line pending flags for Domain D2
* @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
* (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
* @retval None
*/
void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line)
{
/* Check the parameters */
assert_param(IS_EXTI_D2_LINE(EXTI_Line));
SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->PR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
}
#endif /*DUAL_CORE*/
/**
* @brief Configure the EXTI input event line for Domain D1
* @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
@ -912,6 +1087,53 @@ void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint
}
}
#if defined(DUAL_CORE)
/**
* @brief Configure the EXTI input event line for Domain D2
* @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,
* (EXTI_LINE0....EXTI_LINE87)excluding :line45, line81,line83 which are reserved
* @param EXTI_Mode: Specifies which EXTI line is used as interrupt or an event.
* This parameter can be one or a combination of the following values :
* @arg EXTI_MODE_IT : Interrupt Mode selected
* @arg EXTI_MODE_EVT : Event Mode selected
* @param EXTI_LineCmd controls (Enable/Disable) the EXTI line.
* @retval None
*/
void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd )
{
/* Check the parameter */
assert_param(IS_EXTI_D2_LINE(EXTI_Line));
assert_param(IS_EXTI_MODE_LINE(EXTI_Mode));
if( (EXTI_Mode & EXTI_MODE_IT) == EXTI_MODE_IT)
{
if( EXTI_LineCmd == 0UL)
{
/* Clear EXTI line configuration */
CLEAR_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)),(uint32_t)(1UL << (EXTI_Line & 0x1FUL)) );
}
else
{
SET_BIT(*(__IO uint32_t *) (((uint32_t) &(EXTI_D2->IMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
}
}
if( (EXTI_Mode & EXTI_MODE_EVT) == EXTI_MODE_EVT)
{
if( EXTI_LineCmd == 0UL)
{
/* Clear EXTI line configuration */
CLEAR_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
}
else
{
SET_BIT( *(__IO uint32_t *) (((uint32_t) &(EXTI_D2->EMR1)) + ((EXTI_Line >> 5 ) * 0x10UL)), (uint32_t)(1UL << (EXTI_Line & 0x1FUL)));
}
}
}
#endif /*DUAL_CORE*/
/**
* @brief Configure the EXTI input event line for Domain D3
* @param EXTI_Line: Specifies the EXTI LINE, it can be one of the following values,

394
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal.h
View File

@ -54,6 +54,18 @@ typedef enum
/* Exported constants --------------------------------------------------------*/
/** @defgroup REV_ID device revision ID
* @{
*/
#define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */
#define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */
#define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */
#define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */
/**
* @}
*/
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
*/
@ -231,7 +243,11 @@ typedef enum
#define EXTI_LINE43 ((uint32_t)0x2B)
#define EXTI_LINE44 ((uint32_t)0x2C)
/* EXTI_LINE45 Reserved */
#if defined(DUAL_CORE)
#define EXTI_LINE46 ((uint32_t)0x2E)
#else
/* EXTI_LINE46 Reserved */
#endif
#define EXTI_LINE47 ((uint32_t)0x2F)
#define EXTI_LINE48 ((uint32_t)0x30)
#define EXTI_LINE49 ((uint32_t)0x31)
@ -266,6 +282,21 @@ typedef enum
#define EXTI_LINE75 ((uint32_t)0x4B)
#define EXTI_LINE76 ((uint32_t)0x4C)
#if defined(DUAL_CORE)
#define EXTI_LINE77 ((uint32_t)0x4D)
#define EXTI_LINE78 ((uint32_t)0x4E)
#define EXTI_LINE79 ((uint32_t)0x4F)
#define EXTI_LINE80 ((uint32_t)0x50)
/* EXTI_LINE81 Reserved */
#define EXTI_LINE82 ((uint32_t)0x52)
/* EXTI_LINE83 Reserved */
#define EXTI_LINE84 ((uint32_t)0x54)
#define EXTI_LINE85 ((uint32_t)0x55)
#define EXTI_LINE86 ((uint32_t)0x56)
#define EXTI_LINE87 ((uint32_t)0x57)
/* EXTI_LINE88 Reserved */
#else
/* EXTI_LINE77 Reserved */
/* EXTI_LINE78 Reserved */
/* EXTI_LINE79 Reserved */
@ -280,8 +311,24 @@ typedef enum
#define EXTI_LINE87 ((uint32_t)0x57)
/* EXTI_LINE88 Reserved */
#endif
#if defined(DUAL_CORE)
#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84) || \
((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
#else
#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
@ -295,8 +342,53 @@ typedef enum
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
#endif
#if defined(DUAL_CORE)
#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
((LINE) == EXTI_LINE78) || \
((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82))
#else
#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
@ -337,8 +429,51 @@ typedef enum
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \
((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
#else
#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
@ -379,8 +514,53 @@ typedef enum
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
#define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \
((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \
((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
@ -396,6 +576,23 @@ typedef enum
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
((LINE) == EXTI_LINE53))
#else
#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
((LINE) == EXTI_LINE53))
#endif
#define BDMA_CH6_CLEAR ((uint32_t)0x00000000) /*!< BDMA ch6 event selected as D3 domain pendclear source*/
@ -427,6 +624,99 @@ typedef enum
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
* @{
*/
/** @brief SYSCFG Break AXIRAM double ECC lock.
* Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
This feature is available on STM32H7 rev.B and above.
*/
#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)
/** @brief SYSCFG Break ITCM double ECC lock.
* Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
This feature is available on STM32H7 rev.B and above.
*/
#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)
/** @brief SYSCFG Break DTCM double ECC lock.
* Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
This feature is available on STM32H7 rev.B and above.
*/
#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)
/** @brief SYSCFG Break SRAM1 double ECC lock.
* Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
This feature is available on STM32H7 rev.B and above.
*/
#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)
/** @brief SYSCFG Break SRAM2 double ECC lock.
* Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
This feature is available on STM32H7 rev.B and above.
*/
#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)
/** @brief SYSCFG Break SRAM3 double ECC lock.
* Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
This feature is available on STM32H7 rev.B and above.
*/
#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)
/** @brief SYSCFG Break SRAM4 double ECC lock.
* Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
This feature is available on STM32H7 rev.B and above.
*/
#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)
/** @brief SYSCFG Break Backup SRAM double ECC lock.
* Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
This feature is available on STM32H7 rev.B and above.
*/
#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)
/** @brief SYSCFG Break Cortex-M7 Lockup lock.
* Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
This feature is available on STM32H7 rev.B and above.
*/
#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)
/** @brief SYSCFG Break FLASH double ECC lock.
* Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
This feature is available on STM32H7 rev.B and above.
*/
#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)
/** @brief SYSCFG Break PVD lock.
* Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
* @note The selected configuration is locked and can be unlocked only by system reset.
This feature is available on STM32H7 rev.B and above.
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)
#if defined(DUAL_CORE)
/** @brief SYSCFG Break Cortex-M4 Lockup lock.
* Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
This feature is available on STM32H7 rev.B and above.
*/
#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L)
#endif /* DUAL_CORE */
/**
* @}
*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
@ -497,6 +787,83 @@ typedef enum
#define __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
#define __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))
#if defined(DUAL_CORE)
#define __HAL_DBGMCU_FREEZE2_IWDG2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG2))
#define __HAL_DBGMCU_FREEZE2_WWDG2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2))
#define __HAL_DBGMCU_UnFreeze2_IWDG2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2))
#define __HAL_DBGMCU_UnFreeze2_WWDG2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2))
#define __HAL_DBGMCU_FREEZE2_WWDG1() (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1))
#define __HAL_DBGMCU_FREEZE2_TIM2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2))
#define __HAL_DBGMCU_FREEZE2_TIM3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3))
#define __HAL_DBGMCU_FREEZE2_TIM4() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4))
#define __HAL_DBGMCU_FREEZE2_TIM5() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5))
#define __HAL_DBGMCU_FREEZE2_TIM6() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6))
#define __HAL_DBGMCU_FREEZE2_TIM7() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7))
#define __HAL_DBGMCU_FREEZE2_TIM12() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12))
#define __HAL_DBGMCU_FREEZE2_TIM13() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13))
#define __HAL_DBGMCU_FREEZE2_TIM14() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14))
#define __HAL_DBGMCU_FREEZE2_LPTIM1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1))
#define __HAL_DBGMCU_FREEZE2_I2C1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1))
#define __HAL_DBGMCU_FREEZE2_I2C2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2))
#define __HAL_DBGMCU_FREEZE2_I2C3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3))
#define __HAL_DBGMCU_FREEZE2_FDCAN() (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN))
#define __HAL_DBGMCU_FREEZE2_TIM1() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1))
#define __HAL_DBGMCU_FREEZE2_TIM8() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8))
#define __HAL_DBGMCU_FREEZE2_TIM15() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15))
#define __HAL_DBGMCU_FREEZE2_TIM16() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16))
#define __HAL_DBGMCU_FREEZE2_TIM17() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17))
#define __HAL_DBGMCU_FREEZE2_HRTIM() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM))
#define __HAL_DBGMCU_FREEZE2_I2C4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4))
#define __HAL_DBGMCU_FREEZE2_LPTIM2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2))
#define __HAL_DBGMCU_FREEZE2_LPTIM3() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3))
#define __HAL_DBGMCU_FREEZE2_LPTIM4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4))
#define __HAL_DBGMCU_FREEZE2_LPTIM5() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5))
#define __HAL_DBGMCU_FREEZE2_RTC() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC))
#define __HAL_DBGMCU_FREEZE2_IWDG1() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1))
#define __HAL_DBGMCU_UnFreeze2_WWDG1() (DBGMCU->APB3FZ2 &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1))
#define __HAL_DBGMCU_UnFreeze2_TIM2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2))
#define __HAL_DBGMCU_UnFreeze2_TIM3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3))
#define __HAL_DBGMCU_UnFreeze2_TIM4() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4))
#define __HAL_DBGMCU_UnFreeze2_TIM5() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5))
#define __HAL_DBGMCU_UnFreeze2_TIM6() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6))
#define __HAL_DBGMCU_UnFreeze2_TIM7() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7))
#define __HAL_DBGMCU_UnFreeze2_TIM12() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12))
#define __HAL_DBGMCU_UnFreeze2_TIM13() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13))
#define __HAL_DBGMCU_UnFreeze2_TIM14() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14))
#define __HAL_DBGMCU_UnFreeze2_LPTIM1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1))
#define __HAL_DBGMCU_UnFreeze2_I2C1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1))
#define __HAL_DBGMCU_UnFreeze2_I2C2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2))
#define __HAL_DBGMCU_UnFreeze2_I2C3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3))
#define __HAL_DBGMCU_UnFreeze2_FDCAN() (DBGMCU->APB1HFZ2 &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN))
#define __HAL_DBGMCU_UnFreeze2_TIM1() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM1))
#define __HAL_DBGMCU_UnFreeze2_TIM8() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM8))
#define __HAL_DBGMCU_UnFreeze2_TIM15() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM15))
#define __HAL_DBGMCU_UnFreeze2_TIM16() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM16))
#define __HAL_DBGMCU_UnFreeze2_TIM17() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM17))
#define __HAL_DBGMCU_UnFreeze2_HRTIM() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM))
#define __HAL_DBGMCU_UnFreeze2_I2C4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_I2C4))
#define __HAL_DBGMCU_UnFreeze2_LPTIM2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2))
#define __HAL_DBGMCU_UnFreeze2_LPTIM3() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3))
#define __HAL_DBGMCU_UnFreeze2_LPTIM4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4))
#define __HAL_DBGMCU_UnFreeze2_LPTIM5() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5))
#define __HAL_DBGMCU_UnFreeze2_RTC() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_RTC))
#define __HAL_DBGMCU_UnFreeze2_IWDG1() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1))
#endif /*DUAL_CORE*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
@ -533,6 +900,13 @@ void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCF
void HAL_SYSCFG_EnableBOOST(void);
void HAL_SYSCFG_DisableBOOST(void);
void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
#if defined(DUAL_CORE)
void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
void HAL_SYSCFG_EnableCM7BOOT(void);
void HAL_SYSCFG_DisableCM7BOOT(void);
void HAL_SYSCFG_EnableCM4BOOT(void);
void HAL_SYSCFG_DisableCM4BOOT(void);
#endif /*DUAL_CORE*/
void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
void HAL_SYSCFG_EnableIOSpeedOptimize(void);
@ -545,14 +919,28 @@ void HAL_EnableDBGStopMode(void);
void HAL_DisableDBGStopMode(void);
void HAL_EnableDBGStandbyMode(void);
void HAL_DisableDBGStandbyMode(void);
#if defined(DUAL_CORE)
void HAL_EnableDomain2DBGSleepMode(void);
void HAL_DisableDomain2DBGSleepMode(void);
void HAL_EnableDomain2DBGStopMode(void);
void HAL_DisableDomain2DBGStopMode(void);
void HAL_EnableDomain2DBGStandbyMode(void);
void HAL_DisableDomain2DBGStandbyMode(void);
#endif /*DUAL_CORE*/
void HAL_EnableDomain3DBGStopMode(void);
void HAL_DisableDomain3DBGStopMode(void);
void HAL_EnableDomain3DBGStandbyMode(void);
void HAL_DisableDomain3DBGStandbyMode(void);
void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );
void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
#if defined(DUAL_CORE)
void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line);
#endif /*DUAL_CORE*/
void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line);
void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd);
#if defined(DUAL_CORE)
void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd);
#endif /*DUAL_CORE*/
void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc);
void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig);
uint32_t HAL_GetFMCMemorySwappingConfig(void);

1319
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.c
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File diff suppressed because it is too large Load Diff

135
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc.h
View File

@ -60,11 +60,11 @@ typedef struct
uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
The oversampling is either temporary stopped or reset upon an injected
sequence interruption.
If oversampling is enabled on both regular and injected groups, this parameter
is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
(the oversampling buffer is zeroed during injection sequence).
This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
sequence interruption.
If oversampling is enabled on both regular and injected groups, this parameter
is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
(the oversampling buffer is zeroed during injection sequence).
This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
}ADC_OversamplingTypeDef;
@ -81,7 +81,7 @@ typedef struct
* - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
* - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
* (which fulfills the ADC state condition) on the fly).
*/
typedef struct
@ -115,7 +115,7 @@ typedef struct
conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
for low frequency applications.
for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
to free the IRQ vector sequencer.
@ -199,7 +199,7 @@ typedef struct
uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
the new channel setting (or parameter number of conversions adjusted) */
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
@ -222,7 +222,7 @@ typedef struct
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
of another parameter update on the fly) */
uint32_t OffsetNumber; /*!< Select the offset number
@ -231,17 +231,19 @@ typedef struct
uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
Offset value must be a positive number.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
0x3FF, 0xFF or 0x3F respectively.
Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF,
0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
without continuous mode or external trigger that could launch a conversion). */
FunctionalState OffsetRightShift; /*!< Define the Right-shift data after Offset correction.
This parameter is applied only for 16-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE.*/
FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.
This parameter is applied only for 16-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE. */
}ADC_ChannelConfTypeDef;
/**
@ -271,8 +273,8 @@ typedef struct
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
@ -281,9 +283,9 @@ typedef struct
application): intermediate register bitfield [32:7] (26 most significant bits). */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
impacted: the comparison of analog watchdog thresholds is done
@ -346,7 +348,7 @@ typedef struct
#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
/**
* @}
@ -424,7 +426,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @{
*/
#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error (problem of clocking,
#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
enable/disable, erroneous state, ...) */
#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
@ -485,28 +487,27 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
*/
/* ADC group regular trigger sources for all ADC instances */
#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1)
#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2)
#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3)
#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2)
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)
#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4)
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)
#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)
#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)
#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)
#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)
#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4)
#define ADC_EXTERNALTRIG_HR1_ADCTRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)
#define ADC_EXTERNALTRIG_HR1_ADCTRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)
#define ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT)
#define ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT)
#define ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT)
#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_HR1_ADCTRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_HR1_ADCTRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG3 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM1_OUT (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM2_OUT (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM3_OUT (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
@ -578,7 +579,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @}
*/
/** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode
/** @defgroup ADCEx_Calibration_Mode ADC Extended Calibration mode offset mode or linear mode
* @{
*/
#define ADC_CALIB_OFFSET (LL_ADC_CALIB_OFFSET)
@ -612,10 +613,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
#define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */
/* Note: Vbat/4, TempSensor and VREFINT internal channels are available on ADC3 only */
#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference, channel specific to ADC3. */
#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor, channel specific to ADC3. */
#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC3. */
#define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
#define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
/**
@ -629,7 +629,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */
#define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */
#define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)) /*!< DMA circular mode selected */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
* @{
*/
@ -689,6 +691,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/**
* @}
*/
/** @defgroup ADCEx_Left_Bit_Shift ADC Extended Oversampling left Shift
* @{
*/
@ -710,7 +713,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_LEFTBITSHIFT_15 (LL_ADC_LEFT_BIT_SHIFT_15) /*!< ADC 15 bits shift */
/**
* @}
*/
*/
/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
* @{
@ -781,17 +784,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
#define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */
#define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \
ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \
ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */
/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */
#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \
ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \
ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */
/**
* @}
*/
@ -807,6 +799,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
*/
/* Macro reserved for internal HAL driver usage, not intended to be used in */
/* code of final user. */
/**
* @brief Verify the ADC data conversion setting.
* @param DATA : programmed DATA conversion mode.
@ -872,7 +865,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/**
* @brief Verify that a given value is aligned with the ADC resolution range.
* @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
* @param __RESOLUTION__ ADC resolution (16, 14, 12, 10 or 8 bits).
* @param __ADC_VALUE__ value checked against the resolution.
* @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
*/
@ -897,7 +890,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/**
* @brief Verify the ADC clock setting.
* @param __ADC_CLOCK__ programmed ADC clock.
* @param __ADC_CLOCK__ programmed ADC clock.
* @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
*/
#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
@ -918,7 +911,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/**
* @brief Verify the ADC resolution setting.
* @param __RESOLUTION__ programmed ADC resolution.
* @param __RESOLUTION__ programmed ADC resolution.
* @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
*/
#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \
@ -928,7 +921,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
((__RESOLUTION__) == ADC_RESOLUTION_8B) )
/**
* @brief Verify the ADC resolution setting when limited to 8 bits.
* @param __RESOLUTION__: programmed ADC resolution when limited to 8 bits.
* @param __RESOLUTION__ programmed ADC resolution when limited to 8 bits.
* @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
*/
#define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B))
@ -1002,17 +995,16 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
*/
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \
((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_8CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_8CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_16CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_32CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_64CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_810CYCLES_5) )
/**
* @brief Verify the ADC regular channel setting.
* @param __CHANNEL__ programmed ADC regular channel.
* @param __CHANNEL__ programmed ADC regular channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
@ -1062,6 +1054,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/* Maximum delay is 10 microseconds */
/* (refer device RM, parameter Tadcvreg_stup). */
#define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */
/**
* @}
*/
@ -1452,8 +1445,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* In this case the transferred data need to processed with this macro
* to separate the conversion data of ADC master and ADC slave.
* @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
* @arg __LL_ADC_MULTI_MASTER__
* @arg __LL_ADC_MULTI_SLAVE__
* @arg @ref LL_ADC_MULTI_MASTER
* @arg @ref LL_ADC_MULTI_SLAVE
* @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
@ -1505,7 +1498,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_RESOLUTION_12B
* @arg @ref ADC_RESOLUTION_10B
* @arg @ref ADC_RESOLUTION_8B
* @retval ADC conversion data equivalent voltage value (unit: digital value of ADC conversion bitfield)
* @retval ADC conversion data full-scale digital value
*/
#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
__LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
@ -1522,6 +1515,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_RESOLUTION_10B
* @arg @ref ADC_RESOLUTION_8B
* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
* This parameter can be one of the following values:
* @arg @ref ADC_RESOLUTION_16B
* @arg @ref ADC_RESOLUTION_14B
* @arg @ref ADC_RESOLUTION_12B
@ -1771,7 +1765,7 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
*/
/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
@ -1821,9 +1815,6 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc);
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif

66
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.c
View File

@ -2,7 +2,7 @@
******************************************************************************
* @file stm32h7xx_hal_adc_ex.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC)
* peripheral:
* + Operation functions
@ -16,7 +16,7 @@
* ++ Channels configuration on ADC group injected
* + State functions
* ++ ADC group injected contexts queue management
* Other functions (generic functions) are available in file
* Other functions (generic functions) are available in file
* "stm32h7xx_hal_adc.c".
*
@verbatim
@ -121,14 +121,14 @@
* Calibration prerequisite: ADC must be disabled (execute this
* function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
* @param hadc ADC handle
* @param CalibrationMode Selection of calibration offset or
* @param CalibrationMode Selection of calibration offset or
* linear calibration offset.
* @arg ADC_CALIB_OFFSET Channel in mode calibration offset
* @arg ADC_CALIB_OFFSET_LINEARITY Channel in mode linear calibration offset
* @param SingleDiff Selection of single-ended or differential input
* This parameter can be one of the following values:
* @arg ADC_SINGLE_ENDED Channel in mode input single ended
* @arg ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t CalibrationMode, uint32_t SingleDiff)
@ -217,7 +217,7 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single
/**
* @brief Get the calibration factor from automatic conversion result
* @param hadc: ADC handle
* @param hadc ADC handle
* @param LinearCalib_Buffer: Linear calibration factor
* @retval HAL state
*/
@ -236,8 +236,8 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc,
{
for(cnt = 0UL; cnt < 6UL; cnt++)
{
LinearCalib_Buffer[cnt]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> cnt);
}
LinearCalib_Buffer[cnt]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> cnt);
}
}
return tmp_hal_status;
@ -300,7 +300,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32
/**
* @brief Set the linear calibration factor
* @param hadc: ADC handle
* @param hadc ADC handle
* @param LinearCalib_Buffer: Linear calibration factor
* @retval HAL state
*/
@ -349,7 +349,7 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc,
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
/* Set ADC error code to ADC IP internal error */
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
return HAL_ERROR;
@ -357,7 +357,7 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc,
for(cnt = 0UL; cnt < 6UL; cnt++)
{
LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> cnt, LinearCalib_Buffer[cnt]);
LL_ADC_SetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> cnt, LinearCalib_Buffer[cnt]);
}
return HAL_OK;
}
@ -1450,10 +1450,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
{
/* Clear HAL_ADC_STATE_REG_BUSY bit */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
/* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL);
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
/* while DMA transfer is on going) */
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
@ -1729,7 +1729,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
{
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
}
/* JDISCEN and JAUTO bits can't be set at the same time */
assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));
@ -1745,15 +1745,15 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
{
if (hadc->Instance == ADC1)
{
assert_param(IS_ADC1_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
assert_param(IS_ADC1_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
}
if (hadc->Instance == ADC2)
{
assert_param(IS_ADC2_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
assert_param(IS_ADC2_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
}
if (hadc->Instance == ADC3)
{
assert_param(IS_ADC3_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
assert_param(IS_ADC3_DIFF_CHANNEL(sConfigInjected->InjectedChannel));
}
}
@ -1895,9 +1895,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* mode is disabled. */
if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
{
/* ADC channels preselection */
/* ADC channels preselection */
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) & 0x1FUL));
/* If auto-injected mode is disabled: no constraint */
if (sConfigInjected->AutoInjectedConv == DISABLE)
{
@ -1964,7 +1964,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
if (sConfigInjected->InjecOversamplingMode == ENABLE)
{
assert_param(IS_ADC_OVERSAMPLING_RATIO((uint32_t)sConfigInjected->InjecOversampling.Ratio));
assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
/* JOVSE must be reset in case of triggered regular mode */
@ -1993,8 +1993,6 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfigInjected->InjectedChannel, sConfigInjected->InjectedSamplingTime);
/* Set ADC selected offset signed saturation */
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
@ -2006,6 +2004,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, sConfigInjected->InjectedOffsetNumber, sConfigInjected->InjectedChannel, tmpOffsetShifted);
/* Set ADC selected offset signed saturation */
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfigInjected->InjectedOffsetNumber, (sConfigInjected->InjectedOffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
else
{
@ -2013,19 +2014,19 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
/* If this is the case, the corresponding offset number is disabled. */
if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
}
}
@ -2045,7 +2046,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL), sConfigInjected->InjectedSamplingTime);
LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
@ -2187,10 +2188,11 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
/* transition from multimode to independent mode). */
if(multimode->Mode != ADC_MODE_INDEPENDENT)
{
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
/* Note: Delay range depends on selected resolution: */
/* from 1 to 9 clock cycles for 16 bits */
/* from 1 to 9 clock cycles for 14 bits, */

195
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_adc_ex.h
View File

@ -34,14 +34,14 @@
/** @addtogroup ADCEx
* @{
*/
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
* @{
*/
/**
/**
* @brief ADC Injected Conversion Oversampling structure definition
*/
typedef struct
@ -69,7 +69,7 @@ typedef struct
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
typedef struct
{
uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
@ -117,11 +117,13 @@ typedef struct
uint32_t InjectedOffsetRightShift; /*!< Specifies whether the 1 bit Right-shift feature is used or not.
This parameter is applied only for 16-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not.
This parameter is applied only for 16-bit or 8-bit resolution.
This parameter can be set to ENABLE or DISABLE. */
uint32_t InjectedLeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
@ -188,16 +190,18 @@ typedef struct
{
uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode.
This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format:
This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
Delay range depends on selected resolution: */
/* from 1 to 9 clock cycles for 16 bits,
from 1 to 9 clock cycles for 14 bits
from 1 to 8 clock cycles for 12 bits
from 1 to 6 clock cycles for 10 bits
from 1 to 6 clock cycles for 8 bits */
Delay range depends on selected resolution:
from 1 to 9 clock cycles for 16 bits,
from 1 to 9 clock cycles for 14 bits
from 1 to 8 clock cycles for 12 bits
from 1 to 6 clock cycles for 10 bits
from 1 to 6 clock cycles for 8 bits */
}ADC_MultiModeTypeDef;
/**
@ -215,28 +219,27 @@ typedef struct
*/
/* ADC group regular trigger sources for all ADC instances */
#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< Event 0 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< Event 1 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< Event 2 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< Event 3 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< Event 4 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< Event 5 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< Event 6 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< Event 7 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< Event 8 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< Event 9 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< Event 10 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< Event 11 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< Event 12 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< Event 13 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< Event 14 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< Event 15 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< Event 16 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< Event 17 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) /*!< Event 18 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) /*!< Event 19 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) /*!< Event 20 triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
@ -295,15 +298,17 @@ typedef struct
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
/** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting
* @{
*/
#define ADC_DUALMODEDATAFORMAT_DISABLED ((uint32_t)0x00000000) /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */
#define ADC_DUALMODEDATAFORMAT_32_10_BITS ((uint32_t)ADC_CCR_DAMDF_1) /*!< Data formatting mode for 32 down to 10-bit resolution */
#define ADC_DUALMODEDATAFORMAT_8_BITS ((uint32_t)(ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */
#define ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL) /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */
#define ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1) /*!< Data formatting mode for 32 down to 10-bit resolution */
#define ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
* @{
*/
@ -514,6 +519,7 @@ typedef struct
* @retval None
*/
#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))
/**
* @brief Configure the channel number into offset OFRx register.
* @param __CHANNEL__ ADC Channel.
@ -569,11 +575,15 @@ typedef struct
* @param __OFFSET__: Value to be shifted
* @retval None
*/
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)? \
((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL )*2UL)): \
((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)))
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
(((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)
/**
* @brief Shift the AWD1 threshold in function of the selected ADC resolution.
@ -588,10 +598,15 @@ typedef struct
* @param __THRESHOLD__: Value to be shifted
* @retval None
*/
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)? \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL )*2UL)): \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)))
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
(((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)
/**
* @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
@ -606,12 +621,15 @@ typedef struct
* @param __THRESHOLD__: Value to be shifted
* @retval None
*/
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)? \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL )*2UL)): \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)))
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
(((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \
? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \
: \
((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \
)
/**
* @brief Clear Common Control Register.
* @param __HANDLE__ ADC handle.
@ -623,14 +641,12 @@ typedef struct
* @retval Common control register
*/
#define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON)
/**
* @brief Report common register to ADC1 and ADC2
* @brief Report common register to ADC3
* @param __HANDLE__: ADC handle
* @retval Common control register
*/
#define ADC3_COMMON_REGISTER(__HANDLE__) (ADC3_COMMON)
/**
* @brief Report Master Instance
* @param __HANDLE__: ADC handle
@ -659,7 +675,7 @@ typedef struct
: \
RESET \
)
/**
* @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master
* @param __HANDLE__: ADC handle
@ -691,6 +707,7 @@ typedef struct
* @param __HANDLE__: ADC handle
* @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
*/
#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
)? \
@ -705,6 +722,7 @@ typedef struct
* @param __HANDLE__: ADC handle
* @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
*/
#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
)? \
@ -713,9 +731,7 @@ typedef struct
( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \
((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
ADC_CCR_PRESC | \
ADC_CCR_VBATEN | \
@ -777,7 +793,7 @@ typedef struct
* @param __CHANNEL__ programmed ADC channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \
#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \
((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
@ -808,7 +824,7 @@ typedef struct
* @param __CHANNEL__: programmed ADC channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)|| \
#define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) ||\
((__CHANNEL__) == ADC_CHANNEL_3) ||\
((__CHANNEL__) == ADC_CHANNEL_4) ||\
@ -824,33 +840,31 @@ typedef struct
* @param __CHANNEL__: programmed ADC channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)|| \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_18) )
#define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_18) )
/**
* @brief Verify the ADC channel setting in differential mode for ADC3.
* @param __CHANNEL__: programmed ADC channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#define IS_ADC3_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_14) || \
((__CHANNEL__) == ADC_CHANNEL_15) )
#define IS_ADC3_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_14) || \
((__CHANNEL__) == ADC_CHANNEL_15) )
/**
* @brief Verify the ADC single-ended input or differential mode setting.
@ -902,9 +916,8 @@ typedef struct
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
\
((__INJTRIG__) == ADC_SOFTWARE_START) )
\
((__INJTRIG__) == ADC_SOFTWARE_START) )
/**
* @brief Verify the ADC edge trigger setting for injected group.
@ -930,15 +943,6 @@ typedef struct
((__MODE__) == ADC_DUALMODE_INTERL) || \
((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
/**
* @brief Verify the ADC multimode DMA access setting.
* @param __MODE__ programmed ADC multimode DMA access setting.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) )
/**
* @brief Verify the ADC dual data mode setting.
* @param MODE: programmed ADC dual mode setting.
@ -947,7 +951,7 @@ typedef struct
#define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \
((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \
((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS) )
/**
* @brief Verify the ADC multimode delay setting.
* @param __DELAY__ programmed ADC multimode delay setting.
@ -961,8 +965,7 @@ typedef struct
((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) )
((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) )
/**
* @brief Verify the ADC analog watchdog setting.
@ -1006,12 +1009,14 @@ typedef struct
((__EVENT__) == ADC_AWD3_EVENT) || \
((__EVENT__) == ADC_OVR_EVENT) || \
((__EVENT__) == ADC_JQOVF_EVENT) )
/**
* @brief Verify the ADC oversampling ratio.
* @param RATIO: programmed ADC oversampling ratio.
* @retval SET (RATIO is a valid value) or RESET (RATIO is invalid)
*/
#define IS_ADC_OVERSAMPLING_RATIO(RATIO) ((RATIO) < 1024UL)
/**
* @brief Verify the ADC oversampling shift.
* @param __SHIFT__ programmed ADC oversampling shift.
@ -1105,7 +1110,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
/* ADC multimode */
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */

299
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_comp.c
View File

@ -2,96 +2,96 @@
******************************************************************************
* @file stm32h7xx_hal_comp.c
* @author MCD Application Team
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* @brief COMP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the COMP peripheral:
* + Initialization and de-initialization functions
* + Start/Stop operation functions in polling mode
* + Start/Stop operation functions in interrupt mode
* + Peripheral control functions
* + Peripheral state functions
* + Peripheral state functions
@verbatim
================================================================================
##### COMP Peripheral features #####
================================================================================
[..]
[..]
The STM32H7xx device family integrates two analog comparators instances
COMP1 and COMP2:
(#) The COMP input minus (inverting input) and input plus (non inverting input)
can be set to internal references or to GPIO pins
(refer to GPIO list in reference manual).
(#) The COMP output level is available using HAL_COMP_GetOutputLevel()
and can be redirected to other peripherals: GPIO pins (in mode
alternate functions for comparator), timers.
(refer to GPIO list in reference manual).
(#) Pairs of comparators instances can be combined in window mode
(2 consecutive instances odd and even COMP<x> and COMP<x+1>).
(#) The comparators have interrupt capability through the EXTI controller
with wake-up from sleep and stop modes:
(++) COMP1 is internally connected to EXTI Line 20
(++) COMP2 is internally connected to EXTI Line 21
[..]
[..]
From the corresponding IRQ handler, the right interrupt source can be retrieved
using macro __HAL_COMP_COMP1_EXTI_GET_FLAG() and __HAL_COMP_COMP2_EXTI_GET_FLAG().
##### How to use this driver #####
================================================================================
[..]
This driver provides functions to configure and program the comparator instances of
This driver provides functions to configure and program the comparator instances of
STM32H7xx devices.
To use the comparator, perform the following steps:
(#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
(++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
using HAL_GPIO_Init().
(++) If needed, configure the GPIO connected to comparator output in alternate function mode
using HAL_GPIO_Init().
(++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
(++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
interrupt vector using HAL_NVIC_EnableIRQ() function.
(#) Configure the comparator using HAL_COMP_Init() function:
(++) Select the input minus (inverting input)
(++) Select the input plus (non-inverting input)
(++) Select the hysteresis
(++) Select the blanking source
(++) Select the output polarity
(++) Select the output polarity
(++) Select the power mode
(++) Select the window mode
-@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
to enable internal control clock of the comparators.
However, this is a legacy strategy.
Therefore, for compatibility anticipation, it is recommended to
However, this is a legacy strategy.
Therefore, for compatibility anticipation, it is recommended to
implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
In STM32H7,COMP clock enable __HAL_RCC_COMP12_CLK_ENABLE() must
In STM32H7,COMP clock enable __HAL_RCC_COMP12_CLK_ENABLE() must
be implemented by user in "HAL_COMP_MspInit()".
(#) Reconfiguration on-the-fly of comparator can be done by calling again
function HAL_COMP_Init() with new input structure parameters values.
(#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT()to be enabled
with the interrupt through NVIC of the CPU.
(#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT()to be enabled
with the interrupt through NVIC of the CPU.
Note: HAL_COMP_Start_IT() must be called after each interrupt otherwise the interrupt
mode will stay disabled.
(#) Use HAL_COMP_GetOutputLevel() or HAL_COMP_TriggerCallback()
functions to manage comparator outputs(output level or events)
(#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
(#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT()
to disable the interrupt too.
(#) De-initialize the comparator using HAL_COMP_DeInit() function.
(#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
The only way to unlock the comparator is a device hardware reset.
*** Callback registration ***
=============================================
[..]
@ -240,14 +240,14 @@
* @{
*/
/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and de-initialization functions.
/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and de-initialization functions.
*
@verbatim
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions to initialize and de-initialize comparators
[..] This section provides functions to initialize and de-initialize comparators
@endverbatim
* @{
@ -269,7 +269,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
__IO uint32_t wait_loop_index = 0UL;
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
if(hcomp == NULL)
{
@ -288,7 +288,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
assert_param(IS_COMP_BLANKINGSRCE(hcomp->Init.BlankingSrce));
assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
@ -296,10 +296,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
/* Allocate lock resource and initialize it */
hcomp->Lock = HAL_UNLOCKED;
/* Set COMP error code to none */
COMP_CLEAR_ERRORCODE(hcomp);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Init the COMP Callback settings */
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
@ -308,7 +308,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
}
/* Init the low level hardware */
hcomp->MspInitCallback(hcomp);
#else
@ -326,16 +326,16 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
/* Set HYST bits according to hcomp->Init.Hysteresis value */
/* Set POLARITY bit according to hcomp->Init.OutputPol value */
/* Set POWERMODE bits according to hcomp->Init.Mode value */
tmp_csr = (hcomp->Init.InvertingInput | \
hcomp->Init.NonInvertingInput | \
hcomp->Init.BlankingSrce | \
hcomp->Init.Hysteresis | \
hcomp->Init.OutputPol | \
hcomp->Init.Mode );
/* Set parameters in COMP register */
/* Note: Update all bits except read-only, lock and enable bits */
/* Note: Update all bits except read-only, lock and enable bits */
MODIFY_REG(hcomp->Instance->CFGR,
COMP_CFGRx_PWRMODE | COMP_CFGRx_INMSEL | COMP_CFGRx_INPSEL |
COMP_CFGRx_WINMODE | COMP_CFGRx_POLARITY | COMP_CFGRx_HYST |
@ -374,9 +374,9 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
/* Get the EXTI line corresponding to the selected COMP instance */
exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
/* Manage EXTI settings */
if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
{
/* Configure EXTI rising edge */
if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
@ -387,7 +387,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
CLEAR_BIT(EXTI->RTSR1, exti_line);
}
/* Configure EXTI falling edge */
if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
{
@ -397,10 +397,11 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
CLEAR_BIT(EXTI->FTSR1, exti_line);
}
#if !defined (DUAL_CORE)
/* Clear COMP EXTI pending bit (if any) */
WRITE_REG(EXTI_D1->PR1, exti_line);
/* Configure EXTI event mode */
if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
@ -411,7 +412,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
CLEAR_BIT(EXTI_D1->EMR1, exti_line);
}
/* Configure EXTI interrupt mode */
if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
{
@ -426,26 +427,27 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
/* Disable EXTI event mode */
CLEAR_BIT(EXTI_D1->EMR1, exti_line);
/* Disable EXTI interrupt mode */
CLEAR_BIT(EXTI_D1->IMR1, exti_line);
#endif
}
/* Set HAL COMP handle state */
/* Note: Transition from state reset to state ready, */
/* otherwise (coming from state ready or busy) no state update. */
if (hcomp->State == HAL_COMP_STATE_RESET)
{
hcomp->State = HAL_COMP_STATE_READY;
}
}
return status;
}
/**
* @brief DeInitialize the COMP peripheral.
* @brief DeInitialize the COMP peripheral.
* @note Deinitialization cannot be performed if the COMP configuration is locked.
* To unlock the configuration, perform a system reset.
* @param hcomp COMP handle
@ -477,7 +479,7 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
{
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
}
/* DeInit the low level hardware */
hcomp->MspDeInitCallback(hcomp);
#else
@ -487,11 +489,11 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
/* Set HAL COMP handle state */
hcomp->State = HAL_COMP_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hcomp);
}
return status;
}
@ -540,7 +542,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL)
{
/* Update the error code */
@ -548,7 +550,7 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_
return HAL_ERROR;
}
if (HAL_COMP_STATE_READY == hcomp->State)
{
switch (CallbackID)
@ -556,19 +558,19 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_
case HAL_COMP_TRIGGER_CB_ID :
hcomp->TriggerCallback = pCallback;
break;
case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = pCallback;
break;
case HAL_COMP_MSPDEINIT_CB_ID :
hcomp->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
@ -581,15 +583,15 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_
case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = pCallback;
break;
case HAL_COMP_MSPDEINIT_CB_ID :
hcomp->MspDeInitCallback = pCallback;
break;
default :
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
break;
@ -599,11 +601,11 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_
{
/* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */
status = HAL_ERROR;
}
return status;
}
@ -630,7 +632,7 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM
case HAL_COMP_TRIGGER_CB_ID :
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
break;
case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
break;
@ -686,13 +688,13 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM
* @}
*/
/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
* @brief Start-Stop operation functions.
/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
* @brief Start-Stop operation functions.
*
@verbatim
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
===============================================================================
[..] This section provides functions allowing to:
(+) Start a Comparator instance without interrupt.
(+) Stop a Comparator instance without interrupt.
@ -704,16 +706,16 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM
*/
/**
* @brief Start the comparator.
* @brief Start the comparator.
* @param hcomp COMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
{
{
__IO uint32_t wait_loop_index = 0UL;
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
if(hcomp == NULL)
{
@ -740,12 +742,12 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL)));
while(wait_loop_index != 0UL)
{
wait_loop_index--;
}
}
}
else
{
@ -757,14 +759,14 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
}
/**
* @brief Stop the comparator.
* @brief Stop the comparator.
* @param hcomp COMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
{
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
if(hcomp == NULL)
{
@ -795,7 +797,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
status = HAL_ERROR;
}
}
return status;
}
@ -805,11 +807,11 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
{
{
__IO uint32_t wait_loop_index = 0UL;
HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */
if(hcomp == NULL)
{
@ -832,7 +834,7 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
/* Enable the Interrupt comparator */
SET_BIT(hcomp->Instance->CFGR, COMP_CFGRx_ITEN);
hcomp->State = HAL_COMP_STATE_BUSY;
hcomp->State = HAL_COMP_STATE_BUSY;
/* Delay for COMP startup time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
@ -855,28 +857,28 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
}
/**
* @brief Disable the interrupt and Stop the comparator.
* @brief Disable the interrupt and Stop the comparator.
* @param hcomp COMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
{
{
HAL_StatusTypeDef status;
#if !defined (DUAL_CORE)
/* Disable the EXTI Line interrupt mode */
CLEAR_BIT(EXTI_D1->IMR1, COMP_GET_EXTI_LINE(hcomp->Instance));
/* Disable the Interrupt comparator */
#endif
/* Disable the Interrupt comparator */
CLEAR_BIT(hcomp->Instance->CFGR, COMP_CFGRx_ITEN);
status = HAL_COMP_Stop(hcomp);
return status;
}
/**
* @brief Comparator IRQ Handler.
* @brief Comparator IRQ Handler.
* @param hcomp COMP handle
* @retval HAL status
*/
@ -884,10 +886,15 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
{
/* Get the EXTI line corresponding to the selected COMP instance */
uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
#if defined(DUAL_CORE)
/* EXTI line interrupt detected */
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Check COMP EXTI flag */
if(READ_BIT(EXTI_D1->PR1, exti_line) != 0UL)
{
{
/* Check whether comparator is in independent or window mode */
if(READ_BIT(COMP12_COMMON->CFGR, COMP_CFGRx_WINMODE) != 0UL)
{
@ -914,6 +921,72 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
}
else
{
/* Check COMP EXTI flag */
if(READ_BIT(EXTI_D2->PR1, exti_line) != 0UL)
{
/* Check whether comparator is in independent or window mode */
if(READ_BIT(COMP12_COMMON->CFGR, COMP_CFGRx_WINMODE) != 0UL)
{
/* Clear COMP EXTI line pending bit of the pair of comparators */
/* in window mode. */
/* Note: Pair of comparators in window mode can both trig IRQ when */
/* input voltage is changing from "out of window" area */
/* (low or high ) to the other "out of window" area (high or low).*/
/* Both flags must be cleared to call comparator trigger */
/* callback is called once. */
WRITE_REG(EXTI_D2->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
}
else
{
/* Clear COMP EXTI line pending bit */
WRITE_REG(EXTI_D2->PR1, exti_line);
}
/* COMP trigger user callback */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
hcomp->TriggerCallback(hcomp);
#else
HAL_COMP_TriggerCallback(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
}
#else
/* Check COMP EXTI flag */
if(READ_BIT(EXTI_D1->PR1, exti_line) != 0UL)
{
/* Check whether comparator is in independent or window mode */
if(READ_BIT(COMP12_COMMON->CFGR, COMP_CFGRx_WINMODE) != 0UL)
{
/* Clear COMP EXTI line pending bit of the pair of comparators */
/* in window mode. */
/* Note: Pair of comparators in window mode can both trig IRQ when */
/* input voltage is changing from "out of window" area */
/* (low or high ) to the other "out of window" area (high or low).*/
/* Both flags must be cleared to call comparator trigger */
/* callback is called once. */
WRITE_REG(EXTI_D1->PR1, (COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
}
else
{
/* Clear COMP EXTI line pending bit */
WRITE_REG(EXTI_D1->PR1, exti_line);
}
/* COMP trigger user callback */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
hcomp->TriggerCallback(hcomp);
#else
HAL_COMP_TriggerCallback(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
#endif /*DUAL_CORE*/
/* Get COMP interrupt source */
if (__HAL_COMP_GET_IT_SOURCE(hcomp, COMP_IT_EN) != RESET)
{
@ -922,19 +995,19 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
{
/* Clear the COMP channel 1 interrupt flag */
__HAL_COMP_CLEAR_C1IFLAG();
/* Disable COMP interrupt */
__HAL_COMP_DISABLE_IT(hcomp,COMP_IT_EN);
}
if((__HAL_COMP_GET_FLAG( COMP_FLAG_C2I)) != 0UL)
{
/* Clear the COMP channel 2 interrupt flag */
__HAL_COMP_CLEAR_C2IFLAG();
/* Disable COMP interrupt */
__HAL_COMP_DISABLE_IT(hcomp,COMP_IT_EN);
}
/* Change COMP state */
@ -946,8 +1019,8 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
#else
HAL_COMP_TriggerCallback(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
}
}
@ -955,13 +1028,13 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
* @}
*/
/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
* @brief Management functions.
*
@verbatim
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
===============================================================================
[..]
This subsection provides a set of functions allowing to control the comparators.
@ -971,7 +1044,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
/**
* @brief Lock the selected comparator configuration.
* @note A system reset is required to unlock the comparator configuration.
* @note A system reset is required to unlock the comparator configuration.
* @param hcomp COMP handle
* @retval HAL status
*/
@ -992,7 +1065,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
{
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
/* Set HAL COMP handle state */
switch(hcomp->State)
{
@ -1007,18 +1080,18 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
break;
}
}
if(status == HAL_OK)
{
/* Set the lock bit corresponding to selected comparator */
__HAL_COMP_LOCK(hcomp);
}
return status;
return status;
}
/**
* @brief Return the output level (high or low) of the selected comparator.
* @brief Return the output level (high or low) of the selected comparator.
* @note The output level depends on the selected polarity.
* If the polarity is not inverted:
* - Comparator output is low when the input plus is at a lower
@ -1031,19 +1104,19 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
* - Comparator output is low when the input plus is at a higher
* voltage than the input minus
* @param hcomp COMP handle
* @retval Returns the selected comparator output level:
* @retval Returns the selected comparator output level:
* @arg @ref COMP_OUTPUT_LEVEL_LOW
* @arg @ref COMP_OUTPUT_LEVEL_HIGH
*
*
*/
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
{
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
if (hcomp->Instance == COMP1)
{
return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL));
return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL));
}
else
{
@ -1070,13 +1143,13 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
* @}
*/
/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions.
/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral.
@ -1113,7 +1186,7 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
{
/* Check the parameters */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
return hcomp->ErrorCode;
}
/**

159
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_comp.h
View File

@ -36,13 +36,13 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Types COMP Exported Types
* @{
*/
/**
* @brief COMP Init structure definition
/**
* @brief COMP Init structure definition
*/
typedef struct
{
@ -91,7 +91,7 @@ typedef enum
HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
}HAL_COMP_StateTypeDef;
/**
/**
* @brief COMP Handle Structure definition
*/
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
@ -138,7 +138,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/** @defgroup COMP_Exported_Constants COMP Exported Constants
* @{
*/
/** @defgroup COMP_Error_Code COMP Error Code
* @{
*/
@ -149,7 +149,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/**
* @}
*/
/** @defgroup COMP_WindowMode COMP Window Mode
* @{
*/
@ -238,7 +238,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/** @defgroup COMP_OutputLevel COMP Output Level
* @{
*/
*/
/* Note: Comparator output level values are fixed to "0" and "1", */
/* corresponding COMP register bit is managed by HAL function to match */
@ -290,17 +290,17 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/** @defgroup COMP_Interrupts_Definitions COMP Interrupts Definitions
* @{
*/
#define COMP_IT_EN COMP_CFGRx_ITEN
#define COMP_IT_EN COMP_CFGRx_ITEN
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup COMP_Exported_Macros COMP Exported Macros
* @{
@ -328,7 +328,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @param __HANDLE__ COMP handle
* @retval None
*/
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
/**
* @brief Enable the specified comparator.
@ -365,41 +365,41 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/**
* @}
*/
/** @defgroup COMP_Exti_Management COMP external interrupt line management
* @{
*/
/**
* @brief Enable the COMP1 EXTI line rising edge trigger.
* @brief Enable the COMP1 EXTI line rising edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line rising edge trigger.
* @brief Disable the COMP1 EXTI line rising edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI line falling edge trigger.
* @brief Enable the COMP1 EXTI line falling edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line falling edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
@ -407,9 +407,9 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/**
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
@ -419,7 +419,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/**
* @brief Enable the COMP1 EXTI line in interrupt mode.
* @retval None
*/
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
/**
@ -469,34 +469,73 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
*/
#define __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
#if defined(DUAL_CORE)
/**
* @brief Enable the COMP1 D2 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 D2 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 D2 EXTI Line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 D2 EXTI Line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Check whether the COMP1 D2 EXTI line flag is set or not.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP1_EXTID2_GET_FLAG() READ_BIT(EXTI_D2->PR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Clear the COMP1 D2 EXTI flag.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTID2_CLEAR_FLAG() WRITE_REG(EXTI_D2->PR1, COMP_EXTI_LINE_COMP1)
#endif
/**
* @brief Enable the COMP2 EXTI line rising edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line rising edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 EXTI line falling edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line falling edge trigger.
* @brief Disable the COMP2 EXTI line falling edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
@ -505,7 +544,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/**
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
@ -513,7 +552,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/**
* @brief Enable the COMP2 EXTI line.
* @retval None
*/
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
/**
@ -564,13 +603,57 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
*/
#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
#if defined(DUAL_CORE)
/**
* @brief Enable the COMP2 D2 EXTI line
* @retval None
*/
#define __HAL_COMP_COMP2_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 D2 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 D2 EXTI Line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 D2 EXTI Line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Check whether the COMP2 D2 EXTI line flag is set or not.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP2_EXTID2_GET_FLAG() READ_BIT(EXTI_D2->PR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Clear the the COMP2 D2 EXTI flag.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTID2_CLEAR_FLAG() WRITE_REG(EXTI_D2->PR1, COMP_EXTI_LINE_COMP2)
#endif
/** @brief Checks if the specified COMP interrupt source is enabled or disabled.
* @param __HANDLE__: specifies the COMP Handle.
* This parameter can be COMP1 where x: 1 or 2 to select the COMP peripheral.
* @param __INTERRUPT__: specifies the COMP interrupt source to check.
* This parameter can be one of the following values:
* @arg COMP_IT_EN: Comparator interrupt enable
*
*
* @retval The new state of __IT__ (TRUE or FALSE)
*/
#define __HAL_COMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CFGR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
@ -582,7 +665,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @arg COMP_FLAG_C2I: Comparator 2 Interrupt Flag
* @retval The new state of __FLAG__ (TRUE or FALSE)
*/
#define __HAL_COMP_GET_FLAG(__FLAG__) ((COMP12->SR & (__FLAG__)) == (__FLAG__))
#define __HAL_COMP_GET_FLAG(__FLAG__) ((COMP12->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified COMP pending flag.
* @param __FLAG__: specifies the flag to check.
@ -636,7 +719,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @arg COMP_OR_AFOPG3 : Alternate Function PG3 source selection
* @arg COMP_OR_AFOPG4 : Alternate Function PG4 source selection
* @arg COMP_OR_AFOPI1 : Alternate Function PI1 source selection
* @arg COMP_OR_AFOPI4 : Alternate Function PI4 source selection
* @arg COMP_OR_AFOPI4 : Alternate Function PI4 source selection
* @arg COMP_OR_AFOPK2 : Alternate Function PK2 source selection
* @retval None
*/
@ -655,7 +738,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @arg COMP_OR_AFOPG4 : Alternate Function PG4 source selection
* @arg COMP_OR_AFOPI1 : Alternate Function PI1 source selection
* @arg COMP_OR_AFOPI4 : Alternate Function PI4 source selection
* @arg COMP_OR_AFOPK2 : Alternate Function PK2 source selection
* @arg COMP_OR_AFOPK2 : Alternate Function PK2 source selection
* @retval None
*/
#define __HAL_COMP_DISABLE_OR(__AF__) CLEAR_BIT(COMP12->OR, (__AF__))
@ -694,7 +777,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/** @defgroup COMP_Private_Macros COMP Private Macros
* @{
*/
/** @defgroup COMP_GET_EXTI_LINE COMP Private macros to get EXTI line associated with Comparators
/** @defgroup COMP_GET_EXTI_LINE COMP Private macros to get EXTI line associated with Comparators
* @{
*/
/**
@ -720,7 +803,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \

16
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_conf.h
View File

@ -46,6 +46,7 @@
#define HAL_DFSDM_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_DMA2D_MODULE_ENABLED
#define HAL_DSI_MODULE_ENABLED
#define HAL_ETH_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_FDCAN_MODULE_ENABLED
@ -133,6 +134,12 @@
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
@ -162,6 +169,7 @@
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
@ -242,6 +250,10 @@
#include "stm32h7xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32h7xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32h7xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
@ -437,11 +449,11 @@
* If expr is true, it returns no value.
* @retval None
*/
//MBED PATCH #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
//MBED PATCH #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
//MBED PATCH void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus

21
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cortex.c
View File

@ -483,6 +483,26 @@ __weak void HAL_SYSTICK_Callback(void)
*/
}
#if defined(DUAL_CORE)
/**
* @brief Returns the current CPU ID.
* @retval CPU identifier
*/
uint32_t HAL_GetCurrentCPUID(void)
{
if (((SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)
{
return CM7_CPUID;
}
else
{
return CM4_CPUID;
}
}
#else
/**
* @brief Returns the current CPU ID.
* @retval CPU identifier
@ -492,6 +512,7 @@ uint32_t HAL_GetCurrentCPUID(void)
return CM7_CPUID;
}
#endif /*DUAL_CORE*/
/**
* @}
*/

16
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cortex.h
View File

@ -237,6 +237,7 @@ typedef struct
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
#if !defined(CORE_CM4)
#define MPU_REGION_NUMBER8 ((uint8_t)0x08)
#define MPU_REGION_NUMBER9 ((uint8_t)0x09)
#define MPU_REGION_NUMBER10 ((uint8_t)0x0A)
@ -245,6 +246,7 @@ typedef struct
#define MPU_REGION_NUMBER13 ((uint8_t)0x0D)
#define MPU_REGION_NUMBER14 ((uint8_t)0x0E)
#define MPU_REGION_NUMBER15 ((uint8_t)0x0F)
#endif /* !defined(CORE_CM4) */
/**
* @}
@ -272,6 +274,9 @@ typedef struct
*/
#define CM7_CPUID ((uint32_t)0x00000003)
#if defined(DUAL_CORE)
#define CM4_CPUID ((uint32_t)0x00000001)
#endif /*DUAL_CORE*/
/**
* @}
*/
@ -374,6 +379,7 @@ uint32_t HAL_GetCurrentCPUID(void);
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#if !defined(CORE_CM4)
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
@ -390,6 +396,16 @@ uint32_t HAL_GetCurrentCPUID(void);
((NUMBER) == MPU_REGION_NUMBER13) || \
((NUMBER) == MPU_REGION_NUMBER14) || \
((NUMBER) == MPU_REGION_NUMBER15))
#else
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#endif /* !defined(CORE_CM4) */
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
((SIZE) == MPU_REGION_SIZE_64B) || \

341
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp.c
View File

@ -441,6 +441,8 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
/* Read Device ID to indicate CRYP1 IP Version */
hcryp->Version = HAL_GetREVID();
/* Reset Error Code field */
hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
@ -1862,12 +1864,12 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
hcryp->CrypInCount++;
hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
if (hcryp->CrypInCount == (hcryp->Size / 4U))
{
/* Disable interruption */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
@ -1895,16 +1897,16 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
{
/* Disable interruption */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
/* Process unlocked */
__HAL_UNLOCK(hcryp);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Call output transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Output complete callback*/
@ -1913,7 +1915,7 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
/*Call legacy weak Output complete callback*/
HAL_CRYP_OutCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
}
@ -2299,22 +2301,41 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
uint32_t npblb;
uint32_t lastwordsize;
uint32_t temp; /* Temporary CrypOutBuff */
uint32_t temp_cr_algodir;
CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable the DMA transfer for output FIFO */
hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
/* Last block transfer in case of GCM or CCM with Size not %16*/
if (((hcryp->Size) % 16U) != 0U)
{
/* set CrypInCount and CrypOutCount to exact number of word already computed via DMA */
hcryp->CrypInCount = (hcryp->Size / 16U) * 4U ;
hcryp->CrypOutCount = hcryp->CrypInCount;
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
if (hcryp->Version >= REV_ID_B)
{
/* Case of AES GCM payload encryption or AES CCM payload decryption to get right tag */
temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Disable the CRYP */
__HAL_CRYP_DISABLE(hcryp);
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
@ -2709,6 +2730,10 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
{
uint32_t tickstart;
uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
uint32_t npblb ;
uint32_t temp ; /* Temporary CrypOutBuff */
uint32_t index ;
uint32_t lastwordsize ;
uint16_t outcount; /* Temporary CrypOutCount Value */
/* Reset CrypHeaderCount */
@ -2770,6 +2795,12 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
/* Disable the CRYP peripheral */
__HAL_CRYP_DISABLE(hcryp);
if (hcryp->Version >= REV_ID_B)
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
}
/* Select payload phase once the header phase is performed */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
@ -2817,7 +2848,88 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
if ((hcryp->Size % 16U) != 0U)
{
CRYP_Workaround(hcryp, Timeout);
if (hcryp->Version >= REV_ID_B)
{
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
/* Set Npblb in case of AES GCM payload encryption to get right tag*/
if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
{
/* Disable the CRYP */
__HAL_CRYP_DISABLE(hcryp);
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* Write the last input block in the IN FIFO */
for (index = 0U; index < lastwordsize; index ++)
{
hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
/* Pad the data with zeros to have a complete block */
while (index < 4U)
{
hcryp->Instance->DIN = 0U;
index++;
}
/* Wait for OFNE flag to be raised */
if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/*Read the output block from the output FIFO */
if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
{
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
hcryp->CrypOutCount++;
}
}
}
else /* Workaround to be used */
{
/* Workaround 2 for STM32H7 below rev.B To generate correct TAG only when size of the last block of
payload is inferior to 128 bits, in case of GCM encryption or CCM decryption*/
CRYP_Workaround(hcryp, Timeout);
} /* end of NPBLB or Workaround*/
}
@ -2958,6 +3070,11 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
/* Disable the CRYP peripheral */
__HAL_CRYP_DISABLE(hcryp);
if (hcryp->Version >= REV_ID_B)
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
}
/* Select payload phase once the header phase is performed */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
@ -2972,7 +3089,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
}
else if (hcryp->Size >= 16U)
{
/* for STM32H7 : Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
/* for STM32H7 below rev.B : Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
Workaround is implemented in polling mode, so if last block of payload <128bit don't use DMA mode otherwise TAG is incorrectly generated */
/*DMA transfer must not include the last block in case of Size is not %16 */
@ -2986,6 +3103,15 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
/* Compute the number of padding bytes in last block of payload */
npblb = 16U - (uint32_t)hcryp->Size;
if (hcryp->Version >= REV_ID_B)
{
/* Set Npblb in case of AES GCM payload encryption to get right tag*/
if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
{
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
}
}
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
@ -3071,6 +3197,10 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
{
uint32_t tickstart;
uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
uint32_t npblb ;
uint32_t lastwordsize ;
uint32_t temp ; /* Temporary CrypOutBuff */
uint32_t index ;
uint16_t outcount; /* Temporary CrypOutCount Value */
/* Reset CrypHeaderCount */
@ -3092,6 +3222,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
if (hcryp->Version >= REV_ID_B)
{
/* for STM32H7 rev.B and above Write B0 packet into CRYP_DR*/
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
}
else /* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
@ -3120,6 +3260,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
}
}
/* Get tick */
tickstart = HAL_GetTick();
@ -3161,6 +3302,12 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
/* Disable the CRYP peripheral */
__HAL_CRYP_DISABLE(hcryp);
if (hcryp->Version >= REV_ID_B)
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
}
/* Select payload phase once the header phase is performed */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
@ -3208,7 +3355,88 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
if ((hcryp->Size % 16U) != 0U)
{
CRYP_Workaround(hcryp, Timeout);
if (hcryp->Version >= REV_ID_B)
{
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
{
/* Disable the CRYP */
__HAL_CRYP_DISABLE(hcryp);
/* Set Npblb in case of AES CCM payload decryption to get right tag */
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
{
lastwordsize = (16U - npblb) / 4U;
}
else
{
lastwordsize = ((16U - npblb) / 4U) + 1U;
}
/* Write the last input block in the IN FIFO */
for (index = 0U; index < lastwordsize; index ++)
{
hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
hcryp->CrypInCount++;
}
/* Pad the data with zeros to have a complete block */
while (index < 4U)
{
hcryp->Instance->DIN = 0U;
index++;
}
/* Wait for OFNE flag to be raised */
if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
{
/* Disable the CRYP peripheral clock */
__HAL_CRYP_DISABLE(hcryp);
/* Change state */
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
hcryp->State = HAL_CRYP_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hcryp);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
hcryp->ErrorCallback(hcryp);
#else
/*Call legacy weak error callback*/
HAL_CRYP_ErrorCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
/*Read the output block from the output FIFO */
if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
{
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
temp = hcryp->Instance->DOUT;
*(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
hcryp->CrypOutCount++;
}
}
}
else /* No NPBLB, Workaround to be used */
{
/* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
is selected, then the TAG message will be wrong.*/
CRYP_Workaround(hcryp, Timeout);
}
}
/* Return function status */
@ -3245,6 +3473,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
__HAL_CRYP_ENABLE(hcryp);
/*Write the B0 packet into CRYP_DR*/
if (hcryp->Version >= REV_ID_B)
{
/* for STM32H7 rev.B and above data has not to be swapped */
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
}
else /* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
@ -3273,6 +3511,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
}
}
/*Wait for the CRYPEN bit to be cleared*/
count = CRYP_TIMEOUT_GCMCCMINITPHASE;
@ -3342,6 +3581,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
/*Write the B0 packet into CRYP_DR*/
if (hcryp->Version >= REV_ID_B)
{
/* for STM32H7 rev.B and above data has not to be swapped */
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
}
else /* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
@ -3370,6 +3619,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
}
}
/*Wait for the CRYPEN bit to be cleared*/
count = CRYP_TIMEOUT_GCMCCMINITPHASE;
do
@ -3405,6 +3655,12 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
/* Disable the CRYP peripheral */
__HAL_CRYP_DISABLE(hcryp);
if (hcryp->Version >= REV_ID_B)
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
}
/* Select payload phase once the header phase is performed */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
@ -3418,7 +3674,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
}
else if (hcryp->Size >= 16U)
{
/* for STM32H7 : Size should be %4 otherwise Tag will be incorrectly generated for CCM Decryption, Workaround is implemented in polling mode*/
/* for STM32H7 below rev.B :: Size should be %4 otherwise Tag will be incorrectly generated for CCM Decryption, Workaround is implemented in polling mode*/
/*DMA transfer must not include the last block in case of Size is not %16 */
wordsize = wordsize - (wordsize % 4U);
@ -3430,6 +3686,15 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
/* Compute the number of padding bytes in last block of payload */
npblb = 16U - (uint32_t)(hcryp->Size);
if (hcryp->Version >= REV_ID_B)
{
/* Set Npblb in case of AES CCM payload decryption to get right tag*/
if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
{
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
}
}
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
@ -3515,7 +3780,8 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
uint32_t temp; /* Temporary CrypOutBuff */
uint32_t lastwordsize;
uint32_t npblb;
uint32_t temp_cr_algodir;
/***************************** Payload phase *******************************/
if (hcryp->Size == 0U)
@ -3529,7 +3795,7 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
}
else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
{
if ((hcryp->Instance->IMSCR & CRYP_IMSCR_INIM)!= 0x0U)
@ -3547,7 +3813,7 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
/* Call the input data transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Input complete callback*/
@ -3557,8 +3823,8 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
if (hcryp->CrypOutCount < (hcryp->Size / 4U))
if (hcryp->CrypOutCount < (hcryp->Size / 4U))
{
if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
{
@ -3579,16 +3845,16 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
{
/* Disable interrupts */
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
/* Change the CRYP state */
hcryp->State = HAL_CRYP_STATE_READY;
/* Disable CRYP */
__HAL_CRYP_DISABLE(hcryp);
/* Process unlocked */
__HAL_UNLOCK(hcryp);
/* Call output transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/*Call registered Output complete callback*/
@ -3609,7 +3875,25 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
{
/* Compute the number of padding bytes in last block of payload */
npblb = ((((uint32_t)hcryp->Size / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
if (hcryp->Version >= REV_ID_B)
{
/* Set Npblb in case of AES GCM payload encryption and CCM decryption to get right tag */
temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Disable the CRYP */
__HAL_CRYP_DISABLE(hcryp);
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
/* Enable CRYP to start the final phase */
__HAL_CRYP_ENABLE(hcryp);
}
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) == 0U)
@ -3968,6 +4252,11 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
/* Disable the CRYP peripheral */
__HAL_CRYP_DISABLE(hcryp);
if (hcryp->Version >= REV_ID_B)
{
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, 0U);
}
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;

1
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp.h
View File

@ -119,6 +119,7 @@ typedef struct
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
uint32_t Version; /*!< CRYP1 IP version*/
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */

25
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_cryp_ex.c
View File

@ -157,6 +157,16 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
/* Write the number of bits in header (64 bits) followed by the number of bits
in the payload */
/* STM32H7 rev.B and above : data has to be inserted normally (no swapping)*/
if (hcryp->Version >= REV_ID_B)
{
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(headerlength);
hcryp->Instance->DIN = 0U;
hcryp->Instance->DIN = (uint32_t)(inputlength);
}
else/* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
{
hcryp->Instance->DIN = 0U;
@ -189,6 +199,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
{
/* Nothing to do */
}
}
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
@ -301,6 +312,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
ctr0[2] = hcryp->Init.B0[2];
ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3;
/*STM32H7 rev.B and above : data has to be inserted normally (no swapping)*/
if (hcryp->Version >= REV_ID_B)
{
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
}
else /* data has to be swapped according to the DATATYPE */
{
if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
{
hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr));
@ -341,6 +365,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
ctr0addr += 4U;
hcryp->Instance->DIN = *(uint32_t *)(ctr0addr);
}
}
/* Wait for OFNE flag to be raised */
tickstart = HAL_GetTick();
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))

44
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dfsdm.c
View File

@ -157,23 +157,26 @@
*** Callback registration ***
=============================
[..]
The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use functions @ref HAL_DFSDM_Channel_RegisterCallback(),
@ref HAL_DFSDM_Filter_RegisterCallback() or
@ref HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
Use functions HAL_DFSDM_Channel_RegisterCallback(),
HAL_DFSDM_Filter_RegisterCallback() or
HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
Function @ref HAL_DFSDM_Channel_RegisterCallback() allows to register
[..]
Function HAL_DFSDM_Channel_RegisterCallback() allows to register
following callbacks:
(+) CkabCallback : DFSDM channel clock absence detection callback.
(+) ScdCallback : DFSDM channel short circuit detection callback.
(+) MspInitCallback : DFSDM channel MSP init callback.
(+) MspDeInitCallback : DFSDM channel MSP de-init callback.
[..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Function @ref HAL_DFSDM_Filter_RegisterCallback() allows to register
[..]
Function HAL_DFSDM_Filter_RegisterCallback() allows to register
following callbacks:
(+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
(+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
@ -182,26 +185,33 @@
(+) ErrorCallback : DFSDM filter error callback.
(+) MspInitCallback : DFSDM filter MSP init callback.
(+) MspDeInitCallback : DFSDM filter MSP de-init callback.
[..]
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
For specific DFSDM filter analog watchdog callback use dedicated register callback:
@ref HAL_DFSDM_Filter_RegisterAwdCallback().
HAL_DFSDM_Filter_RegisterAwdCallback().
Use functions @ref HAL_DFSDM_Channel_UnRegisterCallback() or
@ref HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
[..]
Use functions HAL_DFSDM_Channel_UnRegisterCallback() or
HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
[..]
HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
This function allows to reset following callbacks:
(+) CkabCallback : DFSDM channel clock absence detection callback.
(+) ScdCallback : DFSDM channel short circuit detection callback.
(+) MspInitCallback : DFSDM channel MSP init callback.
(+) MspDeInitCallback : DFSDM channel MSP de-init callback.
@ref HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
[..]
HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
This function allows to reset following callbacks:
(+) RegConvCpltCallback : DFSDM filter regular conversion complete callback.
(+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
@ -211,26 +221,30 @@
(+) MspInitCallback : DFSDM filter MSP init callback.
(+) MspDeInitCallback : DFSDM filter MSP de-init callback.
[..]
For specific DFSDM filter analog watchdog callback use dedicated unregister callback:
@ref HAL_DFSDM_Filter_UnRegisterAwdCallback().
HAL_DFSDM_Filter_UnRegisterAwdCallback().
[..]
By default, after the call of init function and if the state is RESET
all callbacks are reset to the corresponding legacy weak functions:
examples @ref HAL_DFSDM_ChannelScdCallback(), @ref HAL_DFSDM_FilterErrorCallback().
examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak functions in the init and de-init only when these
callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the init and de-init keep and use
the user MspInit/MspDeInit callbacks (registered beforehand)
[..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the init/de-init.
In that case first register the MspInit/MspDeInit user callbacks using
@ref HAL_DFSDM_Channel_RegisterCallback() or
@ref HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
HAL_DFSDM_Channel_RegisterCallback() or
HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
[..]
When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak callbacks are used.

27
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dma.c
View File

@ -734,8 +734,8 @@ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress,
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
/* calculate DMA base and stream number */
DMA_Base_Registers *regs_dma = NULL;
BDMA_Base_Registers *regs_bdma = NULL;
DMA_Base_Registers *regs_dma;
BDMA_Base_Registers *regs_bdma;
const __IO uint32_t *enableRegister;
uint32_t tickstart = HAL_GetTick();
@ -765,7 +765,6 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
((DMA_Stream_TypeDef *)hdma->Instance)->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT);
((DMA_Stream_TypeDef *)hdma->Instance)->FCR &= ~(DMA_IT_FE);
regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
enableRegister = (__IO uint32_t *)(&(((DMA_Stream_TypeDef *)hdma->Instance)->CR));
}
else /* BDMA channel */
@ -773,7 +772,6 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
/* Disable DMA All Interrupts */
((BDMA_Channel_TypeDef *)hdma->Instance)->CCR &= ~(BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE);
regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
enableRegister = (__IO uint32_t *)(&(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR));
}
@ -805,10 +803,12 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
/* Clear all interrupt flags at correct offset within the register */
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
{
regs_dma = (DMA_Base_Registers *)hdma->StreamBaseAddress;
regs_dma->IFCR = 0x3FUL << (hdma->StreamIndex & 0x1FU);
}
else /* BDMA channel */
{
regs_bdma = (BDMA_Base_Registers *)hdma->StreamBaseAddress;
regs_bdma->IFCR = ((BDMA_IFCR_CGIF0) << (hdma->StreamIndex & 0x1FU));
}
@ -843,7 +843,7 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
BDMA_Base_Registers *regs_bdma = NULL;
BDMA_Base_Registers *regs_bdma;
/* Check the DMA peripheral handle */
if(hdma == NULL)
@ -1067,15 +1067,14 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
/* if timeout then abort the current transfer */
if (HAL_DMA_Abort(hdma) == HAL_OK)
{
/*
Note that the Abort function will
- Clear the transfer error flags
- Unlock
- Set the State
*/
}
/* No need to check return value: as in this case we will return HAL_ERROR with HAL_DMA_ERROR_TIMEOUT error code */
(void) HAL_DMA_Abort(hdma);
/*
Note that the Abort function will
- Clear the transfer error flags
- Unlock
- Set the State
*/
return HAL_ERROR;
}

2705
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dsi.c Normal file
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File diff suppressed because it is too large Load Diff

1352
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_dsi.h Normal file
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File diff suppressed because it is too large Load Diff

61
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_eth.c
View File

@ -1214,6 +1214,11 @@ HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTyp
/* No data to be transferred to the application */
return HAL_ERROR;
}
else
{
descidx = dmarxdesclist->FirstAppDesc;
dmarxdesc = (ETH_DMADescTypeDef *)dmarxdesclist->RxDesc[descidx];
}
}
/* Get intermediate descriptors buffers: in case of the Packet is splitted into multi descriptors */
@ -1460,17 +1465,14 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
{
if(__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMACIER_RIE))
{
/* Call this function to update handle fields */
if(HAL_ETH_IsRxDataAvailable(heth) == 1U)
{
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/*Call registered Receive complete callback*/
heth->RxCpltCallback(heth);
/*Call registered Receive complete callback*/
heth->RxCpltCallback(heth);
#else
/* Receive complete callback */
HAL_ETH_RxCpltCallback(heth);
/* Receive complete callback */
HAL_ETH_RxCpltCallback(heth);
#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
}
/* Clear the Eth DMA Rx IT pending bits */
__HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMACSR_RI | ETH_DMACSR_NIS);
@ -1588,8 +1590,43 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
heth->MACLPIEvent = (uint32_t)(0x0U);
}
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* check ETH WAKEUP exti flag */
if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
{
/* Clear ETH WAKEUP Exti pending bit */
__HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/* Call registered WakeUp callback*/
heth->WakeUpCallback(heth);
#else
/* ETH WAKEUP callback */
HAL_ETH_WakeUpCallback(heth);
#endif
}
}
else
{
/* check ETH WAKEUP exti flag */
if(__HAL_ETH_WAKEUP_EXTID2_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
{
/* Clear ETH WAKEUP Exti pending bit */
__HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
/* Call registered WakeUp callback*/
heth->WakeUpCallback(heth);
#else
/* ETH WAKEUP callback */
HAL_ETH_WakeUpCallback(heth);
#endif
}
}
#else
/* check ETH WAKEUP exti flag */
if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != RESET)
if(__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
{
/* Clear ETH WAKEUP Exti pending bit */
__HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE);
@ -1601,6 +1638,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
HAL_ETH_WakeUpCallback(heth);
#endif
}
#endif
}
/**
@ -2827,11 +2865,16 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket
/* only if the packet is splitted into more than one descriptors > 1 */
while (txbuffer->next != NULL)
{
/* Clear the LD bit of previous descriptor */
CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD);
/* Increment current tx descriptor index */
INCR_TX_DESC_INDEX(descidx, 1U);
/* Get current descriptor address */
dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx];
/* Clear the FD bit of new Descriptor */
CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD);
/* Current Tx Descriptor Owned by DMA: cannot be used by the application */
if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN)
{

752
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_eth.h
View File

File diff suppressed because it is too large Load Diff

114
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_exti.c
View File

@ -16,8 +16,8 @@
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt
(++) Event
(++) Interrupt (CORE1 or CORE2 in case of dual core line )
(++) Event (CORE1 or CORE2 in case of dual core line )
(++) a combination of the previous
(+) Configurable Exti lines can be configured with 3 different triggers
@ -284,6 +284,45 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
/* Store event mode */
*regaddr = regval;
#if defined (DUAL_CORE)
/* Configure interrupt mode for Core2 : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_CORE2_INTERRUPT) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* The event mode cannot be configured if the line does not support it */
assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != EXTI_MODE_CORE2_EVENT));
/* Configure event mode : read current mode */
regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_CORE2_EVENT) != 0x00U)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
#endif /* DUAL_CORE */
/* Configure the D3 PendClear source in case of Wakeup target is Any */
if ((pExtiConfig->Line & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL)
{
@ -380,6 +419,26 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
{
pExtiConfig->Mode |= EXTI_MODE_EVENT;
}
#if defined (DUAL_CORE)
regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Mode = EXTI_MODE_CORE2_INTERRUPT;
}
/* Get event mode */
regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00U)
{
pExtiConfig->Mode |= EXTI_MODE_CORE2_EVENT;
}
#endif /*DUAL_CORE*/
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00U)
@ -500,6 +559,18 @@ HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
regval = (*regaddr & ~maskline);
*regaddr = regval;
#if defined (DUAL_CORE)
/* 1] Clear CM4 interrupt mode */
regaddr = (__IO uint32_t *)(&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
/* 2] Clear CM4 event mode */
regaddr = (__IO uint32_t *)(&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
#endif /* DUAL_CORE */
/* 3] Clear triggers in case of configurable lines */
if ((hexti->Line & EXTI_CONFIG) != 0x00U)
{
@ -639,7 +710,20 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
}
else /* Cortex-M4*/
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
}
#else
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
#endif /* DUAL_CORE */
/* Get pending bit */
regval = (*regaddr & maskline);
@ -685,7 +769,20 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1UL << linepos);
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
}
else /* Cortex-M4 */
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
}
#else
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
#endif /* DUAL_CORE */
/* return 1 if bit is set else 0 */
regval = ((*regaddr & maskline) >> linepos);
@ -717,7 +814,20 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1UL << (hexti->Line & EXTI_PIN_MASK));
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
}
else /* Cortex-M4 */
{
/* Get pending register address */
regaddr = (__IO uint32_t *)(&EXTI->C2PR1 + (EXTI_MODE_OFFSET * offset));
}
#else
regaddr = (__IO uint32_t *)(&EXTI->PR1 + (EXTI_MODE_OFFSET * offset));
#endif /* DUAL_CORE */
/* Clear Pending bit */
*regaddr = maskline;

35
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_exti.h
View File

@ -169,15 +169,27 @@ typedef struct
#define EXTI_LINE_76 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
#define EXTI_LINE_77 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)
#if defined (DUAL_CORE)
#define EXTI_LINE_78 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU)
#else
#define EXTI_LINE_78 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
#endif /* DUAL_CORE */
#define EXTI_LINE_79 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU)
#if defined (DUAL_CORE)
#define EXTI_LINE_80 (EXTI_DIRECT | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U)
#else
#define EXTI_LINE_80 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)
#endif /* DUAL_CORE */
#define EXTI_LINE_81 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U)
#if defined (DUAL_CORE)
#define EXTI_LINE_82 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U)
#else
#define EXTI_LINE_82 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U)
#endif /* DUAL_CORE */
#define EXTI_LINE_83 (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)
#define EXTI_LINE_84 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U)
@ -195,6 +207,12 @@ typedef struct
#define EXTI_MODE_NONE 0x00000000U
#define EXTI_MODE_INTERRUPT 0x00000001U
#define EXTI_MODE_EVENT 0x00000002U
#if defined(DUAL_CORE)
#define EXTI_MODE_CORE1_INTERRUPT EXTI_MODE_INTERRUPT
#define EXTI_MODE_CORE1_EVENT EXTI_MODE_EVENT
#define EXTI_MODE_CORE2_INTERRUPT 0x00000010U
#define EXTI_MODE_CORE2_EVENT 0x00000020U
#endif /* DUAL_CORE */
/**
* @}
*/
@ -294,14 +312,24 @@ typedef struct
#define EXTI_TARGET_MSK_NONE (0x00UL << EXTI_TARGET_SHIFT)
#define EXTI_TARGET_MSK_D3SRD (0x01UL << EXTI_TARGET_SHIFT)
#define EXTI_TARGET_MSK_CPU1 (0x02UL << EXTI_TARGET_SHIFT)
#if defined (DUAL_CORE)
#define EXTI_TARGET_MSK_CPU2 (0x04UL << EXTI_TARGET_SHIFT)
#define EXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)
#define EXTI_TARGET_MSK_ALL_CPU (EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)
#else
#define EXTI_TARGET_MASK (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1)
#define EXTI_TARGET_MSK_ALL_CPU EXTI_TARGET_MSK_CPU1
#endif /* DUAL_CORE */
#define EXTI_TARGET_MSK_ALL EXTI_TARGET_MASK
/**
* @brief EXTI Mask for interrupt & event mode
*/
#if defined (DUAL_CORE)
#define EXTI_MODE_MASK (EXTI_MODE_CORE1_EVENT | EXTI_MODE_CORE1_INTERRUPT | EXTI_MODE_CORE2_INTERRUPT | EXTI_MODE_CORE2_EVENT)
#else
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
#endif /* DUAL_CORE */
/**
* @brief EXTI Mask for trigger possibilities
@ -324,8 +352,15 @@ typedef struct
#define IS_EXTI_PROPERTY(__LINE__) ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))
#if defined (DUAL_CORE)
#define IS_EXTI_TARGET(__LINE__) ((((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || \
(((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU2) || \
(((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL_CPU) || \
(((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
#else
#define IS_EXTI_TARGET(__LINE__) ((((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1) || \
(((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))
#endif
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \
IS_EXTI_PROPERTY(__LINE__) && IS_EXTI_TARGET(__LINE__) && \

22
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash.c
View File

@ -186,6 +186,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress,
}
__ISB();
__DSB();
/* Program the 256 bits flash word */
do
@ -196,6 +197,7 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress,
row_index--;
} while (row_index != 0U);
__ISB();
__DSB();
/* Wait for last operation to be completed */
@ -265,22 +267,13 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
}
else
{
/* Set internal variables used by the IRQ handler */
if(IS_FLASH_PROGRAM_ADDRESS_BANK1(FlashAddress))
{
bank = FLASH_BANK_1;
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
}
else
{
bank = FLASH_BANK_2;
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2;
}
pFlash.Address = FlashAddress;
if(bank == FLASH_BANK_1)
{
/* Set internal variables used by the IRQ handler */
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK1;
/* Set PG bit */
SET_BIT(FLASH->CR1, FLASH_CR_PG);
@ -290,6 +283,9 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
}
else
{
/* Set internal variables used by the IRQ handler */
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_BANK2;
/* Set PG bit */
SET_BIT(FLASH->CR2, FLASH_CR_PG);
@ -299,6 +295,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
}
__ISB();
__DSB();
/* Program the 256 bits flash word */
do
@ -309,6 +306,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
row_index--;
} while (row_index != 0U);
__ISB();
__DSB();
}

189
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.c
View File

@ -120,6 +120,10 @@ static void FLASH_OB_GetSecureArea(uint32_t *SecureAreaConfig, uint32_t *SecureA
static void FLASH_CRC_AddSector(uint32_t Sector, uint32_t Bank);
static void FLASH_CRC_SelectAddress(uint32_t CRCStartAddr, uint32_t CRCEndAddr, uint32_t Bank);
#if defined(DUAL_CORE)
static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1);
static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1);
#endif /*DUAL_CORE*/
/**
* @}
*/
@ -439,12 +443,25 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
}
#if defined(DUAL_CORE)
/*CM7 Boot Address configuration*/
if((pOBInit->OptionType & OPTIONBYTE_CM7_BOOTADD) == OPTIONBYTE_CM7_BOOTADD)
{
FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
}
/*CM4 Boot Address configuration*/
if((pOBInit->OptionType & OPTIONBYTE_CM4_BOOTADD) == OPTIONBYTE_CM4_BOOTADD)
{
FLASH_OB_CM4BootAddConfig(pOBInit->CM4BootConfig, pOBInit->CM4BootAddr0, pOBInit->CM4BootAddr1);
}
#else /* Single Core*/
/*Boot Address configuration*/
if((pOBInit->OptionType & OPTIONBYTE_BOOTADD) == OPTIONBYTE_BOOTADD)
{
FLASH_OB_BootAddConfig(pOBInit->BootConfig, pOBInit->BootAddr0, pOBInit->BootAddr1);
}
#endif /*DUAL_CORE*/
/*Bank1 secure area configuration*/
if((pOBInit->OptionType & OPTIONBYTE_SECURE_AREA) == OPTIONBYTE_SECURE_AREA)
{
@ -496,8 +513,14 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
/*Get Boot Address*/
FLASH_OB_GetBootAdd(&(pOBInit->BootAddr0), &(pOBInit->BootAddr1));
#if defined(DUAL_CORE)
pOBInit->OptionType |= OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD;
/*Get CM4 Boot Address*/
FLASH_OB_GetCM4BootAdd(&(pOBInit->CM4BootAddr0), &(pOBInit->CM4BootAddr1));
#else
pOBInit->OptionType |= OPTIONBYTE_BOOTADD;
#endif /*DUAL_CORE*/
}
/**
@ -959,9 +982,40 @@ static void FLASH_OB_RDPConfig(uint32_t RDPLevel)
*/
static uint32_t FLASH_OB_GetRDP(void)
{
return (FLASH->OPTSR_CUR & FLASH_OPTSR_RDP);
uint32_t rdp_level = READ_BIT(FLASH->OPTSR_CUR, FLASH_OPTSR_RDP);
if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2))
{
return (OB_RDP_LEVEL_1);
}
else
{
return rdp_level;
}
}
#if defined(DUAL_CORE)
/**
* @brief Program the FLASH User Option Byte.
*
* @note To configure the user option bytes, the option lock bit OPTLOCK must
* be cleared with the call of the HAL_FLASH_OB_Unlock() function.
*
* @note To validate the user option bytes, the option bytes must be reloaded
* through the call of the HAL_FLASH_OB_Launch() function.
*
* @param UserType The FLASH User Option Bytes to be modified :
* a combination of @ref FLASHEx_OB_USER_Type
*
* @param UserConfig The FLASH User Option Bytes values:
* IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
* FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
* SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
* nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
*
* @retval HAL status
*/
#else
/**
* @brief Program the FLASH User Option Byte.
*
@ -981,7 +1035,7 @@ static uint32_t FLASH_OB_GetRDP(void)
*
* @retval HAL status
*/
#endif /*DUAL_CORE*/
static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
{
uint32_t optr_reg_val = 0;
@ -999,7 +1053,17 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG1_SW);
optr_reg_mask |= FLASH_OPTSR_IWDG1_SW;
}
#if defined(DUAL_CORE)
if((UserType & OB_USER_IWDG2_SW) != 0U)
{
/* IWDG2_SW option byte should be modified */
assert_param(IS_OB_IWDG2_SOURCE(UserConfig & FLASH_OPTSR_IWDG2_SW));
/* Set value and mask for IWDG2_SW option byte */
optr_reg_val |= (UserConfig & FLASH_OPTSR_IWDG2_SW);
optr_reg_mask |= FLASH_OPTSR_IWDG2_SW;
}
#endif /*DUAL_CORE*/
if((UserType & OB_USER_NRST_STOP_D1) != 0U)
{
/* NRST_STOP option byte should be modified */
@ -1060,7 +1124,47 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
optr_reg_mask |= FLASH_OPTSR_SECURITY;
}
#if defined(DUAL_CORE)
if((UserType & OB_USER_BCM4) != 0U)
{
/* BCM4 option byte should be modified */
assert_param(IS_OB_USER_BCM4(UserConfig & FLASH_OPTSR_BCM4));
/* Set value and mask for BCM4 option byte */
optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM4);
optr_reg_mask |= FLASH_OPTSR_BCM4;
}
if((UserType & OB_USER_BCM7) != 0U)
{
/* BCM7 option byte should be modified */
assert_param(IS_OB_USER_BCM7(UserConfig & FLASH_OPTSR_BCM7));
/* Set value and mask for BCM7 option byte */
optr_reg_val |= (UserConfig & FLASH_OPTSR_BCM7);
optr_reg_mask |= FLASH_OPTSR_BCM7;
}
if((UserType & OB_USER_NRST_STOP_D2) != 0U)
{
/* NRST_STOP option byte should be modified */
assert_param(IS_OB_STOP_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STOP_D2));
/* Set value and mask for NRST_STOP option byte */
optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STOP_D2);
optr_reg_mask |= FLASH_OPTSR_NRST_STOP_D2;
}
if((UserType & OB_USER_NRST_STDBY_D2) != 0U)
{
/* NRST_STDBY option byte should be modified */
assert_param(IS_OB_STDBY_D2_RESET(UserConfig & FLASH_OPTSR_NRST_STBY_D2));
/* Set value and mask for NRST_STDBY option byte */
optr_reg_val |= (UserConfig & FLASH_OPTSR_NRST_STBY_D2);
optr_reg_mask |= FLASH_OPTSR_NRST_STBY_D2;
}
#endif /*DUAL_CORE*/
if((UserType & OB_USER_SWAP_BANK) != 0U)
{
/* SWAP_BANK_OPT option byte should be modified */
@ -1085,6 +1189,16 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
MODIFY_REG(FLASH->OPTSR_PRG, optr_reg_mask, optr_reg_val);
}
#if defined(DUAL_CORE)
/**
* @brief Return the FLASH User Option Byte value.
* @retval The FLASH User Option Bytes values
* IWDG1_SW(Bit4), IWDG2_SW(Bit 5), nRST_STOP_D1(Bit 6), nRST_STDY_D1(Bit 7),
* FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
* SECURITY(Bit 21), BCM4(Bit 22), BCM7(Bit 23), nRST_STOP_D2(Bit 24),
* nRST_STDY_D2(Bit 25), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
*/
#else
/**
* @brief Return the FLASH User Option Byte value.
* @retval The FLASH User Option Bytes values
@ -1092,6 +1206,7 @@ static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
* FZ_IWDG_STOP(Bit 17), FZ_IWDG_SDBY(Bit 18), ST_RAM_SIZE(Bit[19:20]),
* SECURITY(Bit 21), IO_HSLV (Bit 29) and SWAP_BANK_OPT(Bit 31).
*/
#endif /*DUAL_CORE*/
static uint32_t FLASH_OB_GetUser(void)
{
uint32_t userConfig = READ_REG(FLASH->OPTSR_CUR);
@ -1250,7 +1365,11 @@ static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, u
assert_param(IS_BOOT_ADDRESS(BootAddress0));
/* Configure CM7 BOOT ADD0 */
#if defined(DUAL_CORE)
MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD0, (BootAddress0 >> 16));
#else /* Single Core*/
MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD0, (BootAddress0 >> 16));
#endif /* DUAL_CORE */
}
if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
@ -1259,7 +1378,11 @@ static void FLASH_OB_BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, u
assert_param(IS_BOOT_ADDRESS(BootAddress1));
/* Configure CM7 BOOT ADD1 */
#if defined(DUAL_CORE)
MODIFY_REG(FLASH->BOOT7_PRG, FLASH_BOOT7_BCM7_ADD1, BootAddress1);
#else /* Single Core*/
MODIFY_REG(FLASH->BOOT_PRG, FLASH_BOOT_ADD1, BootAddress1);
#endif /* DUAL_CORE */
}
}
@ -1273,12 +1396,72 @@ static void FLASH_OB_GetBootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
{
uint32_t regvalue;
#if defined(DUAL_CORE)
regvalue = FLASH->BOOT7_CUR;
(*BootAddress0) = (regvalue & FLASH_BOOT7_BCM7_ADD0) << 16;
(*BootAddress1) = (regvalue & FLASH_BOOT7_BCM7_ADD1);
#else /* Single Core */
regvalue = FLASH->BOOT_CUR;
(*BootAddress0) = (regvalue & FLASH_BOOT_ADD0) << 16;
(*BootAddress1) = (regvalue & FLASH_BOOT_ADD1);
#endif /* DUAL_CORE */
}
#if defined(DUAL_CORE)
/**
* @brief Set CM4 Boot address
* @param BootOption Boot address option byte to be programmed,
* This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION
(OB_BOOT_ADD0, OB_BOOT_ADD1 or OB_BOOT_ADD_BOTH)
*
* @param BootAddress0 Specifies the CM4 Boot Address 0.
* @param BootAddress1 Specifies the CM4 Boot Address 1.
* @retval HAL Status
*/
static void FLASH_OB_CM4BootAddConfig(uint32_t BootOption, uint32_t BootAddress0, uint32_t BootAddress1)
{
/* Check the parameters */
assert_param(IS_OB_BOOT_ADD_OPTION(BootOption));
if((BootOption & OB_BOOT_ADD0) == OB_BOOT_ADD0)
{
/* Check the parameters */
assert_param(IS_BOOT_ADDRESS(BootAddress0));
/* Configure CM4 BOOT ADD0 */
MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD0, (BootAddress0 >> 16));
}
if((BootOption & OB_BOOT_ADD1) == OB_BOOT_ADD1)
{
/* Check the parameters */
assert_param(IS_BOOT_ADDRESS(BootAddress1));
/* Configure CM4 BOOT ADD1 */
MODIFY_REG(FLASH->BOOT4_PRG, FLASH_BOOT4_BCM4_ADD1, BootAddress1);
}
}
/**
* @brief Get CM4 Boot address
* @param BootAddress0 Specifies the CM4 Boot Address 0.
* @param BootAddress1 Specifies the CM4 Boot Address 1.
* @retval HAL Status
*/
static void FLASH_OB_GetCM4BootAdd(uint32_t *BootAddress0, uint32_t *BootAddress1)
{
uint32_t regvalue;
regvalue = FLASH->BOOT4_CUR;
(*BootAddress0) = (regvalue & FLASH_BOOT4_BCM4_ADD0) << 16;
(*BootAddress1) = (regvalue & FLASH_BOOT4_BCM4_ADD1);
}
#endif /*DUAL_CORE*/
/**
* @brief Set secure area configuration
* @param SecureAreaConfig specify if the secure area will be deleted or not

95
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_flash_ex.h
View File

@ -111,6 +111,17 @@ typedef struct
uint32_t BootAddr1; /*!< Boot Address 1.
This parameter must be a value between begin and end of a bank */
#if defined(DUAL_CORE)
uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1
or both.
This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
uint32_t CM4BootAddr0; /*!< CM4 Boot Address 0.
This parameter must be a value between begin and end of a bank */
uint32_t CM4BootAddr1; /*!< CM4 Boot Address 1.
This parameter must be a value between begin and end of a bank */
#endif /*DUAL_CORE*/
uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not
when RDP level decreased from Level 1 to Level 0 or during a mass erase.
@ -199,7 +210,13 @@ typedef struct
#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */
#define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */
#define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */
#if defined(DUAL_CORE)
#define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */
#define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */
#define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */
#else /* Single core*/
#define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */
#endif /*DUAL_CORE*/
/**
* @}
*/
@ -378,6 +395,26 @@ typedef struct
* @}
*/
#if defined(DUAL_CORE)
/** @defgroup FLASHEx_OB_BCM7 FLASHEx OB BCM7
* @{
*/
#define OB_BCM7_DISABLE 0x00000000U /*!< CM7 Boot disabled */
#define OB_BCM7_ENABLE FLASH_OPTSR_BCM7 /*!< CM7 Boot enabled */
/**
* @}
*/
/** @defgroup FLASHEx_OB_BCM4 FLASHEx OB BCM4
* @{
*/
#define OB_BCM4_DISABLE 0x00000000U /*!< CM4 Boot disabled */
#define OB_BCM4_ENABLE FLASH_OPTSR_BCM4 /*!< CM4 Boot enabled */
/**
* @}
*/
#endif /*DUAL_CORE*/
/** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW
* @{
@ -388,6 +425,16 @@ typedef struct
* @}
*/
#if defined(DUAL_CORE)
/** @defgroup FLASHEx_OB_IWDG2_SW FLASHEx OB IWDG2 SW
* @{
*/
#define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW /*!< Hardware independent watchdog 2*/
#define OB_IWDG2_HW 0x00000000U /*!< Software independent watchdog 2*/
/**
* @}
*/
#endif
/** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1
* @{
@ -407,6 +454,25 @@ typedef struct
* @}
*/
#if defined(DUAL_CORE)
/** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2
* @{
*/
#define OB_STOP_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to stop mode */
#define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */
/**
* @}
*/
/** @defgroup FLASHEx_OB_NRST_STDBY_D2 FLASHEx OB NRST STDBY D2
* @{
*/
#define OB_STDBY_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to standby mode */
#define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */
/**
* @}
*/
#endif
/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK
* @{
@ -448,6 +514,13 @@ typedef struct
#define OB_USER_SECURITY 0x0040U /*!< security selection */
#define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */
#define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */
#if defined(DUAL_CORE)
#define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */
#define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */
#define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */
#define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection*/
#define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection*/
#endif /*DUAL_CORE*/
/**
* @}
@ -598,8 +671,11 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
((VALUE) == OB_WRPSTATE_ENABLE))
#if defined(DUAL_CORE)
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
#else
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
#endif /*DUAL_CORE*/
#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
@ -663,7 +739,9 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
#if defined(DUAL_CORE)
#define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
#endif /*DUAL_CORE*/
#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
@ -677,7 +755,20 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
#if defined(DUAL_CORE)
#define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
#define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
#define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
#define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))
#else
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
#endif
#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \
((VALUE) == OB_BOOT_ADD1) || \

20
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_gpio.c
View File

@ -131,6 +131,10 @@
#define FALLING_EDGE (0x00200000U)
#define GPIO_OUTPUT_TYPE (0x00000010U)
#if defined(DUAL_CORE)
#define EXTI_CPU1 (0x01000000U)
#define EXTI_CPU2 (0x02000000U)
#endif /*DUAL_CORE*/
#define GPIO_NUMBER (16U)
/**
* @}
@ -173,7 +177,11 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
uint32_t temp;
EXTI_Core_TypeDef *EXTI_CurrentCPU;
#if defined(DUAL_CORE) && defined(CORE_CM4)
EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
#else
EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
#endif
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
@ -301,7 +309,11 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
uint32_t tmp;
EXTI_Core_TypeDef *EXTI_CurrentCPU;
#if defined(DUAL_CORE) && defined(CORE_CM4)
EXTI_CurrentCPU = EXTI_D2; /* EXTI for CM4 CPU */
#else
EXTI_CurrentCPU = EXTI_D1; /* EXTI for CM7 CPU */
#endif
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
@ -495,12 +507,20 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
#if defined(DUAL_CORE) && defined(CORE_CM4)
if (__HAL_GPIO_EXTID2_GET_IT(GPIO_Pin) != 0x00U)
{
__HAL_GPIO_EXTID2_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
#else
/* EXTI line interrupt detected */
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00U)
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
#endif
}
/**

34
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_gpio.h
View File

@ -199,6 +199,40 @@ typedef enum
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
#if defined(DUAL_CORE)
/**
* @brief Checks whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__: specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending flags.
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))
#endif
/**
* @brief Generates a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the EXTI line to check.

10
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_gpio_ex.h
View File

@ -54,6 +54,14 @@ extern "C" {
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF0_D2PWREN ((uint8_t)0x00) /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */
#if defined(DUAL_CORE)
#define GPIO_AF0_C2DSLEEP ((uint8_t)0x00) /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#define GPIO_AF0_C2SLEEP ((uint8_t)0x00) /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
#endif /* DUAL_CORE */
/**
* @brief AF 1 selection
@ -176,6 +184,7 @@ extern "C" {
#define GPIO_AF10_COMP1 ((uint8_t)0xA) /* COMP1 Alternate Function mapping */
#define GPIO_AF10_COMP2 ((uint8_t)0xA) /* COMP2 Alternate Function mapping */
#define GPIO_AF10_LTDC ((uint8_t)0xA) /* LTDC Alternate Function mapping */
#define GPIO_AF10_CRS_SYNC ((uint8_t)0xA) /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above */
/**
@ -207,6 +216,7 @@ extern "C" {
* @brief AF 13 selection
*/
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */
#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */
#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */

15
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hash.c
View File

@ -284,15 +284,15 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim
*/
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
{
/* Check the parameters */
assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
/* Check the hash handle allocation */
if(hhash == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
if (hhash->State == HAL_HASH_STATE_RESET)
{
@ -1367,14 +1367,15 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash)
}
/* Disable DMA channel */
if (HAL_DMA_Abort(hhash->hdmain) ==HAL_OK)
{
/*
/*
Note that the Abort function will
- Clear the transfer error flags
- Unlock
- Set the State
*/
*/
if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear DMAE bit */

20
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hcd.c
View File

@ -42,11 +42,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* @attention
*
* <h2><center>&copy; Copyright (c) YYYY STMicroelectronics.
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@ -114,6 +110,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx;
/* Check the HCD handle allocation */
if (hhcd == NULL)
{
@ -123,6 +121,8 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
USBx = hhcd->Instance;
if (hhcd->State == HAL_HCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@ -151,6 +151,12 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
hhcd->State = HAL_HCD_STATE_BUSY;
/* Disable DMA mode for FS instance */
if ((USBx->CID & (0x1U << 8)) == 0U)
{
hhcd->Init.dma_enable = 0U;
}
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
@ -1300,6 +1306,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
(hhcd->hc[ch_num].ep_type == EP_TYPE_BULK))
{
hhcd->hc[ch_num].ErrCnt = 0U;
if (hhcd->Init.dma_enable == 0U)
{
hhcd->hc[ch_num].state = HC_NAK;
@ -1419,7 +1426,8 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum)
if (hhcd->hc[ch_num].state == HC_XFRC)
{
hhcd->hc[ch_num].urb_state = URB_DONE;
if (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) ||
(hhcd->hc[ch_num].ep_type == EP_TYPE_INTR))
{
hhcd->hc[ch_num].toggle_out ^= 1U;
}

7
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hcd.h
View File

@ -108,9 +108,10 @@ typedef struct
/** @defgroup HCD_Speed HCD Speed
* @{
*/
#define HCD_SPEED_HIGH 0U
#define HCD_SPEED_LOW 2U
#define HCD_SPEED_FULL 3U
#define HCD_SPEED_HIGH USBH_HS_SPEED
#define HCD_SPEED_FULL USBH_FS_SPEED
#define HCD_SPEED_LOW USBH_LS_SPEED
/**
* @}
*/

1
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.c
View File

@ -7849,7 +7849,6 @@ static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
/* Set the output set/reset crossbar */
hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
shift = 0U;
break;
}

52
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hrtim.h
View File

@ -171,7 +171,8 @@ typedef struct
/**
* @brief Simple output compare mode configuration definition
*/
typedef struct {
typedef struct
{
uint32_t Period; /*!< Specifies the timer period.
The period value must be above 3 periods of the fHRTIM clock.
Maximum value is = 0xFFDFU */
@ -186,7 +187,8 @@ typedef struct {
/**
* @brief Simple output compare mode configuration definition
*/
typedef struct {
typedef struct
{
uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive).
This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
@ -200,7 +202,8 @@ typedef struct {
/**
* @brief Simple PWM output mode configuration definition
*/
typedef struct {
typedef struct
{
uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
The compare value must be above or equal to 3 periods of the fHRTIM clock */
uint32_t Polarity; /*!< Specifies the output polarity.
@ -212,7 +215,8 @@ typedef struct {
/**
* @brief Simple capture mode configuration definition
*/
typedef struct {
typedef struct
{
uint32_t Event; /*!< Specifies the external event triggering the capture.
This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
@ -226,7 +230,8 @@ typedef struct {
/**
* @brief Simple One Pulse mode configuration definition
*/
typedef struct {
typedef struct
{
uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
The compare value must be above or equal to 3 periods of the fHRTIM clock */
uint32_t OutputPolarity; /*!< Specifies the output polarity.
@ -246,7 +251,8 @@ typedef struct {
/**
* @brief Timer configuration definition
*/
typedef struct {
typedef struct
{
uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master.
Specifies which interrupts requests must enabled for the timer.
This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
@ -315,7 +321,8 @@ typedef struct {
/**
* @brief Compare unit configuration definition
*/
typedef struct {
typedef struct
{
uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit.
The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
@ -328,7 +335,8 @@ typedef struct {
/**
* @brief Capture unit configuration definition
*/
typedef struct {
typedef struct
{
uint32_t Trigger; /*!< Specifies source(s) triggering the capture.
This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
} HRTIM_CaptureCfgTypeDef;
@ -336,7 +344,8 @@ typedef struct {
/**
* @brief Output configuration definition
*/
typedef struct {
typedef struct
{
uint32_t Polarity; /*!< Specifies the output polarity.
This parameter can be any value of @ref HRTIM_Output_Polarity */
uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
@ -358,7 +367,8 @@ typedef struct {
/**
* @brief External event filtering in timing units configuration definition
*/
typedef struct {
typedef struct
{
uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit.
This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
uint32_t Latch; /*!< Specifies whether or not the signal is latched.
@ -368,7 +378,8 @@ typedef struct {
/**
* @brief Dead time feature configuration definition
*/
typedef struct {
typedef struct
{
uint32_t Prescaler; /*!< Specifies the dead-time prescaler.
This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
uint32_t RisingValue; /*!< Specifies the dead-time following a rising edge.
@ -387,12 +398,13 @@ typedef struct {
This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
uint32_t FallingSignLock; /*!< Specifies whether or not dead-time falling sign is write protected.
This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
} HRTIM_DeadTimeCfgTypeDef ;
} HRTIM_DeadTimeCfgTypeDef;
/**
* @brief Chopper mode configuration definition
*/
typedef struct {
typedef struct
{
uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
This parameter can be a value of @ref HRTIM_Chopper_Frequency */
uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
@ -404,7 +416,8 @@ typedef struct {
/**
* @brief External event channel configuration definition
*/
typedef struct {
typedef struct
{
uint32_t Source; /*!< Identifies the source of the external event.
This parameter can be a value of @ref HRTIM_External_Event_Sources */
uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
@ -420,7 +433,8 @@ typedef struct {
/**
* @brief Fault channel configuration definition
*/
typedef struct {
typedef struct
{
uint32_t Source; /*!< Identifies the source of the fault.
This parameter can be a value of @ref HRTIM_Fault_Sources */
uint32_t Polarity; /*!< Specifies the polarity of the fault event.
@ -434,7 +448,8 @@ typedef struct {
/**
* @brief Burst mode configuration definition
*/
typedef struct {
typedef struct
{
uint32_t Mode; /*!< Specifies the burst mode operating mode.
This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
uint32_t ClockSource; /*!< Specifies the burst mode clock source.
@ -454,7 +469,8 @@ typedef struct {
/**
* @brief ADC trigger configuration definition
*/
typedef struct {
typedef struct
{
uint32_t UpdateSource; /*!< Specifies the ADC trigger update source.
This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source */
uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion.
@ -1684,7 +1700,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!<
/** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
* @{
* @brief Constants defining the events that can be used tor trig the burst
* @brief Constants defining the events that can be used to trig the burst
* mode operation
*/
#define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */

88
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hsem.c
View File

@ -10,7 +10,7 @@
* + Semaphore Status check
* + Semaphore Clear Key Set and Get
* + Release and release all functions
* + Semaphore notification enabling and disabling and callback functions
* + Semaphore notification enabling and disabling and callnack functions
* + IRQ handler management
*
*
@ -100,6 +100,19 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#if defined(DUAL_CORE)
#ifndef HSEM_R_MASTERID
#define HSEM_R_MASTERID HSEM_R_COREID
#endif
#ifndef HSEM_RLR_MASTERID
#define HSEM_RLR_MASTERID HSEM_RLR_COREID
#endif
#ifndef HSEM_CR_MASTERID
#define HSEM_CR_MASTERID HSEM_CR_COREID
#endif
#endif /* DUAL_CORE */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@ -141,6 +154,17 @@ HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
assert_param(IS_HSEM_SEMID(SemID));
assert_param(IS_HSEM_PROCESSID(ProcessID));
#if USE_MULTI_CORE_SHARED_CODE != 0U
/* First step write R register with MasterID, processID and take bit=1*/
HSEM->R[SemID] = ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK);
/* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
if (HSEM->R[SemID] == ((ProcessID & HSEM_R_PROCID) | ((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_R_MASTERID) | HSEM_R_LOCK))
{
/*take success when MasterID and ProcessID match and take bit set*/
return HAL_OK;
}
#else
/* First step write R register with MasterID, processID and take bit=1*/
HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
@ -150,6 +174,7 @@ HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
/*take success when MasterID and ProcessID match and take bit set*/
return HAL_OK;
}
#endif
/* Semaphore take fails*/
return HAL_ERROR;
@ -165,12 +190,21 @@ HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
/* Check the parameters */
assert_param(IS_HSEM_SEMID(SemID));
#if USE_MULTI_CORE_SHARED_CODE != 0U
/* Read the RLR register to take the semaphore */
if (HSEM->RLR[SemID] == (((HAL_GetCurrentCPUID() << POSITION_VAL(HSEM_R_MASTERID)) & HSEM_RLR_MASTERID) | HSEM_RLR_LOCK))
{
/*take success when MasterID match and take bit set*/
return HAL_OK;
}
#else
/* Read the RLR register to take the semaphore */
if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
{
/*take success when MasterID match and take bit set*/
return HAL_OK;
}
#endif
/* Semaphore take fails */
return HAL_ERROR;
@ -282,7 +316,21 @@ uint32_t HAL_HSEM_GetClearKey(void)
*/
void HAL_HSEM_ActivateNotification(uint32_t SemMask)
{
#if USE_MULTI_CORE_SHARED_CODE != 0U
/*enable the semaphore mask interrupts */
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
{
/*Use interrupt line 0 for CPU1 Master */
HSEM->C1IER |= SemMask;
}
else /* HSEM_CPU2_COREID */
{
/*Use interrupt line 1 for CPU2 Master*/
HSEM->C2IER |= SemMask;
}
#else
HSEM_COMMON->IER |= SemMask;
#endif
}
/**
@ -292,7 +340,21 @@ void HAL_HSEM_ActivateNotification(uint32_t SemMask)
*/
void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
{
#if USE_MULTI_CORE_SHARED_CODE != 0U
/*enable the semaphore mask interrupts */
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
{
/*Use interrupt line 0 for CPU1 Master */
HSEM->C1IER &= ~SemMask;
}
else /* HSEM_CPU2_COREID */
{
/*Use interrupt line 1 for CPU2 Master*/
HSEM->C2IER &= ~SemMask;
}
#else
HSEM_COMMON->IER &= ~SemMask;
#endif
}
/**
@ -302,7 +364,30 @@ void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
void HAL_HSEM_IRQHandler(void)
{
uint32_t statusreg;
#if USE_MULTI_CORE_SHARED_CODE != 0U
if (HAL_GetCurrentCPUID() == HSEM_CPU1_COREID)
{
/* Get the list of masked freed semaphores*/
statusreg = HSEM->C1MISR; /*Use interrupt line 0 for CPU1 Master*/
/*Disable Interrupts*/
HSEM->C1IER &= ~((uint32_t)statusreg);
/*Clear Flags*/
HSEM->C1ICR = ((uint32_t)statusreg);
}
else /* HSEM_CPU2_COREID */
{
/* Get the list of masked freed semaphores*/
statusreg = HSEM->C2MISR;/*Use interrupt line 1 for CPU2 Master*/
/*Disable Interrupts*/
HSEM->C2IER &= ~((uint32_t)statusreg);
/*Clear Flags*/
HSEM->C2ICR = ((uint32_t)statusreg);
}
#else
/* Get the list of masked freed semaphores*/
statusreg = HSEM_COMMON->MISR;
@ -312,6 +397,7 @@ void HAL_HSEM_IRQHandler(void)
/*Clear Flags*/
HSEM_COMMON->ICR = ((uint32_t)statusreg);
#endif
/* Call FreeCallback */
HAL_HSEM_FreeCallback(statusreg);
}

36
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_hsem.h
View File

@ -53,34 +53,64 @@ extern "C" {
* @param __SEM_MASK__: semaphores Mask
* @retval None.
*/
#if defined(DUAL_CORE)
#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
(HSEM->C1IER |= (__SEM_MASK__)) : \
(HSEM->C2IER |= (__SEM_MASK__)))
#else
#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
#endif /* DUAL_CORE */
/**
* @brief Disables the specified HSEM interrupts.
* @param __SEM_MASK__: semaphores Mask
* @retval None.
*/
#if defined(DUAL_CORE)
#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
(HSEM->C1IER &= ~(__SEM_MASK__)) : \
(HSEM->C2IER &= ~(__SEM_MASK__)))
#else
#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
#endif /* DUAL_CORE */
/**
* @brief Checks whether interrupt has occurred or not for semaphores specified by a mask.
* @param __SEM_MASK__: semaphores Mask
* @retval semaphores Mask : Semaphores where an interrupt occurred.
*/
#if defined(DUAL_CORE)
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
((__SEM_MASK__) & HSEM->C1MISR) : \
((__SEM_MASK__) & HSEM->C2MISR1))
#else
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
#endif /* DUAL_CORE */
/**
* @brief Get the semaphores release status flags.
* @param __SEM_MASK__: semaphores Mask
* @retval semaphores Mask : Semaphores where Release flags rise.
*/
#if defined(DUAL_CORE)
#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
(__SEM_MASK__) & HSEM->C1ISR : \
(__SEM_MASK__) & HSEM->C2ISR)
#else
#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
#endif /* DUAL_CORE */
/**
* @brief Clears the HSEM Interrupt flags.
* @param __SEM_MASK__: semaphores Mask
* @retval None.
*/
#if defined(DUAL_CORE)
#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
(HSEM->C1ICR |= (__SEM_MASK__)) : \
(HSEM->C2ICR |= (__SEM_MASK__)))
#else
#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
#endif /* DUAL_CORE */
/**
* @}
@ -155,7 +185,13 @@ void HAL_HSEM_IRQHandler(void);
#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
#if defined(DUAL_CORE)
#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
((__COREID__) == HSEM_CPU2_COREID))
#else
#define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID)
#endif
/**
* @}

79
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2c.c
View File

@ -223,12 +223,12 @@
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
to register an interrupt callback.
[..]
Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
@ -243,9 +243,9 @@
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
[..]
Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
@ -262,9 +262,9 @@
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
[..]
By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
@ -273,7 +273,7 @@
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
@ -281,7 +281,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
or @ref HAL_I2C_Init() function.
[..]
When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@ -4595,11 +4595,12 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
uint16_t devaddress;
uint32_t tmpITFlags = ITFlags;
/* Process Locked */
__HAL_LOCK(hi2c);
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@ -4612,8 +4613,11 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
@ -4623,7 +4627,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
hi2c->XferSize--;
hi2c->XferCount--;
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
@ -4634,7 +4638,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
hi2c->XferSize--;
hi2c->XferCount--;
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
@ -4674,7 +4678,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
}
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
{
if (hi2c->XferCount == 0U)
{
@ -4705,10 +4709,10 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
/* Nothing to do */
}
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
I2C_ITMasterCplt(hi2c, tmpITFlags);
}
/* Process Unlocked */
@ -4728,11 +4732,12 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
uint32_t tmpoptions = hi2c->XferOptions;
uint32_t tmpITFlags = ITFlags;
/* Process locked */
__HAL_LOCK(hi2c);
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
@ -4743,7 +4748,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
I2C_ITListenCplt(hi2c, tmpITFlags);
}
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
{
@ -4779,10 +4784,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
}
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET))
{
if (hi2c->XferCount > 0U)
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
@ -4800,11 +4808,11 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
I2C_ITSlaveSeqCplt(hi2c);
}
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
{
I2C_ITAddrCplt(hi2c, ITFlags);
I2C_ITAddrCplt(hi2c, tmpITFlags);
}
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
@ -4837,10 +4845,10 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
}
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
/* Process Unlocked */
@ -5012,18 +5020,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
/* Split check of hdmarx, for MISRA compliance */
if (hi2c->hdmarx != NULL)
{
if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)
{
treatdmanack = 1U;
if (__HAL_DMA_GET_COUNTER(hi2c->hdmarx) == 0U)
{
treatdmanack = 1U;
}
}
}
/* Split check of hdmatx, for MISRA compliance */
if (hi2c->hdmatx != NULL)
{
if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET)
{
treatdmanack = 1U;
if (__HAL_DMA_GET_COUNTER(hi2c->hdmatx) == 0U)
{
treatdmanack = 1U;
}
}
}
@ -5532,6 +5546,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
{
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
uint32_t tmpITFlags = ITFlags;
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
@ -5569,8 +5584,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
}
/* Store Last receive data if any */
if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET)
if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)
{
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
@ -5604,11 +5622,14 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
if (hi2c->State == HAL_I2C_STATE_LISTEN)
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
I2C_ITListenCplt(hi2c, tmpITFlags);
}
}
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
/* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
I2C_ITSlaveSeqCplt(hi2c);
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;

10
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2c.h
View File

@ -86,17 +86,17 @@ typedef struct
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 IP initilisation status\n
* 0 : Reset (IP not initialized)\n
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)\n
* b5 Peripheral initialization status\n
* 0 : Reset (peripheral not initialized)\n
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (IP in Address Listen Mode)\n
* 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (IP busy with some configuration or internal operations)\n
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n

3
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2c_ex.h
View File

@ -140,6 +140,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
/**
* @}
*/

2141
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2s.c
View File

File diff suppressed because it is too large Load Diff

650
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2s.h
View File

@ -46,45 +46,35 @@ extern "C" {
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint32_t Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref I2S_MSB_LSB_transmission */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref I2S_MSB_LSB_transmission */
uint32_t WSInversion; /*!< Control the Word Select Inversion.
This parameter can be a value of @ref I2S_WSInversion */
uint32_t WSInversion; /*!< Control the Word Select Inversion.
This parameter can be a value of @ref I2S_WSInversion */
uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions
This parameter can be a value of @ref I2S_IO_Swap */
uint32_t Data24BitAlignment; /*!< Specifies the Data Padding for 24 bits data lenght
This parameter can be a value of @ref I2S_Data_24Bit_Alignment */
uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level.
This parameter can be a value of @ref I2S_Fifo_Threshold */
uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
This parameter can be a value of @ref I2S_Master_Keep_IO_State */
uint32_t SlaveExtendFREDetection; /*!< Control the channel length in SLAVE.
This parameter can be a value of @ref I2S_SlaveExtendFREDetection */
uint32_t Data24BitAlignment; /*!< Specifies the Data Padding for 24 bits data length
This parameter can be a value of @ref I2S_Data_24Bit_Alignment */
uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
This parameter can be a value of @ref SPI_Master_Keep_IO_State */
} I2S_InitTypeDef;
@ -93,14 +83,13 @@ typedef struct
*/
typedef enum
{
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
HAL_I2S_STATE_RESET = 0x00UL, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01UL, /*!< I2S initialized and ready for use */
HAL_I2S_STATE_BUSY = 0x02UL, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06UL, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07UL /*!< I2S error state */
} HAL_I2S_StateTypeDef;
/**
@ -108,65 +97,68 @@ typedef enum
*/
typedef struct __I2S_HandleTypeDef
{
SPI_TypeDef *Instance; /*!< I2S registers base address */
SPI_TypeDef *Instance; /*!< I2S registers base address */
I2S_InitTypeDef Init; /*!< I2S communication parameters */
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
decremented when a sample is received
NbSamplesReceived = RxBufferSize-RxBufferCount) */
void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
I2S_InitTypeDef Init; /*!< I2S communication parameters */
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter */
void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
__IO uint32_t ErrorCode; /*!< I2S Error code */
void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
__IO uint32_t ErrorCode; /*!< I2S Error code
This parameter can be a value of @ref I2S_Error */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
} I2S_HandleTypeDef;
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
/**
* @brief HAL I2S Callback ID enumeration definition
*/
typedef enum
{
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< I2S TxRx Completed callback ID */
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< I2S TxRx Half Completed callback ID */
HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
HAL_I2S_TX_COMPLETE_CB_ID = 0x00UL, /*!< I2S Tx Completed callback ID */
HAL_I2S_RX_COMPLETE_CB_ID = 0x01UL, /*!< I2S Rx Completed callback ID */
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< I2S Tx Half Completed callback ID */
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< I2S Rx Half Completed callback ID */
HAL_I2S_ERROR_CB_ID = 0x06UL, /*!< I2S Error callback ID */
HAL_I2S_MSPINIT_CB_ID = 0x07UL, /*!< I2S Msp Init callback ID */
HAL_I2S_MSPDEINIT_CB_ID = 0x08UL /*!< I2S Msp DeInit callback ID */
} HAL_I2S_CallbackIDTypeDef;
@ -184,23 +176,18 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
/**
* @defgroup I2S_Error_Defintion I2S Error Defintion
* @brief I2S Error Code
/** @defgroup I2S_Error I2S Error
* @{
*/
#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2S_ERROR_UDR (0x00000001U) /*!< I2S Underrun error */
#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< I2S Overrun error */
#define HAL_I2S_ERROR_FRE (0x00000004U) /*!< I2S Frame format error */
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
#define HAL_I2S_ERROR_TIMEOUT (0x00000010U) /*!< Timeout error */
#define HAL_I2S_ERROR_PRESCALER (0x00000020U) /*!< Prescaler error */
#define HAL_I2S_ERROR_NOT_SUPPORTED (0x00000040U) /*!< Requested operation not supported */
#define HAL_I2S_ERROR_NO_TRANSFER (0x00000080U) /*!< No on going transfert */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#define HAL_I2S_ERROR_NONE (0x00000000UL) /*!< No error */
#define HAL_I2S_ERROR_TIMEOUT (0x00000001UL) /*!< Timeout error */
#define HAL_I2S_ERROR_OVR (0x00000002UL) /*!< OVR error */
#define HAL_I2S_ERROR_UDR (0x00000004UL) /*!< UDR error */
#define HAL_I2S_ERROR_DMA (0x00000008UL) /*!< DMA transfer error */
#define HAL_I2S_ERROR_PRESCALER (0x00000010UL) /*!< Prescaler Calculation error */
#define HAL_I2S_ERROR_FRE (0x00000020UL) /*!< FRE error */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000040UL) /*!< Invalid Callback error */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
@ -209,12 +196,12 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
/** @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MODE_SLAVE_TX (0x00000000U)
#define I2S_MODE_SLAVE_RX (0x00000002U)
#define I2S_MODE_MASTER_TX (0x00000004U)
#define I2S_MODE_MASTER_RX (0x00000006U)
#define I2S_MODE_SLAVE_FD (0x00000008U)
#define I2S_MODE_MASTER_FD (0x0000000AU)
#define I2S_MODE_SLAVE_TX (0x00000000UL)
#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
#define I2S_MODE_SLAVE_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2)
#define I2S_MODE_MASTER_FULLDUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
/**
* @}
*/
@ -222,11 +209,11 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS (0x00000000U)
#define I2S_STANDARD_MSB (0x00000010U)
#define I2S_STANDARD_LSB (0x00000020U)
#define I2S_STANDARD_PCM_SHORT (0x00000030U)
#define I2S_STANDARD_PCM_LONG (0x000000B0U)
#define I2S_STANDARD_PHILIPS (0x00000000UL)
#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
#define I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
/**
* @}
*/
@ -234,10 +221,10 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B (0x00000000U)
#define I2S_DATAFORMAT_16B_EXTENDED (0x00000400U)
#define I2S_DATAFORMAT_24B (0x00000500U)
#define I2S_DATAFORMAT_32B (0x00000600U)
#define I2S_DATAFORMAT_16B (0x00000000UL)
#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define I2S_DATAFORMAT_24B (SPI_I2SCFGR_DATLEN_0)
#define I2S_DATAFORMAT_32B (SPI_I2SCFGR_DATLEN_1)
/**
* @}
*/
@ -245,8 +232,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
/** @defgroup I2S_MCLK_Output I2S MCLK Output
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE SPI_I2SCFGR_MCKOE
#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
#define I2S_MCLKOUTPUT_DISABLE (0x00000000UL)
/**
* @}
*/
@ -254,34 +241,34 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIOFREQ_192K (192000U)
#define I2S_AUDIOFREQ_96K (96000U)
#define I2S_AUDIOFREQ_48K (48000U)
#define I2S_AUDIOFREQ_44K (44100U)
#define I2S_AUDIOFREQ_32K (32000U)
#define I2S_AUDIOFREQ_22K (22050U)
#define I2S_AUDIOFREQ_16K (16000U)
#define I2S_AUDIOFREQ_11K (11025U)
#define I2S_AUDIOFREQ_8K (8000U)
#define I2S_AUDIOFREQ_DEFAULT (2U)
#define I2S_AUDIOFREQ_192K (192000UL)
#define I2S_AUDIOFREQ_96K (96000UL)
#define I2S_AUDIOFREQ_48K (48000UL)
#define I2S_AUDIOFREQ_44K (44100UL)
#define I2S_AUDIOFREQ_32K (32000UL)
#define I2S_AUDIOFREQ_22K (22050UL)
#define I2S_AUDIOFREQ_16K (16000UL)
#define I2S_AUDIOFREQ_11K (11025UL)
#define I2S_AUDIOFREQ_8K (8000UL)
#define I2S_AUDIOFREQ_DEFAULT (2UL)
/**
* @}
*/
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
/** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
* @{
*/
#define I2S_CPOL_LOW (0x00000000U)
#define I2S_CPOL_HIGH SPI_I2SCFGR_CKPOL
#define I2S_CPOL_LOW (0x00000000UL)
#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
/**
* @}
*/
/** @defgroup I2S_MSB_LSB_transmission I2S MSB LSB Transmission
/** @defgroup I2S_MSB_LSB_Transmission I2S MSB LSB Transmission
* @{
*/
#define I2S_FIRSTBIT_MSB (0x00000000U)
#define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST
#define I2S_FIRSTBIT_MSB (0x00000000UL)
#define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST
/**
* @}
*/
@ -289,17 +276,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
/** @defgroup I2S_WSInversion I2S Word Select Inversion
* @{
*/
#define I2S_WS_INVERSION_DISABLE (0x00000000U)
#define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV
/**
* @}
*/
/** @defgroup I2S_IO_Swap Control I2S IO Swap
* @{
*/
#define I2S_IO_SWAP_DISABLE (0x00000000U)
#define I2S_IO_SWAP_ENABLE SPI_CFG2_IOSWP
#define I2S_WS_INVERSION_DISABLE (0x00000000UL)
#define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV
/**
* @}
*/
@ -307,31 +285,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
/** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit
* @{
*/
#define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000U)
#define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT
/**
* @}
*/
/** @defgroup I2S_Fifo_Threshold I2S Fifo Threshold
* @{
*/
#define I2S_FIFO_THRESHOLD_01DATA (0x00000000U)
#define I2S_FIFO_THRESHOLD_02DATA (0x00000020U)
#define I2S_FIFO_THRESHOLD_03DATA (0x00000040U)
#define I2S_FIFO_THRESHOLD_04DATA (0x00000060U)
#define I2S_FIFO_THRESHOLD_05DATA (0x00000080U)
#define I2S_FIFO_THRESHOLD_06DATA (0x000000A0U)
#define I2S_FIFO_THRESHOLD_07DATA (0x000000C0U)
#define I2S_FIFO_THRESHOLD_08DATA (0x000000E0U)
#define I2S_FIFO_THRESHOLD_09DATA (0x00000100U)
#define I2S_FIFO_THRESHOLD_10DATA (0x00000120U)
#define I2S_FIFO_THRESHOLD_11DATA (0x00000140U)
#define I2S_FIFO_THRESHOLD_12DATA (0x00000160U)
#define I2S_FIFO_THRESHOLD_13DATA (0x00000180U)
#define I2S_FIFO_THRESHOLD_14DATA (0x000001A0U)
#define I2S_FIFO_THRESHOLD_15DATA (0x000001C0U)
#define I2S_FIFO_THRESHOLD_16DATA (0x000001E0U)
#define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000UL)
#define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT
/**
* @}
*/
@ -339,44 +294,35 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
/** @defgroup I2S_Master_Keep_IO_State Keep IO State
* @{
*/
#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
#define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
#define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
/**
* @}
*/
/** @defgroup I2S_SlaveExtendFREDetection Slave Extend FRE Detection
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
* @{
*/
#define I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE (0x00000000U)
#define I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE SPI_I2SCFGR_FIXCH
#define I2S_IT_RXP SPI_IER_RXPIE
#define I2S_IT_TXP SPI_IER_TXPIE
#define I2S_IT_UDR SPI_IER_UDRIE
#define I2S_IT_OVR SPI_IER_OVRIE
#define I2S_IT_FRE SPI_IER_TIFREIE
#define I2S_IT_ERR (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)
/**
* @}
*/
/** @defgroup I2S_Interrupt_definition I2S Interrupt definition
/** @defgroup I2S_Flags_Definition I2S Flags Definition
* @{
*/
#define I2S_IT_TXP SPI_IER_TXPIE
#define I2S_IT_RXP SPI_IER_RXPIE
#define I2S_IT_OVR SPI_IER_OVRIE
#define I2S_IT_UDR SPI_IER_UDRIE
#define I2S_IT_TIFRE SPI_IER_TIFREIE
#define I2S_IT_ERR (SPI_IER_OVRIE | SPI_IER_UDRIE | SPI_IER_TIFREIE)
#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag : Rx-Packet available flag */
#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag : Tx-Packet space available flag */
#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag : Underrun flag */
#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag : Overrun flag */
#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag : TI mode frame format error flag */
/**
* @}
*/
/** @defgroup I2S_Flag_definition I2S Flag definition
* @{
*/
#define I2S_FLAG_TXP SPI_SR_TXP /* I2S status flag: Tx-Packet space available */
#define I2S_FLAG_RXP SPI_SR_RXP /* I2S status flag: Rx-Packet available */
#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag: Underrun flag */
#define I2S_FLAG_RXWNE SPI_SR_RXWNE /* I2S RxFIFO Word Not Empty */
#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag: Overrun flag */
#define I2S_FLAG_TIFRE SPI_SR_TIFRE /* I2S Error flag: TI mode frame format error flag */
#define I2S_FLAG_MASK (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)
/**
* @}
*/
@ -384,127 +330,125 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2S_Exported_Macros I2S Exported Macros
/** @defgroup I2S_Exported_macros I2S Exported Macros
* @{
*/
/** @brief Reset I2S handle state
* @param __HANDLE__: specifies the I2S Handle.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
#endif
/** @brief Enable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__: specifies the I2S Handle.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
/** @brief Disable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__: specifies the I2S Handle.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))
/** @brief Enable the specified I2S interrupts.
* @param __HANDLE__: specifies the I2S Handle.
* @param __INTERRUPT__: specifies the interrupt source to enable.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
* @arg I2S_IT_RXP : Rx-Packet available interrupt
* @arg I2S_IT_OVR : Overrun interrupt
* @arg I2S_IT_UDR : Underrun interrupt
* @arg I2S_IT_TIFRE: TI mode frame format error interrupt
* @arg I2S_IT_ERR: Error interrupt
* @arg I2S_IT_RXP : Rx-Packet available interrupt
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
* @arg I2S_IT_UDR : Underrun interrupt
* @arg I2S_IT_OVR : Overrun interrupt
* @arg I2S_IT_FRE : TI mode frame format error interrupt
* @arg I2S_IT_ERR : Error interrupt enable
* @retval None
*/
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
/** @brief Disable the specified I2S interrupts.
* @param __HANDLE__: specifies the I2S Handle.
* @param __INTERRUPT__: specifies the interrupt source to disable.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
* @arg I2S_IT_RXP : Rx-Packet available interrupt
* @arg I2S_IT_OVR : Overrun interrupt
* @arg I2S_IT_UDR : Underrun interrupt
* @arg I2S_IT_TIFRE: TI mode frame format error interrupt
* @arg I2S_IT_ERR : Error interrupt
* @arg I2S_IT_RXP : Rx-Packet available interrupt
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
* @arg I2S_IT_UDR : Underrun interrupt
* @arg I2S_IT_OVR : Overrun interrupt
* @arg I2S_IT_FRE : TI mode frame format error interrupt
* @arg I2S_IT_ERR : Error interrupt enable
* @retval None
*/
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
* @param __HANDLE__: specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
* @param __INTERRUPT__: specifies the I2S interrupt source to check.
/** @brief Check if the specified I2S interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
* @arg I2S_IT_RXP : Rx-Packet available interrupt
* @arg I2S_IT_OVR : Overrun interrupt
* @arg I2S_IT_UDR : Underrun interrupt
* @arg I2S_IT_TIFRE: TI mode frame format error interrupt
* @arg I2S_IT_ERR : Error interrupt
* @arg I2S_IT_RXP : Rx-Packet available interrupt
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
* @arg I2S_IT_UDR : Underrun interrupt
* @arg I2S_IT_OVR : Overrun interrupt
* @arg I2S_IT_FRE : TI mode frame format error interrupt
* @arg I2S_IT_ERR : Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2S flag is set or not.
* @param __HANDLE__: specifies the I2S Handle.
* @param __FLAG__: specifies the flag to check.
/** @brief Check whether the specified I2S flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_TXP : Tx-Packet space available flag
* @arg I2S_FLAG_RXP : Rx-Packet available flag
* @arg I2S_FLAG_UDR : Underrun flag
* @arg I2S_FLAG_RXWNE: RxFIFO Word Not Empty flag
* @arg I2S_FLAG_OVR : Overrun flag
* @arg I2S_FLAG_TIFRE: TI mode frame format error flag
* @arg I2S_FLAG_RXP : Rx-Packet available flag
* @arg I2S_FLAG_TXP : Tx-Packet space available flag
* @arg I2S_FLAG_UDR : Underrun flag
* @arg I2S_FLAG_OVR : Overrun flag
* @arg I2S_FLAG_FRE : TI mode frame format error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__: specifies the I2S Handle.
/** @brief Clear the I2S OVR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
/** @brief Clears the I2S OVR pending flag.
* @param __HANDLE__: specifies the I2S Handle.
/** @brief Clear the I2S UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
/** @brief Clear the I2S TIFRE pending flag.
/** @brief Clear the I2S FRE pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
/** @brief Clear the I2S SUSP pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
/**
* @}
*/
#define __HAL_I2S_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
/* Include I2S HAL Extended module */
#include "stm32h7xx_hal_i2s_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup I2S_Exported_Functions I2S Exported Functions
/** @addtogroup I2S_Exported_Functions
* @{
*/
/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
/** @addtogroup I2S_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
@ -514,15 +458,15 @@ void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hspi, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hspi, HAL_I2S_CallbackIDTypeDef CallbackID);
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
/** @addtogroup I2S_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
@ -533,7 +477,6 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
/* Non-Blocking mode: DMA */
@ -554,7 +497,7 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
* @}
*/
/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
/** @addtogroup I2S_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/
@ -564,95 +507,107 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2S_Private_Constants I2S Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_Private I2S Private
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
((MODE) == I2S_MODE_SLAVE_RX) || \
((MODE) == I2S_MODE_MASTER_TX) || \
((MODE) == I2S_MODE_MASTER_RX) || \
((MODE) == I2S_MODE_SLAVE_FD) || \
((MODE) == I2S_MODE_MASTER_FD))
#define IS_I2S_FD_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_FD) || \
((MODE) == I2S_MODE_MASTER_FD))
#define IS_I2S_MASTER(MODE) (((MODE) == I2S_MODE_MASTER_TX) || \
((MODE) == I2S_MODE_MASTER_RX) || \
((MODE) == I2S_MODE_MASTER_FD))
#define IS_I2S_TX_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
((MODE) == I2S_MODE_MASTER_TX) || \
((MODE) == I2S_MODE_SLAVE_FD) || \
((MODE) == I2S_MODE_MASTER_FD))
#define IS_I2S_RX_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_RX) || \
((MODE) == I2S_MODE_MASTER_RX) || \
((MODE) == I2S_MODE_SLAVE_FD) || \
((MODE) == I2S_MODE_MASTER_FD))
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
((STANDARD) == I2S_STANDARD_MSB) || \
((STANDARD) == I2S_STANDARD_LSB) || \
((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
((STANDARD) == I2S_STANDARD_PCM_LONG))
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
((FORMAT) == I2S_DATAFORMAT_24B) || \
((FORMAT) == I2S_DATAFORMAT_32B))
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
((FREQ) == I2S_AUDIOFREQ_DEFAULT))
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
((CPOL) == I2S_CPOL_HIGH))
#define IS_I2S_FIRST_BIT(FIRSTBIT) (((FIRSTBIT) == I2S_FIRSTBIT_MSB) || \
((FIRSTBIT) == I2S_FIRSTBIT_LSB))
#define IS_I2S_WS_INVERSION(WSINV) (((WSINV) == I2S_WS_INVERSION_DISABLE) || \
((WSINV) == I2S_WS_INVERSION_ENABLE))
#define IS_I2S_IO_SWAP(IOSWAP) (((IOSWAP) == I2S_IO_SWAP_DISABLE) || \
((IOSWAP) == I2S_IO_SWAP_ENABLE))
#define IS_I2S_DATA_24BIT_ALIGNMENT(ALIGNMENT) (((ALIGNMENT) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
((ALIGNMENT) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
#define IS_I2S_FIFO_THRESHOLD(FTHLV) (((FTHLV) == I2S_FIFO_THRESHOLD_01DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_02DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_03DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_04DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_05DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_06DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_07DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_08DATA))
#define IS_I2S_MASTER_KEEP_IO_STATE(AFCNTR) (((AFCNTR) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \
((AFCNTR) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
#define IS_I2S_SLAVE_EXTEND_FRE_DETECTION(FIXCH) (((FIXCH) == I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE) || \
((FIXCH) == I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE))
/**
* @}
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of I2S SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXP : Rx-Packet available flag
* @arg I2S_FLAG_TXP : Tx-Packet space available flag
* @arg I2S_FLAG_UDR : Underrun flag
* @arg I2S_FLAG_OVR : Overrun flag
* @arg I2S_FLAG_FRE : TI mode frame format error flag
* @retval SET or RESET.
*/
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
/* Define the private group ***************************************************/
/******************************************************************************/
/** @defgroup I2S_Private I2S Private
* @{
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __IER__ copy of I2S IER register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_RXP : Rx-Packet available interrupt
* @arg I2S_IT_TXP : Tx-Packet space available interrupt
* @arg I2S_IT_UDR : Underrun interrupt
* @arg I2S_IT_OVR : Overrun interrupt
* @arg I2S_IT_FRE : TI mode frame format error interrupt
* @arg I2S_IT_ERR : Error interrupt enable
* @retval SET or RESET.
*/
/**
* @}
#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__) ((((__IER__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if I2S Mode parameter is in allowed range.
* @param __MODE__ specifies the I2S Mode.
* This parameter can be a value of @ref I2S_Mode
* @retval None
*/
/******************************************************************************/
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
((__MODE__) == I2S_MODE_SLAVE_RX) || \
((__MODE__) == I2S_MODE_MASTER_TX) || \
((__MODE__) == I2S_MODE_MASTER_RX) || \
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX) || \
((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
#define IS_I2S_MASTER(__MODE__) (((__MODE__) == I2S_MODE_MASTER_TX) || \
((__MODE__) == I2S_MODE_MASTER_RX) || \
((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))
#define IS_I2S_SLAVE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
((__MODE__) == I2S_MODE_SLAVE_RX) || \
((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
((__STANDARD__) == I2S_STANDARD_MSB) || \
((__STANDARD__) == I2S_STANDARD_LSB) || \
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
((__FORMAT__) == I2S_DATAFORMAT_32B))
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
((__CPOL__) == I2S_CPOL_HIGH))
#define IS_I2S_FIRST_BIT(__BIT__) (((__BIT__) == I2S_FIRSTBIT_MSB) || \
((__BIT__) == I2S_FIRSTBIT_LSB))
#define IS_I2S_WS_INVERSION(__WSINV__) (((__WSINV__) == I2S_WS_INVERSION_DISABLE) || \
((__WSINV__) == I2S_WS_INVERSION_ENABLE))
#define IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
#define IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__) (((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \
((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
/**
* @}
*/
@ -665,17 +620,10 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7xx_HAL_I2S_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1500
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2s_ex.c
View File

File diff suppressed because it is too large Load Diff

93
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_i2s_ex.h
View File

@ -31,6 +31,7 @@ extern "C" {
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
/** @addtogroup I2SEx I2SEx
* @{
*/
@ -38,6 +39,81 @@ extern "C" {
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2SEx_Exported_Macros I2S Extended Exported Macros
* @{
*/
#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
/** @brief Enable or disable the specified I2SExt peripheral.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
/** @brief Enable or disable the specified I2SExt interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__))
#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
/** @brief Checks if the specified I2SExt interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2SExt flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun flag
* @arg I2S_FLAG_OVR: Overrun flag
* @arg I2S_FLAG_FRE: Frame error flag
* @arg I2S_FLAG_CHSIDE: Channel Side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the I2SExt OVR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{ \
__IO uint32_t tmpreg_ovr = 0x00U; \
tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\
tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\
UNUSED(tmpreg_ovr); \
}while(0U)
/** @brief Clears the I2SExt UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__) do{ \
__IO uint32_t tmpreg_udr = 0x00U; \
tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
UNUSED(tmpreg_udr); \
}while(0U)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
* @{
@ -49,12 +125,16 @@ extern "C" {
/* Extended features functions *************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
/* I2S Callbacks used in non blocking modes (Interrupt and DMA) */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size);
/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
/**
@ -75,6 +155,11 @@ void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
/**
* @}
*/

15
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_iwdg.c
View File

@ -36,7 +36,8 @@
(+) Debug mode : When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
__HAL_DBGMCU_FREEZE_IWDG1() or __HAL_DBGMCU_FREEZE2_IWDG2() and
__HAL_DBGMCU_UnFreeze_IWDG1 or __HAL_DBGMCU_UnFreeze2_IWDG2() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
The IWDG timeout may vary due to LSI frequency dispersion. STM32H7xx
@ -49,17 +50,17 @@
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
(+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts downcounting.
(+) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
IWDG_WINR.
clock is forced ON and IWDG counter starts counting down.
(+) Enable write access to configuration registers:
IWDG_PR, IWDG_RLR and IWDG_WINR.
(+) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(+) wait for status flags to be reset
(+) Wait for status flags to be reset.
(+) Depending on window parameter:
(++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function withy exact time base.
function with exact time base.
(++) Else modify Window register. This will automatically reload
watchdog counter.
@ -167,7 +168,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
/* Enable IWDG. LSI is turned on automaticaly */
/* Enable IWDG. LSI is turned on automatically */
__HAL_IWDG_START(hiwdg);
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing

3
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_iwdg.h
View File

@ -119,7 +119,7 @@ typedef struct
/**
* @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
* (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
* @param __HANDLE__ IWDG handle
* @retval None
*/
@ -219,6 +219,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
*/
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
/**
* @}
*/

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_jpeg.h
View File

@ -28,6 +28,8 @@ extern "C" {
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
#if defined (JPEG)
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
@ -642,6 +644,8 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);
* @}
*/
#endif /* JPEG */
#ifdef __cplusplus
}
#endif

28
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_lptim.c
View File

@ -1446,8 +1446,6 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
* @}
*/
/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks
* @brief LPTIM IRQ handler.
*
@ -1848,31 +1846,31 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti
break;
case HAL_LPTIM_COMPARE_MATCH_CB_ID :
hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak IC Msp Init Callback */
hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */
break;
case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID :
hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak IC Msp DeInit Callback */
hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */
break;
case HAL_LPTIM_TRIGGER_CB_ID :
hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak OC Msp Init Callback */
hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */
break;
case HAL_LPTIM_COMPARE_WRITE_CB_ID :
hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak OC Msp DeInit Callback */
hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */
break;
case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID :
hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak PWM Msp Init Callback */
hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */
break;
case HAL_LPTIM_DIRECTION_UP_CB_ID :
hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak PWM Msp DeInit Callback */
hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */
break;
case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak One Pulse Msp Init Callback */
hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */
break;
default :
@ -1971,7 +1969,7 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */
lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */
lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */
lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */
lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */
}
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
@ -2062,19 +2060,19 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
switch ((uint32_t)lptim->Instance)
{
case LPTIM1_BASE:
__HAL_RCC_LPTIM1_CONFIG(0UL);
__HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_D2PCLK1);
break;
case LPTIM2_BASE:
__HAL_RCC_LPTIM2_CONFIG(0UL);
__HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_D3PCLK1);
break;
case LPTIM3_BASE:
__HAL_RCC_LPTIM3_CONFIG(0UL);
__HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_D3PCLK1);
break;
case LPTIM4_BASE:
__HAL_RCC_LPTIM4_CONFIG(0UL);
__HAL_RCC_LPTIM4_CONFIG(RCC_LPTIM4CLKSOURCE_D3PCLK1);
break;
case LPTIM5_BASE:
__HAL_RCC_LPTIM5_CONFIG(0UL);
__HAL_RCC_LPTIM5_CONFIG(RCC_LPTIM5CLKSOURCE_D3PCLK1);
break;
default:
break;

3
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_lptim.h
View File

@ -130,7 +130,7 @@ typedef enum
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
} HAL_LPTIM_StateTypeDef;
/**
@ -352,7 +352,6 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
* @{
*/
#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define LPTIM_IT_UP LPTIM_IER_UPIE
#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE

139
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ltdc.c
View File

@ -14,12 +14,24 @@
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Program the required configuration through the following parameters:
the LTDC timing, the horizontal and vertical polarity,
the pixel clock polarity, Data Enable polarity and the LTDC background color value
using HAL_LTDC_Init() function
[..]
The LTDC HAL driver can be used as follows:
(#) Declare a LTDC_HandleTypeDef handle structure, for example: LTDC_HandleTypeDef hltdc;
(#) Initialize the LTDC low level resources by implementing the HAL_LTDC_MspInit() API:
(##) Enable the LTDC interface clock
(##) NVIC configuration if you need to use interrupt process
(+++) Configure the LTDC interrupt priority
(+++) Enable the NVIC LTDC IRQ Channel
(#) Initialize the required configuration through the following parameters:
the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity,
Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function
*** Configuration ***
=========================
[..]
(#) Program the required configuration through the following parameters:
the pixel format, the blending factors, input alpha value, the window size
and the image size using HAL_LTDC_ConfigLayer() function for foreground
@ -73,58 +85,65 @@
(+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts.
(+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not.
*** Callback registration ***
=============================================
The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Function @ref HAL_LTDC_RegisterCallback() to register a callback.
Function @ref HAL_LTDC_RegisterCallback() allows to register following callbacks:
(+) LineEventCallback : LTDC Line Event Callback.
(+) ReloadEventCallback : LTDC Reload Event Callback.
(+) ErrorCallback : LTDC Error Callback
(+) MspInitCallback : LTDC MspInit.
(+) MspDeInitCallback : LTDC MspDeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
Use function @ref HAL_LTDC_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_LTDC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) LineEventCallback : LTDC Line Event Callback.
(+) ReloadEventCallback : LTDC Reload Event Callback.
(+) ErrorCallback : LTDC Error Callback
(+) MspInitCallback : LTDC MspInit.
(+) MspDeInitCallback : LTDC MspDeInit.
By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_LTDC_LineEventCallback(), @ref HAL_LTDC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak function in the HAL_LTDC_Init/ @ref HAL_LTDC_DeInit only when
these callbacks are null (not registered beforehand).
if not, MspInit or MspDeInit are not null, the @ref HAL_LTDC_Init/ @ref HAL_LTDC_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_LTDC_RegisterCallback() before calling @ref HAL_LTDC_DeInit
or HAL_LTDC_Init function.
When The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
[..]
(@) You can refer to the LTDC HAL driver header file for more useful macros
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use function HAL_LTDC_RegisterCallback() to register a callback.
[..]
Function HAL_LTDC_RegisterCallback() allows to register following callbacks:
(+) LineEventCallback : LTDC Line Event Callback.
(+) ReloadEventCallback : LTDC Reload Event Callback.
(+) ErrorCallback : LTDC Error Callback
(+) MspInitCallback : LTDC MspInit.
(+) MspDeInitCallback : LTDC MspDeInit.
[..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
[..]
Use function HAL_LTDC_UnRegisterCallback() to reset a callback to the default
weak function.
HAL_LTDC_UnRegisterCallback() takes as parameters the HAL peripheral handle
and the callback ID.
[..]
This function allows to reset following callbacks:
(+) LineEventCallback : LTDC Line Event Callback
(+) ReloadEventCallback : LTDC Reload Event Callback
(+) ErrorCallback : LTDC Error Callback
(+) MspInitCallback : LTDC MspInit
(+) MspDeInitCallback : LTDC MspDeInit.
[..]
By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples HAL_LTDC_LineEventCallback(), HAL_LTDC_ErrorCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak (surcharged) functions in the HAL_LTDC_Init() and HAL_LTDC_DeInit()
only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_LTDC_Init() and HAL_LTDC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using HAL_LTDC_RegisterCallback() before calling HAL_LTDC_DeInit()
or HAL_LTDC_Init() function.
[..]
When the compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
* @attention
@ -143,12 +162,14 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
#ifdef HAL_LTDC_MODULE_ENABLED
#if defined (LTDC)
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#ifdef HAL_LTDC_MODULE_ENABLED
#if defined (LTDC)
/** @defgroup LTDC LTDC
* @brief LTDC HAL module driver
* @{
@ -2131,12 +2152,12 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
* @}
*/
#endif /* LTDC */
#endif /* HAL_LTDC_MODULE_ENABLED */
/**
* @}
*/
#endif /* LTDC */
#endif /* HAL_LTDC_MODULE_ENABLED */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

5
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ltdc.h
View File

@ -25,10 +25,10 @@
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
#if defined (LTDC)
/** @addtogroup STM32H7xx_HAL_Driver
* @{
@ -524,6 +524,8 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer
* @}
*/
/* Include LTDC HAL Extension module */
#include "stm32h7xx_hal_ltdc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LTDC_Exported_Functions
@ -675,6 +677,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
* @}
*/
#endif /* LTDC */
#ifdef __cplusplus
}

149
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ltdc_ex.c Normal file
View File

@ -0,0 +1,149 @@
/**
******************************************************************************
* @file stm32h7xx_hal_ltdc_ex.c
* @author MCD Application Team
* @brief LTDC Extension HAL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED)
#if defined (LTDC) && defined (DSI)
/** @defgroup LTDCEx LTDCEx
* @brief LTDC HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
* @{
*/
/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the LTDC
@endverbatim
* @{
*/
/**
* @brief Retrieve common parameters from DSI Video mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
* the DSI video mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarity is inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
/* Retrieve vertical timing parameters from DSI */
hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U;
hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U;
hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U;
hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U;
return HAL_OK;
}
/**
* @brief Retrieve common parameters from DSI Adapted command mode configuration structure
* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
* the DSI command mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarities are inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC && DSI */
#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

86
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ltdc_ex.h Normal file
View File

@ -0,0 +1,86 @@
/**
******************************************************************************
* @file stm32h7xx_hal_ltdc_ex.h
* @author MCD Application Team
* @brief Header file of LTDC HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_LTDC_EX_H
#define STM32H7xx_HAL_LTDC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
#if defined (LTDC) && defined (DSI)
#include "stm32h7xx_hal_dsi.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup LTDCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LTDCEx_Exported_Functions
* @{
*/
/** @addtogroup LTDCEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg);
HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC && DSI */
#ifdef __cplusplus
}
#endif
#endif /* STM32H7xx_HAL_LTDC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

42
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mdios.c
View File

@ -144,8 +144,8 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)
#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)
#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)
#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100U)
#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180U)
@ -771,9 +771,42 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
}
hmdios->ErrorCode = HAL_MDIOS_ERROR_NONE;
}
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
{
/* Clear MDIOS WAKEUP Exti pending bit */
__HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
/*Call registered WakeUp callback*/
hmdios->WakeUpCallback(hmdios);
#else
/* MDIOS WAKEUP callback */
HAL_MDIOS_WakeUpCallback(hmdios);
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
}
}
else
{
if(__HAL_MDIOS_WAKEUP_EXTID2_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
{
/* Clear MDIOS WAKEUP Exti D2 pending bit */
__HAL_MDIOS_WAKEUP_EXTID2_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)
/*Call registered WakeUp callback*/
hmdios->WakeUpCallback(hmdios);
#else
/* MDIOS WAKEUP callback */
HAL_MDIOS_WakeUpCallback(hmdios);
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
}
}
#else
/* check MDIOS WAKEUP exti flag */
if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != RESET)
if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(MDIOS_WAKEUP_EXTI_LINE) != (uint32_t)RESET)
{
/* Clear MDIOS WAKEUP Exti pending bit */
__HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(MDIOS_WAKEUP_EXTI_LINE);
@ -781,10 +814,11 @@ void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
/*Call registered WakeUp callback*/
hmdios->WakeUpCallback(hmdios);
#else
/* MDIOS WAKEUP callback */
/* MDIOS WAKEUP callback */
HAL_MDIOS_WakeUpCallback(hmdios);
#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */
}
#endif
}
/**

32
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mdios.h
View File

@ -387,6 +387,17 @@ typedef void (*pMDIOS_CallbackTypeDef)(MDIOS_HandleTypeDef * hmdios); /*!< poin
*/
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI->IMR2 |= (__EXTI_LINE__))
#if defined(DUAL_CORE)
/**
* @brief Enable the MDIOS WAKEUP Exti Line by Domain2.
* @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be enabled.
* This parameter can be:
* @arg MDIOS_WAKEUP_EXTI_LINE
* @retval None.
*/
#define __HAL_MDIOS_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI->C2IMR2 |= (__EXTI_LINE__))
#endif
/**
* @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
* @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
@ -396,6 +407,16 @@ typedef void (*pMDIOS_CallbackTypeDef)(MDIOS_HandleTypeDef * hmdios); /*!< poin
*/
#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR2 & (__EXTI_LINE__))
#if defined(DUAL_CORE)
/**
* @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
* @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
* This parameter can be:
* @arg MDIOS_WAKEUP_EXTI_LINE
* @retval EXTI MDIOS WAKEUP Line Status.
*/
#define __HAL_MDIOS_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR2 & (__EXTI_LINE__))
#endif
/**
* @brief Clear the MDIOS WAKEUP Exti flag.
* @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
@ -405,6 +426,17 @@ typedef void (*pMDIOS_CallbackTypeDef)(MDIOS_HandleTypeDef * hmdios); /*!< poin
*/
#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR2 = (__EXTI_LINE__))
#if defined(DUAL_CORE)
/**
* @brief Clear the MDIOS WAKEUP Exti flag.
* @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
* This parameter can be:
* @arg MDIOS_WAKEUP_EXTI_LINE
* @retval None.
*/
#define __HAL_MDIOS_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR2 = (__EXTI_LINE__))
#endif
/**
* @brief enable rising edge interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.

318
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc.c
View File

@ -192,7 +192,8 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
@ -509,7 +510,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
@ -544,8 +545,9 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
/* Read block(s) in polling mode */
if(NumberOfBlocks > 1U)
@ -600,6 +602,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
return HAL_TIMEOUT;
}
}
__SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
/* Send stop transmission command in case of multiblock read */
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
@ -647,7 +650,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
@ -689,7 +692,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
@ -718,6 +721,16 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
return HAL_ERROR;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
@ -742,15 +755,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
return HAL_ERROR;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
/* Write block(s) in polling mode */
while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
{
@ -780,6 +784,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
return HAL_TIMEOUT;
}
}
__SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
/* Send stop transmission command in case of multiblock write */
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U))
@ -827,7 +832,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
@ -867,7 +872,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
@ -883,20 +888,13 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
hmmc->pRxBuffPtr = pData;
hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
@ -908,6 +906,16 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
return HAL_ERROR;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
/* Read Blocks in IT mode */
if(NumberOfBlocks > 1U)
{
@ -933,9 +941,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData,
return HAL_ERROR;
}
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF));
return HAL_OK;
}
else
@ -971,7 +976,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
@ -1006,6 +1011,17 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData
return HAL_ERROR;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
{
@ -1030,15 +1046,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData
return HAL_ERROR;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_ENABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
return HAL_OK;
}
else
@ -1090,22 +1097,11 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
hmmc->pRxBuffPtr = pData;
hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks;
hmmc->State = HAL_MMC_STATE_BUSY;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
/* Set Block Size for Card */
errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE);
if(errorstate != HAL_MMC_ERROR_NONE)
@ -1117,12 +1113,21 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData
return HAL_ERROR;
}
/* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
/* Enable transfer interrupts */
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND));
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
hmmc->Instance->IDMABASE0 = (uint32_t) pData ;
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
/* Read Blocks in DMA mode */
if(NumberOfBlocks > 1U)
@ -1184,7 +1189,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
{
@ -1229,8 +1234,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
hmmc->Instance->IDMABASE0 = (uint32_t) pData ;
hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF;
/* Write Blocks in Polling mode */
if(NumberOfBlocks > 1U)
@ -1282,7 +1287,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd,
if(hmmc->State == HAL_MMC_STATE_READY)
{
hmmc->ErrorCode = HAL_DMA_ERROR_NONE;
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
if(end_add < start_add)
{
@ -1386,53 +1391,16 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\
SDMMC_IT_RXFIFOHF);
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
__SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
if((context & MMC_CONTEXT_DMA) != 0U)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
__SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
hmmc->Instance->DLEN = 0;
hmmc->Instance->DCTRL = 0;
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ;
/* Stop Transfer for Write Single/Multi blocks or Read Multi blocks */
if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode = errorstate;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
}
if(((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->TxCpltCallback(hmmc);
#else
HAL_MMC_TxCpltCallback(hmmc);
#endif
}
if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->RxCpltCallback(hmmc);
#else
HAL_MMC_RxCpltCallback(hmmc);
#endif
}
hmmc->State = HAL_MMC_STATE_READY;
}
if((context & MMC_CONTEXT_IT) != 0U)
{
/* Stop Transfer for Write Multi blocks or Read Multi blocks */
if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
@ -1448,7 +1416,45 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
if(((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->TxCpltCallback(hmmc);
#else
HAL_MMC_TxCpltCallback(hmmc);
#endif
}
if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
{
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->RxCpltCallback(hmmc);
#else
HAL_MMC_RxCpltCallback(hmmc);
#endif
}
}
else if((context & MMC_CONTEXT_IT) != 0U)
{
/* Stop Transfer for Write Multi blocks or Read Multi blocks */
if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U))
{
errorstate = SDMMC_CmdStopTransfer(hmmc->Instance);
if(errorstate != HAL_MMC_ERROR_NONE)
{
hmmc->ErrorCode |= errorstate;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
}
/* Clear all the static flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
hmmc->State = HAL_MMC_STATE_READY;
if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U))
@ -1468,72 +1474,89 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
#endif
}
}
else
{
/* Nothing to do */
}
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXFIFOHE) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE);
MMC_Write_IT(hmmc);
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXFIFOHF) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF);
MMC_Read_IT(hmmc);
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL| SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_TXUNDERR) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL);
/* Set Error code */
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
}
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
}
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
}
if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
{
hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN;
}
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DCRCFAIL);
/* Disable all interrupts */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
__SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
hmmc->Instance->CMD |= SDMMC_CMD_CMDSTOP;
hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance);
hmmc->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP);
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DABORT);
if((context & MMC_CONTEXT_IT) != 0U)
{
/* Set the MMC state to ready to be able to start again the process */
hmmc->State = HAL_MMC_STATE_READY;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT);
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DTIMEOUT);
HAL_MMC_ErrorCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
else if((context & MMC_CONTEXT_DMA) != 0U)
{
if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE)
{
/* Disable Internal DMA */
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC);
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
/* Set the MMC state to ready to be able to start again the process */
hmmc->State = HAL_MMC_STATE_READY;
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_RXOVERR);
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_RXOVERR);
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
}
else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET)
{
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_TXUNDERR);
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_TXUNDERR);
#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
hmmc->ErrorCallback(hmmc);
#else
HAL_MMC_ErrorCallback(hmmc);
#endif
HAL_MMC_ErrorCallback(hmmc);
#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */
}
}
else
{
/* Nothing to do */
}
}
else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_IDMABTC) != RESET)
@ -2209,8 +2232,6 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
cardstate = ((resp1 >> 9U) & 0x0FU);
/* Clear all the static flags */
__SDMMC_CLEAR_FLAG(hmmc->Instance, SDMMC_STATIC_FLAGS);
return (HAL_MMC_CardStateTypeDef)cardstate;
}
@ -2235,6 +2256,10 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc)
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
hmmc->State = HAL_MMC_STATE_READY;
/* Initialize the MMC operation */
hmmc->Context = MMC_CONTEXT_NONE;
CardState = HAL_MMC_GetCardState(hmmc);
if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
@ -2261,11 +2286,15 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc)
__HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\
SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR);
/* If IDMA Context, disable Internal DMA */
hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA;
/* Clear All flags */
__HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
CardState = HAL_MMC_GetCardState(hmmc);
hmmc->State = HAL_MMC_STATE_READY;
if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING))
{
hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance);
@ -2376,7 +2405,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
return hmmc->ErrorCode;
}
//////////////////////////////////////////////
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
if(errorstate != HAL_MMC_ERROR_NONE)
@ -2391,10 +2419,6 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
Init.ClockDiv = hmmc->Init.ClockDiv;
(void)SDMMC_Init(hmmc->Instance, Init);
/////////////////////////////////////
/* Configure SDMMC peripheral interface */
//SDMMC_Init(hmmc->Instance, hmmc->Init);
/* All cards are initialized */
return HAL_MMC_ERROR_NONE;

3
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc.h
View File

@ -6,7 +6,8 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the

3
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc_ex.c
View File

@ -21,7 +21,8 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the

3
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_mmc_ex.h
View File

@ -6,7 +6,8 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the

443
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pcd.c
View File

@ -73,14 +73,6 @@
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
/**
* USB_OTG_CORE VERSION ID
*/
#define USB_OTG_CORE_ID_300A 0x4F54300AU
#define USB_OTG_CORE_ID_310A 0x4F54310AU
#define USB_OTG_CORE_ID_320A 0x4F54320AU
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
@ -97,6 +89,8 @@
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/**
* @}
@ -128,6 +122,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx;
uint8_t i;
/* Check the PCD handle allocation */
@ -139,6 +134,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
USBx = hpcd->Instance;
if (hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@ -174,6 +171,12 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->State = HAL_PCD_STATE_BUSY;
/* Disable DMA mode for FS instance */
if ((USBx->CID & (0x1U << 8)) == 0U)
{
hpcd->Init.dma_enable = 0U;
}
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
@ -185,11 +188,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
}
/* Force Device Mode*/
if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK)
{
hpcd->State = HAL_PCD_STATE_ERROR;
return HAL_ERROR;
}
(void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);
/* Init endpoints structures */
for (i = 0U; i < hpcd->Init.dev_endpoints; i++)
@ -225,20 +224,13 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->USB_Address = 0U;
hpcd->State = HAL_PCD_STATE_READY;
/* Activate LPM */
if (hpcd->Init.lpm_enable == 1U)
{
(void)HAL_PCDEx_ActivateLPM(hpcd);
}
/* Activate Battery charging */
if (hpcd->Init.battery_charging_enable == 1U)
{
(void)HAL_PCDEx_ActivateBCD(hpcd);
}
(void)USB_DevDisconnect(hpcd->Instance);
return HAL_OK;
@ -997,7 +989,19 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
__HAL_LOCK(hpcd);
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
if ((hpcd->Init.battery_charging_enable == 1U) &&
(hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
{
/* Enable USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
}
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
(void)USB_DevConnect(hpcd->Instance);
__HAL_PCD_ENABLE(hpcd);
__HAL_UNLOCK(hpcd);
@ -1016,8 +1020,8 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
if (USB_StopDevice(hpcd->Instance) != HAL_OK)
{
__HAL_UNLOCK(hpcd);
return HAL_ERROR;
__HAL_UNLOCK(hpcd);
return HAL_ERROR;
}
(void)USB_DevDisconnect(hpcd->Instance);
@ -1035,12 +1039,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t TempReg = USBx_BASE + 0x40U;
uint32_t gSNPSiD = *(uint32_t *) TempReg;
uint32_t i, ep_intr, epint, epnum = 0U;
uint32_t fifoemptymsk, temp;
USB_OTG_EPTypeDef *ep;
uint32_t hclk;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
@ -1073,93 +1074,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
if (gSNPSiD > USB_OTG_CORE_ID_300A)
{
/* setup/out transaction management for Core ID >= 310A */
if (hpcd->Init.dma_enable == 1U)
{
if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U)
{
CLEAR_OUT_EP_INTR(epnum, (1U << 15));
}
}
}
if (hpcd->Init.dma_enable == 1U)
{
hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
}
if (gSNPSiD == USB_OTG_CORE_ID_310A)
{
if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U)
{
CLEAR_OUT_EP_INTR(epnum, (1U << 15));
}
else
{
if ((USBx_OUTEP(0U)->DOEPINT & (1U << 5)) != 0U)
{
CLEAR_OUT_EP_INTR(epnum, (1U << 5));
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
if (hpcd->Init.dma_enable == 1U)
{
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
{
/* this is ZLP, so prepare EP0 for next setup */
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
}
(void)PCD_EP_OutXfrComplete_int(hpcd, epnum);
}
if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
{
if (gSNPSiD == USB_OTG_CORE_ID_310A)
{
if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U)
{
CLEAR_OUT_EP_INTR(epnum, (1U << 15));
}
}
if (gSNPSiD > USB_OTG_CORE_ID_300A)
{
/* setup/out transaction management for Core ID >= 310A */
if (hpcd->Init.dma_enable == 1U)
{
if ((USBx_OUTEP(0U)->DOEPINT & (1U << 15)) != 0U)
{
CLEAR_OUT_EP_INTR(epnum, (1U << 15));
}
}
}
/* Inform the upper layer that a setup packet is available */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/* Class B setup phase done for previous decoded setup */
(void)PCD_EP_OutSetupPacket_int(hpcd, epnum);
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
@ -1168,13 +1089,21 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
}
#ifdef USB_OTG_DOEPINT_OTEPSPR
/* Clear Status Phase Received interrupt */
if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
if (hpcd->Init.dma_enable == 1U)
{
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
#endif /* USB_OTG_DOEPINT_OTEPSPR */
/* Clear OUT NAK interrupt */
if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);
}
}
epnum++;
ep_intr >>= 1U;
@ -1289,7 +1218,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
/* Handle LPM Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
{
@ -1315,7 +1244,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/* Handle Reset Interrupt */
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
@ -1333,24 +1262,33 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if (hpcd->Init.use_dedicated_ep1 != 0U)
{
USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |
USB_OTG_DOEPMSK_XFRCM |
USB_OTG_DOEPMSK_EPDM;
USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |
USB_OTG_DIEPMSK_XFRCM |
USB_OTG_DIEPMSK_EPDM;
}
else
{
#ifdef USB_OTG_DOEPINT_OTEPSPR
USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
#else
USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
#endif /* USB_OTG_DOEPINT_OTEPSPR */
USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
USB_OTG_DOEPMSK_XFRCM |
USB_OTG_DOEPMSK_EPDM |
USB_OTG_DOEPMSK_OTEPSPRM |
USB_OTG_DOEPMSK_NAKM;
USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
USB_OTG_DIEPMSK_XFRCM |
USB_OTG_DIEPMSK_EPDM;
}
/* Set Default Address to 0 */
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
/* setup EP0 to receive SETUP packets */
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
(void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,
(uint8_t *)hpcd->Setup);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
}
@ -1359,85 +1297,12 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
{
(void)USB_ActivateSetup(hpcd->Instance);
hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);
if (USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
{
hpcd->Init.speed = USB_OTG_SPEED_HIGH;
hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10U) & USB_OTG_GUSBCFG_TRDT);
}
else
{
hpcd->Init.speed = USB_OTG_SPEED_FULL;
/* The USBTRD is configured according to the tables below, depending on AHB frequency
used by application. In the low AHB frequency range it is used to stretch enough the USB response
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
latency to the Data FIFO */
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
if ((hclk >= 14200000U) && (hclk < 15000000U))
{
/* hclk Clock Range between 14.2-15 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xFU << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if ((hclk >= 15000000U) && (hclk < 16000000U))
{
/* hclk Clock Range between 15-16 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xEU << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if ((hclk >= 16000000U) && (hclk < 17200000U))
{
/* hclk Clock Range between 16-17.2 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xDU << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if ((hclk >= 17200000U) && (hclk < 18500000U))
{
/* hclk Clock Range between 17.2-18.5 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xCU << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if ((hclk >= 18500000U) && (hclk < 20000000U))
{
/* hclk Clock Range between 18.5-20 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xBU << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if ((hclk >= 20000000U) && (hclk < 21800000U))
{
/* hclk Clock Range between 20-21.8 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xAU << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if ((hclk >= 21800000U) && (hclk < 24000000U))
{
/* hclk Clock Range between 21.8-24 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x9U << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if ((hclk >= 24000000U) && (hclk < 27700000U))
{
/* hclk Clock Range between 24-27.7 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x8U << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if ((hclk >= 27700000U) && (hclk < 32000000U))
{
/* hclk Clock Range between 27.7-32 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x7U << 10) & USB_OTG_GUSBCFG_TRDT);
}
else /* if(hclk >= 32000000) */
{
/* hclk Clock Range between 32-200 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x6U << 10) & USB_OTG_GUSBCFG_TRDT);
}
}
/* Set USB Turnaround time */
(void)USB_SetTurnaroundTime(hpcd->Instance,
HAL_RCC_GetHCLKFreq(),
(uint8_t)hpcd->Init.speed);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->ResetCallback(hpcd);
@ -1461,7 +1326,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)
{
(void)USB_ReadPacket(USBx, ep->xfer_buff, (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
(void)USB_ReadPacket(USBx, ep->xfer_buff,
(uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));
ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
}
@ -1744,7 +1611,19 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
{
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
__HAL_LOCK(hpcd);
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
if ((hpcd->Init.battery_charging_enable == 1U) &&
(hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))
{
/* Enable USB Transceiver */
USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
}
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
(void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
@ -2144,7 +2023,8 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
}
len32b = (len + 3U) / 4U;
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, (uint8_t)hpcd->Init.dma_enable);
(void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,
(uint8_t)hpcd->Init.dma_enable);
ep->xfer_buff += len;
ep->xfer_count += len;
@ -2158,6 +2038,163 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
return HAL_OK;
}
/**
* @brief process EP OUT transfer complete interrupt.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if (hpcd->Init.dma_enable == 1U)
{
if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */
{
/* StupPktRcvd = 1 this is a setup packet */
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
/* Inform the upper layer that a setup packet is available */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)
{
/* StupPktRcvd = 1 this is a setup packet */
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
else
{
/* out data packet received over EP0 */
hpcd->OUT_ep[epnum].xfer_count =
hpcd->OUT_ep[epnum].maxpacket -
(USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))
{
/* this is ZLP, so prepare EP0 for next setup */
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
}
}
else
{
/* ... */
}
}
else
{
if (gSNPSiD == USB_OTG_CORE_ID_310A)
{
/* StupPktRcvd = 1 this is a setup packet */
if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
else
{
if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);
}
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
else
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);
#else
HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
return HAL_OK;
}
/**
* @brief process EP OUT setup packet received interrupt.
* @param hpcd PCD handle
* @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);
uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;
if (hpcd->Init.dma_enable == 1U)
{
/* StupPktRcvd = 1 pending setup packet int */
if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
}
else
{
if ((gSNPSiD == USB_OTG_CORE_ID_310A) &&
((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);
}
}
/* Inform the upper layer that a setup packet is available */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->SetupStageCallback(hpcd);
#else
HAL_PCD_SetupStageCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))
{
(void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
return HAL_OK;
}
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

61
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pcd.h
View File

@ -152,9 +152,9 @@ typedef struct
/** @defgroup PCD_Speed PCD Speed
* @{
*/
#define PCD_SPEED_HIGH 0U
#define PCD_SPEED_HIGH_IN_FULL 1U
#define PCD_SPEED_FULL 2U
#define PCD_SPEED_HIGH USBD_HS_SPEED
#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED
#define PCD_SPEED_FULL USBD_FS_SPEED
/**
* @}
*/
@ -169,19 +169,6 @@ typedef struct
* @}
*/
/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
* @{
*/
#ifndef USBD_HS_TRDT_VALUE
#define USBD_HS_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
#ifndef USBD_FS_TRDT_VALUE
#define USBD_FS_TRDT_VALUE 5U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
*/
/** @defgroup PCD_Error_Code_definition PCD Error Code definition
* @brief PCD Error Code definition
* @{
@ -221,24 +208,8 @@ typedef struct
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI_D1->PR2 &(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI_D1->PR2 = (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
EXTI->FTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \
EXTI->RTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE; \
} while(0U)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI_D1->PR2 &(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI_D1->PR2 = (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
EXTI->FTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \
EXTI->RTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE; \
} while(0U)
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
@ -412,6 +383,32 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
* @}
*/
#if defined (USB_OTG_FS) || defined (USB_OTG_HS)
#ifndef USB_OTG_DOEPINT_OTEPSPR
#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */
#endif
#ifndef USB_OTG_DOEPMSK_OTEPSPRM
#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */
#endif
#ifndef USB_OTG_DOEPINT_NAK
#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */
#endif
#ifndef USB_OTG_DOEPMSK_NAKM
#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */
#endif
#ifndef USB_OTG_DOEPINT_STPKTRX
#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */
#endif
#ifndef USB_OTG_DOEPMSK_NYETM
#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */
#endif
#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{

136
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pcd_ex.c
View File

@ -159,98 +159,93 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t USBx_BASE = (uint32_t)USBx;
uint32_t tickstart = HAL_GetTick();
/* Start BCD When device is connected */
if ((USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS) == USB_OTG_DCTL_SDIS)
/* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
/* Wait Detect flag or a timeout is happen*/
while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
{
/* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
/* Wait Detect flag or a timeout is happen*/
while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > 1000U)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > 1000U)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
return;
}
return;
}
}
/* Right response got */
HAL_Delay(200U);
/* Right response got */
HAL_Delay(200U);
/* Check Detect flag*/
if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
{
/* Check Detect flag*/
if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)
{
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/*Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
/*Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
{
/* Case of Standard Downstream Port */
if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)
{
/* Case of Standard Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* start secondary detection to check connection to Charging Downstream
Port or Dedicated Charging Port */
USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
{
/* case Dedicated Charging Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* start secondary detection to check connection to Charging Downstream
Port or Dedicated Charging Port */
USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;
HAL_Delay(50U);
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
HAL_Delay(50U);
if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)
{
/* case Dedicated Charging Port */
/* case Charging Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
else
{
/* case Charging Downstream Port */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
}
/* Battery Charging capability discovery finished */
(void)HAL_PCDEx_DeActivateBCD(hpcd);
/* Battery Charging capability discovery finished */
(void)HAL_PCDEx_DeActivateBCD(hpcd);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#else
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
}
/**
@ -262,13 +257,17 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = 1U;
/* Enable DCD : Data Contact Detect */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
/* Power Down USB tranceiver */
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
/* Enable Battery charging */
USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;
hpcd->battery_charging_active = 1U;
return HAL_OK;
}
@ -280,8 +279,15 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = 0U;
USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);
USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);
/* Disable Battery charging */
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
hpcd->battery_charging_active = 0U;
return HAL_OK;
}

46
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pwr.c
View File

@ -45,8 +45,10 @@
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#if !defined (DUAL_CORE)
#define PVD_MODE_IT ((uint32_t)0x00010000U)
#define PVD_MODE_EVT ((uint32_t)0x00020000U)
#endif /* DUAL_CORE */
#define PVD_RISING_EDGE ((uint32_t)0x00000001U)
#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
#define PVD_RISING_FALLING_EDGE ((uint32_t)0x00000003U)
@ -260,11 +262,14 @@ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
/* Clear any previous config */
#if !defined (DUAL_CORE)
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
__HAL_PWR_PVD_EXTI_DISABLE_IT();
#endif /* DUAL_CORE */
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
#if !defined (DUAL_CORE)
/* Configure interrupt mode */
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
@ -276,6 +281,7 @@ void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
{
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
}
#endif /* DUAL_CORE */
/* Configure the edge */
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
@ -429,6 +435,11 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
/* Store the new value */
PWR->CR1 = tmpreg;
#if defined(DUAL_CORE)
/* Keep DSTOP mode when D1 domain enters Deepsleep */
CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1);
#else
/* Keep DSTOP mode when D1 domain enters Deepsleep */
CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
@ -437,6 +448,7 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
/* Keep DSTOP mode when D3 domain enters Deepsleep */
CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
#endif /*DUAL_CORE*/
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
@ -469,6 +481,11 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
*/
void HAL_PWR_EnterSTANDBYMode(void)
{
#if defined(DUAL_CORE)
/* Keep DSTANDBY mode when D1 domain enters Deepsleep */
SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
SET_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1);
#else
/* Keep DSTANDBY mode when D1 domain enters Deepsleep */
SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
@ -477,6 +494,7 @@ void HAL_PWR_EnterSTANDBYMode(void)
/* Keep DSTANDBY mode when D3 domain enters Deepsleep */
SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
#endif /*DUAL_CORE*/
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
@ -547,6 +565,33 @@ void HAL_PWR_DisableSEVOnPend(void)
*/
void HAL_PWR_PVD_IRQHandler(void)
{
#if defined(DUAL_CORE)
/* PVD EXTI line interrupt detected */
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Check PWR EXTI flag */
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback();
/* Clear PWR EXTI pending bit */
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
}
}
else
{
/* Check PWR EXTI D2 flag */
if(__HAL_PWR_PVD_EXTID2_GET_FLAG() != RESET)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback();
/* Clear PWR EXTI D2 pending bit */
__HAL_PWR_PVD_EXTID2_CLEAR_FLAG();
}
}
#else
/* PVD EXTI line interrupt detected */
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
{
@ -556,6 +601,7 @@ void HAL_PWR_PVD_IRQHandler(void)
/* Clear PWR EXTI pending bit */
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
}
#endif /*DUAL_CORE*/
}
/**

159
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pwr.h
View File

@ -122,6 +122,7 @@ typedef struct
/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
* @{
*/
#define PWR_REGULATOR_VOLTAGE_SCALE0 ((uint32_t)0x00000000)
#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)
#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)
@ -136,13 +137,25 @@ typedef struct
#define PWR_FLAG_SB_D1 ((uint8_t)0x02U)
#define PWR_FLAG_SB_D2 ((uint8_t)0x03U)
#define PWR_FLAG_SB ((uint8_t)0x04U)
#if defined(DUAL_CORE)
#define PWR_FLAG_CPU_HOLD ((uint8_t)0x05U)
#define PWR_FLAG_CPU2_HOLD ((uint8_t)0x06U)
#define PWR_FLAG2_STOP ((uint8_t)0x07U)
#define PWR_FLAG2_SB_D1 ((uint8_t)0x08U)
#define PWR_FLAG2_SB_D2 ((uint8_t)0x09U)
#define PWR_FLAG2_SB ((uint8_t)0x0AU)
#endif /*DUAL_CORE*/
#define PWR_FLAG_PVDO ((uint8_t)0x0BU)
#define PWR_FLAG_AVDO ((uint8_t)0x0CU)
#define PWR_FLAG_ACTVOSRDY ((uint8_t)0x0DU)
#define PWR_FLAG_ACTVOS ((uint8_t)0x0EU)
#define PWR_FLAG_BRR ((uint8_t)0x0FU)
#define PWR_FLAG_VOSRDY ((uint8_t)0x10U)
#if defined(SMPS)
#define PWR_FLAG_SMPSEXTRDY ((uint8_t)0x11U)
#else
#define PWR_FLAG_SCUEN ((uint8_t)0x11U)
#endif /* SMPS */
/**
* @}
*/
@ -167,22 +180,93 @@ typedef struct
* @param __REGULATOR__: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
* not operate at the maximum frequency (refer to the datasheets for more details).
* This parameter can be one of the following values:
* This parameter can be one of the following values:
* @arg PWR_REGULATOR_VOLTAGE_SCALE0: Regulator voltage output Scale 0 mode
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
* @note PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when Vcore is supplied from LDO.
* the SYSCFG Clock must be enabled before selecting PWR_REGULATOR_VOLTAGE_SCALE0
* using macro __HAL_RCC_SYSCFG_CLK_ENABLE().
* Transition to PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when the system is already in
* PWR_REGULATOR_VOLTAGE_SCALE1.
* transition from PWR_REGULATOR_VOLTAGE_SCALE0 is only possible to PWR_REGULATOR_VOLTAGE_SCALE1
* then once in PWR_REGULATOR_VOLTAGE_SCALE1 it is possible to switch to another voltage scale.
* After each regulator voltage setting, wait on PWR_FLAG_VOSRDY to be set using macro __HAL_PWR_GET_FLAG
* To enter low power mode , and if current regulator voltage is PWR_REGULATOR_VOLTAGE_SCALE0 then first
* switch to PWR_REGULATOR_VOLTAGE_SCALE1 before entering low power mode.
*
* @retval None
*/
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
do { \
__IO uint32_t tmpreg = 0x00; \
MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
__IO uint32_t tmpreg = 0x00; \
if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \
{ \
MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \
/* Delay after setting the voltage scaling */ \
tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
UNUSED(tmpreg); \
MODIFY_REG(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN, SYSCFG_PWRCR_ODEN); \
/* Delay after setting the syscfg boost setting */ \
tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
} \
else \
{ \
CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
/* Delay after setting the syscfg boost setting */ \
tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
} \
UNUSED(tmpreg); \
} while(0)
#if defined(DUAL_CORE)
/** @brief Check PWR PVD/AVD and VOSflags are set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
* For this reason, this bit is equal to 0 after Standby or reset
* until the PVDE bit is set.
* @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
* by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode.
* For this reason, this bit is equal to 0 after Standby or reset
* until the AVDE bit is set.
* @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* @arg PWR_FLAG_SMPSEXTRDY: SMPS External supply ready flag.
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
* when the device wakes up from Standby mode or by a system reset
* or power reset.
* @arg PWR_FLAG_SB: StandBy flag
* @arg PWR_FLAG_STOP: STOP flag
* @arg PWR_FLAG_SB_D1: StandBy D1 flag
* @arg PWR_FLAG_SB_D2: StandBy D2 flag
* @arg PWR_FLAG_CPU1_HOLD: CPU1 system wake up with hold
* @arg PWR_FLAG_CPU2_HOLD: CPU2 system wake up with hold
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
((__FLAG__) == PWR_FLAG_SMPSEXTRDY)?((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) : \
((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
((__FLAG__) == PWR_FLAG_CPU_HOLD)?((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) : \
((__FLAG__) == PWR_FLAG_CPU2_HOLD)?((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) : \
((__FLAG__) == PWR_FLAG_SB)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
((__FLAG__) == PWR_FLAG2_SB)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) : \
((__FLAG__) == PWR_FLAG_STOP)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
((__FLAG__) == PWR_FLAG2_STOP)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) : \
((__FLAG__) == PWR_FLAG_SB_D1)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
((__FLAG__) == PWR_FLAG2_SB_D1)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) : \
((__FLAG__) == PWR_FLAG_SB_D2)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) : \
(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2))
#else
/** @brief Check PWR PVD/AVD and VOSflags are set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
@ -218,8 +302,23 @@ do { \
((__FLAG__) == PWR_FLAG_STOP)?((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
((__FLAG__) == PWR_FLAG_SB_D1)?((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
/** @brief Clear PWR flags.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_SB: Standby flag.
* @arg PWR_CPU_FLAGS: Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
* @retval None.
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \
do { \
SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \
SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
} while(0)
#else
/** @brief Clear PWR flags.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
@ -228,6 +327,7 @@ do { \
* @retval None.
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
#endif /*DUAL_CORE*/
/**
* @brief Enable the PVD EXTI Line 16.
@ -235,24 +335,56 @@ do { \
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
#if defined(DUAL_CORE)
/**
* @brief Enable the PVD EXTI D2 Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
#endif /*DUAL_CORE*/
/**
* @brief Disable the PVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
#if defined(DUAL_CORE)
/**
* @brief Disable the PVD EXTI D2 Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
#endif /*DUAL_CORE*/
/**
* @brief Enable event on PVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
#if defined(DUAL_CORE)
/**
* @brief Enable event on PVD EXTI D2 Line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
#endif /*DUAL_CORE*/
/**
* @brief Disable event on PVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
#if defined(DUAL_CORE)
/**
* @brief Disable event on PVD EXTI D2 Line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
#endif /*DUAL_CORE*/
/**
* @brief Enable the PVD Extended Interrupt Rising Trigger.
* @retval None.
@ -305,12 +437,29 @@ do { \
*/
#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET)
#if defined(DUAL_CORE)
/**
* @brief checks whether the specified PVD Exti interrupt flag is set or not.
* @retval EXTI D2 PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET)
#endif /*DUAL_CORE*/
/**
* @brief Clear the PVD EXTI flag.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
#if defined(DUAL_CORE)
/**
* @brief Clear the PVD EXTI D2 flag.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
#endif /*DUAL_CORE*/
/**
* @brief Generates a Software interrupt on PVD EXTI line.
* @retval None.

344
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pwr_ex.c
View File

@ -133,6 +133,94 @@
* @{
*/
#if defined(SMPS)
/**
* @brief Configure the system Power Supply.
* @param SupplySource: Specifies the Power Supply source to set after a system startup.
* This parameter can be one of the following values:
* @arg PWR_LDO_SUPPLY The LDO regulator supplies the Vcore Power Domains.
* The SMPS regulator is Bypassed.
*
* @arg PWR_DIRECT_SMPS_SUPPLY The SMPS supplies the Vcore Power Domains.
* The LDO is Bypassed.
*
* @arg PWR_SMPS_1V8_SUPPLIES_LDO The SMPS 1.8V output supplies the LDO.
* The Vcore Power Domains are supplied from the LDO.
*
* @arg PWR_SMPS_2V5_SUPPLIES_LDO The SMPS 2.5V output supplies the LDO.
* The Vcore Power Domains are supplied from the LDO.
*
* @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO The SMPS 1.8V output supplies external circuits and the LDO.
* The Vcore Power Domains are supplied from the LDO.
*
* @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO The SMPS 2.5V output supplies external circuits and the LDO.
* The Vcore Power Domains are supplied from the LDO.
*
* @arg PWR_SMPS_1V8_SUPPLIES_EXT The SMPS 1.8V output supplies external circuits.
* The LDO is Bypassed.
* The Vcore Power Domains are supplied from external source.
*
* @arg PWR_SMPS_2V5_SUPPLIES_EXT The SMPS 2.5V output supplies external circuits.
* The LDO is Bypassed.
* The Vcore Power Domains are supplied from external source.
*
* @arg PWR_EXTERNAL_SOURCE_SUPPLY The SMPS and the LDO are Bypassed.
* The Vcore Power Domains are supplied from external source.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
{
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_PWR_SUPPLY(SupplySource));
if((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
{
if((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
{
/* Supply configuration update locked, can't apply a new regulator config */
return HAL_ERROR;
}
}
/* Set the power supply configuration */
MODIFY_REG(PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till voltage level flag is set */
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ACTVOSRDY))
{
if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
{
return HAL_TIMEOUT;
}
}
/* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */
if((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||
(SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||
(SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT) ||
(SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT))
{
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till SMPS external supply ready flag is set */
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_SMPSEXTRDY))
{
if((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY_US)
{
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
#else
/**
* @brief Configure the system Power Supply.
* @param SupplySource: Specifies the Power Supply source to set after a system startup.
@ -176,6 +264,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource)
return HAL_OK;
}
#endif /*SMPS*/
/**
@ -454,6 +543,10 @@ void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Dom
/* Keep DSTOP mode when D1 domain enters Deepsleep */
CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
#if defined(DUAL_CORE)
CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1);
#endif /*DUAL_CORE*/
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
@ -480,11 +573,44 @@ void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Dom
{
/* Keep DSTOP mode when D2 domain enters Deepsleep */
CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
#if defined(DUAL_CORE)
/* Check Core */
assert_param(IS_PWR_D2_CPU(HAL_GetCurrentCPUID()));
CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* Ensure that all instructions done before entering STOP mode */
__DSB();
__ISB();
/* Select Stop mode entry */
if(STOPEntry == PWR_STOPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
#endif /*DUAL_CORE*/
}
else
{
/* Keep DSTOP mode when D3 domain enters Deepsleep */
CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
#if defined(DUAL_CORE)
CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3);
#endif /*DUAL_CORE*/
}
}
@ -497,7 +623,21 @@ void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Dom
*/
void HAL_PWREx_ClearPendingEvent(void)
{
#if defined(DUAL_CORE)
/* Check Core */
if(HAL_GetCurrentCPUID() == CM7_CPUID)
{
__WFE();
}
else
{
__SEV();
__WFE();
}
#else
__WFE();
#endif /*DUAL_CORE*/
}
/**
@ -533,6 +673,10 @@ void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain)
/* Allow DSTANDBY mode when D1 domain enters Deepsleep */
SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D1);
#if defined(DUAL_CORE)
SET_BIT(PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1);
#endif /*DUAL_CORE*/
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
@ -548,11 +692,33 @@ void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain)
{
/* Allow DSTANDBY mode when D2 domain enters Deepsleep */
SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D2);
#if defined(DUAL_CORE)
/* Check Core */
assert_param(IS_PWR_D2_CPU(HAL_GetCurrentCPUID()));
SET_BIT(PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2);
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
__force_stores();
#endif
/* Request Wait For Interrupt */
__WFI();
#endif /*DUAL_CORE*/
}
else
{
/* Allow DSTANDBY mode when D3 domain enters Deepsleep */
SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D3);
#if defined(DUAL_CORE)
SET_BIT(PWR-> CPU2CR, PWR_CPU2CR_PDDS_D3);
#endif /*DUAL_CORE*/
}
}
@ -572,8 +738,117 @@ void HAL_PWREx_ConfigD3Domain(uint32_t D3State)
/* Keep D3 in run mode */
MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State);
#if defined(DUAL_CORE)
MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_RUN_D3, D3State);
#endif /*DUAL_CORE*/
}
#if defined(DUAL_CORE)
/**
* @brief Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a given domain.
* @param DomainFlags: Specifies the Domain flags to be cleared.
* This parameter can be one of the following values:
* @arg PWR_D1_DOMAIN_FLAGS: Clear D1 Domain flags.
* @arg PWR_D2_DOMAIN_FLAGS: Clear D2 Domain flags.
* @retval None.
*/
void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags)
{
/* Check the parameters */
assert_param(IS_PWR_DOMAIN_FLAG(DomainFlags));
if (DomainFlags == PWR_D1_DOMAIN_FLAGS)
{
/* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
}
else
{
/* Clear D2 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF);
}
}
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
/**
* @brief Hold the CPU and their allocated peripherals when exiting from STOP mode.
* @param CPU: Specifies the core to be held.
* This parameter can be one of the following values:
* @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master.
* @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_PWR_CORE(CPU));
if (PWR_CORE_CPU2 == CPU)
{
/* If CPU1 is not held */
if(PWR_CPU2CR_HOLD1 != (PWR->CPU2CR & PWR_CPU2CR_HOLD1))
{
/* Set HOLD2 bit */
SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
}
else
{
status = HAL_ERROR;
}
}
else if (PWR_CORE_CPU1 == CPU)
{
/* If CPU2 is not held */
if(PWR_CPUCR_HOLD2 != (PWR->CPUCR & PWR_CPUCR_HOLD2))
{
/* Set HOLD1 bit */
SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
}
else
{
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
}
return status;
}
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
/**
* @brief Release the CPU and their allocated peripherals after a wake-up from STOP mode.
* @param CPU: Specifies the core to be released.
* This parameter can be one of the following values:
* @arg PWR_CORE_CPU1: Release the CPU1 and their allocated peripherals from holding.
* @arg PWR_CORE_CPU2: Release the CPU2 and their allocated peripherals from holding.
* @retval None
*/
void HAL_PWREx_ReleaseCore(uint32_t CPU)
{
/* Check the parameters */
assert_param(IS_PWR_CORE(CPU));
if (PWR_CORE_CPU2 == CPU)
{
/* Reset HOLD2 bit */
CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
}
else
{
/* Reset HOLD1 bit */
CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
}
}
#endif /*DUAL_CORE*/
/**
* @brief Enable the Flash Power Down in Stop mode.
* @retval None
@ -622,10 +897,10 @@ void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams)
/* Enable and Specify the Wake-Up pin polarity and the pull configuration
for the event detection (rising or falling edge) */
MODIFY_REG(PWR->WKUPEPR, regMask, pinConfig);
#ifndef DUAL_CORE
/* Configure the Wakeup Pin EXTI Line */
MODIFY_REG(EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos));
#endif
}
/**
@ -1189,11 +1464,14 @@ void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD)
MODIFY_REG(PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
/* Clear any previous config */
#if !defined (DUAL_CORE)
__HAL_PWR_AVD_EXTI_DISABLE_EVENT();
__HAL_PWR_AVD_EXTI_DISABLE_IT();
#endif
__HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();
__HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();
#if !defined (DUAL_CORE)
/* Configure the interrupt mode */
if(AVD_MODE_IT == (sConfigAVD->Mode & AVD_MODE_IT))
{
@ -1205,7 +1483,7 @@ void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD)
{
__HAL_PWR_AVD_EXTI_ENABLE_EVENT();
}
#endif
/* Configure the edge */
if(AVD_RISING_EDGE == (sConfigAVD->Mode & AVD_RISING_EDGE))
{
@ -1245,6 +1523,65 @@ void HAL_PWREx_DisableAVD(void)
*/
void HAL_PWREx_PVD_AVD_IRQHandler(void)
{
#if defined(DUAL_CORE)
/* PVD EXTI line interrupt detected */
if(READ_BIT(PWR->CR1, PWR_CR1_PVDEN) != 0U)
{
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Check PWR D1 EXTI flag */
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback();
/* Clear PWR EXTI D1 pending bit */
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
}
}
else
{
/* Check PWR EXTI D2 flag */
if(__HAL_PWR_PVD_EXTID2_GET_FLAG() != RESET)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback();
/* Clear PWR EXTI D2 pending bit */
__HAL_PWR_PVD_EXTID2_CLEAR_FLAG();
}
}
}
/* AVD EXTI line interrupt detected */
if(READ_BIT(PWR->CR1, PWR_CR1_AVDEN) != 0U)
{
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
/* Check PWR EXTI D1 flag */
if(__HAL_PWR_AVD_EXTI_GET_FLAG() != RESET)
{
/* PWR AVD interrupt user callback */
HAL_PWREx_AVDCallback();
/* Clear PWR EXTI D1 pending bit */
__HAL_PWR_AVD_EXTI_CLEAR_FLAG();
}
}
else
{
/* Check PWR EXTI D2 flag */
if(__HAL_PWR_AVD_EXTID2_GET_FLAG() != RESET)
{
/* PWR AVD interrupt user callback */
HAL_PWREx_AVDCallback();
/* Clear PWR EXTI D2 pending bit */
__HAL_PWR_AVD_EXTID2_CLEAR_FLAG();
}
}
}
#else
/* PVD EXTI line interrupt detected */
if(READ_BIT(PWR->CR1, PWR_CR1_PVDEN) != 0U)
{
@ -1272,6 +1609,7 @@ void HAL_PWREx_PVD_AVD_IRQHandler(void)
__HAL_PWR_AVD_EXTI_CLEAR_FLAG();
}
}
#endif /*DUAL_CORE*/
}
/**

112
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_pwr_ex.h
View File

@ -135,6 +135,17 @@ typedef struct
* @}
*/
#if defined(DUAL_CORE)
/** @defgroup PWREx_Core_Select PWREx Core definition
* @{
*/
#define PWR_CORE_CPU1 ((uint32_t)0x00000000U)
#define PWR_CORE_CPU2 ((uint32_t)0x00000001U)
/**
* @}
*/
#endif /*DUAL_CORE*/
/** @defgroup PWREx_Domains PWREx Domains definition
* @{
*/
@ -148,7 +159,12 @@ typedef struct
/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
* @{
*/
#if defined(DUAL_CORE)
#define PWR_D1_DOMAIN_FLAGS ((uint32_t)0x00000000U)
#define PWR_D2_DOMAIN_FLAGS ((uint32_t)0x00000001U)
#else
#define PWR_CPU_FLAGS ((uint32_t)0x00000000U)
#endif /*DUAL_CORE*/
/**
* @}
*/
@ -167,8 +183,23 @@ typedef struct
* @{
*/
#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */
#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< the LDO Bypass. The Core domain is supplied from an external source */
#if defined(SMPS)
#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are suppplied from the SMPS only */
#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */
#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */
#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */
#define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */
#endif /* SMPS */
#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */
#if defined(SMPS)
#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
#else
#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
#endif /* SMPS */
/**
* @}
*/
@ -258,24 +289,56 @@ typedef struct
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
#if defined(DUAL_CORE)
/**
* @brief Enable the AVD EXTI D2 Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
#endif /*DUAL_CORE*/
/**
* @brief Disable the AVD EXTI Line 16
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
#if defined(DUAL_CORE)
/**
* @brief Disable the AVD EXTI D2 Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
#endif /*DUAL_CORE*/
/**
* @brief Enable event on AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
#if defined(DUAL_CORE)
/**
* @brief Enable event on AVD EXTI D2 Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
#endif /*DUAL_CORE*/
/**
* @brief Disable event on AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
#if defined(DUAL_CORE)
/**
* @brief Disable event on AVD EXTI D2 Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
#endif /*DUAL_CORE*/
/**
* @brief Enable the AVD Extended Interrupt Rising Trigger.
* @retval None.
@ -327,12 +390,28 @@ do { \
*/
#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET)
#if defined(DUAL_CORE)
/**
* @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.
* @retval EXTI D2 AVD Line Status.
*/
#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET)
#endif /*DUAL_CORE*/
/**
* @brief Clear the AVD EXTI flag.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
#if defined(DUAL_CORE)
/**
* @brief Clear the AVD EXTI D2 flag.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
#endif /*DUAL_CORE*/
/**
* @}
*/
@ -365,6 +444,15 @@ void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Dom
void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
#if defined(DUAL_CORE)
void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags);
/* Power core holding functions */
HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);
void HAL_PWREx_ReleaseCore(uint32_t CPU);
#endif /*DUAL_CORE*/
/* Clear pending event function */
void HAL_PWREx_ClearPendingEvent(void);
@ -445,8 +533,21 @@ void HAL_PWREx_AVDCallback(void);
/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
* @{
*/
#if defined(SMPS)
#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) || \
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) || \
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) || \
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) || \
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) || \
((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
#else
#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
#endif /*SMPS*/
#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) || \
((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) || \
@ -504,6 +605,15 @@ void HAL_PWREx_AVDCallback(void);
#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
#if defined(DUAL_CORE)
#define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)
#define IS_PWR_DOMAIN_FLAG(FLAG) (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \
((FLAG) == PWR_D2_DOMAIN_FLAGS))
#endif /*DUAL_CORE*/
/**
* @}
*/

16
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ramecc.c
View File

@ -294,10 +294,10 @@ HAL_StatusTypeDef HAL_RAMECC_StopMonitor(RAMECC_HandleTypeDef *hramecc)
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @param Noftications Select the notification.
* @param Notifications Select the notification.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMECC_EnableNotifiaction(RAMECC_HandleTypeDef *hramecc, uint32_t Noftications)
HAL_StatusTypeDef HAL_RAMECC_EnableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
{
/* Check the RAMECC peripheral handle */
if(hramecc == NULL)
@ -310,12 +310,12 @@ HAL_StatusTypeDef HAL_RAMECC_EnableNotifiaction(RAMECC_HandleTypeDef *hramecc, u
/* Check the parameters */
assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance));
assert_param(IS_RAMECC_INTERRUPT(Noftications));
assert_param(IS_RAMECC_INTERRUPT(Notifications));
if((state == HAL_RAMECC_STATE_READY) || (state == HAL_RAMECC_STATE_BUSY))
{
/* Enable RAMECC interrupts */
__HAL_RAMECC_ENABLE_IT(hramecc, Noftications);
__HAL_RAMECC_ENABLE_IT(hramecc, Notifications);
}
else
{
@ -334,10 +334,10 @@ HAL_StatusTypeDef HAL_RAMECC_EnableNotifiaction(RAMECC_HandleTypeDef *hramecc, u
* @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains
* the configuration information for the specified RAMECC
* Monitor.
* @param Noftications Select the notification.
* @param Notifications Select the notification.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_RAMECC_DisableNotifiaction(RAMECC_HandleTypeDef *hramecc, uint32_t Noftications)
HAL_StatusTypeDef HAL_RAMECC_DisableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications)
{
/* Check the RAMECC peripheral handle */
if(hramecc == NULL)
@ -350,12 +350,12 @@ HAL_StatusTypeDef HAL_RAMECC_DisableNotifiaction(RAMECC_HandleTypeDef *hramecc,
/* Check the parameters */
assert_param(IS_RAMECC_MONITOR_ALL_INSTANCE(hramecc->Instance));
assert_param(IS_RAMECC_INTERRUPT(Noftications));
assert_param(IS_RAMECC_INTERRUPT(Notifications));
if((state == HAL_RAMECC_STATE_READY) || (state == HAL_RAMECC_STATE_BUSY))
{
/* Disable RAMECC interrupts */
__HAL_RAMECC_DISABLE_IT(hramecc, Noftications);
__HAL_RAMECC_DISABLE_IT(hramecc, Notifications);
}
else
{

4
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_ramecc.h
View File

@ -218,8 +218,8 @@ HAL_StatusTypeDef HAL_RAMECC_DeInit(RAMECC_HandleTypeDef *hramecc);
*/
HAL_StatusTypeDef HAL_RAMECC_StartMonitor(RAMECC_HandleTypeDef *hramecc);
HAL_StatusTypeDef HAL_RAMECC_StopMonitor(RAMECC_HandleTypeDef *hramecc);
HAL_StatusTypeDef HAL_RAMECC_EnableNotifiaction(RAMECC_HandleTypeDef *hramecc, uint32_t Noftications);
HAL_StatusTypeDef HAL_RAMECC_DisableNotifiaction(RAMECC_HandleTypeDef *hramecc, uint32_t Noftications);
HAL_StatusTypeDef HAL_RAMECC_EnableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
HAL_StatusTypeDef HAL_RAMECC_DisableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
void HAL_RAMECC_IRQHandler(RAMECC_HandleTypeDef *hramecc);
HAL_StatusTypeDef HAL_RAMECC_RegisterCallback(RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc));
HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc);

24
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c
View File

@ -205,7 +205,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
}
/* Set HSITRIM[6:0] bits to the reset value */
SET_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM_5);
SET_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM_6);
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
@ -719,6 +719,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
assert_param(IS_RCC_PLLFRACN_VALUE(RCC_OscInitStruct->PLL.PLLFRACN));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
@ -743,6 +744,9 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
/* Disable PLLFRACN . */
__HAL_RCC_PLLFRACN_DISABLE();
/* Configure PLL PLL1FRACN */
__HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
@ -1361,7 +1365,14 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->CSIState = RCC_CSI_OFF;
}
RCC_OscInitStruct->CSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_CSITRIM) >> RCC_ICSCR_CSITRIM_Pos);
if(HAL_GetREVID() <= REV_ID_Y)
{
RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk) >> HAL_RCC_REV_Y_CSITRIM_Pos);
}
else
{
RCC_OscInitStruct->CSICalibrationValue = (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
}
/* Get the HSI configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
@ -1373,7 +1384,14 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
if(HAL_GetREVID() <= REV_ID_Y)
{
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk) >> HAL_RCC_REV_Y_HSITRIM_Pos);
}
else
{
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
}
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)

2927
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.h
View File

File diff suppressed because it is too large Load Diff

114
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc_ex.c
View File

@ -94,7 +94,7 @@ static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t D
* parameters in the RCC_PeriphCLKInitTypeDef.
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals
* clocks(SDMMC, CKPER, FMC, QSPI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123,
* clocks(SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123,
* USART234578, USART16, RNG, HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
* SAI4A,SAI4B,SPI6,RTC).
* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
@ -567,6 +567,43 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
}
#if defined(DSI)
/*---------------------------- DSI configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI)
{
switch(PeriphClkInit->DsiClockSelection)
{
case RCC_DSICLKSOURCE_PLL2: /* PLL2 is used as clock source for DSI*/
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2),DIVIDER_Q_UPDATE);
/* DSI clock source configuration done later after clock selection check */
break;
case RCC_DSICLKSOURCE_PHY:
/* PHY is used as clock source for DSI*/
/* DSI clock source configuration done later after clock selection check */
break;
default:
ret = HAL_ERROR;
break;
}
if(ret == HAL_OK)
{
/* Set the source of DSI clock*/
__HAL_RCC_DSI_CONFIG(PeriphClkInit->DsiClockSelection);
}
else
{
/* set overall return value */
status = ret;
}
}
#endif /*DSI*/
#if defined(FDCAN1) || defined(FDCAN2)
/*---------------------------- FDCAN configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
@ -1202,6 +1239,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
}
#if defined(LTDC)
/*-------------------------------------- LTDC Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
{
@ -1210,6 +1248,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
status=HAL_ERROR;
}
}
#endif /* LTDC */
/*------------------------------ RNG Configuration -------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
@ -1317,7 +1356,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
* @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers.
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
* returns the configuration information for the Extended Peripherals clocks :
* (SDMMC, CKPER, FMC, QSPI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123,
* (SDMMC, CKPER, FMC, QSPI, DSI, SPI45, SPDIF, DFSDM1, FDCAN, SWPMI,SAI23, SAI1, SPI123,
* USART234578, USART16, RNG,HRTIM1, I2C123, USB,CEC, LPTIM1, LPUART1, I2C4, LPTIM2, LPTIM345, ADC,
* SAI4A,SAI4B,SPI6,RTC,TIM).
* @retval None
@ -1332,8 +1371,12 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
RCC_PERIPHCLK_SPI123 | RCC_PERIPHCLK_SPI45 | RCC_PERIPHCLK_SPI6 | RCC_PERIPHCLK_FDCAN |
RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC |
RCC_PERIPHCLK_SWPMI1 | RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_CEC |
RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_SPDIFRX | RCC_PERIPHCLK_HRTIM1 |
RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_CKPER;
RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_QSPI | RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_SPDIFRX |
RCC_PERIPHCLK_HRTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_CKPER;
#if defined(LTDC)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LTDC;
#endif /* LTDC */
/* Get the PLL3 Clock configuration -----------------------------------------------*/
PeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3)>> RCC_PLLCKSELR_DIVM3_Pos);
@ -1408,6 +1451,11 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
/* Get the QSPI clock source -----------------------------------------------*/
PeriphClkInit->QspiClockSelection = __HAL_RCC_GET_QSPI_SOURCE();
#if defined(DSI)
/* Get the DSI clock source ------------------------------------------------*/
PeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE();
#endif /*DSI*/
/* Get the CKPER clock source ----------------------------------------------*/
PeriphClkInit->CkperClockSelection = __HAL_RCC_GET_CLKP_SOURCE();
@ -1441,7 +1489,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
PLL3_ClocksTypeDef pll3_clocks;
/* This variable is used to store the SAI clock frequency (value in Hz) */
uint32_t frequency = 0;
uint32_t frequency;
/* This variable is used to store the SAI and CKP clock source */
uint32_t saiclocksource;
uint32_t ckpclocksource;
@ -1513,6 +1561,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
default :
{
frequency = 0;
break;
}
}
@ -1584,6 +1633,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
default :
{
frequency = 0;
break;
}
}
@ -1656,6 +1706,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
default :
{
frequency = 0;
break;
}
}
@ -1728,6 +1779,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
default :
{
frequency = 0;
break;
}
}
@ -1799,6 +1851,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
}
default :
{
frequency = 0;
break;
}
}
@ -1857,6 +1910,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
default :
{
frequency = 0;
break;
}
}
@ -2167,6 +2221,43 @@ void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk)
__HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk);
}
#if defined(DUAL_CORE)
/**
* @brief Enable COREx boot independently of CMx_B option byte value
* @param RCC_BootCx: Boot Core to be enabled
* This parameter can be one of the following values:
* @arg RCC_BOOT_C1: CM7 core selection
* @arg RCC_BOOT_C2: CM4 core selection
* @note This bit can be set by software but is cleared by hardware after a system reset or STANDBY
*
* @retval None
*/
void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx)
{
assert_param(IS_RCC_BOOT_CORE(RCC_BootCx));
SET_BIT(RCC->GCR, RCC_BootCx) ;
}
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
/**
* @brief Configure WWDGx to generate a system reset not only CPUx reset(default) when a time-out occurs
* @param RCC_WWDGx: WWDGx to be configured
* This parameter can be one of the following values:
* @arg RCC_WWDG1: WWDG1 generates system reset
* @arg RCC_WWDG2: WWDG2 generates system reset
* @note This bit can be set by software but is cleared by hardware during a system reset
*
* @retval None
*/
void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
{
assert_param(IS_RCC_SCOPE_WWDG(RCC_WWDGx));
SET_BIT(RCC->GCR, RCC_WWDGx) ;
}
#else
/**
* @brief Configure WWDG1 to generate a system reset not only CPU reset(default) when a time-out occurs
@ -2183,6 +2274,8 @@ void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
SET_BIT(RCC->GCR, RCC_WWDGx) ;
}
#endif /*DUAL_CORE*/
/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
* @brief Extended Clock Recovery System Control functions
@ -2274,8 +2367,15 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
/* Set the SYNCDIV[2:0] bits according to Pre-scaler value */
/* Set the SYNCSRC[1:0] bits according to Source value */
/* Set the SYNCSPOL bit according to Polarity value */
value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
if ((HAL_GetREVID() <= REV_ID_Y) && (pInit->Source == RCC_CRS_SYNC_SOURCE_USB2))
{
/* Use Rev.Y value of USB2 */
value = (pInit->Prescaler | RCC_CRS_SYNC_SOURCE_PIN | pInit->Polarity);
}
else
{
value = (pInit->Prescaler | pInit->Source | pInit->Polarity);
}
/* Set the RELOAD[15:0] bits according to ReloadValue value */
value |= pInit->ReloadValue;
/* Set the FELIM[7:0] bits according to ErrorLimitValue value */

251
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc_ex.h
View File

@ -152,6 +152,10 @@ typedef struct
uint32_t QspiClockSelection; /*!< Specifies QSPI clock source
This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */
#if defined(DSI)
uint32_t DsiClockSelection; /*!< Specifies DSI clock source
This parameter can be a value of @ref RCCEx_DSI_Clock_Source */
#endif /*DSI*/
uint32_t SdmmcClockSelection; /*!< Specifies SDMMC clock source
This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */
@ -348,9 +352,14 @@ typedef struct
#define RCC_PERIPHCLK_CEC (0x00800000U)
#define RCC_PERIPHCLK_FMC (0x01000000U)
#define RCC_PERIPHCLK_QSPI (0x02000000U)
#define RCC_PERIPHCLK_DSI (0x04000000U)
#define RCC_PERIPHCLK_SPDIFRX (0x08000000U)
#define RCC_PERIPHCLK_HRTIM1 (0x10000000U)
#if defined(LTDC)
#define RCC_PERIPHCLK_LTDC (0x20000000U)
#endif /* LTDC */
#define RCC_PERIPHCLK_TIM (0x40000000U)
#define RCC_PERIPHCLK_CKPER (0x80000000U)
@ -966,6 +975,17 @@ typedef struct
/**
* @}
*/
#if defined(DSI)
/** @defgroup RCCEx_DSI_Clock_Source RCCEx DSI Clock Source
* @{
*/
#define RCC_DSICLKSOURCE_PHY (0x00000000U)
#define RCC_DSICLKSOURCE_PLL2 RCC_D1CCIPR_DSISEL
/**
* @}
*/
#endif /*DSI*/
/** @defgroup RCCEx_FMC_Clock_Source RCCEx FMC Clock Source
* @{
@ -1087,6 +1107,31 @@ typedef struct
* @}
*/
#if defined(DUAL_CORE)
/** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx
* @{
*/
#define RCC_BOOT_C1 RCC_GCR_BOOT_C1
#define RCC_BOOT_C2 RCC_GCR_BOOT_C2
/**
* @}
*/
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
/** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx
* @{
*/
#define RCC_WWDG1 RCC_GCR_WW1RSC
#define RCC_WWDG2 RCC_GCR_WW2RSC
/**
* @}
*/
#else
/** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx
* @{
@ -1097,6 +1142,8 @@ typedef struct
* @}
*/
#endif /*DUAL_CORE*/
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
* @{
*/
@ -1114,10 +1161,10 @@ typedef struct
/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
* @{
*/
#define RCC_CRS_SYNC_SOURCE_USB2 (0x00000000U) /*!< Synchro Signal source USB2 SOF */
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB1 SOF (default) */
#define RCC_CRS_SYNC_SOURCE_PIN (0x00000000U) /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and abobe devices only */
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB1 SOF (default) */
#define RCC_CRS_SYNC_SOURCE_USB2 (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0) /*!< Synchro Signal source USB2 SOF */
/**
@ -1238,7 +1285,7 @@ typedef struct
* @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
* @note Enabling/disabling those Clocks can be done only when the PLL2 is disabled,
* This is mainly used to save Power.
* @param __RCC_PLL2ClockOut__: Specifies the PLL2 clock to be outputted
* @param __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted
* This parameter can be one of the following values:
* @arg RCC_PLL2_DIVP: This clock is used to generate system clock (up to 400MHZ)
* @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
@ -1262,24 +1309,24 @@ typedef struct
* @brief Macro to configures the PLL2 multiplication and division factors.
* @note This function must be used only when PLL2 is disabled.
*
* @param __PLL2M__: specifies the division factor for PLL2 VCO input clock
* @param __PLL2M__ specifies the division factor for PLL2 VCO input clock
* This parameter must be a number between 1 and 63.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 16 MHz.
*
* @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock
* @param __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock
* This parameter must be a number between 4 and 512.
* @note You have to set the PLL2N parameter correctly to ensure that the VCO
* output frequency is between 150 and 420 MHz (when in medium VCO range) or
* between 192 and 836 MHZ (when in wide VCO range)
*
* @param __PLL2P__: specifies the division factor for peripheral kernel clocks
* @param __PLL2P__ specifies the division factor for peripheral kernel clocks
* This parameter must be a number between 2 and 128 (where odd numbers not allowed)
*
* @param __PLL2Q__: specifies the division factor for peripheral kernel clocks
* @param __PLL2Q__ specifies the division factor for peripheral kernel clocks
* This parameter must be a number between 1 and 128
*
* @param __PLL2R__: specifies the division factor for peripheral kernel clocks
* @param __PLL2R__ specifies the division factor for peripheral kernel clocks
* This parameter must be a number between 1 and 128
*
* @retval None
@ -1296,7 +1343,7 @@ typedef struct
*
* @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
*
* @param __RCC_PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO
* @param __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO
* It should be a value between 0 and 8191
* @note Warning: the software has to set correctly these bits to insure that the VCO
* output frequency is between its valid frequency range, which is:
@ -1309,7 +1356,7 @@ typedef struct
#define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,(uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)
/** @brief Macro to select the PLL2 reference frequency range.
* @param __RCC_PLL2VCIRange__: specifies the PLL2 input frequency range
* @param __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range
* This parameter can be one of the following values:
* @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
* @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
@ -1322,7 +1369,7 @@ typedef struct
/** @brief Macro to select the PLL2 reference frequency range.
* @param __RCC_PLL2VCORange__: Specifies the PLL2 input frequency range
* @param __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range
* This parameter can be one of the following values:
* @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz
* @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
@ -1353,7 +1400,7 @@ typedef struct
* @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
* @note Enabling/disabling those Clocks can be done only when the PLL3 is disabled,
* This is mainly used to save Power.
* @param __RCC_PLL3ClockOut__: specifies the PLL3 clock to be outputted
* @param __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted
* This parameter can be one of the following values:
* @arg RCC_PLL3_DIVP: This clock is used to generate system clock (up to 400MHZ)
* @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
@ -1368,24 +1415,24 @@ typedef struct
* @brief Macro to configures the PLL3 multiplication and division factors.
* @note This function must be used only when PLL3 is disabled.
*
* @param __PLL3M__: specifies the division factor for PLL3 VCO input clock
* @param __PLL3M__ specifies the division factor for PLL3 VCO input clock
* This parameter must be a number between 1 and 63.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 16 MHz.
*
* @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock
* @param __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock
* This parameter must be a number between 4 and 512.
* @note You have to set the PLL3N parameter correctly to ensure that the VCO
* output frequency is between 150 and 420 MHz (when in medium VCO range) or
* between 192 and 836 MHZ (when in wide VCO range)
*
* @param __PLL3P__: specifies the division factor for peripheral kernel clocks
* @param __PLL3P__ specifies the division factor for peripheral kernel clocks
* This parameter must be a number between 2 and 128 (where odd numbers not allowed)
*
* @param __PLL3Q__: specifies the division factor for peripheral kernel clocks
* @param __PLL3Q__ specifies the division factor for peripheral kernel clocks
* This parameter must be a number between 1 and 128
*
* @param __PLL3R__: specifies the division factor for peripheral kernel clocks
* @param __PLL3R__ specifies the division factor for peripheral kernel clocks
* This parameter must be a number between 1 and 128
*
* @retval None
@ -1404,7 +1451,7 @@ typedef struct
*
* @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
*
* @param __RCC_PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO
* @param __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO
* It should be a value between 0 and 8191
* @note Warning: the software has to set correctly these bits to insure that the VCO
* output frequency is between its valid frequency range, which is:
@ -1417,7 +1464,7 @@ typedef struct
#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
/** @brief Macro to select the PLL3 reference frequency range.
* @param __RCC_PLL3VCIRange__: specifies the PLL1 input frequency range
* @param __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range
* This parameter can be one of the following values:
* @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
* @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
@ -1430,7 +1477,7 @@ typedef struct
/** @brief Macro to select the PLL3 reference frequency range.
* @param __RCC_PLL3VCORange__: specifies the PLL1 input frequency range
* @param __RCC_PLL3VCORange__ specifies the PLL1 input frequency range
* This parameter can be one of the following values:
* @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz
* @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
@ -1440,7 +1487,7 @@ typedef struct
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
/**
* @brief Macro to Configure the SAI1 clock source.
* @param __RCC_SAI1CLKSource__: defines the SAI1 clock source. This clock is derived
* @param __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived
* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
* This parameter can be one of the following values:
* @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
@ -1465,7 +1512,7 @@ typedef struct
/**
* @brief Macro to Configure the SPDIFRX clock source.
* @param __RCC_SPDIFCLKSource__: defines the SPDIFRX clock source. This clock is derived
* @param __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived
* from system PLL, PLL2, PLL3, or internal OSC clock
* This parameter can be one of the following values:
* @arg RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL
@ -1484,7 +1531,7 @@ typedef struct
/**
* @brief Macro to Configure the SAI2/3 clock source.
* @param __RCC_SAI23CLKSource__: defines the SAI2/3 clock source. This clock is derived
* @param __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived
* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
* This parameter can be one of the following values:
* @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
@ -1509,7 +1556,7 @@ typedef struct
/**
* @brief Macro to Configure the SAI2 clock source.
* @param __RCC_SAI2CLKSource__: defines the SAI2 clock source. This clock is derived
* @param __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived
* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
* This parameter can be one of the following values:
* @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
@ -1534,7 +1581,7 @@ typedef struct
/**
* @brief Macro to Configure the SAI3 clock source.
* @param __RCC_SAI3CLKSource__: defines the SAI3 clock source. This clock is derived
* @param __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived
* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
* This parameter can be one of the following values:
* @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
@ -1559,7 +1606,7 @@ typedef struct
/**
* @brief Macro to Configure the SAI4A clock source.
* @param __RCC_SAI4ACLKSource__: defines the SAI4A clock source. This clock is derived
* @param __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived
* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
* This parameter can be one of the following values:
* @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL
@ -1584,7 +1631,7 @@ typedef struct
/**
* @brief Macro to Configure the SAI4B clock source.
* @param __RCC_SAI4BCLKSource__: defines the SAI4B clock source. This clock is derived
* @param __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived
* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
* This parameter can be one of the following values:
* @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
@ -1609,7 +1656,7 @@ typedef struct
/** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).
*
* @param __I2C123CLKSource__: specifies the I2C1/2/3 clock source.
* @param __I2C123CLKSource__ specifies the I2C1/2/3 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
* @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
@ -1630,7 +1677,7 @@ typedef struct
/** @brief macro to configure the I2C1 clock (I2C1CLK).
*
* @param __I2C1CLKSource__: specifies the I2C1 clock source.
* @param __I2C1CLKSource__ specifies the I2C1 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
* @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
@ -1651,7 +1698,7 @@ typedef struct
/** @brief macro to configure the I2C2 clock (I2C2CLK).
*
* @param __I2C2CLKSource__: specifies the I2C2 clock source.
* @param __I2C2CLKSource__ specifies the I2C2 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
* @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
@ -1672,7 +1719,7 @@ typedef struct
/** @brief macro to configure the I2C3 clock (I2C3CLK).
*
* @param __I2C3CLKSource__: specifies the I2C3 clock source.
* @param __I2C3CLKSource__ specifies the I2C3 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
* @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
@ -1693,7 +1740,7 @@ typedef struct
/** @brief macro to configure the I2C4 clock (I2C4CLK).
*
* @param __I2C4CLKSource__: specifies the I2C4 clock source.
* @param __I2C4CLKSource__ specifies the I2C4 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
* @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
@ -1714,7 +1761,7 @@ typedef struct
/** @brief macro to configure the USART1/6 clock (USART16CLK).
*
* @param __USART16CLKSource__: specifies the USART1/6 clock source.
* @param __USART16CLKSource__ specifies the USART1/6 clock source.
* This parameter can be one of the following values:
* @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock
* @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock
@ -1739,7 +1786,7 @@ typedef struct
/** @brief macro to configure the USART234578 clock (USART234578CLK).
*
* @param __USART234578CLKSource__: specifies the USART2/3/4/5/7/8 clock source.
* @param __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source.
* This parameter can be one of the following values:
* @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
* @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
@ -1764,7 +1811,7 @@ typedef struct
/** @brief macro to configure the USART1 clock (USART1CLK).
*
* @param __USART1CLKSource__: specifies the USART1 clock source.
* @param __USART1CLKSource__ specifies the USART1 clock source.
* This parameter can be one of the following values:
* @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
* @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
@ -1789,7 +1836,7 @@ typedef struct
/** @brief macro to configure the USART2 clock (USART2CLK).
*
* @param __USART2CLKSource__: specifies the USART2 clock source.
* @param __USART2CLKSource__ specifies the USART2 clock source.
* This parameter can be one of the following values:
* @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
* @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
@ -1814,7 +1861,7 @@ typedef struct
/** @brief macro to configure the USART3 clock (USART3CLK).
*
* @param __USART3CLKSource__: specifies the USART3 clock source.
* @param __USART3CLKSource__ specifies the USART3 clock source.
* This parameter can be one of the following values:
* @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
* @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
@ -1839,7 +1886,7 @@ typedef struct
/** @brief macro to configure the UART4 clock (UART4CLK).
*
* @param __UART4CLKSource__: specifies the UART4 clock source.
* @param __UART4CLKSource__ specifies the UART4 clock source.
* This parameter can be one of the following values:
* @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
* @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
@ -1864,7 +1911,7 @@ typedef struct
/** @brief macro to configure the UART5 clock (UART5CLK).
*
* @param __UART5CLKSource__: specifies the UART5 clock source.
* @param __UART5CLKSource__ specifies the UART5 clock source.
* This parameter can be one of the following values:
* @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
* @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
@ -1889,7 +1936,7 @@ typedef struct
/** @brief macro to configure the USART6 clock (USART6CLK).
*
* @param __USART6CLKSource__: specifies the USART6 clock source.
* @param __USART6CLKSource__ specifies the USART6 clock source.
* This parameter can be one of the following values:
* @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
* @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
@ -1914,7 +1961,7 @@ typedef struct
/** @brief macro to configure the UART5 clock (UART7CLK).
*
* @param __UART7CLKSource__: specifies the UART7 clock source.
* @param __UART7CLKSource__ specifies the UART7 clock source.
* This parameter can be one of the following values:
* @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
* @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
@ -1939,7 +1986,7 @@ typedef struct
/** @brief macro to configure the UART8 clock (UART8CLK).
*
* @param __UART8CLKSource__: specifies the UART8 clock source.
* @param __UART8CLKSource__ specifies the UART8 clock source.
* This parameter can be one of the following values:
* @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
* @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
@ -1964,7 +2011,7 @@ typedef struct
/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
*
* @param __LPUART1CLKSource__: specifies the LPUART1 clock source.
* @param __LPUART1CLKSource__ specifies the LPUART1 clock source.
* This parameter can be one of the following values:
* @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
* @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
@ -1987,8 +2034,10 @@ typedef struct
*/
#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
/** @brief macro to get the LPTIM1 clock source.
* @retval The clock source can be one of the following values:
/** @brief macro to configure the LPTIM1 clock source.
*
* @param __LPTIM1CLKSource__ specifies the LPTIM1 clock source.
* This parameter can be one of the following values:
* @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
* @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
* @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
@ -2011,8 +2060,10 @@ typedef struct
*/
#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
/** @brief macro to get the LPTIM2 clock source.
* @retval The clock source can be one of the following values:
/** @brief macro to configure the LPTIM2 clock source.
*
* @param __LPTIM2CLKSource__ specifies the LPTIM2 clock source.
* This parameter can be one of the following values:
* @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
* @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
* @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
@ -2035,8 +2086,9 @@ typedef struct
*/
#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
/** @brief macro to get the LPTIM3/4/5 clock source.
* @retval The clock source can be one of the following values:
/** @brief macro to configure the LPTIM3/4/5 clock source.
*
* @param __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source.
* @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
* @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
* @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
@ -2059,8 +2111,9 @@ typedef struct
*/
#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
/** @brief macro to get the LPTIM3 clock source.
* @retval The clock source can be one of the following values:
/** @brief macro to configure the LPTIM3 clock source.
*
* @param __LPTIM3CLKSource__ specifies the LPTIM3 clock source.
* @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
* @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
* @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
@ -2083,8 +2136,9 @@ typedef struct
*/
#define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
/** @brief macro to get the LPTIM4 clock source.
* @retval The clock source can be one of the following values:
/** @brief macro to configure the LPTIM4 clock source.
*
* @param __LPTIM4CLKSource__ specifies the LPTIM4 clock source.
* @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
* @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
* @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
@ -2108,7 +2162,8 @@ typedef struct
#define __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
/** @brief macro to configure the LPTIM5 clock source.
* @retval The clock source can be one of the following values:
*
* @param __LPTIM5CLKSource__ specifies the LPTIM5 clock source.
* @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
* @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
* @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
@ -2132,7 +2187,8 @@ typedef struct
#define __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
/** @brief macro to configure the QSPI clock source.
* @retval The clock source can be one of the following values:
*
* @param __QSPICLKSource__ specifies the QSPI clock source.
* @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
* @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock
* @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock
@ -2151,8 +2207,28 @@ typedef struct
*/
#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
/** @brief macro to configure the FMC clock source.
#if defined(DSI)
/** @brief macro to configure the DSI clock source.
*
* @param __DSICLKSource__ specifies the DSI clock source.
* @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock
* @arg RCC_RCC_DSICLKSOURCE_PLL2 : PLL2_Q Clock clock is selected as DSI byte lane clock
*/
#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \
MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))
/** @brief macro to get the DSI clock source.
* @retval The clock source can be one of the following values:
* @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock
* @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock
*/
#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))
#endif /*DSI*/
/** @brief macro to configure the FMC clock source.
*
* @param __FMCCLKSource__ specifies the FMC clock source.
* @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
* @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
* @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
@ -2172,7 +2248,7 @@ typedef struct
#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
/** @brief Macro to configure the USB clock (USBCLK).
* @param __USBCLKSource__: specifies the USB clock source.
* @param __USBCLKSource__ specifies the USB clock source.
* This parameter can be one of the following values:
* @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
* @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
@ -2191,7 +2267,7 @@ typedef struct
/** @brief Macro to configure the ADC clock
* @param __ADCCLKSource__: specifies the ADC digital interface clock source.
* @param __ADCCLKSource__ specifies the ADC digital interface clock source.
* This parameter can be one of the following values:
* @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
* @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
@ -2209,7 +2285,7 @@ typedef struct
#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
/** @brief Macro to configure the SWPMI1 clock
* @param __SWPMI1CLKSource__: specifies the SWPMI1 clock source.
* @param __SWPMI1CLKSource__ specifies the SWPMI1 clock source.
* This parameter can be one of the following values:
* @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
* @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
@ -2225,7 +2301,7 @@ typedef struct
#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
/** @brief Macro to configure the DFSDM1 clock
* @param __DFSDM1CLKSource__: specifies the DFSDM1 clock source.
* @param __DFSDM1CLKSource__ specifies the DFSDM1 clock source.
* This parameter can be one of the following values:
* @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
* @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
@ -2242,7 +2318,7 @@ typedef struct
/** @brief macro to configure the CEC clock (CECCLK).
*
* @param __CECCLKSource__: specifies the CEC clock source.
* @param __CECCLKSource__ specifies the CEC clock source.
* This parameter can be one of the following values:
* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
* @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
@ -2261,7 +2337,7 @@ typedef struct
/** @brief Macro to configure the CLKP : Oscillator clock for peripheral
* @param __CLKPSource__: specifies Oscillator clock for peripheral
* @param __CLKPSource__ specifies Oscillator clock for peripheral
* This parameter can be one of the following values:
* @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
* @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
@ -2280,7 +2356,7 @@ typedef struct
#if defined(FDCAN1) || defined(FDCAN2)
/** @brief Macro to configure the FDCAN clock
* @param __FDCANCLKSource__: specifies clock source for FDCAN
* @param __FDCANCLKSource__ specifies clock source for FDCAN
* This parameter can be one of the following values:
* @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
* @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
@ -2299,7 +2375,7 @@ typedef struct
#endif /*FDCAN1 || FDCAN2*/
/**
* @brief Macro to Configure the SPI1/2/3 clock source.
* @param __RCC_SPI123CLKSource__: defines the SPI1/2/3 clock source. This clock is derived
* @param __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived
* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
* This parameter can be one of the following values:
* @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
@ -2324,7 +2400,7 @@ typedef struct
/**
* @brief Macro to Configure the SPI1 clock source.
* @param __RCC_SPI1CLKSource__: defines the SPI1 clock source. This clock is derived
* @param __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived
* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
* This parameter can be one of the following values:
* @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
@ -2349,7 +2425,7 @@ typedef struct
/**
* @brief Macro to Configure the SPI2 clock source.
* @param __RCC_SPI2CLKSource__: defines the SPI2 clock source. This clock is derived
* @param __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived
* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
* This parameter can be one of the following values:
* @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
@ -2374,7 +2450,7 @@ typedef struct
/**
* @brief Macro to Configure the SPI3 clock source.
* @param __RCC_SPI3CLKSource__: defines the SPI3 clock source. This clock is derived
* @param __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived
* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
* This parameter can be one of the following values:
* @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
@ -2399,7 +2475,7 @@ typedef struct
/**
* @brief Macro to Configure the SPI4/5 clock source.
* @param __RCC_SPI45CLKSource__: defines the SPI4/5 clock source. This clock is derived
* @param __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived
* from system PCLK, PLL2, PLL3, OSC
* This parameter can be one of the following values:
* @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
@ -2426,7 +2502,7 @@ typedef struct
/**
* @brief Macro to Configure the SPI4 clock source.
* @param __RCC_SPI4CLKSource__: defines the SPI4 clock source. This clock is derived
* @param __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived
* from system PCLK, PLL2, PLL3, OSC
* This parameter can be one of the following values:
* @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
@ -2453,7 +2529,7 @@ typedef struct
/**
* @brief Macro to Configure the SPI5 clock source.
* @param __RCC_SPI5CLKSource__: defines the SPI5 clock source. This clock is derived
* @param __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived
* from system PCLK, PLL2, PLL3, OSC
* This parameter can be one of the following values:
* @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
@ -2480,7 +2556,7 @@ typedef struct
/**
* @brief Macro to Configure the SPI6 clock source.
* @param __RCC_SPI6CLKSource__: defines the SPI6 clock source. This clock is derived
* @param __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived
* from system PCLK, PLL2, PLL3, OSC
* This parameter can be one of the following values:
* @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
@ -2506,7 +2582,7 @@ typedef struct
#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
/** @brief Macro to configure the SDMMC clock
* @param __SDMMCCLKSource__: specifies clock source for SDMMC
* @param __SDMMCCLKSource__ specifies clock source for SDMMC
* This parameter can be one of the following values:
* @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock
* @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock
@ -2520,7 +2596,7 @@ typedef struct
/** @brief macro to configure the RNG clock (RNGCLK).
*
* @param __RNGCLKSource__: specifies the RNG clock source.
* @param __RNGCLKSource__ specifies the RNG clock source.
* This parameter can be one of the following values:
* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
* @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
@ -2560,7 +2636,7 @@ typedef struct
#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
/** @brief Macro to configure the Timers clocks prescalers
* @param __PRESC__ : specifies the Timers clocks prescalers selection
* @param __PRESC__ specifies the Timers clocks prescalers selection
* This parameter can be one of the following values:
* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
* equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,
@ -2756,6 +2832,9 @@ void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
void HAL_RCCEx_EnableLSECSS(void);
void HAL_RCCEx_DisableLSECSS(void);
#if defined(DUAL_CORE)
void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);
#endif /*DUAL_CORE*/
void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
/**
* @}
@ -3090,6 +3169,12 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) || \
((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
#if defined(DSI)
#define IS_RCC_DSICLK(__SOURCE__) \
(((__SOURCE__) == RCC_DSICLKSOURCE_PHY) || \
((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))
#endif /*DSI*/
#define IS_RCC_FMCCLK(__SOURCE__) \
(((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) || \
((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) || \
@ -3133,13 +3218,23 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
(((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
((VALUE) == RCC_TIMPRES_ACTIVATED))
#if defined(DUAL_CORE)
#define IS_RCC_BOOT_CORE(CORE) (((CORE) == RCC_BOOT_C1) || \
((CORE) == RCC_BOOT_C2))
#endif /*DUAL_CORE*/
#if defined(DUAL_CORE)
#define IS_RCC_SCOPE_WWDG(WWDG) (((WWDG) == RCC_WWDG1) || \
((WWDG) == RCC_WWDG2))
#else
#define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1)
#endif /*DUAL_CORE*/
#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1))
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))
#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \

13
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rtc.c
View File

@ -1400,8 +1400,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
__HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
}
#if !defined(DUAL_CORE)
/* RTC Alarm Interrupt Configuration: EXTI configuration */
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
#endif
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
/* Enable the write protection for RTC registers */
@ -1583,7 +1585,18 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
{
/* Clear the EXTI's line Flag for RTC Alarm */
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
__HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
}
else
{
__HAL_RTC_ALARM_EXTID2_CLEAR_FLAG();
}
#else
__HAL_RTC_ALARM_EXTI_CLEAR_FLAG();
#endif
/* Get the AlarmA interrupt source enable status */
if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0u)

39
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rtc.h
View File

@ -618,6 +618,32 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
#if defined(DUAL_CORE)
/**
* @brief Enable interrupt on the RTC Alarm associated D2 Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTID2_ENABLE_IT() (EXTI_D2->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable interrupt on the RTC Alarm associated D2 Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTID2_DISABLE_IT() (EXTI_D2->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable event on the RTC Alarm associated D2 Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTID2_ENABLE_EVENT() (EXTI_D2->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable event on the RTC Alarm associated D2 Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTID2_DISABLE_EVENT() (EXTI_D2->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
#endif
/**
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None
@ -670,6 +696,19 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
*/
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
#if defined(DUAL_CORE)
/**
* @brief Check whether the RTC Alarm associated D2 Exti line interrupt flag is set or not.
* @retval Line Status
*/
#define __HAL_RTC_ALARM_EXTID2_GET_FLAG() (EXTI_D2->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Clear the RTC Alarm associated D2 Exti line flag.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTID2_CLEAR_FLAG() (EXTI_D2->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
#endif
/**
* @brief Generate a Software interrupt on RTC Alarm associated Exti line.
* @retval None

62
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rtc_ex.c
View File

@ -243,8 +243,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti
/* Enable IT timestamp */
__HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
#if !defined(DUAL_CORE)
/* RTC timestamp Interrupt Configuration: EXTI configuration */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
#endif
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
@ -697,8 +699,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType
/* Copy desired configuration into configuration register */
hrtc->Instance->TAMPCR = tmpreg;
/* RTC Tamper Interrupt Configuration: EXTI configuration */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
#if !defined(DUAL_CORE)
/* RTC Tamper Interrupt Configuration: EXTI configuration */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT();
#endif
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();
@ -764,7 +768,18 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T
void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
{
/* Clear the EXTI's Flag for RTC TimeStamp and Tamper */
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
}
else
{
__HAL_RTC_TAMPER_TIMESTAMP_EXTID2_CLEAR_FLAG();
}
#else
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG();
#endif
/* Get the TimeStamp interrupt source enable status */
if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0u)
@ -1222,9 +1237,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t
/* Configure the clock source */
hrtc->Instance->CR |= (uint32_t)WakeUpClock;
#if !defined(DUAL_CORE)
/* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
#endif
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
/* Configure the Interrupt in the RTC_CR register */
@ -1314,22 +1330,32 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
*/
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
{
/* Clear the EXTI's line Flag for RTC WakeUpTimer */
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
/* Get the pending status of the WAKEUPTIMER Interrupt */
if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0u)
{
/* Clear the WAKEUPTIMER interrupt pending bit */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
/* WAKEUPTIMER callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->WakeUpTimerEventCallback(hrtc);
/* Clear the EXTI's line Flag for RTC WakeUpTimer */
#if defined(DUAL_CORE)
if (HAL_GetCurrentCPUID() == CM7_CPUID)
{
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
}
else
{
__HAL_RTC_WAKEUPTIMER_EXTID2_CLEAR_FLAG();
}
#else
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
__HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG();
#endif
/* Get the pending status of the WAKEUPTIMER Interrupt */
if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0u)
{
/* Clear the WAKEUPTIMER interrupt pending bit */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
/* WAKEUPTIMER callback */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
hrtc->WakeUpTimerEventCallback(hrtc);
#else
HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
}
}
/* Change RTC state */
hrtc->State = HAL_RTC_STATE_READY;

83
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rtc_ex.h
View File

@ -726,6 +726,33 @@ typedef struct
*/
#define __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT() (EXTI->D3PMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
#if defined(DUAL_CORE)
/**
* @brief Enable interrupt on the RTC WakeUp Timer associated D2 Exti line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTID2_ENABLE_IT() (EXTI_D2->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable interrupt on the RTC WakeUp Timer associated D2 Exti line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTID2_DISABLE_IT() (EXTI_D2->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable event on the RTC WakeUp Timer associated D2 Exti line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTID2_ENABLE_EVENT() (EXTI_D2->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable event on the RTC WakeUp Timer associated D2 Exti line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTID2_DISABLE_EVENT() (EXTI_D2->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
#endif /* DUAL_CORE */
/**
* @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.
* @retval None
@ -821,6 +848,48 @@ typedef struct
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
#if defined(DUAL_CORE)
/**
* @brief Check whether the RTC WakeUp Timer associated D2 Exti line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTID2_GET_FLAG() (EXTI_D2->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Clear the RTC WakeUp Timer associated D2 Exti line flag.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTID2_CLEAR_FLAG() (EXTI_D2->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Enable interrupt on the RTC Tamper and Timestamp associated D2 Exti line.
* @retval None
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_ENABLE_IT() (EXTI_D2->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
* @brief Disable interrupt on the RTC Tamper and Timestamp associated D2 Exti line.
* @retval None
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_DISABLE_IT() (EXTI_D2->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
/**
* @brief Enable event on the RTC Tamper and Timestamp associated D2 Exti line.
* @retval None
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_ENABLE_EVENT() (EXTI_D2->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
/**
* @brief Disable event on the RTC Tamper and Timestamp associated D2 Exti line.
* @retval None
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_DISABLE_EVENT() (EXTI_D2->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))
#endif
/**
* @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
* @retval None
@ -873,6 +942,20 @@ typedef struct
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
#if defined(DUAL_CORE)
/**
* @brief Check whether the RTC Tamper and Timestamp associated D2 Exti line interrupt flag is set or not.
* @retval Line Status
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_GET_FLAG() (EXTI_D2->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Clear the RTC Tamper and Timestamp associated D2 Exti line flag.
* @retval None
*/
#define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_CLEAR_FLAG() (EXTI_D2->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)
#endif
/**
* @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line
* @retval None

142
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sai.c
View File

@ -141,12 +141,13 @@
*** Callback registration ***
=============================
[..]
The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use functions @ref HAL_SAI_RegisterCallback() to register a user callback.
Use functions HAL_SAI_RegisterCallback() to register a user callback.
Function @ref HAL_SAI_RegisterCallback() allows to register following callbacks:
[..]
Function HAL_SAI_RegisterCallback() allows to register following callbacks:
(+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete.
(+) TxCpltCallback : SAI transmit complete.
@ -154,13 +155,16 @@
(+) ErrorCallback : SAI error.
(+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit.
[..]
This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function.
Use function @ref HAL_SAI_UnRegisterCallback() to reset a callback to the default
[..]
Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
@ref HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID.
[..]
This function allows to reset following callbacks:
(+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete.
@ -170,23 +174,26 @@
(+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit.
By default, after the @ref HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
[..]
By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples @ref HAL_SAI_RxCpltCallback(), @ref HAL_SAI_ErrorCallback().
examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_SAI_Init
and @ref HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_SAI_Init and @ref HAL_SAI_DeInit
reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_SAI_RegisterCallback before calling @ref HAL_SAI_DeInit
or @ref HAL_SAI_Init function.
using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
or HAL_SAI_Init function.
[..]
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used.
@ -385,7 +392,10 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit));
assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing));
assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro));
if (HAL_GetREVID() >= REV_ID_B) /* STM32H7xx Rev.B and above */
{
assert_param(IS_SAI_BLOCK_MCK_OUTPUT(hsai->Init.MckOutput));
}
assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive));
assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider));
assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold));
@ -551,19 +561,19 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
}
/* Configure Master Clock Divider using the following formula :
- If NOMCK = 1 :
- If NODIV = 1 :
MCKDIV[5:0] = SAI_CK_x / (FS * (FRL + 1))
- If NOMCK = 0 :
- If NODIV = 0 :
MCKDIV[5:0] = SAI_CK_x / (FS * (OSR + 1) * 256) */
if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE)
{
/* NOMCK = 1 */
/* NODIV = 1 */
/* (freq x 10) to keep Significant digits */
tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength);
}
else
{
/* NOMCK = 0 */
/* NODIV = 0 */
uint32_t tmposr;
tmposr = (hsai->Init.MckOverSampling == SAI_MCK_OVERSAMPLING_ENABLE) ? 2U : 1U;
/* (freq x 10) to keep Significant digits */
@ -592,17 +602,35 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
/* SAI Block Configuration -------------------------------------------------*/
/* SAI CR1 Configuration */
hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \
SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \
SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \
SAI_xCR1_NOMCK | SAI_xCR1_MCKDIV | SAI_xCR1_OSR);
if (HAL_GetREVID() >= REV_ID_B) /* STM32H7xx Rev.B and above */
{
hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \
SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \
SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \
SAI_xCR1_NODIV | SAI_xCR1_MCKDIV | SAI_xCR1_OSR | \
SAI_xCR1_MCKEN);
hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \
hsai->Init.DataSize | hsai->Init.FirstBit | \
ckstr_bits | syncen_bits | \
hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \
hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \
hsai->Init.MckOverSampling);
hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \
hsai->Init.DataSize | hsai->Init.FirstBit | \
ckstr_bits | syncen_bits | \
hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \
hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \
hsai->Init.MckOverSampling | hsai->Init.MckOutput);
}
else /* STM32H7xx Rev.Y */
{
hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \
SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \
SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \
SAI_xCR1_NODIV | SAI_xCR1_MCKDIV | SAI_xCR1_OSR);
hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \
hsai->Init.DataSize | hsai->Init.FirstBit | \
ckstr_bits | syncen_bits | \
hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \
hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20) | \
hsai->Init.MckOverSampling);
}
/* SAI CR2 Configuration */
hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL);
@ -1061,10 +1089,8 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint
hsai->Instance->CLRFR = 0xFFFFFFFFU;
/* Disable SAI peripheral */
if (SAI_Disable(hsai) != HAL_OK)
{
/* Nothing to do because state update, unlock and error return will be performed later */
}
/* No need to check return value because state update, unlock and error return will be performed later */
(void) SAI_Disable(hsai);
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
@ -1174,10 +1200,8 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1
hsai->Instance->CLRFR = 0xFFFFFFFFU;
/* Disable SAI peripheral */
if (SAI_Disable(hsai) != HAL_OK)
{
/* Nothing to do because state update, unlock and error return will be performed later */
}
/* No need to check return value because state update, unlock and error return will be performed later */
(void) SAI_Disable(hsai);
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
@ -1814,7 +1838,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
/* Call SAI error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
hsai->ErrorCallback(hsai);
#else
HAL_SAI_ErrorCallback(hsai);
#endif
}
}
if (hsai->hdmarx != NULL)
@ -1829,17 +1857,19 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
/* Call SAI error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
hsai->ErrorCallback(hsai);
#else
HAL_SAI_ErrorCallback(hsai);
#endif
}
}
}
else
{
/* Abort SAI */
if (HAL_SAI_Abort(hsai) != HAL_OK)
{
/* Nothing to do because HAL_SAI_ErrorCallback will be called later */
}
/* No need to check return value because HAL_SAI_ErrorCallback will be called later */
(void) HAL_SAI_Abort(hsai);
/* Set error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
@ -1871,7 +1901,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
/* Call SAI error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
hsai->ErrorCallback(hsai);
#else
HAL_SAI_ErrorCallback(hsai);
#endif
}
}
if (hsai->hdmarx != NULL)
@ -1886,17 +1920,19 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
/* Call SAI error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
hsai->ErrorCallback(hsai);
#else
HAL_SAI_ErrorCallback(hsai);
#endif
}
}
}
else
{
/* Abort SAI */
if (HAL_SAI_Abort(hsai) != HAL_OK)
{
/* Nothing to do because HAL_SAI_ErrorCallback will be called later */
}
/* No need to check return value because HAL_SAI_ErrorCallback will be called later */
(void) HAL_SAI_Abort(hsai);
/* Set error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
@ -1928,7 +1964,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
/* Call SAI error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
hsai->ErrorCallback(hsai);
#else
HAL_SAI_ErrorCallback(hsai);
#endif
}
}
if (hsai->hdmarx != NULL)
@ -1943,7 +1983,11 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
/* Call SAI error callback */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
hsai->ErrorCallback(hsai);
#else
HAL_SAI_ErrorCallback(hsai);
#endif
}
}
}
@ -2723,10 +2767,8 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma)
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
/* Disable SAI peripheral */
if (SAI_Disable(hsai) != HAL_OK)
{
/* Nothing to do because state will be updated and HAL_SAI_ErrorCallback will be called later */
}
/* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
(void) SAI_Disable(hsai);
/* Set the SAI state ready to be able to start again the process */
hsai->State = HAL_SAI_STATE_READY;
@ -2763,10 +2805,8 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG)
{
/* Disable SAI peripheral */
if (SAI_Disable(hsai) != HAL_OK)
{
/* Nothing to do because state will be updated and HAL_SAI_ErrorCallback will be called later */
}
/* No need to check return value because state will be updated and HAL_SAI_ErrorCallback will be called later */
(void) SAI_Disable(hsai);
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);

21
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sai.h
View File

@ -92,6 +92,10 @@ typedef struct
@note If both audio blocks of same SAI are used, this parameter has
to be set to the same value for each audio block */
uint32_t MckOutput; /*!< Specifies whether master clock output will be generated or not.
This parameter can be a value of @ref SAI_Block_MckOutput
@note This feature is only available on STM32H7xx Rev.B and above */
uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
This parameter can be a value of @ref SAI_Block_Output_Drive
@note This value has to be set before enabling the audio block
@ -102,7 +106,8 @@ typedef struct
@note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
should be aligned to a number equal to a power of 2, from 8 to 256.
If bit NODIV in the SAI_xCR1 register is set, the frame length can
take any of the values from 8 to 256. */
take any of the values from 8 to 256.
@note The NODIV bit is the same as NOMCK bit in STM32H7xx rev.Y */
uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
@ -308,6 +313,15 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
* @}
*/
/** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output
* @{
*/
#define SAI_MCK_OUTPUT_DISABLE 0x00000000U
#define SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN
/**
* @}
*/
/** @defgroup SAI_Protocol SAI Supported protocol
* @{
*/
@ -445,7 +459,7 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
* @{
*/
#define SAI_MASTERDIVIDER_ENABLE 0x00000000U
#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NOMCK
#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV
/**
* @}
*/
@ -865,6 +879,9 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI3) || \
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI4))
#define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
((VALUE) == SAI_MCK_OUTPUT_DISABLE))
#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))

356
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd.c
View File

@ -189,7 +189,8 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
@ -223,6 +224,12 @@
*/
/* Private macro -------------------------------------------------------------*/
#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2)
#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)? \
DLYB_SDMMC1 : DLYB_SDMMC2 )
#elif defined (DLYB_SDMMC1)
#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 )
#endif
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
@ -242,6 +249,7 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd);
static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd);
#if (USE_SD_TRANSCEIVER != 0U)
static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd);
static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd);
#endif /* USE_SD_TRANSCEIVER */
/**
* @}
@ -2465,7 +2473,27 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
}
break;
}
case SDMMC_SPEED_MODE_HIGH:
case SDMMC_SPEED_MODE_DDR:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardType == CARD_SDHC_SDXC))
{
hsd->Instance->CLKCR |= 0x00100000U;
/* Enable DDR Mode*/
if (SD_DDR_Mode(hsd) != HAL_SD_ERROR_NONE)
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
}
}
else
{
hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE;
status = HAL_ERROR;
}
break;
}
case SDMMC_SPEED_MODE_HIGH:
{
if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) ||
(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) ||
@ -2794,72 +2822,110 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
if(errorstate != HAL_SD_ERROR_NONE)
{
hsd->SdCard.CardVersion = CARD_V1_X;
/* CMD0: GO_IDLE_STATE */
errorstate = SDMMC_CmdGoIdleState(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
}
else
{
hsd->SdCard.CardVersion = CARD_V2_X;
}
/* SEND CMD55 APP_CMD with RCA as 0 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
if(errorstate != HAL_SD_ERROR_NONE)
if( hsd->SdCard.CardVersion == CARD_V2_X)
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
else
{
/* SD CARD */
/* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
/* SEND CMD55 APP_CMD with RCA as 0 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
if(errorstate != HAL_SD_ERROR_NONE)
{
/* SEND CMD55 APP_CMD with RCA as 0 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
}
/* SD CARD */
/* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U))
{
/* SEND CMD55 APP_CMD with RCA as 0 */
errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send CMD41 */
errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
if(errorstate != HAL_SD_ERROR_NONE)
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
}
/* Get command response */
response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
/* Get operating voltage*/
validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
count++;
}
if(count >= SDMMC_MAX_VOLT_TRIAL)
{
return HAL_SD_ERROR_INVALID_VOLTRANGE;
}
if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
{
hsd->SdCard.CardType = CARD_SDHC_SDXC;
#if (USE_SD_TRANSCEIVER != 0U)
if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
{
hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
/* Start switching procedue */
hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN;
/* Send CMD11 to switch 1.8V mode */
errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Send CMD41 */
errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY);
if(errorstate != HAL_SD_ERROR_NONE)
/* Check to CKSTOP */
while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
{
return HAL_SD_ERROR_UNSUPPORTED_FEATURE;
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
/* Get command response */
response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1);
/* Clear CKSTOP Flag */
hsd->Instance->ICR = SDMMC_FLAG_CKSTOP;
/* Get operating voltage*/
validvoltage = (((response >> 31U) == 1U) ? 1U : 0U);
count++;
}
if(count >= SDMMC_MAX_VOLT_TRIAL)
{
return HAL_SD_ERROR_INVALID_VOLTRANGE;
}
if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
{
hsd->SdCard.CardType = CARD_SDHC_SDXC;
#if (USE_SD_TRANSCEIVER != 0U)
if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY)
/* Check to BusyD0 */
if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
{
hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
/* Error when activate Voltage Switch in SDMMC Peripheral */
return SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
else
{
/* Enable Transceiver Switch PIN */
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->DriveTransceiver_1_8V_Callback(SET);
#else
HAL_SD_DriveTransceiver_1_8V_Callback(SET);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/* Start switching procedue */
hsd->Instance->POWER |= SDMMC_POWER_VSWITCHEN;
/* Switch ready */
hsd->Instance->POWER |= SDMMC_POWER_VSWITCH;
/* Send CMD11 to switch 1.8V mode */
errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Check to CKSTOP */
while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP)
/* Check VSWEND Flag */
while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
{
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
@ -2867,58 +2933,27 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
}
}
/* Clear CKSTOP Flag */
hsd->Instance->ICR = SDMMC_FLAG_CKSTOP;
/* Clear VSWEND Flag */
hsd->Instance->ICR = SDMMC_FLAG_VSWEND;
/* Check to BusyD0 */
if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0)
/* Check BusyD0 status */
if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
{
/* Error when activate Voltage Switch in SDMMC Peripheral */
return SDMMC_ERROR_UNSUPPORTED_FEATURE;
/* Error when enabling 1.8V mode */
return HAL_SD_ERROR_INVALID_VOLTRANGE;
}
else
{
/* Enable Transceiver Switch PIN */
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->DriveTransceiver_1_8V_Callback(SET);
#else
HAL_SD_DriveTransceiver_1_8V_Callback(SET);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
/* Switch to 1.8V OK */
/* Switch ready */
hsd->Instance->POWER |= SDMMC_POWER_VSWITCH;
/* Disable VSWITCH FLAG from SDMMC Peripheral */
hsd->Instance->POWER = 0x13U;
/* Check VSWEND Flag */
while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND)
{
if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT)
{
return HAL_SD_ERROR_TIMEOUT;
}
}
/* Clear VSWEND Flag */
hsd->Instance->ICR = SDMMC_FLAG_VSWEND;
/* Check BusyD0 status */
if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0)
{
/* Error when enabling 1.8V mode */
return HAL_SD_ERROR_INVALID_VOLTRANGE;
}
/* Switch to 1.8V OK */
/* Disable VSWITCH FLAG from SDMMC Peripheral */
hsd->Instance->POWER = 0x13U;
/* Clean Status flags */
hsd->Instance->ICR = 0xFFFFFFFFU;
}
hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
/* Clean Status flags */
hsd->Instance->ICR = 0xFFFFFFFFU;
}
#endif /* USE_SD_TRANSCEIVER */
hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED;
}
#endif /* USE_SD_TRANSCEIVER */
}
return HAL_SD_ERROR_NONE;
@ -3444,7 +3479,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd)
* @param hsd: SD handle
* @retval SD Card error state
*/
uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
{
uint32_t errorstate = HAL_SD_ERROR_NONE;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
@ -3555,7 +3590,7 @@ uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
/* Enable DelayBlock Peripheral */
/* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */
MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_1);
if (DelayBlock_Enable(DLYB_SDMMC1) != HAL_OK)
if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
}
@ -3565,6 +3600,137 @@ uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd)
return errorstate;
}
/**
* @brief Switches the SD card to Double Data Rate (DDR) mode.
* This API must be used after "Transfer State"
* @note This operation should be followed by the configuration
* of PLL to have SDMMCCK clock less than 50MHz
* @param hsd: SD handle
* @retval SD Card error state
*/
static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd)
{
uint32_t errorstate = HAL_SD_ERROR_NONE;
SDMMC_DataInitTypeDef sdmmc_datainitstructure;
uint32_t SD_hs[16] = {0};
uint32_t count, loop = 0 ;
uint32_t Timeout = HAL_GetTick();
if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED)
{
/* Standard Speed Card <= 12.5Mhz */
return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE;
}
if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED)
{
/* Initialize the Data control register */
hsd->Instance->DCTRL = 0;
errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64);
if (errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
/* Configure the SD DPSM (Data Path State Machine) */
sdmmc_datainitstructure.DataTimeOut = SDMMC_DATATIMEOUT;
sdmmc_datainitstructure.DataLength = 64;
sdmmc_datainitstructure.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B ;
sdmmc_datainitstructure.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE;
if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
}
errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_DDR50_SWITCH_PATTERN);
if(errorstate != HAL_SD_ERROR_NONE)
{
return errorstate;
}
while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND ))
{
if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF))
{
for (count = 0U; count < 8U; count++)
{
SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance);
}
loop ++;
}
if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT)
{
hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT;
hsd->State= HAL_SD_STATE_READY;
return HAL_SD_ERROR_TIMEOUT;
}
}
if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT);
errorstate = 0;
return errorstate;
}
else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL);
errorstate = SDMMC_ERROR_DATA_CRC_FAIL;
return errorstate;
}
else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR))
{
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR);
errorstate = SDMMC_ERROR_RX_OVERRUN;
return errorstate;
}
else
{
/* No error flag set */
}
/* Clear all the static flags */
__HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS);
/* Test if the switch mode is ok */
if ((((uint8_t*)SD_hs)[13] & 2U) != 2U)
{
errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
}
else
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
hsd->DriveTransceiver_1_8V_Callback(SET);
#else
HAL_SD_DriveTransceiver_1_8V_Callback(SET);
#endif /* USE_HAL_SD_REGISTER_CALLBACKS */
#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2)
/* Enable DelayBlock Peripheral */
/* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */
MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_1);
if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK)
{
return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR);
}
#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */
}
}
return errorstate;
}
#endif /* USE_SD_TRANSCEIVER */
/**

3
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd.h
View File

@ -6,7 +6,8 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the

3
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd_ex.c
View File

@ -21,7 +21,8 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the

3
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_sd_ex.h
View File

@ -6,7 +6,8 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the

16
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_smbus.c
View File

@ -89,12 +89,12 @@
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
to register an interrupt callback.
[..]
Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
@ -106,9 +106,9 @@
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
[..]
Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
@ -122,9 +122,9 @@
(+) ErrorCallback : callback for error detection.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
[..]
By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
@ -133,7 +133,7 @@
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
@ -141,7 +141,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
or @ref HAL_SMBUS_Init() function.
[..]
When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.

70
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_spi.c
View File

@ -2569,55 +2569,57 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART));
}
/* Reset Callbacks */
hspi->hdmarx->XferAbortCallback = NULL;
hspi->hdmatx->XferAbortCallback = NULL;
/* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized
before any call to DMA Abort functions */
if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN) && (hspi->hdmatx != NULL))
if(hspi->hdmatx != NULL)
{
/* Set DMA Abort Complete callback if UART DMA Tx request if enabled */
hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
}
if ((HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) && (hspi->hdmarx != NULL))
{
/* Set DMA Abort Complete callback if UART DMA Rx request if enabled */
hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
}
/* Disable the SPI DMA Tx request if enabled */
if ((HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) && (hspi->hdmatx != NULL))
{
dma_tx_abort_done = 0UL;
/* Abort DMA Tx Handle linked to SPI Peripheral */
if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN))
{
if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER)
/* Set DMA Abort Complete callback if SPI DMA Tx request if enabled */
hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
dma_tx_abort_done = 0UL;
/* Abort DMA Tx Handle linked to SPI Peripheral */
if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
{
dma_tx_abort_done = 1UL;
hspi->hdmatx->XferAbortCallback = NULL;
if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER)
{
dma_tx_abort_done = 1UL;
hspi->hdmatx->XferAbortCallback = NULL;
}
}
}
else
{
hspi->hdmatx->XferAbortCallback = NULL;
}
}
/* Disable the SPI DMA Rx request if enabled */
if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN) && (hspi->hdmarx != NULL))
if(hspi->hdmarx != NULL)
{
dma_rx_abort_done = 0UL;
/* Abort DMA Rx Handle linked to SPI Peripheral */
if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN))
{
if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER)
/* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */
hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
dma_rx_abort_done = 0UL;
/* Abort DMA Rx Handle linked to SPI Peripheral */
if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
{
dma_rx_abort_done = 1UL;
hspi->hdmarx->XferAbortCallback = NULL;
if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER)
{
dma_rx_abort_done = 1UL;
hspi->hdmarx->XferAbortCallback = NULL;
}
}
}
else
{
hspi->hdmarx->XferAbortCallback = NULL;
}
}
/* If no running DMA transfer, finish cleanup and call callbacks */

183
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim.c
View File

@ -98,18 +98,22 @@
*** Callback registration ***
=============================================
[..]
The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
[..]
Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
@ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function.
[..]
Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
weak function.
@ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
[..]
These functions allow to register/unregister following callbacks:
(+) Base_MspInitCallback : TIM Base Msp Init Callback.
(+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
@ -140,15 +144,18 @@
(+) BreakCallback : TIM Break Callback.
(+) Break2Callback : TIM Break2 Callback.
[..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions:
examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
[..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
functionalities in the Init / DeInit only when these callbacks are null
(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
[..]
Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
Exception done MspInit / MspDeInit that can be registered / unregistered
in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
@ -156,13 +163,14 @@ all interrupt callbacks are set to the corresponding weak functions:
In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
[..]
When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
@endverbatim
******************************************************************************
* @attention
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
@ -216,7 +224,7 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig);
TIM_SlaveConfigTypeDef *sSlaveConfig);
/**
* @}
*/
@ -227,8 +235,8 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
*/
/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
* @brief Time Base functions
*
* @brief Time Base functions
*
@verbatim
==============================================================================
##### Time Base functions #####
@ -559,8 +567,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
*/
/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
* @brief TIM Output Compare functions
*
* @brief TIM Output Compare functions
*
@verbatim
==============================================================================
##### TIM Output Compare functions #####
@ -929,7 +937,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{
uint32_t tmpsmcr;
uint32_t tmpsmcr;
/* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@ -1136,8 +1144,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
* @brief TIM PWM functions
*
* @brief TIM PWM functions
*
@verbatim
==============================================================================
##### TIM PWM functions #####
@ -1714,8 +1722,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
*/
/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
* @brief TIM Input Capture functions
*
* @brief TIM Input Capture functions
*
@verbatim
==============================================================================
##### TIM Input Capture functions #####
@ -2249,8 +2257,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
* @brief TIM One Pulse functions
*
* @brief TIM One Pulse functions
*
@verbatim
==============================================================================
##### TIM One Pulse functions #####
@ -2563,8 +2571,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
*/
/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
* @brief TIM Encoder functions
*
* @brief TIM Encoder functions
*
@verbatim
==============================================================================
##### TIM Encoder functions #####
@ -2966,7 +2974,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
* @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length)
{
/* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
@ -3149,8 +3158,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
* @}
*/
/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
* @brief TIM IRQ handler management
*
* @brief TIM IRQ handler management
*
@verbatim
==============================================================================
##### IRQ handler management #####
@ -3363,8 +3372,8 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
*/
/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
* @brief TIM Peripheral Control functions
*
* @brief TIM Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
@ -3740,7 +3749,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel)
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
uint32_t OutputChannel, uint32_t InputChannel)
{
TIM_OC_InitTypeDef temp1;
@ -3863,7 +3873,13 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_DCR
* @arg TIM_DMABASE_CCMR3
* @arg TIM_DMABASE_CCR5
* @arg TIM_DMABASE_CCR6
* @arg TIM_DMABASE_AF1
* @arg TIM_DMABASE_AF2
* @arg TIM_DMABASE_TISEL
*
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@ -3876,12 +3892,14 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
* @param BurstBuffer The Buffer address.
* @param BurstLength DMA Burst length. This parameter can be one value
* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
uint32_t *BurstBuffer, uint32_t BurstLength)
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
((BurstLength) >> 8U) + 1U);
}
/**
@ -3907,7 +3925,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_DCR
* @arg TIM_DMABASE_CCMR3
* @arg TIM_DMABASE_CCR5
* @arg TIM_DMABASE_CCR6
* @arg TIM_DMABASE_AF1
* @arg TIM_DMABASE_AF2
* @arg TIM_DMABASE_TISEL
*
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@ -3924,8 +3948,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
* between 1 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@ -3965,7 +3990,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -3981,7 +4007,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -3997,7 +4024,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -4013,7 +4041,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -4029,7 +4058,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -4045,7 +4075,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -4061,7 +4092,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -4070,9 +4102,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint
default:
break;
}
/* configure the DMA Burst Mode */
htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Configure the DMA Burst Mode */
htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
@ -4169,7 +4201,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_DCR
* @arg TIM_DMABASE_CCMR3
* @arg TIM_DMABASE_CCR5
* @arg TIM_DMABASE_CCR6
* @arg TIM_DMABASE_AF1
* @arg TIM_DMABASE_AF2
* @arg TIM_DMABASE_TISEL
*
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@ -4182,12 +4220,14 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @param BurstBuffer The Buffer address.
* @param BurstLength DMA Burst length. This parameter can be one value
* between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
uint32_t *BurstBuffer, uint32_t BurstLength)
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
((BurstLength) >> 8U) + 1U);
}
/**
@ -4213,7 +4253,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
* @arg TIM_DMABASE_CCR3
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_DCR
* @arg TIM_DMABASE_CCMR3
* @arg TIM_DMABASE_CCR5
* @arg TIM_DMABASE_CCR6
* @arg TIM_DMABASE_AF1
* @arg TIM_DMABASE_AF2
* @arg TIM_DMABASE_TISEL
*
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@ -4230,8 +4276,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
* between 1 and 0xFFFF.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@ -4271,7 +4318,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -4287,7 +4335,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -4303,7 +4352,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -4319,7 +4369,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -4335,7 +4386,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -4351,7 +4403,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -4367,7 +4420,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA stream */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength) != HAL_OK)
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@ -4377,7 +4431,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3
break;
}
/* configure the DMA Burst Mode */
/* Configure the DMA Burst Mode */
htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
@ -4545,7 +4599,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
/* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
{
htim->State = HAL_TIM_STATE_READY;
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_ERROR;
}
@ -4865,9 +4919,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
htim->State = HAL_TIM_STATE_BUSY;
if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{
htim->State = HAL_TIM_STATE_READY;
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_ERROR;
}
@ -4895,7 +4949,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig)
TIM_SlaveConfigTypeDef *sSlaveConfig)
{
/* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@ -4906,9 +4960,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
htim->State = HAL_TIM_STATE_BUSY;
if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{
htim->State = HAL_TIM_STATE_READY;
htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim);
return HAL_ERROR;
}
@ -4998,8 +5052,8 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
*/
/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
* @brief TIM Callbacks functions
*
* @brief TIM Callbacks functions
*
@verbatim
==============================================================================
##### TIM Callbacks functions #####
@ -5203,7 +5257,8 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
* @param pCallback pointer to the callback function
* @retval status
*/
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
pTIM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@ -5663,8 +5718,8 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
*/
/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
* @brief TIM Peripheral State functions
*
* @brief TIM Peripheral State functions
*
@verbatim
==============================================================================
##### Peripheral State functions #####
@ -6450,7 +6505,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
* @retval None
*/
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig)
TIM_SlaveConfigTypeDef *sSlaveConfig)
{
uint32_t tmpsmcr;
uint32_t tmpccmr1;

215
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim.h
View File

@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
@ -448,7 +448,6 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#define TIM_DMABASE_BDTR 0x00000011U
#define TIM_DMABASE_DCR 0x00000012U
#define TIM_DMABASE_DMAR 0x00000013U
#define TIM_DMABASE_OR 0x00000014U
#define TIM_DMABASE_CCMR3 0x00000015U
#define TIM_DMABASE_CCR5 0x00000016U
#define TIM_DMABASE_CCR6 0x00000017U
@ -456,6 +455,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
#define TIM_DMABASE_AF1 0x00000018U
#define TIM_DMABASE_AF2 0x00000019U
#endif /* TIM_BREAK_INPUT_SUPPORT */
#define TIM_DMABASE_TISEL 0x00000020U
/**
* @}
*/
@ -1129,15 +1129,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @retval None
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \
} \
} while(0)
do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \
} \
} while(0)
/**
* @brief Disable the TIM main Output.
@ -1146,15 +1146,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
} \
} while(0)
do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
} \
} while(0)
/**
* @brief Disable the TIM main Output.
@ -1289,7 +1289,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @arg TIM_IT_BREAK: Break interrupt
* @retval The state of TIM_IT (SET or RESET).
*/
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
== (__INTERRUPT__)) ? SET : RESET)
/** @brief Clear the TIM interrupt pending bits.
* @param __HANDLE__ TIM handle
@ -1337,8 +1338,7 @@ mode.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
((__HANDLE__)->Instance->CNT)
#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
/**
* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
@ -1347,18 +1347,17 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
do{ \
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
} while(0)
do{ \
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
} while(0)
/**
* @brief Get the TIM Autoreload Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
((__HANDLE__)->Instance->ARR)
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
/**
* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
@ -1371,11 +1370,11 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
do{ \
(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
(__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0)
do{ \
(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
(__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0)
/**
* @brief Get the TIM Clock Division value on runtime.
@ -1385,8 +1384,7 @@ mode.
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
@ -1406,10 +1404,10 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
do{ \
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
} while(0)
do{ \
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
} while(0)
/**
* @brief Get the TIM Input Capture prescaler on runtime.
@ -1447,12 +1445,12 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
/**
* @brief Get the TIM Capture Compare Register value on runtime.
@ -1468,12 +1466,12 @@ mode.
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
((__HANDLE__)->Instance->CCR6))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
((__HANDLE__)->Instance->CCR6))
/**
* @brief Set the TIM Output compare preload.
@ -1489,12 +1487,12 @@ mode.
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
/**
* @brief Reset the TIM Output compare preload.
@ -1510,12 +1508,12 @@ mode.
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
@ -1525,8 +1523,7 @@ mode.
* enabled)
* @retval None
*/
#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
/**
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
@ -1539,8 +1536,7 @@ mode.
* _ Update generation through the slave mode controller
* @retval None
*/
#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
/**
* @brief Set the TIM Capture x input polarity on runtime.
@ -1558,10 +1554,10 @@ mode.
* @retval None
*/
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
do{ \
TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0)
do{ \
TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0)
/**
* @}
@ -1609,9 +1605,10 @@ mode.
((__BASE__) == TIM_DMABASE_CCMR3) || \
((__BASE__) == TIM_DMABASE_CCR5) || \
((__BASE__) == TIM_DMABASE_CCR6) || \
((__BASE__) == TIM_DMABASE_OR) || \
((__BASE__) == TIM_DMABASE_AF1) || \
((__BASE__) == TIM_DMABASE_AF2))
((__BASE__) == TIM_DMABASE_AF2) || \
((__BASE__) == TIM_DMABASE_TISEL))
#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
@ -1873,28 +1870,28 @@ mode.
((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
/**
* @}
@ -2032,7 +2029,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
@ -2056,21 +2054,25 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
uint32_t OutputChannel, uint32_t InputChannel);
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -2096,7 +2098,8 @@ void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
pTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@ -2126,8 +2129,8 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/* Private functions----------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions
* @{
*/
* @{
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
@ -2146,8 +2149,8 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @}
*/
* @}
*/
/* End of private functions --------------------------------------------------*/
/**

15
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.c
View File

@ -62,7 +62,7 @@
@endverbatim
******************************************************************************
* @attention
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
@ -73,7 +73,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal.h"
@ -1467,7 +1467,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@ -1522,7 +1523,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@ -1578,7 +1580,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource)
{
/* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@ -2179,7 +2182,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/

52
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_tim_ex.h
View File

@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
@ -326,9 +326,9 @@ TIMEx_BreakInputConfigTypeDef;
*/
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
* @{
*/
* @brief Timer Hall Sensor functions
* @{
*/
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
@ -350,9 +350,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
*/
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
* @{
*/
* @brief Timer Complementary Output Compare functions
* @{
*/
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -370,9 +370,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
*/
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
* @{
*/
* @brief Timer Complementary PWM functions
* @{
*/
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -389,9 +389,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
* @{
*/
* @brief Timer Complementary One Pulse functions
* @{
*/
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
@ -405,17 +405,23 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
* @brief Peripheral Control functions
* @{
*/
/* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
#if defined(TIM_BREAK_INPUT_SUPPORT)
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
#endif /* TIM_BREAK_INPUT_SUPPORT */
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
@ -453,7 +459,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);

8
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_wwdg.c
View File

@ -32,10 +32,10 @@
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
(++) Counter min (T[5;0] = 0x00) @56 MHz(PCLK1) with zero prescaler:
max timeout before reset: ~73.14 µs
(++) Counter max (T[5;0] = 0x3F) @56 MHz(PCLK1) with prescaler dividing by 128:
max timeout before reset: ~599.18 ms
(++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
max timeout before reset: ~73.14µs
(++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
max timeout before reset: ~599.18ms
==============================================================================
##### How to use this driver #####

16
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_adc.c
View File

@ -25,7 +25,7 @@
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0UL)
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32H7xx_LL_Driver
@ -46,7 +46,7 @@
*/
/* Definitions of ADC hardware constraints delays */
/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
/* not timeout values: */
/* Timeout values for ADC operations are dependent to device clock */
/* configuration (system clock versus ADC clock), */
@ -61,8 +61,7 @@
/* - ADC clock from synchronous clock with AHB prescaler 512, */
/* APB prescaler 16, ADC prescaler 4. */
/* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
/* with highest ratio CPU clock frequency vs HSI clock frequency: */
/* CPU clock frequency max 72MHz, PLL freq 72MHz: ratio 1. */
/* with highest ratio CPU clock frequency vs HSI clock frequency */
/* Unit: CPU cycles. */
#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
@ -158,6 +157,7 @@
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM2_OUT) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM3_OUT) \
)
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
|| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
@ -232,6 +232,7 @@
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) \
)
#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
@ -348,6 +349,7 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
/* Release reset of ADC clock (core clock) */
LL_AHB4_GRP1_ReleaseReset(LL_AHB4_GRP1_PERIPH_ADC3);
}
return SUCCESS;
}
@ -523,6 +525,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
{
/* Time-out error */
status = ERROR;
break;
}
}
@ -543,6 +546,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
{
/* Time-out error */
status = ERROR;
break;
}
}
}
@ -613,7 +617,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
SET_BIT(ADCx->CFGR, ADC_CFGR_JQDIS);
/* Reset register CFGR2 */
CLEAR_BIT(ADCx->CFGR2,
CLEAR_BIT(ADCx->CFGR2,
( ADC_CFGR2_LSHIFT | ADC_CFGR2_OVSR | ADC_CFGR2_RSHIFT1
| ADC_CFGR2_RSHIFT4 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT2
| ADC_CFGR2_RSHIFT1 | ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS
@ -676,7 +680,7 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
/* Reset register DR */
/* Note: bits in access mode read only, no direct reset applicable */
/* Reset register OFR1 */
/* Reset register OFR1 */
CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_SSATE);
/* Reset register OFR2 */
CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_SSATE);

421
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_adc.h
View File

@ -323,9 +323,21 @@ extern "C" {
#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
/* Internal register offset for ADC analog watchdog threshold configuration */
#define LL_ADC_AWD1_TR 0x00000000U /* GAP vs LTR1 / 4 */
#define LL_ADC_AWD2_TR 0x00000024U /* GAP vs LTR1 / 4 */
#define LL_ADC_AWD3_TR 0x00000026U /* GAP vs LTR1 / 4 */
#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
/* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */
/* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */
#define ADC_AWD_TR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define ADC_AWD_TR12_REGOFFSETGAP_VAL (0x00000022UL)
/* Legacy literals */
#define LL_ADC_AWD1_TR LL_ADC_AWD1
#define LL_ADC_AWD2_TR LL_ADC_AWD2
#define LL_ADC_AWD3_TR LL_ADC_AWD3
/* Internal mask for ADC offset: */
/* Internal register offset for ADC offset number configuration */
@ -349,15 +361,16 @@ extern "C" {
/* ADC internal channels related definitions */
/* Internal voltage reference VrefInt */
#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define VREFINT_CAL_VREF (3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
/* Temperature sensor */
#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL_VREFANALOG (3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
/**
* @}
*/
@ -456,6 +469,7 @@ typedef struct
uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */
uint32_t LowPowerMode; /*!< Set ADC low power mode.
This parameter can be a value of @ref ADC_LL_EC_LP_MODE
@ -484,7 +498,7 @@ typedef struct
*/
typedef struct
{
uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
@note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
@ -544,7 +558,7 @@ typedef struct
*/
typedef struct
{
uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
@note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
@ -695,8 +709,11 @@ typedef struct
/** @defgroup ADC_LL_EC_BOOST_MODE ADC instance - Boost mode
* @{
*/
#define LL_ADC_BOOST_MODE_20MHZ (0x00000000UL) /*!< Boost mode is configured for frequency <= 20Mhz */
#define LL_ADC_BOOST_MODE_50MHZ (ADC_CR_BOOST) /*!< Boost mode is configured for frequency > 20Mhz */
#define LL_ADC_BOOST_MODE_6MHZ25 (0x00000000UL) /*!< Boost mode is configured for frequency <= 6.25Mhz */
#define LL_ADC_BOOST_MODE_12MHZ5 ( ADC_CR_BOOST_0) /*!< Boost mode is configured for 6.25Mhz < frequency <= 12.5Mhz */
#define LL_ADC_BOOST_MODE_20MHZ ( ADC_CR_BOOST_1 ) /*!< Boost mode is configured for 12.5Mhz < frequency <= 20Mhz */
#define LL_ADC_BOOST_MODE_25MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 ) /*!< Boost mode is configured for 20Mhz < frequency <= 25Mhz */
#define LL_ADC_BOOST_MODE_50MHZ ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0) /*!< Boost mode is configured for frequency > 25Mhz */
/**
* @}
*/
@ -710,6 +727,7 @@ typedef struct
/**
* @}
*/
/** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_WORD ADC instance - Calibration linearity words
* @{
*/
@ -722,6 +740,7 @@ typedef struct
/**
* @}
*/
/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
* @{
*/
@ -734,25 +753,25 @@ typedef struct
* @}
*/
/** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
/** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift
* @{
*/
#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC No bit shift */
#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift */
#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift */
#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC convesion data */
#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC convesion data */
/**
* @}
*/
@ -827,9 +846,10 @@ typedef struct
#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */
/*!< ADC3 is defined only in the case of STM32H7XX */
#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */
#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */
#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */
#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */
#define LL_ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
#define LL_ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
/**
@ -840,27 +860,27 @@ typedef struct
* @{
*/
#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: HRTIM TRG2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
@ -890,23 +910,11 @@ typedef struct
#define LL_ADC_REG_DR_TRANSFER (0x00000000UL) /*!< ADC conversions are transferred to DR rigister */
#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
#define LL_ADC_REG_DFSDM_TRANSFER (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred to DFSDM */
#define LL_ADC_REG_DFSDM_TRANSFER (ADC_CFGR_DMNGT_1 ) /*!< ADC conversion data are transferred to DFSDM */
/**
* @}
*/
#if defined(DFSDM1_Channel0)
/** @defgroup ADC_LL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
* @{
*/
#define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */
#define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DMNGT) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
/**
* @}
*/
#endif
/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
* @{
*/
@ -982,27 +990,27 @@ typedef struct
* @{
*/
#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group injected conversion trigger internal: SW start. */
#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
/**
* @}
*/
@ -1175,9 +1183,9 @@ typedef struct
#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */
#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */
#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */
#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */
#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */
#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */
@ -1191,8 +1199,8 @@ typedef struct
/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
* @{
*/
#define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL)
#define LL_ADC_AWD_THRESHOLD_LOW (0x0UL)
#define LL_ADC_AWD_THRESHOLD_HIGH (0x1UL) /*!< ADC analog watchdog threshold high */
#define LL_ADC_AWD_THRESHOLD_LOW (0x0UL) /*!< ADC analog watchdog threshold low */
/**
* @}
*/
@ -1218,7 +1226,6 @@ typedef struct
* @}
*/
/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
* @{
*/
@ -1296,14 +1303,14 @@ typedef struct
/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
* @note Only ADC IP HW delays are defined in ADC LL driver driver,
* @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
* @{
*/
/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
/* not timeout values. */
/* Timeout values for ADC operations are dependent to device clock */
/* configuration (system clock versus ADC clock), */
@ -1329,13 +1336,13 @@ typedef struct
/* Delay for internal voltage reference stabilization time. */
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "tSTART_RUN"). */
/* parameter "ts_vrefint"). */
/* Unit: us */
#define LL_ADC_DELAY_VREFINT_STAB_US (5UL) /*!< Delay for internal voltage reference stabilization time */
/* Delay for temperature sensor stabilization time. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* parameter "tSTART_RUN"). */
/* Unit: us */
#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */
@ -1357,6 +1364,7 @@ typedef struct
/* At maximum CPU speed (400 MHz), this means */
/* 3.58 * 400 MHz = 524400 CPU cycles */
#define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT (524400UL) /*!< ADC linearity set/clear bit delay */
/**
* @}
*/
@ -1434,7 +1442,7 @@ typedef struct
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -1442,13 +1450,13 @@ typedef struct
* @retval Value between Min_Data=0 and Max_Data=18
*/
#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
? ( \
((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
) \
: \
( \
POSITION_VAL((__CHANNEL__)) \
(uint32_t)POSITION_VAL((__CHANNEL__)) \
) \
)
@ -1485,7 +1493,7 @@ typedef struct
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -1552,7 +1560,7 @@ typedef struct
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -1602,7 +1610,7 @@ typedef struct
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -1652,7 +1660,7 @@ typedef struct
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.
* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
@ -1709,7 +1717,7 @@ typedef struct
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -1801,7 +1809,7 @@ typedef struct
* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)
* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)
* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)
*
*
* (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.
@ -1934,6 +1942,7 @@ typedef struct
(ADC3_COMMON) \
) \
)
/**
* @brief Helper macro to check if all ADC instances sharing the same
* ADC common instance are disabled.
@ -1951,6 +1960,7 @@ typedef struct
* Value "1" if at least one ADC instance sharing the same ADC common instance
* is enabled.
*/
#if defined(ADC3_COMMON)
#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
(((__ADCXY_COMMON__) == ADC12_COMMON) \
? ( \
@ -1962,6 +1972,11 @@ typedef struct
(LL_ADC_IsEnabled(ADC3)) \
) \
)
#else
#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
(LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
#endif
/**
* @brief Helper macro to define the ADC conversion data full-scale digital
* value corresponding to the selected ADC resolution.
@ -2546,7 +2561,21 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, ui
*/
__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
}
else /* rev.V */
{
if(LL_ADC_RESOLUTION_8B == Resolution)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);
}
else
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
}
}
}
/**
@ -2564,10 +2593,23 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution
*/
__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
}
else
{
if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)
{
return (LL_ADC_RESOLUTION_8B);
}
else
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
}
}
}
/**
* @brief Set ADC low power mode.
* @note Description of ADC low power modes:
@ -2688,6 +2730,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @note On STM32H7, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
* @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
* OFR1 OFFSET1 LL_ADC_SetOffset\n
* OFR1 OFFSET1_EN LL_ADC_SetOffset\n
@ -2732,7 +2776,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -2765,6 +2809,8 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3
* - To get the channel number in decimal format:
* process the returned value with the helper macro
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* @note On STM32H7, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
* @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
* OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
* OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
@ -2801,7 +2847,7 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -2838,7 +2884,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Off
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
}
@ -2861,10 +2907,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offse
*/
__STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)
{
if ((Offsety == LL_ADC_OFFSET_1) || (Offsety == LL_ADC_OFFSET_2) || (Offsety == LL_ADC_OFFSET_3) || (Offsety == LL_ADC_OFFSET_4))
{
MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << Offsety);
}
MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
}
/**
@ -2883,14 +2926,7 @@ __STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offset
*/
__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety)
{
if ((Offsety == LL_ADC_OFFSET_1) || (Offsety == LL_ADC_OFFSET_2) || (Offsety == LL_ADC_OFFSET_3) || (Offsety == LL_ADC_OFFSET_4))
{
return (uint32_t) ((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << Offsety))) >> Offsety);
}
else
{
return 0UL;
}
return (uint32_t) ((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));
}
/**
@ -2950,7 +2986,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uin
/**
* @brief Set ADC group regular conversion trigger source:
* internal (SW start) or from external IP (timer event,
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
* @note On this STM32 serie, setting trigger source to external trigger
* also set trigger polarity to rising edge
@ -2999,7 +3035,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri
/**
* @brief Get ADC group regular conversion trigger source:
* internal (SW start) or from external IP (timer event,
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
* @note To determine whether group regular trigger source is
* internal (SW start) or external, without detail
@ -3351,7 +3387,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -3451,7 +3487,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -3534,7 +3570,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t
* - Available in Data Register
* - Transfered by DMA in one shot mode
* - Transfered by DMA in circular mode
* - Transfered to DFSDM data register
* - Transfered to DFSDM data register
* @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
@ -3598,7 +3634,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
/**
* @brief Set ADC group injected conversion trigger source:
* internal (SW start) or from external IP (timer event,
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
* @note On this STM32 serie, setting trigger source to external trigger
* also set trigger polarity to rising edge
@ -3647,7 +3683,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri
/**
* @brief Get ADC group injected conversion trigger source:
* internal (SW start) or from external IP (timer event,
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
* @note To determine whether group injected trigger source is
* internal (SW start) or external, without detail
@ -3840,6 +3876,8 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On STM32H7, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
* @note On this STM32 serie, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
@ -3880,7 +3918,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -3950,7 +3988,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -4098,6 +4136,8 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On STM32H7, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
* @note On this STM32 serie, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
@ -4171,7 +4211,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -4202,7 +4242,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -4233,7 +4273,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -4264,7 +4304,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -4385,7 +4425,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -4471,7 +4511,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C
* @arg @ref LL_ADC_CHANNEL_VBAT (1)
* @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)
*
*
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.\n
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
@ -4738,7 +4778,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t
* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG (0)(2)
* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ (0)(2)
* @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ (2)
*
*
* (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n
* (1) On STM32H7, parameter available only on ADC instance: ADC3.\n
* (2) On STM32H7, parameter available only on ADC instance: ADC2.
@ -4880,7 +4920,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t
* @arg @ref LL_ADC_AWD_CHANNEL_19_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_19_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ
*
*
* (0) On STM32H7, parameter available only on analog watchdog number: AWD1.
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
@ -4937,7 +4977,6 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint
}
return AnalogWDMonitChannels;
}
/**
@ -4984,9 +5023,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint
* TR3 LT3 LL_ADC_SetAnalogWDThresholds
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1_TR
* @arg @ref LL_ADC_AWD2_TR
* @arg @ref LL_ADC_AWD3_TR
* @arg @ref LL_ADC_AWD1
* @arg @ref LL_ADC_AWD2
* @arg @ref LL_ADC_AWD3
* @param AWDThresholdsHighLow This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
@ -4998,15 +5037,19 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
/* Set bits with content of parameter "AWDThresholdValue" with bits */
/* position in register and register position depending on parameters */
/* "AWDThresholdsHighLow" and "AWDy". */
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (AWDy + AWDThresholdsHighLow));
MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ (AWDThresholdsHighLow));
MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);
}
/**
* @brief Get ADC analog watchdog threshold value of threshold high,
* threshold low or raw data with ADC thresholds high and low
* concatenated.
* @note If raw data with ADC thresholds high and low is retrieved,
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
@ -5018,18 +5061,20 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW
* TR3 LT3 LL_ADC_GetAnalogWDThresholds
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1_TR
* @arg @ref LL_ADC_AWD2_TR
* @arg @ref LL_ADC_AWD3_TR
* @arg @ref LL_ADC_AWD1
* @arg @ref LL_ADC_AWD2
* @arg @ref LL_ADC_AWD3
* @param AWDThresholdsHighLow This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
/* Register position depending on parameters "AWDThresholdsHighLow" and "AWDy". */
register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (AWDy + AWDThresholdsHighLow));
register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)
+ ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)
+ (AWDThresholdsHighLow));
return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));
}
@ -5225,17 +5270,26 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
* ADC state:
* ADC boost must be configured, without calibration on going, without conversion
* on going on group regular.
* @rmtoll CR BOOST LL_ADC_SetBoostMode\n
* CR BOOST LL_ADC_GetBoostMode
* @rmtoll CR BOOST LL_ADC_SetBoostMode
* @param ADCx ADC instance
* @param BoostMode This parameter can be one of the following values:
* @arg @ref LL_ADC_BOOST_MODE_20MHZ , Boost mode is configured for frequency <= 20Mhz
* @arg @ref LL_ADC_BOOST_MODE_50MHZ , Boost mode is configured for frequency > 20Mhz
* @arg @ref LL_ADC_BOOST_MODE_6MHZ25
* @arg @ref LL_ADC_BOOST_MODE_12MHZ5
* @arg @ref LL_ADC_BOOST_MODE_20MHZ
* @arg @ref LL_ADC_BOOST_MODE_25MHZ
* @arg @ref LL_ADC_BOOST_MODE_50MHZ
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)
{
MODIFY_REG(ADCx->CR, ADC_CR_BOOST, BoostMode);
if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
{
MODIFY_REG(ADCx->CR, ADC_CR_BOOST_0, (BoostMode >> 2UL));
}
else /* Cut 2.x */
{
MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));
}
}
/**
@ -5244,15 +5298,20 @@ __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)
* ADC state:
* ADC boost must be configured, without calibration on going, without conversion
* on going on group regular.
* @rmtoll CR BOOST LL_ADC_SetBoostMode\n
* CR BOOST LL_ADC_GetBoostMode
* @rmtoll CR BOOST LL_ADC_GetBoostMode
* @param ADCx ADC instance
* @retval LL_ADC_BOOST_MODE_20MHZ : Boost mode is configured for frequency <= 20Mhz
* LL_ADC_BOOST_MODE_50MHZ : Boost mode is configured for frequency > 20Mhz
* @retval 0: Boost disabled 1: Boost enabled
*/
__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CR, ADC_CR_BOOST));
if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */
{
return (uint32_t)READ_BIT(ADCx->CR, ADC_CR_BOOST_0);
}
else /* Cut 2.x */
{
return ((READ_BIT(ADCx->CR, ADC_CR_BOOST) == (ADC_CR_BOOST)) ? 1UL : 0UL);
}
}
/**
@ -5421,21 +5480,24 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_CO
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (1)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (2)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (2)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (3)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (3)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (4)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (4)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (6)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (7)
*
* (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.
* (2) Parameter available only if ADC resolution is 16, 14 or 12 bits.
* (3) Parameter available only if ADC resolution is 16 or 14 bits.
* (4) Parameter available only if ADC resolution is 16 bits.
* (3) Parameter available only if ADC resolution is 10 or 8 bits.
* (4) Parameter available only if ADC resolution is 16 or 14 bits.
* (5) Parameter available only if ADC resolution is 16 bits.
* (6) Parameter available only if ADC resolution is 12 bits.
* (7) Parameter available only if ADC resolution is 16 or 14 bits.
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
@ -5452,21 +5514,24 @@ __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_C
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (1)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (2)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (2)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (3)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (3)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (4)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (4)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (6)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (7)
*
* (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.
* (2) Parameter available only if ADC resolution is 16, 14 or 12 bits.
* (3) Parameter available only if ADC resolution is 16 or 14 bits.
* (4) Parameter available only if ADC resolution is 16 bits.
* (3) Parameter available only if ADC resolution is 10 or 8 bits.
* (4) Parameter available only if ADC resolution is 16 or 14 bits.
* (5) Parameter available only if ADC resolution is 16 bits.
* (6) Parameter available only if ADC resolution is 12 bits.
* (7) Parameter available only if ADC resolution is 16 or 14 bits.
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
{

3422
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_bus.h
View File

File diff suppressed because it is too large Load Diff

2
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_cortex.h
View File

@ -107,6 +107,7 @@ extern "C" {
#define LL_MPU_REGION_NUMBER5 0x05UL /*!< REGION Number 5 */
#define LL_MPU_REGION_NUMBER6 0x06UL /*!< REGION Number 6 */
#define LL_MPU_REGION_NUMBER7 0x07UL /*!< REGION Number 7 */
#if !defined(CORE_CM4)
#define LL_MPU_REGION_NUMBER8 0x08UL /*!< REGION Number 8 */
#define LL_MPU_REGION_NUMBER9 0x09UL /*!< REGION Number 9 */
#define LL_MPU_REGION_NUMBER10 0x0AUL /*!< REGION Number 10 */
@ -115,6 +116,7 @@ extern "C" {
#define LL_MPU_REGION_NUMBER13 0x0DUL /*!< REGION Number 13 */
#define LL_MPU_REGION_NUMBER14 0x0EUL /*!< REGION Number 14 */
#define LL_MPU_REGION_NUMBER15 0x0FUL /*!< REGION Number 15 */
#endif /* !defined(CORE_CM4) */
/**
* @}
*/

98
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_exti.c
View File

@ -126,6 +126,23 @@ ErrorStatus LL_EXTI_DeInit(void)
LL_EXTI_WriteReg(PR2, EXTI_PR2_PR_Msk);
LL_EXTI_WriteReg(PR3, EXTI_PR3_PR_Msk);
#if defined(DUAL_CORE)
/* Interrupt mask register set to default reset values for Core 2 (Coretx-M4)*/
LL_EXTI_WriteReg(C2IMR1, 0x00000000U);
LL_EXTI_WriteReg(C2IMR2, 0x00000000U);
LL_EXTI_WriteReg(C2IMR3, 0x00000000U);
/* Event mask register set to default reset values */
LL_EXTI_WriteReg(C2EMR1, 0x00000000U);
LL_EXTI_WriteReg(C2EMR2, 0x00000000U);
LL_EXTI_WriteReg(C2EMR3, 0x00000000U);
/* Clear Pending requests */
LL_EXTI_WriteReg(C2PR1, EXTI_PR1_PR_Msk);
LL_EXTI_WriteReg(C2PR2, EXTI_PR2_PR_Msk);
LL_EXTI_WriteReg(C2PR3, EXTI_PR3_PR_Msk);
#endif /* DUAL_CORE*/
return SUCCESS;
}
@ -175,6 +192,29 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
/* Disable event on provided Lines for Cortex-M7 */
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
}
#if defined(DUAL_CORE)
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
{
/* Enable IT on provided Lines for Cortex-M4 */
LL_C2_EXTI_EnableIT_0_31 (EXTI_InitStruct->Line_0_31);
}
else
{
/* Disable IT on provided Lines for Cortex-M4*/
LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
}
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
{
/* Enable event on provided Lines for Cortex-M4 */
LL_C2_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
}
else
{
/* Disable event on provided Lines for Cortex-M4*/
LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
}
#endif /* DUAL_CORE */
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
{
@ -226,6 +266,29 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
/* Disable event on provided Lines for Cortex-M7 */
LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
}
#if defined(DUAL_CORE)
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
{
/* Enable IT on provided Lines for Cortex-M4 */
LL_C2_EXTI_EnableIT_32_63 (EXTI_InitStruct->Line_32_63);
}
else
{
/* Disable IT on provided Lines for Cortex-M4 */
LL_C2_EXTI_DisableIT_32_63 (EXTI_InitStruct->Line_32_63);
}
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
{
/* Enable event on provided Lines for Cortex-M4 */
LL_C2_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63);
}
else
{
/* Disable event on provided Lines for Cortex-M4 */
LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
}
#endif /* DUAL_CORE */
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
{
@ -278,6 +341,30 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
}
#if defined(DUAL_CORE)
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT)
{
/* Enable IT on provided Lines for Cortex-M4 */
LL_C2_EXTI_EnableIT_64_95 (EXTI_InitStruct->Line_64_95);
}
else
{
/* Disable IT on provided Lines for Cortex-M4 */
LL_C2_EXTI_DisableIT_64_95 (EXTI_InitStruct->Line_64_95);
}
if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT)
{
/* Enable event on provided Lines for Cortex-M4 */
LL_C2_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95);
}
else
{
/* Disable event on provided Lines for Cortex-M4 */
LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
}
#endif /* DUAL_CORE */
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
{
switch (EXTI_InitStruct->Trigger)
@ -317,6 +404,17 @@ ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
#if defined(DUAL_CORE)
/* Disable IT on provided Lines for Cortex-M4*/
LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
LL_C2_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63);
LL_C2_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95);
/* Disable event on provided Lines for Cortex-M4 */
LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63);
LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95);
#endif /* DUAL_CORE */
}
return status;

969
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_ll_exti.h
View File

@ -200,6 +200,16 @@ typedef struct
#define LL_EXTI_MODE_EVENT ((uint8_t)0x02U) /*!< Cortex-M7 Event Mode */
#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x03U) /*!< Cortex-M7 Interrupt & Event Mode */
#if defined(DUAL_CORE)
#define LL_EXTI_MODE_C1_IT LL_EXTI_MODE_IT /*!< Cortex-M7 Interrupt Mode */
#define LL_EXTI_MODE_C1_EVENT LL_EXTI_MODE_EVENT /*!< Cortex-M7 Event Mode */
#define LL_EXTI_MODE_C1_IT_EVENT LL_EXTI_MODE_IT_EVENT /*!< Cortex-M7 Interrupt & Event Mode */
#define LL_EXTI_MODE_C2_IT ((uint8_t)0x10U) /*!< Cortex-M4 Interrupt Mode */
#define LL_EXTI_MODE_C2_EVENT ((uint8_t)0x20U) /*!< Cortex-M4 Event Mode */
#define LL_EXTI_MODE_C2_IT_EVENT ((uint8_t)0x30U) /*!< Cortex-M4 Interrupt & Event Mode */
#endif /* DUAL_CORE */
/**
* @}
*/
@ -648,6 +658,381 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
}
#if defined(DUAL_CORE)
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
* @rmtoll C2IMR1 IMx LL_C2_EXTI_EnableIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_23
* @arg @ref LL_EXTI_LINE_24
* @arg @ref LL_EXTI_LINE_25
* @arg @ref LL_EXTI_LINE_26
* @arg @ref LL_EXTI_LINE_27
* @arg @ref LL_EXTI_LINE_28
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->C2IMR1, ExtiLine);
}
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
* @rmtoll C2IMR2 IMx LL_C2_EXTI_EnableIT_32_63
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_32
* @arg @ref LL_EXTI_LINE_33
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_35
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42
* @arg @ref LL_EXTI_LINE_43
* @arg @ref LL_EXTI_LINE_44
* @arg @ref LL_EXTI_LINE_46
* @arg @ref LL_EXTI_LINE_47
* @arg @ref LL_EXTI_LINE_48
* @arg @ref LL_EXTI_LINE_49
* @arg @ref LL_EXTI_LINE_50
* @arg @ref LL_EXTI_LINE_51
* @arg @ref LL_EXTI_LINE_52
* @arg @ref LL_EXTI_LINE_53
* @arg @ref LL_EXTI_LINE_54
* @arg @ref LL_EXTI_LINE_55
* @arg @ref LL_EXTI_LINE_56
* @arg @ref LL_EXTI_LINE_57
* @arg @ref LL_EXTI_LINE_58
* @arg @ref LL_EXTI_LINE_59
* @arg @ref LL_EXTI_LINE_60
* @arg @ref LL_EXTI_LINE_61
* @arg @ref LL_EXTI_LINE_62
* @arg @ref LL_EXTI_LINE_63
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine)
{
SET_BIT(EXTI->C2IMR2, ExtiLine);
}
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 64 to 95
* @rmtoll C2IMR3 IMx LL_C2_EXTI_EnableIT_64_95
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_64
* @arg @ref LL_EXTI_LINE_65
* @arg @ref LL_EXTI_LINE_66
* @arg @ref LL_EXTI_LINE_67
* @arg @ref LL_EXTI_LINE_68
* @arg @ref LL_EXTI_LINE_69
* @arg @ref LL_EXTI_LINE_70
* @arg @ref LL_EXTI_LINE_71
* @arg @ref LL_EXTI_LINE_72
* @arg @ref LL_EXTI_LINE_73
* @arg @ref LL_EXTI_LINE_74
* @arg @ref LL_EXTI_LINE_75
* @arg @ref LL_EXTI_LINE_76
* @arg @ref LL_EXTI_LINE_77
* @arg @ref LL_EXTI_LINE_78
* @arg @ref LL_EXTI_LINE_79
* @arg @ref LL_EXTI_LINE_80
* @arg @ref LL_EXTI_LINE_82
* @arg @ref LL_EXTI_LINE_84
* @arg @ref LL_EXTI_LINE_85
* @arg @ref LL_EXTI_LINE_86
* @arg @ref LL_EXTI_LINE_87
* @arg @ref LL_EXTI_LINE_ALL_64_95
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_EnableIT_64_95(uint32_t ExtiLine)
{
SET_BIT(EXTI->C2IMR3, ExtiLine);
}
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2
* @rmtoll C2IMR1 IMx LL_C2_EXTI_DisableIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_23
* @arg @ref LL_EXTI_LINE_24
* @arg @ref LL_EXTI_LINE_25
* @arg @ref LL_EXTI_LINE_26
* @arg @ref LL_EXTI_LINE_27
* @arg @ref LL_EXTI_LINE_28
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->C2IMR1, ExtiLine);
}
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2
* @rmtoll C2IMR2 IMx LL_C2_EXTI_DisableIT_32_63
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_32
* @arg @ref LL_EXTI_LINE_33
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_35
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42
* @arg @ref LL_EXTI_LINE_43
* @arg @ref LL_EXTI_LINE_44
* @arg @ref LL_EXTI_LINE_46
* @arg @ref LL_EXTI_LINE_47
* @arg @ref LL_EXTI_LINE_48
* @arg @ref LL_EXTI_LINE_49
* @arg @ref LL_EXTI_LINE_50
* @arg @ref LL_EXTI_LINE_51
* @arg @ref LL_EXTI_LINE_52
* @arg @ref LL_EXTI_LINE_53
* @arg @ref LL_EXTI_LINE_54
* @arg @ref LL_EXTI_LINE_55
* @arg @ref LL_EXTI_LINE_56
* @arg @ref LL_EXTI_LINE_57
* @arg @ref LL_EXTI_LINE_58
* @arg @ref LL_EXTI_LINE_59
* @arg @ref LL_EXTI_LINE_60
* @arg @ref LL_EXTI_LINE_61
* @arg @ref LL_EXTI_LINE_62
* @arg @ref LL_EXTI_LINE_63
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->C2IMR2, ExtiLine);
}
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 64 to 95 for cpu2
* @rmtoll C2IMR3 IMx LL_C2_EXTI_DisableIT_64_95
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_64
* @arg @ref LL_EXTI_LINE_65
* @arg @ref LL_EXTI_LINE_66
* @arg @ref LL_EXTI_LINE_67
* @arg @ref LL_EXTI_LINE_68
* @arg @ref LL_EXTI_LINE_69
* @arg @ref LL_EXTI_LINE_70
* @arg @ref LL_EXTI_LINE_71
* @arg @ref LL_EXTI_LINE_72
* @arg @ref LL_EXTI_LINE_73
* @arg @ref LL_EXTI_LINE_74
* @arg @ref LL_EXTI_LINE_75
* @arg @ref LL_EXTI_LINE_76
* @arg @ref LL_EXTI_LINE_77
* @arg @ref LL_EXTI_LINE_78
* @arg @ref LL_EXTI_LINE_79
* @arg @ref LL_EXTI_LINE_80
* @arg @ref LL_EXTI_LINE_82
* @arg @ref LL_EXTI_LINE_84
* @arg @ref LL_EXTI_LINE_85
* @arg @ref LL_EXTI_LINE_86
* @arg @ref LL_EXTI_LINE_87
* @arg @ref LL_EXTI_LINE_ALL_64_95
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_DisableIT_64_95(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->C2IMR3, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2
* @rmtoll C2IMR1 IMx LL_C2_EXTI_IsEnabledIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_23
* @arg @ref LL_EXTI_LINE_24
* @arg @ref LL_EXTI_LINE_25
* @arg @ref LL_EXTI_LINE_26
* @arg @ref LL_EXTI_LINE_27
* @arg @ref LL_EXTI_LINE_28
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
}
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2
* @rmtoll C2IMR2 IMx LL_C2_EXTI_IsEnabledIT_32_63
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_32
* @arg @ref LL_EXTI_LINE_33
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_35
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42
* @arg @ref LL_EXTI_LINE_43
* @arg @ref LL_EXTI_LINE_44
* @arg @ref LL_EXTI_LINE_46
* @arg @ref LL_EXTI_LINE_47
* @arg @ref LL_EXTI_LINE_48
* @arg @ref LL_EXTI_LINE_49
* @arg @ref LL_EXTI_LINE_50
* @arg @ref LL_EXTI_LINE_51
* @arg @ref LL_EXTI_LINE_52
* @arg @ref LL_EXTI_LINE_53
* @arg @ref LL_EXTI_LINE_54
* @arg @ref LL_EXTI_LINE_55
* @arg @ref LL_EXTI_LINE_56
* @arg @ref LL_EXTI_LINE_57
* @arg @ref LL_EXTI_LINE_58
* @arg @ref LL_EXTI_LINE_59
* @arg @ref LL_EXTI_LINE_60
* @arg @ref LL_EXTI_LINE_61
* @arg @ref LL_EXTI_LINE_62
* @arg @ref LL_EXTI_LINE_63
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine))? 1U : 0U);
}
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95
* @rmtoll C2IMR3 IMx LL_C2_EXTI_IsEnabledIT_64_95
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_64
* @arg @ref LL_EXTI_LINE_65
* @arg @ref LL_EXTI_LINE_66
* @arg @ref LL_EXTI_LINE_67
* @arg @ref LL_EXTI_LINE_68
* @arg @ref LL_EXTI_LINE_69
* @arg @ref LL_EXTI_LINE_70
* @arg @ref LL_EXTI_LINE_71
* @arg @ref LL_EXTI_LINE_72
* @arg @ref LL_EXTI_LINE_73
* @arg @ref LL_EXTI_LINE_74
* @arg @ref LL_EXTI_LINE_75
* @arg @ref LL_EXTI_LINE_76
* @arg @ref LL_EXTI_LINE_77
* @arg @ref LL_EXTI_LINE_78
* @arg @ref LL_EXTI_LINE_79
* @arg @ref LL_EXTI_LINE_80
* @arg @ref LL_EXTI_LINE_82
* @arg @ref LL_EXTI_LINE_84
* @arg @ref LL_EXTI_LINE_85
* @arg @ref LL_EXTI_LINE_86
* @arg @ref LL_EXTI_LINE_87
* @arg @ref LL_EXTI_LINE_ALL_64_95
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->C2IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
}
#endif /* DUAL_CORE */
/**
* @}
@ -1021,6 +1406,382 @@ __STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
}
#if defined(DUAL_CORE)
/**
* @brief Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2
* @rmtoll C2EMR1 EMx LL_C2_EXTI_EnableEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_23
* @arg @ref LL_EXTI_LINE_24
* @arg @ref LL_EXTI_LINE_25
* @arg @ref LL_EXTI_LINE_26
* @arg @ref LL_EXTI_LINE_27
* @arg @ref LL_EXTI_LINE_28
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->C2EMR1, ExtiLine);
}
/**
* @brief Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2
* @rmtoll C2EMR2 EMx LL_C2_EXTI_EnableEvent_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32
* @arg @ref LL_EXTI_LINE_33
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_35
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42
* @arg @ref LL_EXTI_LINE_43
* @arg @ref LL_EXTI_LINE_44
* @arg @ref LL_EXTI_LINE_46
* @arg @ref LL_EXTI_LINE_47
* @arg @ref LL_EXTI_LINE_48
* @arg @ref LL_EXTI_LINE_49
* @arg @ref LL_EXTI_LINE_50
* @arg @ref LL_EXTI_LINE_51
* @arg @ref LL_EXTI_LINE_52
* @arg @ref LL_EXTI_LINE_53
* @arg @ref LL_EXTI_LINE_54
* @arg @ref LL_EXTI_LINE_55
* @arg @ref LL_EXTI_LINE_56
* @arg @ref LL_EXTI_LINE_57
* @arg @ref LL_EXTI_LINE_58
* @arg @ref LL_EXTI_LINE_59
* @arg @ref LL_EXTI_LINE_60
* @arg @ref LL_EXTI_LINE_61
* @arg @ref LL_EXTI_LINE_62
* @arg @ref LL_EXTI_LINE_63
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
{
SET_BIT(EXTI->C2EMR2, ExtiLine);
}
/**
* @brief Enable ExtiLine Event request for Lines in range 64 to 95 for cpu2
* @rmtoll C2EMR3 EMx LL_C2_EXTI_EnableEvent_64_95
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_64
* @arg @ref LL_EXTI_LINE_65
* @arg @ref LL_EXTI_LINE_66
* @arg @ref LL_EXTI_LINE_67
* @arg @ref LL_EXTI_LINE_68
* @arg @ref LL_EXTI_LINE_69
* @arg @ref LL_EXTI_LINE_70
* @arg @ref LL_EXTI_LINE_71
* @arg @ref LL_EXTI_LINE_72
* @arg @ref LL_EXTI_LINE_73
* @arg @ref LL_EXTI_LINE_74
* @arg @ref LL_EXTI_LINE_75
* @arg @ref LL_EXTI_LINE_76
* @arg @ref LL_EXTI_LINE_77
* @arg @ref LL_EXTI_LINE_78
* @arg @ref LL_EXTI_LINE_79
* @arg @ref LL_EXTI_LINE_80
* @arg @ref LL_EXTI_LINE_82
* @arg @ref LL_EXTI_LINE_84
* @arg @ref LL_EXTI_LINE_85
* @arg @ref LL_EXTI_LINE_86
* @arg @ref LL_EXTI_LINE_87
* @arg @ref LL_EXTI_LINE_ALL_64_95
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_EnableEvent_64_95(uint32_t ExtiLine)
{
SET_BIT(EXTI->C2EMR3, ExtiLine);
}
/**
* @brief Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2
* @rmtoll C2EMR1 EMx LL_C2_EXTI_DisableEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_23
* @arg @ref LL_EXTI_LINE_24
* @arg @ref LL_EXTI_LINE_25
* @arg @ref LL_EXTI_LINE_26
* @arg @ref LL_EXTI_LINE_27
* @arg @ref LL_EXTI_LINE_28
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->C2EMR1, ExtiLine);
}
/**
* @brief Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2
* @rmtoll C2EMR2 EMx LL_C2_EXTI_DisableEvent_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32
* @arg @ref LL_EXTI_LINE_33
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_35
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42
* @arg @ref LL_EXTI_LINE_43
* @arg @ref LL_EXTI_LINE_44
* @arg @ref LL_EXTI_LINE_46
* @arg @ref LL_EXTI_LINE_47
* @arg @ref LL_EXTI_LINE_48
* @arg @ref LL_EXTI_LINE_49
* @arg @ref LL_EXTI_LINE_50
* @arg @ref LL_EXTI_LINE_51
* @arg @ref LL_EXTI_LINE_52
* @arg @ref LL_EXTI_LINE_53
* @arg @ref LL_EXTI_LINE_54
* @arg @ref LL_EXTI_LINE_55
* @arg @ref LL_EXTI_LINE_56
* @arg @ref LL_EXTI_LINE_57
* @arg @ref LL_EXTI_LINE_58
* @arg @ref LL_EXTI_LINE_59
* @arg @ref LL_EXTI_LINE_60
* @arg @ref LL_EXTI_LINE_61
* @arg @ref LL_EXTI_LINE_62
* @arg @ref LL_EXTI_LINE_63
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->C2EMR2, ExtiLine);
}
/**
* @brief Disable ExtiLine Event request for Lines in range 64 to 95 for cpu2
* @rmtoll C2EMR3 EMx LL_C2_EXTI_DisableEvent_64_95
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_64
* @arg @ref LL_EXTI_LINE_65
* @arg @ref LL_EXTI_LINE_66
* @arg @ref LL_EXTI_LINE_67
* @arg @ref LL_EXTI_LINE_68
* @arg @ref LL_EXTI_LINE_69
* @arg @ref LL_EXTI_LINE_70
* @arg @ref LL_EXTI_LINE_71
* @arg @ref LL_EXTI_LINE_72
* @arg @ref LL_EXTI_LINE_73
* @arg @ref LL_EXTI_LINE_74
* @arg @ref LL_EXTI_LINE_75
* @arg @ref LL_EXTI_LINE_76
* @arg @ref LL_EXTI_LINE_77
* @arg @ref LL_EXTI_LINE_78
* @arg @ref LL_EXTI_LINE_79
* @arg @ref LL_EXTI_LINE_80
* @arg @ref LL_EXTI_LINE_82
* @arg @ref LL_EXTI_LINE_84
* @arg @ref LL_EXTI_LINE_85
* @arg @ref LL_EXTI_LINE_86
* @arg @ref LL_EXTI_LINE_87
* @arg @ref LL_EXTI_LINE_ALL_64_95
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_DisableEvent_64_95(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->C2EMR3, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2
* @rmtoll C2EMR1 EMx LL_C2_EXTI_IsEnabledEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_23
* @arg @ref LL_EXTI_LINE_24
* @arg @ref LL_EXTI_LINE_25
* @arg @ref LL_EXTI_LINE_26
* @arg @ref LL_EXTI_LINE_27
* @arg @ref LL_EXTI_LINE_28
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
}
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2
* @rmtoll C2EMR2 EMx LL_C2_EXTI_IsEnabledEvent_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32
* @arg @ref LL_EXTI_LINE_33
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_35
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42
* @arg @ref LL_EXTI_LINE_43
* @arg @ref LL_EXTI_LINE_44
* @arg @ref LL_EXTI_LINE_46
* @arg @ref LL_EXTI_LINE_47
* @arg @ref LL_EXTI_LINE_48
* @arg @ref LL_EXTI_LINE_49
* @arg @ref LL_EXTI_LINE_50
* @arg @ref LL_EXTI_LINE_51
* @arg @ref LL_EXTI_LINE_52
* @arg @ref LL_EXTI_LINE_53
* @arg @ref LL_EXTI_LINE_54
* @arg @ref LL_EXTI_LINE_55
* @arg @ref LL_EXTI_LINE_56
* @arg @ref LL_EXTI_LINE_57
* @arg @ref LL_EXTI_LINE_58
* @arg @ref LL_EXTI_LINE_59
* @arg @ref LL_EXTI_LINE_60
* @arg @ref LL_EXTI_LINE_61
* @arg @ref LL_EXTI_LINE_62
* @arg @ref LL_EXTI_LINE_63
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
}
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 for cpu2
* @rmtoll C2EMR3 EMx LL_C2_EXTI_IsEnabledEvent_64_95
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_64
* @arg @ref LL_EXTI_LINE_65
* @arg @ref LL_EXTI_LINE_66
* @arg @ref LL_EXTI_LINE_67
* @arg @ref LL_EXTI_LINE_68
* @arg @ref LL_EXTI_LINE_69
* @arg @ref LL_EXTI_LINE_70
* @arg @ref LL_EXTI_LINE_71
* @arg @ref LL_EXTI_LINE_72
* @arg @ref LL_EXTI_LINE_73
* @arg @ref LL_EXTI_LINE_74
* @arg @ref LL_EXTI_LINE_75
* @arg @ref LL_EXTI_LINE_76
* @arg @ref LL_EXTI_LINE_77
* @arg @ref LL_EXTI_LINE_78
* @arg @ref LL_EXTI_LINE_79
* @arg @ref LL_EXTI_LINE_80
* @arg @ref LL_EXTI_LINE_82
* @arg @ref LL_EXTI_LINE_84
* @arg @ref LL_EXTI_LINE_85
* @arg @ref LL_EXTI_LINE_86
* @arg @ref LL_EXTI_LINE_87
* @arg @ref LL_EXTI_LINE_ALL_64_95
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->C2EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
}
#endif /* DUAL_CORE */
/**
* @}
*/
@ -1788,6 +2549,214 @@ __STATIC_INLINE void LL_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
WRITE_REG(EXTI->PR3, ExtiLine);
}
#if defined(DUAL_CORE)
/**
* @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 for cpu2
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll C2PR1 PIFx LL_C2_EXTI_IsActiveFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->C2PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);
}
/**
* @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63 for cpu2
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll C2PR2 PIFx LL_C2_EXTI_IsActiveFlag_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_49
* @arg @ref LL_EXTI_LINE_51
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->C2PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);
}
/**
* @brief Check if the ExtLine Flag is set or not for Lines in range 64 to 95 for cpu2
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll C2PR3 PIFx LL_C2_EXTI_IsActiveFlag_64_95
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_82
* @arg @ref LL_EXTI_LINE_84
* @arg @ref LL_EXTI_LINE_85
* @arg @ref LL_EXTI_LINE_86
* @arg @ref LL_EXTI_LINE_ALL_64_95
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->C2PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);
}
/**
* @brief Read ExtLine Combination Flag for Lines in range 0 to 31 for cpu2
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll C2PR1 PIFx LL_C2_EXTI_ReadFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
{
return (uint32_t)(READ_BIT(EXTI->C2PR1, ExtiLine));
}
/**
* @brief Read ExtLine Combination Flag for Lines in range 32 to 63 for cpu2
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll C2PR2 PIFx LL_C2_EXTI_ReadFlag_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_49
* @arg @ref LL_EXTI_LINE_51
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
{
return (uint32_t)(READ_BIT(EXTI->C2PR2, ExtiLine));
}
/**
* @brief Read ExtLine Combination Flag for Lines in range 64 to 95 for cpu2
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll C2PR3 PIFx LL_C2_EXTI_ReadFlag_64_95
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_82
* @arg @ref LL_EXTI_LINE_84
* @arg @ref LL_EXTI_LINE_85
* @arg @ref LL_EXTI_LINE_86
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_64_95(uint32_t ExtiLine)
{
return (uint32_t)(READ_BIT(EXTI->C2PR3, ExtiLine));
}
/**
* @brief Clear ExtLine Flags for Lines in range 0 to 31 for cpu2
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll C2PR1 PIFx LL_C2_EXTI_ClearFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
{
WRITE_REG(EXTI->C2PR1, ExtiLine);
}
/**
* @brief Clear ExtLine Flags for Lines in range 32 to 63 for cpu2
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll C2PR2 PIFx LL_C2_EXTI_ClearFlag_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_49
* @arg @ref LL_EXTI_LINE_51
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
{
WRITE_REG(EXTI->C2PR2, ExtiLine);
}
/**
* @brief Clear ExtLine Flags for Lines in range 64 to 95 for cpu2
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll C2PR3 PIFx LL_C2_EXTI_ClearFlag_64_95
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_82
* @arg @ref LL_EXTI_LINE_84
* @arg @ref LL_EXTI_LINE_85
* @arg @ref LL_EXTI_LINE_86
* @retval None
*/
__STATIC_INLINE void LL_C2_EXTI_ClearFlag_64_95(uint32_t ExtiLine)
{
WRITE_REG(EXTI->C2PR3, ExtiLine);
}
#endif /* DUAL_CORE */
/**
* @brief Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31
* @rmtoll D3PMR1 MRx LL_D3_EXTI_EnablePendMask_0_31

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