mirror of https://github.com/ARMmbed/mbed-os.git
STM32 WATCHDOG : use ST HAL in order to make code commun for all STM32
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feec85cc37
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4300e5d6c4
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@ -1,5 +1,5 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2017 ARM Limited
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* Copyright (c) 2006-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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@ -14,17 +14,15 @@
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* limitations under the License.
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*/
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#include "watchdog_api.h"
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#include "reset_reason_api.h"
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#ifdef DEVICE_WATCHDOG
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#include "watchdog_api.h"
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#include "reset_reason_api.h"
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#include "device.h"
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#include "mbed_error.h"
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#include <stdbool.h>
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#define LSI_RC_HZ 32000 // Frequency of the low-speed internal RC oscillator that drives IWDG
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#define MAX_IWDG_PR 0x6 // Max value of Prescaler_divider bits (PR) of Prescaler_register (IWDG_PR)
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#define MAX_IWDG_RL 0xFFFUL // Max value of Watchdog_counter_reload_value bits (RL) of Reload_register (IWDG_RLR).
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@ -36,12 +34,12 @@
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// and Watchdog_counter_reload_value bits (RL) of Reload_register (IWDG_RLR)
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// to a timeout value [ms].
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#define PR_RL2UINT64_TIMEOUT_MS(PR_BITS, RL_BITS) \
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((PR2PRESCALER_DIV(PR_BITS)) * (RL_BITS) * 1000ULL / (LSI_RC_HZ))
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((PR2PRESCALER_DIV(PR_BITS)) * (RL_BITS) * 1000ULL / (LSI_VALUE))
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// Convert Prescaler_divider bits (PR) of Prescaler_register (IWDG_PR) and a timeout value [ms]
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// to Watchdog_counter_reload_value bits (RL) of Reload_register (IWDG_RLR)
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#define PR_TIMEOUT_MS2RL(PR_BITS, TIMEOUT_MS) \
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((TIMEOUT_MS) * (LSI_RC_HZ) / (PR2PRESCALER_DIV(PR_BITS)) / 1000UL)
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((TIMEOUT_MS) * (LSI_VALUE) / (PR2PRESCALER_DIV(PR_BITS)) / 1000UL)
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#define MAX_TIMEOUT_MS_UINT64 PR_RL2UINT64_TIMEOUT_MS(MAX_IWDG_PR, MAX_IWDG_RL)
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#if (MAX_TIMEOUT_MS_UINT64 > UINT32_MAX)
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@ -64,6 +62,8 @@ static uint8_t pick_min_iwdg_pr(const uint32_t timeout_ms) {
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return INVALID_IWDG_PR;
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}
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IWDG_HandleTypeDef IwdgHandle;
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watchdog_status_t hal_watchdog_init(const watchdog_config_t *config)
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{
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const uint8_t pr = pick_min_iwdg_pr(config->timeout_ms);
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@ -72,40 +72,25 @@ watchdog_status_t hal_watchdog_init(const watchdog_config_t *config)
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}
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const uint32_t rl = PR_TIMEOUT_MS2RL(pr, config->timeout_ms);
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// Set the Key_value bits (KEY) of Key_register (IWDG_KR) to 0x5555
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// in order to enable write access to IWDG_PR and IWDG_RLR registers.
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MODIFY_REG(IWDG->KR, IWDG_KR_KEY_Msk, (IWDG_KR_KEY_Msk & (0x5555U << IWDG_KR_KEY_Pos)));
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IwdgHandle.Instance = IWDG;
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// Wait for the Watchdog_prescaler_value_update bit (PVU) of
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// Status_register (IWDG_SR) to be reset.
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while (READ_BIT(IWDG->SR, IWDG_SR_PVU)) {
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IwdgHandle.Init.Prescaler = pr;
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IwdgHandle.Init.Reload = rl;
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#if defined IWDG_WINR_WIN
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IwdgHandle.Init.Window = IWDG_WINDOW_DISABLE;
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#endif
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if (HAL_IWDG_Init(&IwdgHandle) != HAL_OK)
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{
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error("HAL_IWDG_Init error\n");
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}
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// Set the Prescaler_divider bits (PR) of Prescaler_register (IWDG_PR).
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MODIFY_REG(IWDG->PR, IWDG_PR_PR_Msk, (IWDG_PR_PR_Msk & (pr << IWDG_PR_PR_Pos)));
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// Wait for the Watchdog_counter_reload_value_update bit (RVU) of
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// Status_register (IWDG_SR) to be reset.
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while (READ_BIT(IWDG->SR, IWDG_SR_RVU)) {
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}
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// Set the Watchdog_counter_reload_value bits (RL) of Reload_register (IWDG_RLR).
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MODIFY_REG(IWDG->RLR, IWDG_RLR_RL_Msk, (IWDG_RLR_RL_Msk & (rl << IWDG_RLR_RL_Pos)));
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// Set the Key_value bits (KEY) of Key_register (IWDG_KR) to 0xAAAA
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// in order to reload IWDG_RLR register value.
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MODIFY_REG(IWDG->KR, IWDG_KR_KEY_Msk, (IWDG_KR_KEY_Msk & (0xAAAAU << IWDG_KR_KEY_Pos)));
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// Set the Key_value bits (KEY) of Key_register (IWDG_KR) to 0xCCCC
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// in order to start the watchdog.
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MODIFY_REG(IWDG->KR, IWDG_KR_KEY_Msk, (IWDG_KR_KEY_Msk & (0xCCCCU << IWDG_KR_KEY_Pos)));
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return WATCHDOG_STATUS_OK;
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}
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void hal_watchdog_kick(void)
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{
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// Set the Key_value bits (KEY) of Key_register (IWDG_KR) to 0xAAAA
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// in order to reload IWDG_RLR register value.
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MODIFY_REG(IWDG->KR, IWDG_KR_KEY_Msk, (IWDG_KR_KEY_Msk & (0xAAAAU << IWDG_KR_KEY_Pos)));
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HAL_IWDG_Refresh(&IwdgHandle);
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}
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watchdog_status_t hal_watchdog_stop(void)
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