mirror of https://github.com/ARMmbed/mbed-os.git
Add IAR support for the target AN382 of MPS2.
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target AN382(ARM_MPS2_M0). Add "IAR" to supported_toolchain list. Change-Id: I2b2ad7645166c4f973a8baa9c394521514183767 Signed-off-by: Shawn Shan <shawn.shan@arm.com>pull/9870/head
Shawn Shan
parent
b3ee6cb706
commit
6374790b26
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License) you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* This file is derivative of mbed-os V5.10.4 CM3DS MPS2.icf for IAR
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*/
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/* Code memory zones */
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define symbol ZBT_SSRAM1_START = 0x00000000;
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define symbol ZBT_SSRAM1_SIZE = 0x00400000; /* 4 MiB */
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/* Data memory zones */
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define symbol ZBT_SSRAM23_START = 0x20000000;
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define symbol ZBT_SSRAM23_SIZE = 0x00400000; /* 4 MiB */
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/* NVIC vector numbers and size. */
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define symbol NVIC_NUM_VECTORS = 16 + 48;
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define symbol NVIC_VECTORS_SIZE = NVIC_NUM_VECTORS * 4;
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/* Specials */
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define symbol __ICFEDIT_intvec_start__ = ZBT_SSRAM1_START;
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/* Memory Regions */
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define symbol __ICFEDIT_region_ROM_start__ = ZBT_SSRAM1_START;
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define symbol __ICFEDIT_region_ROM_end__ = ZBT_SSRAM1_START + ZBT_SSRAM1_SIZE - 1;
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/*
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* At execution, RAM is set to be in ZBT SSRAM2 and 3, just after the vector
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* table previously moved from Flash.
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*/
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define symbol __ICFEDIT_region_RAM_start__ = ZBT_SSRAM23_START + NVIC_VECTORS_SIZE;
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define symbol __ICFEDIT_region_RAM_end__ = ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE;
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/* Sizes */
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/* Heap and Stack size */
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define symbol __ICFEDIT_size_heap__ = 0x1000;
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define symbol __ICFEDIT_size_cstack__ = 0x400;
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM_region { readwrite,
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block CSTACK, block HEAP };
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@ -0,0 +1,317 @@
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;/*
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; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Licensed under the Apache License, Version 2.0 (the License); you may
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; * not use this file except in compliance with the License.
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; * You may obtain a copy of the License at
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; *
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; * http://www.apache.org/licenses/LICENSE-2.0
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; *
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; * Unless required by applicable law or agreed to in writing, software
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; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; * See the License for the specific language governing permissions and
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; * limitations under the License.
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; */
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;/*
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; * This file is derivative of mbed-os V5.10.4 CM3DS startup_MPS2.S for IAR
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; */
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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PUBLIC __vector_table_0x1c
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PUBLIC __Vectors
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PUBLIC __Vectors_End
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PUBLIC __Vectors_Size
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DATA
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__vector_table
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DCD sfe(CSTACK) ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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__vector_table_0x1c
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD UARTRX0_Handler ; UART 0 RX Handler
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DCD UARTTX0_Handler ; UART 0 TX Handler
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DCD UARTRX1_Handler ; UART 1 RX Handler
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DCD UARTTX1_Handler ; UART 1 TX Handler
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DCD UARTRX2_Handler ; UART 2 RX Handler
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DCD UARTTX2_Handler ; UART 2 TX Handler
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DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
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DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
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DCD TIMER0_Handler ; TIMER 0 handler
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DCD TIMER1_Handler ; TIMER 1 handler
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DCD DUALTIMER_HANDLER ; Dual timer handler
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DCD SPI_Handler ; SPI exceptions Handler
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DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
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DCD ETHERNET_Handler ; Ethernet Overflow Handler
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DCD I2S_Handler ; I2S Handler
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DCD TSC_Handler ; Touch Screen handler
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DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
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DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
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DCD UARTRX3_Handler ; UART 3 RX Handler
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DCD UARTTX3_Handler ; UART 3 TX Handler
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DCD UARTRX4_Handler ; UART 4 RX Handler
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DCD UARTTX4_Handler ; UART 4 TX Handler
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DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
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DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
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DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
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DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
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DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
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DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
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DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
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DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
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DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
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DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
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__Vectors_End
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__Vectors EQU __vector_table
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__Vectors_Size EQU __Vectors_End - __Vectors
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER:NOROOT(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK UARTRX0_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UARTRX0_Handler
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B UARTRX0_Handler
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PUBWEAK UARTTX0_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UARTTX0_Handler
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B UARTTX0_Handler
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PUBWEAK UARTRX1_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UARTRX1_Handler
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B UARTRX1_Handler
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PUBWEAK UARTTX1_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UARTTX1_Handler
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B UARTTX1_Handler
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PUBWEAK UARTRX2_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UARTRX2_Handler
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B UARTRX2_Handler
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PUBWEAK UARTTX2_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UARTTX2_Handler
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B UARTTX2_Handler
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PUBWEAK PORT0_COMB_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT0_COMB_Handler
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B PORT0_COMB_Handler
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PUBWEAK PORT1_COMB_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT1_COMB_Handler
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B PORT1_COMB_Handler
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PUBWEAK TIMER0_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIMER0_Handler
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B TIMER0_Handler
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PUBWEAK TIMER1_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TIMER1_Handler
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B TIMER1_Handler
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PUBWEAK DUALTIMER_HANDLER
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SECTION .text:CODE:REORDER:NOROOT(1)
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DUALTIMER_HANDLER
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B DUALTIMER_HANDLER
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PUBWEAK SPI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SPI_Handler
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B SPI_Handler
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PUBWEAK UARTOVF_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UARTOVF_Handler
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B UARTOVF_Handler
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PUBWEAK ETHERNET_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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ETHERNET_Handler
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B ETHERNET_Handler
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PUBWEAK I2S_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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I2S_Handler
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B I2S_Handler
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PUBWEAK TSC_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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TSC_Handler
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B TSC_Handler
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PUBWEAK PORT2_COMB_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT2_COMB_Handler
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B PORT2_COMB_Handler
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PUBWEAK PORT3_COMB_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT3_COMB_Handler
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B PORT3_COMB_Handler
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PUBWEAK UARTRX3_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UARTRX3_Handler
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B UARTRX3_Handler
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PUBWEAK UARTTX3_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UARTTX3_Handler
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B UARTTX3_Handler
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PUBWEAK UARTRX4_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UARTRX4_Handler
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B UARTRX4_Handler
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PUBWEAK UARTTX4_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UARTTX4_Handler
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B UARTTX4_Handler
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PUBWEAK ADCSPI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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ADCSPI_Handler
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B ADCSPI_Handler
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PUBWEAK SHIELDSPI_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SHIELDSPI_Handler
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B SHIELDSPI_Handler
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PUBWEAK PORT0_0_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT0_0_Handler
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B PORT0_0_Handler
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PUBWEAK PORT0_1_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT0_1_Handler
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B PORT0_1_Handler
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PUBWEAK PORT0_2_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT0_2_Handler
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B PORT0_2_Handler
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PUBWEAK PORT0_3_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT0_3_Handler
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B PORT0_3_Handler
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PUBWEAK PORT0_4_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT0_4_Handler
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B PORT0_4_Handler
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PUBWEAK PORT0_5_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT0_5_Handler
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B PORT0_5_Handler
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PUBWEAK PORT0_6_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT0_6_Handler
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B PORT0_6_Handler
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PUBWEAK PORT0_7_Handler
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SECTION .text:CODE:REORDER:NOROOT(1)
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PORT0_7_Handler
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B PORT0_7_Handler
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END
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@ -5205,7 +5205,7 @@
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"ARM_MPS2_M0": {
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"inherits": ["ARM_MPS2_Target"],
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"core": "Cortex-M0",
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"supported_toolchains": ["ARM", "GCC_ARM"],
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"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
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"extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0"],
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"macros": [
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"CMSDK_CM0",
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