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STM32 WATCHDOG : increase timeout value

pull/10657/head
jeromecoutant 2018-03-29 10:56:54 +02:00 committed by Filip Jagodzinski
parent 4300e5d6c4
commit 570e9b0bf4
8 changed files with 15 additions and 28 deletions
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6
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c
View File

@ -124,10 +124,8 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to LSI variation, we need to wait at
least 6 cycles so 39 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 39U
/* MBED */
#define HAL_IWDG_DEFAULT_TIMEOUT 96u
/**
* @}
*/

1
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c
View File

@ -121,6 +121,7 @@
higher prescaler (256), and according to HSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48U
/**
* @}
*/

6
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_iwdg.c
View File

@ -119,10 +119,8 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to HSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48U
/* MBED */
#define HAL_IWDG_DEFAULT_TIMEOUT 96u
/**
* @}
*/

6
targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_iwdg.c
View File

@ -124,10 +124,8 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256U), and according to HSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/* MBED */
#define HAL_IWDG_DEFAULT_TIMEOUT 96u
/**
* @}
*/

6
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c
View File

@ -117,10 +117,8 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to HSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48U
/* MBED */
#define HAL_IWDG_DEFAULT_TIMEOUT 96u
/**
* @}
*/

6
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c
View File

@ -124,10 +124,8 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to LSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/* MBED */
#define HAL_IWDG_DEFAULT_TIMEOUT 96u
/**
* @}
*/

6
targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_iwdg.c
View File

@ -118,10 +118,8 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to HSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/* MBED */
#define HAL_IWDG_DEFAULT_TIMEOUT 96u
/**
* @}
*/

6
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c
View File

@ -124,10 +124,8 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to HSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/* MBED */
#define HAL_IWDG_DEFAULT_TIMEOUT 96u
/**
* @}
*/