diff --git a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c
index 1899f1f862..c0be82e22e 100644
--- a/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c
+++ b/targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_iwdg.c
@@ -124,10 +124,8 @@
 /** @defgroup IWDG_Private_Defines IWDG Private Defines
   * @{
   */
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With 
-   higher prescaler (256), and according to LSI variation, we need to wait at 
-   least 6 cycles so 39 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT            39U
+/* MBED */
+#define HAL_IWDG_DEFAULT_TIMEOUT            96u
 /**
   * @}
   */
diff --git a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c
index d654662cc5..b762736e78 100644
--- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c
+++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_iwdg.c
@@ -121,6 +121,7 @@
    higher prescaler (256), and according to HSI variation, we need to wait at
    least 6 cycles so 48 ms. */
 #define HAL_IWDG_DEFAULT_TIMEOUT            48U
+
 /**
   * @}
   */
diff --git a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_iwdg.c
index b680c070fd..f75e2eac66 100644
--- a/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_iwdg.c
+++ b/targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_iwdg.c
@@ -119,10 +119,8 @@
 /** @defgroup IWDG_Private_Defines IWDG Private Defines
   * @{
   */
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With 
-   higher prescaler (256), and according to HSI variation, we need to wait at
-   least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT            48U
+/* MBED */
+#define HAL_IWDG_DEFAULT_TIMEOUT            96u
 /**
   * @}
   */
diff --git a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_iwdg.c
index 479f4d9507..b576778df2 100644
--- a/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_iwdg.c
+++ b/targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_iwdg.c
@@ -124,10 +124,8 @@
 /** @defgroup IWDG_Private_Defines IWDG Private Defines
   * @{
   */
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With 
-   higher prescaler (256U), and according to HSI variation, we need to wait at 
-   least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT            48u
+/* MBED */
+#define HAL_IWDG_DEFAULT_TIMEOUT            96u
 /**
   * @}
   */
diff --git a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c
index 672aad1624..721f6011b3 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c
@@ -117,10 +117,8 @@
 /** @defgroup IWDG_Private_Defines IWDG Private Defines
   * @{
   */
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With 
-   higher prescaler (256), and according to HSI variation, we need to wait at
-   least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT            48U
+/* MBED */
+#define HAL_IWDG_DEFAULT_TIMEOUT            96u
 /**
   * @}
   */
diff --git a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c
index 4a2dda8465..85dc479446 100644
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c
@@ -124,10 +124,8 @@
 /** @defgroup IWDG_Private_Defines IWDG Private Defines
   * @{
   */
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With 
-   higher prescaler (256), and according to LSI variation, we need to wait at 
-   least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT            48u
+/* MBED */
+#define HAL_IWDG_DEFAULT_TIMEOUT            96u
 /**
   * @}
   */
diff --git a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_iwdg.c
index 7f89b5611a..c057cff97c 100644
--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_iwdg.c
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_iwdg.c
@@ -118,10 +118,8 @@
 /** @defgroup IWDG_Private_Defines IWDG Private Defines
   * @{
   */
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With 
-   higher prescaler (256), and according to HSI variation, we need to wait at 
-   least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT            48u
+/* MBED */
+#define HAL_IWDG_DEFAULT_TIMEOUT            96u
 /**
   * @}
   */
diff --git a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c
index e5080c41b1..a415996a53 100644
--- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c
+++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_iwdg.c
@@ -124,10 +124,8 @@
 /** @defgroup IWDG_Private_Defines IWDG Private Defines
   * @{
   */
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With 
-   higher prescaler (256), and according to HSI variation, we need to wait at 
-   least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT            48u
+/* MBED */
+#define HAL_IWDG_DEFAULT_TIMEOUT            96u
 /**
   * @}
   */