mirror of https://github.com/ARMmbed/mbed-os.git
[M2351] Remove unnecessary toolchain directory TOOLCHAIN_ARM_MICRO
ccli8
parent
120e43ed14
commit
26ff0677dc
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@ -1,172 +0,0 @@
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#! armcc -E
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/* Default flash/SRAM partition
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*
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* Default flash partition:
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* Secure: 256KiB
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* Non-secure: 256KiB
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*
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* Default SRAM partition:
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* Secure: 32KiB
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* Non-secure: 64KiB
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*/
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#ifndef MBED_ROM_SIZE_S
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#define MBED_ROM_SIZE_S (0x40000)
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#endif
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#ifndef MBED_RAM_SIZE_S
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#define MBED_RAM_SIZE_S (0x8000)
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#endif
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#ifndef NU_TZ_NSC_SIZE
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#define NU_TZ_NSC_SIZE (0x1000)
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#endif
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#if defined(DOMAIN_NS) && DOMAIN_NS
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#ifndef MBED_APP_START
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#define MBED_APP_START (0x10000000 + MBED_ROM_START + MBED_ROM_SIZE_S)
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#endif
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#ifndef MBED_APP_SIZE
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#define MBED_APP_SIZE (MBED_ROM_SIZE - MBED_ROM_SIZE_S)
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#endif
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#ifndef MBED_RAM_APP_START
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#define MBED_RAM_APP_START (0x10000000 + MBED_RAM_START + MBED_RAM_SIZE_S)
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#endif
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#ifndef MBED_RAM_APP_SIZE
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#define MBED_RAM_APP_SIZE (MBED_RAM_SIZE - MBED_RAM_SIZE_S)
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#endif
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#if !defined(MBED_BOOT_STACK_SIZE)
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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#else
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#ifndef MBED_APP_START
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#define MBED_APP_START MBED_ROM_START
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#endif
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#ifndef MBED_APP_SIZE
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#define MBED_APP_SIZE MBED_ROM_SIZE_S
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#endif
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#ifndef MBED_RAM_APP_START
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#define MBED_RAM_APP_START MBED_RAM_START
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#endif
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#ifndef MBED_RAM_APP_SIZE
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#define MBED_RAM_APP_SIZE MBED_RAM_SIZE_S
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#endif
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#if !defined(MBED_BOOT_STACK_SIZE)
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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#endif
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/* Requirements for NSC location
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*
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* 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
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* 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
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* 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
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* 4. NSC region size defaults to 4KiB if not defined.
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*/
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#define NU_TZ_NSC_START (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
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#if defined(DOMAIN_NS) && DOMAIN_NS
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LR_IROM1 MBED_APP_START
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{
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/* load address = execution address */
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ER_IROM1 +0
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{
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*(RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE
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{
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}
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/* Reserve for vectors
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*
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* Vector table base address is required to be 128-byte aligned at a minimum.
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* A PE might impose further restrictions on it. */
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ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
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{
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}
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/* 16 byte-aligned */
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RW_IRAM1 AlignExpr(+0, 16)
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{
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.ANY (+RW +ZI)
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}
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
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{
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}
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}
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ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
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ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_APP_START + MBED_RAM_APP_SIZE)
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#else
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LR_IROM1 MBED_APP_START
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{
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/* load address = execution address */
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ER_IROM1 +0
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{
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*(RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE
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{
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}
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/* Reserve for vectors
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*
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* Vector table base address is required to be 128-byte aligned at a minimum.
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* A PE might impose further restrictions on it. */
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ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))
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{
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}
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/* 16 byte-aligned */
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RW_IRAM1 AlignExpr(+0, 16)
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{
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.ANY (+RW +ZI)
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}
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ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
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{
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}
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}
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LR_IROM_NSC NU_TZ_NSC_START NU_TZ_NSC_SIZE
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{
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ER_IROM_NSC +0
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{
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*(Veneer$$CMSE)
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}
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ER_IROM_NSC_PAD +0 FILL 0xFFFFFFFF (NU_TZ_NSC_START + NU_TZ_NSC_SIZE - ImageLimit(ER_IROM_NSC))
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{
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}
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}
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ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_START)
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ScatterAssert(LoadLimit(LR_IROM_NSC) <= (NU_TZ_NSC_START + NU_TZ_NSC_SIZE))
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/* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */
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ScatterAssert(LoadBase(LR_IROM_NSC) >= 0x4000)
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ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE))
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#endif
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