mirror of https://github.com/ARMmbed/mbed-os.git
Added support for PSA target to WIFI_BT board
Added WiFi_Bt CM4 PSA target in mbedos json Added SPE-NSPE mailbox initialization for CM4 SystemInit Made similar to FUTURE_SEQUANA configurations Copied FUTURE_SEQUANA CM0 SPM part for WiFi_Bt smoke test Added CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets Sorted files for new CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets Copied files for CY8CKIT_062_WIFI_BT_M0_PSA from FUTURE_SEQUANA Copied and updated cm0p start files Corrected according to FUTURE_SEQUANA Changes to M0 startup files to have SPM started Fixed implicit declaration warning Commented interrupts enabling according to FUTURE_SEQUANA flow Updated prebuild spm_smore CM0 hex for CM4 target Turned on greentea environment Used special memory region for common CM0/CM4 data Updated prebuild CM0 SPM hex Placed shared memory region for flash operations into SPM shared memory region Updated cyprotection code and configuration Start address of protected regions is set by a defined number from target.json Added masters pcMask configuration Added support for PSA target to WIFI_BT board Enabled resources protection for SPM Aligned RAM usage according to Cypress FlashBoot and CyBootloader alligned protection config Added CYW943012P6EVB_01_M0 target Enlarged heap size, remobed nv_seed Added heap reservation in linker script from mbed-os Removed heap size definition turned on nv_seed config Removed nv_seed macros Enabled protection for PSoC6 CM0 Added PSoC6 CM0 PSA readme Enabled mbed_hal-spm test Enabled nv_seed and removed unneeded ipc config define Added SPDX string to feature_ble cypress target files Removed unneeded supported_toolchains lines for Cypress targets Disabled protection settings Corrected flash initialization for PSoC6 CM0 PSA Changed PSoC6 IPC6 protection for flash Enabled special flash initialization and enabled protection settings Updated and added new prebuild PSoC6 CM0 PSA hex files Disabled HW TRNG and CRC for PSoC6 CM4 PSA target Added missing const to allow types to match Updated PSoC6 WIFI_BT_PSA prebuilt directory Moved PSoC6 shared section usage area definition to begin of ld Added initial ARM_STD linker and startup files for PSoC6 CM0 Added initial IAR linker and startup files for PSoC6 CM0 Added defines to disable some SPM protection settings for PSoC64 Moved Flash function variables into separate memory region Added defines for new Public area definition Updated PSoC6 CM0_PSA hex-filespull/9908/head
Oleg Kapshii
Ryan Morse
parent
277c91f3b7
commit
aedec74b9a
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@ -33,7 +33,7 @@ using namespace utest::v1;
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#define THREAD_STACK_SIZE 512
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#elif defined(__ARM_FM)
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#define THREAD_STACK_SIZE 512
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#elif defined(TARGET_FUTURE_SEQUANA_PSA)
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#elif defined(TARGET_FUTURE_SEQUANA_PSA) || defined(TARGET_CY8CKIT_062_WIFI_BT_PSA)
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#define THREAD_STACK_SIZE 512
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#else
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#define THREAD_STACK_SIZE 320 /* larger stack cause out of heap memory on some 16kB RAM boards in multi thread test*/
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@ -41,7 +41,7 @@ volatile bool thread_should_continue = true;
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#define THREAD_STACK_SIZE 512
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#elif defined(__ARM_FM)
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#define THREAD_STACK_SIZE 512
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#elif defined(TARGET_FUTURE_SEQUANA_PSA)
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#elif defined(TARGET_FUTURE_SEQUANA_PSA) || defined(TARGET_CY8CKIT_062_WIFI_BT_PSA)
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#define THREAD_STACK_SIZE 512
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#else
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#define THREAD_STACK_SIZE 256
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@ -36,7 +36,7 @@
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#define PARALLEL_THREAD_STACK_SIZE 512
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#elif defined(__ARM_FM)
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#define PARALLEL_THREAD_STACK_SIZE 512
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#elif defined(TARGET_FUTURE_SEQUANA_PSA)
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#elif defined(TARGET_FUTURE_SEQUANA_PSA) || defined(TARGET_CY8CKIT_062_WIFI_BT_PSA)
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#define PARALLEL_THREAD_STACK_SIZE 512
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#else
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#define PARALLEL_THREAD_STACK_SIZE 384
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@ -2,6 +2,7 @@
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* mbed Microcontroller Library
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* Copyright (c) 2017-2017 ARM Limited
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* Copyright (c) 2017-2018 Future Electronics
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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@ -2,6 +2,7 @@
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* mbed Microcontroller Library
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* Copyright (c) 2017-2017 ARM Limited
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* Copyright (c) 2017-2018 Future Electronics
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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@ -2,6 +2,7 @@
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* mbed Microcontroller Library
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* Copyright (c) 2017-2017 ARM Limited
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* Copyright (c) 2017-2018 Future Electronics
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2018 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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@ -14,6 +14,9 @@
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"FUTURE_SEQUANA_M0_PSA": {
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"storage_type": "TDB_INTERNAL"
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},
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"CY8CKIT_062_WIFI_BT_M0_PSA": {
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"storage_type": "TDB_INTERNAL"
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},
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"K66F": {
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"storage_type": "TDB_INTERNAL"
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},
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@ -14,6 +14,10 @@
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"FUTURE_SEQUANA_M0_PSA": {
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"internal_size": "0x8000",
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"internal_base_address": "0x10078000"
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},
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"CY8CKIT_062_WIFI_BT_M0_PSA": {
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"internal_size": "0x8000",
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"internal_base_address": "0x10078000"
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}
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}
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}
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@ -49,6 +49,24 @@
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},
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"FUTURE_SEQUANA_M0_PSA": {
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"enabled" : false
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},
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"CY8CKIT_062_WIFI_BT": {
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"area_1_address": "0x100F8000",
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"area_1_size": 16384,
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"area_2_address": "0x100FC000",
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"area_2_size": 16384
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},
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"CY8CKIT_062_WIFI_BT_M0": {
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"area_1_address": "0x10078000",
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"area_1_size": 16384,
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"area_2_address": "0x1007C000",
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"area_2_size": 16384
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},
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"CY8CKIT_062_WIFI_BT_PSA": {
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"enabled" : false
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},
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"CY8CKIT_062_WIFI_BT_M0_PSA": {
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"enabled" : false
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}
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}
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}
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@ -1,6 +1,7 @@
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/*
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* mbed Microcontroller Library
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* Copyright (c) 2017-2018 Future Electronics
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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@ -1,6 +1,7 @@
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/*
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* mbed Microcontroller Library
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* Copyright (c) 2017-2018 Future Electronics
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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@ -3,8 +3,8 @@
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; to pass a scatter file through a C preprocessor.
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;*******************************************************************************
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;* \file cy8c6xx7_cm4_dual.scat
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;* \version `$CY_MAJOR_VERSION`.`$CY_MINOR_VERSION`
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;* \file cy8c6xx7_cm0plus.scat
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;* \version 2.30
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;*
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;* Linker file for the ARMCC.
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;*
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@ -43,19 +43,27 @@
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;******************************************************************************/
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#if !defined(MBED_ROM_START)
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#define MBED_ROM_START 0x10002000
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#define MBED_ROM_START 0x10000000
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#endif
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#if !defined(MBED_ROM_SIZE)
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#define MBED_ROM_SIZE 0x000FE000
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#define MBED_ROM_SIZE 0x80000
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#endif
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#if !defined(MBED_RAM_START)
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#define MBED_RAM_START 0x08002000
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#define MBED_RAM_START 0x08000000
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#endif
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#if !defined(MBED_RAM_SIZE)
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#define MBED_RAM_SIZE 0x00045800
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#define MBED_RAM_SIZE 0x10000
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#endif
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#if !defined(MBED_PUBLIC_RAM_START)
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#define MBED_PUBLIC_RAM_START 0x08047600
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#endif
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#if !defined(MBED_PUBLIC_RAM_SIZE)
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#define MBED_PUBLIC_RAM_SIZE 0x200
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#endif
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#if !defined(MBED_BOOT_STACK_SIZE)
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@ -67,20 +75,23 @@
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; The defines below describe the location and size of blocks of memory in the target.
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; Use these defines to specify the memory regions available for allocation.
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; The following defines control RAM and flash memory allocation for the CM4 core.
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; You can change the memory allocation by editing RAM and Flash defines.
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; Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
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; Using this memory region for other purposes will lead to unexpected behavior.
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; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
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; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
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; The following defines control RAM and flash memory allocation for the CM0+ core.
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; You can change the memory allocation by editing the RAM and Flash defines.
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; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
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; where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.scat'.
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; RAM
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; RAM
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#define RAM_START MBED_RAM_START
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#define RAM_SIZE MBED_RAM_SIZE
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; Public RAM
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#define PUBLIC_RAM_START MBED_PUBLIC_RAM_START
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#define PUBLIC_RAM_SIZE MBED_PUBLIC_RAM_SIZE
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; Flash
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; Flash
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#define FLASH_START MBED_ROM_START
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#define FLASH_SIZE MBED_ROM_SIZE
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; The following defines describe a 32K flash region used for EEPROM emulation.
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; The following defines describe a 32K flash region used for EEPROM emulation.
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; This region can also be used as the general purpose flash.
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; You can assign sections to this memory region for only one of the cores.
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; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
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@ -118,8 +129,13 @@
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#define EFUSE_SIZE 0x100000
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LR_IROM1 FLASH_START FLASH_SIZE
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LR_IROM1 FLASH_START (FLASH_SIZE - 0x8000)
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{
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.cy_app_header +0
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{
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* (.cy_app_header)
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}
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ER_FLASH_VECTORS +0
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{
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* (RESET, +FIRST)
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@ -148,29 +164,17 @@ LR_IROM1 FLASH_START FLASH_SIZE
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{
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* (.noinit)
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}
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; Application heap area (HEAP)
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ARM_LIB_HEAP +0
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{
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* (HEAP)
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}
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; Stack region growing down
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ARM_LIB_STACK RAM_START+RAM_SIZE -Stack_Size
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{
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* (STACK)
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ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -Stack_Size
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{ ; Stack region growing down
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}
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; Used for the digital signature of the secure application and the
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; Bootloader SDK application. The size of the section depends on the required
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; data size.
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.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
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RW_IRAM2 PUBLIC_RAM_START UNINIT
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{
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* (.cy_app_signature)
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* (.cy_pub_ram)
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}
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}
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; Emulated EEPROM Flash area
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LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
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{
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@ -0,0 +1,321 @@
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;/**************************************************************************//**
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; * @file startup_psoc6_01_cm0plus.s
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; * @brief CMSIS Core Device Startup File for
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; * ARMCM0plus Device Series
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; * @version V5.00
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; * @date 02. March 2016
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; ******************************************************************************/
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;/*
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; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Licensed under the Apache License, Version 2.0 (the License); you may
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; * not use this file except in compliance with the License.
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; * You may obtain a copy of the License at
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; *
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; * www.apache.org/licenses/LICENSE-2.0
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; *
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; * Unless required by applicable law or agreed to in writing, software
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; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
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; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; * See the License for the specific language governing permissions and
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; * limitations under the License.
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; */
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;/*
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;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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;*/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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IF :DEF:__STACK_SIZE
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Stack_Size EQU __STACK_SIZE
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ELSE
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Stack_Size EQU 0x00001000
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ENDIF
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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IF :DEF:__HEAP_SIZE
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Heap_Size EQU __HEAP_SIZE
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ELSE
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Heap_Size EQU 0x00000400
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ENDIF
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD 0x0000000D ; NMI Handler located at ROM code
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External interrupts Description
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DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0
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DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1
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DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2
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DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3
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DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4
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DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5
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DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6
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DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7
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DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8
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DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9
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DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10
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DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11
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DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12
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DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13
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DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14
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DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15
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DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16
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DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17
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DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18
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DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19
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DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20
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DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21
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DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22
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DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23
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DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24
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DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25
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DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26
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DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27
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DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28
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DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29
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DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30
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DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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EXPORT __ramVectors
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AREA RESET_RAM, READWRITE, NOINIT
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__ramVectors SPACE __Vectors_Size
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AREA |.text|, CODE, READONLY
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; Weak function for startup customization
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;
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; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
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; because this function is executed as the first instruction in the ResetHandler.
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; The PDL is also not initialized to use the proper register offsets.
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; The user of this function is responsible for initializing the PDL and resources before using them.
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;
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Cy_OnResetUser PROC
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EXPORT Cy_OnResetUser [WEAK]
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BX LR
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ENDP
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT __main
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; Define strong function for startup customization
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BL Cy_OnResetUser
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||||
|
||||
; Disable global interrupts
|
||||
;CPSID I
|
||||
|
||||
; Copy vectors from ROM to RAM
|
||||
LDR r1, =__Vectors
|
||||
LDR r0, =__ramVectors
|
||||
LDR r2, =__Vectors_Size
|
||||
Vectors_Copy
|
||||
LDR r3, [r1]
|
||||
STR r3, [r0]
|
||||
ADDS r0, r0, #4
|
||||
ADDS r1, r1, #4
|
||||
SUBS r2, r2, #1
|
||||
CMP r2, #0
|
||||
BNE Vectors_Copy
|
||||
|
||||
; Update Vector Table Offset Register. */
|
||||
LDR r0, =__ramVectors
|
||||
LDR r1, =0xE000ED08
|
||||
STR r0, [r1]
|
||||
dsb 0xF
|
||||
|
||||
LDR R0, =__main
|
||||
BLX R0
|
||||
|
||||
; Should never get here
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Cy_SysLib_FaultHandler PROC
|
||||
EXPORT Cy_SysLib_FaultHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
HardFault_Handler PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
movs r0, #4
|
||||
mov r1, LR
|
||||
tst r0, r1
|
||||
beq L_MSP
|
||||
mrs r0, PSP
|
||||
bl L_API_call
|
||||
L_MSP
|
||||
mrs r0, MSP
|
||||
L_API_call
|
||||
bl Cy_SysLib_FaultHandler
|
||||
ENDP
|
||||
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT Default_Handler [WEAK]
|
||||
EXPORT NvicMux0_IRQHandler [WEAK]
|
||||
EXPORT NvicMux1_IRQHandler [WEAK]
|
||||
EXPORT NvicMux2_IRQHandler [WEAK]
|
||||
EXPORT NvicMux3_IRQHandler [WEAK]
|
||||
EXPORT NvicMux4_IRQHandler [WEAK]
|
||||
EXPORT NvicMux5_IRQHandler [WEAK]
|
||||
EXPORT NvicMux6_IRQHandler [WEAK]
|
||||
EXPORT NvicMux7_IRQHandler [WEAK]
|
||||
EXPORT NvicMux8_IRQHandler [WEAK]
|
||||
EXPORT NvicMux9_IRQHandler [WEAK]
|
||||
EXPORT NvicMux10_IRQHandler [WEAK]
|
||||
EXPORT NvicMux11_IRQHandler [WEAK]
|
||||
EXPORT NvicMux12_IRQHandler [WEAK]
|
||||
EXPORT NvicMux13_IRQHandler [WEAK]
|
||||
EXPORT NvicMux14_IRQHandler [WEAK]
|
||||
EXPORT NvicMux15_IRQHandler [WEAK]
|
||||
EXPORT NvicMux16_IRQHandler [WEAK]
|
||||
EXPORT NvicMux17_IRQHandler [WEAK]
|
||||
EXPORT NvicMux18_IRQHandler [WEAK]
|
||||
EXPORT NvicMux19_IRQHandler [WEAK]
|
||||
EXPORT NvicMux20_IRQHandler [WEAK]
|
||||
EXPORT NvicMux21_IRQHandler [WEAK]
|
||||
EXPORT NvicMux22_IRQHandler [WEAK]
|
||||
EXPORT NvicMux23_IRQHandler [WEAK]
|
||||
EXPORT NvicMux24_IRQHandler [WEAK]
|
||||
EXPORT NvicMux25_IRQHandler [WEAK]
|
||||
EXPORT NvicMux26_IRQHandler [WEAK]
|
||||
EXPORT NvicMux27_IRQHandler [WEAK]
|
||||
EXPORT NvicMux28_IRQHandler [WEAK]
|
||||
EXPORT NvicMux29_IRQHandler [WEAK]
|
||||
EXPORT NvicMux30_IRQHandler [WEAK]
|
||||
EXPORT NvicMux31_IRQHandler [WEAK]
|
||||
|
||||
NvicMux0_IRQHandler
|
||||
NvicMux1_IRQHandler
|
||||
NvicMux2_IRQHandler
|
||||
NvicMux3_IRQHandler
|
||||
NvicMux4_IRQHandler
|
||||
NvicMux5_IRQHandler
|
||||
NvicMux6_IRQHandler
|
||||
NvicMux7_IRQHandler
|
||||
NvicMux8_IRQHandler
|
||||
NvicMux9_IRQHandler
|
||||
NvicMux10_IRQHandler
|
||||
NvicMux11_IRQHandler
|
||||
NvicMux12_IRQHandler
|
||||
NvicMux13_IRQHandler
|
||||
NvicMux14_IRQHandler
|
||||
NvicMux15_IRQHandler
|
||||
NvicMux16_IRQHandler
|
||||
NvicMux17_IRQHandler
|
||||
NvicMux18_IRQHandler
|
||||
NvicMux19_IRQHandler
|
||||
NvicMux20_IRQHandler
|
||||
NvicMux21_IRQHandler
|
||||
NvicMux22_IRQHandler
|
||||
NvicMux23_IRQHandler
|
||||
NvicMux24_IRQHandler
|
||||
NvicMux25_IRQHandler
|
||||
NvicMux26_IRQHandler
|
||||
NvicMux27_IRQHandler
|
||||
NvicMux28_IRQHandler
|
||||
NvicMux29_IRQHandler
|
||||
NvicMux30_IRQHandler
|
||||
NvicMux31_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
|
||||
; [] END OF FILE
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy8c6xx7_cm4_dual.ld
|
||||
* \file cy8c6xx7_cm0plus.ld
|
||||
* \version 2.30
|
||||
*
|
||||
* Linker file for the GNU C compiler.
|
||||
|
|
@ -41,19 +41,27 @@ GROUP(-lgcc -lc -lnosys)
|
|||
ENTRY(Reset_Handler)
|
||||
|
||||
#if !defined(MBED_ROM_START)
|
||||
#define MBED_ROM_START 0x10002000
|
||||
#define MBED_ROM_START 0x10000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_ROM_SIZE)
|
||||
#define MBED_ROM_SIZE 0x000FE000
|
||||
#define MBED_ROM_SIZE 0x80000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_RAM_START)
|
||||
#define MBED_RAM_START 0x08002000
|
||||
#define MBED_RAM_START 0x08000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_RAM_SIZE)
|
||||
#define MBED_RAM_SIZE 0x00045800
|
||||
#define MBED_RAM_SIZE 0x10000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_PUBLIC_RAM_START)
|
||||
#define MBED_PUBLIC_RAM_START 0x08047600
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_PUBLIC_RAM_SIZE)
|
||||
#define MBED_PUBLIC_RAM_SIZE 0x200
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_BOOT_STACK_SIZE)
|
||||
|
|
@ -75,15 +83,14 @@ EXTERN(Reset_Handler)
|
|||
*/
|
||||
MEMORY
|
||||
{
|
||||
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
|
||||
/* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
|
||||
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
|
||||
* Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
|
||||
* Using this memory region for other purposes will lead to unexpected behavior.
|
||||
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
|
||||
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
|
||||
* Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
|
||||
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
|
||||
*/
|
||||
ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
|
||||
flash (rx) : ORIGIN = MBED_ROM_START, LENGTH = MBED_ROM_SIZE
|
||||
public_ram (rw) : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE
|
||||
flash (rx) : ORIGIN = MBED_ROM_START, LENGTH = (MBED_ROM_SIZE - 0x8000)
|
||||
|
||||
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
|
||||
* You can assign sections to this memory region for only one of the cores.
|
||||
|
|
@ -141,6 +148,11 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
|
|||
|
||||
SECTIONS
|
||||
{
|
||||
.cy_app_header :
|
||||
{
|
||||
KEEP(*(.cy_app_header))
|
||||
} > flash
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
|
@ -194,7 +206,7 @@ SECTIONS
|
|||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
|
@ -216,7 +228,7 @@ SECTIONS
|
|||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
|
|
@ -257,7 +269,6 @@ SECTIONS
|
|||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
|
|
@ -318,7 +329,22 @@ SECTIONS
|
|||
__HeapLimit = .;
|
||||
} > ram
|
||||
|
||||
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (NOLOAD):
|
||||
{
|
||||
KEEP(*(.stack*))
|
||||
} > ram
|
||||
|
||||
/* Public RAM */
|
||||
.cy_pub_ram (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.cy_pub_ram))
|
||||
} > public_ram
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(ram) + LENGTH(ram);
|
||||
|
|
@ -329,14 +355,6 @@ SECTIONS
|
|||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
|
||||
|
||||
/* Used for the digital signature of the secure application and the Bootloader SDK application.
|
||||
* The size of the section depends on the required data size. */
|
||||
.cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
|
||||
{
|
||||
KEEP(*(.cy_app_signature))
|
||||
} > flash
|
||||
|
||||
|
||||
/* Emulated EEPROM Flash area */
|
||||
.cy_em_eeprom :
|
||||
{
|
||||
|
|
@ -0,0 +1,416 @@
|
|||
/**************************************************************************//**
|
||||
* @file startup_psoc6_01_cm0plus.S
|
||||
* @brief CMSIS Core Device Startup File for
|
||||
* ARMCM0plus Device Series
|
||||
* @version V5.00
|
||||
* @date 02. March 2016
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/* Address of the NMI handler */
|
||||
#define CY_NMI_HANLDER_ADDR 0x0000000D
|
||||
|
||||
/* The CPU VTOR register */
|
||||
#define CY_CPU_VTOR_ADDR 0xE000ED08
|
||||
|
||||
/* Copy flash vectors and data section to RAM */
|
||||
#define __STARTUP_COPY_MULTIPLE
|
||||
|
||||
/* Clear single BSS section */
|
||||
#define __STARTUP_CLEAR_BSS
|
||||
|
||||
.syntax unified
|
||||
.arch armv6-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x00001000
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0x00000400
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .vectors
|
||||
.align 2
|
||||
.globl __Vectors
|
||||
__Vectors:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long CY_NMI_HANLDER_ADDR /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts Description */
|
||||
.long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */
|
||||
.long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */
|
||||
.long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */
|
||||
.long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */
|
||||
.long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */
|
||||
.long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */
|
||||
.long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */
|
||||
.long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */
|
||||
.long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */
|
||||
.long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */
|
||||
.long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */
|
||||
.long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */
|
||||
.long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */
|
||||
.long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */
|
||||
.long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */
|
||||
.long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */
|
||||
.long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */
|
||||
.long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */
|
||||
.long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */
|
||||
.long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */
|
||||
.long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */
|
||||
.long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */
|
||||
.long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */
|
||||
.long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */
|
||||
.long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */
|
||||
.long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */
|
||||
.long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */
|
||||
.long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */
|
||||
.long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */
|
||||
.long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */
|
||||
.long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */
|
||||
.long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */
|
||||
|
||||
.size __Vectors, . - __Vectors
|
||||
.equ __VectorsSize, . - __Vectors
|
||||
|
||||
.section .ram_vectors
|
||||
.align 2
|
||||
.globl __ramVectors
|
||||
__ramVectors:
|
||||
.space __VectorsSize
|
||||
.size __ramVectors, . - __ramVectors
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
|
||||
/*
|
||||
* Device startup customization
|
||||
*
|
||||
* Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
|
||||
* because this function is executed as the first instruction in the ResetHandler.
|
||||
* The PDL is also not initialized to use the proper register offsets.
|
||||
* The user of this function is responsible for initializing the PDL and resources before using them.
|
||||
*/
|
||||
.weak Cy_OnResetUser
|
||||
.func Cy_OnResetUser, Cy_OnResetUser
|
||||
.type Cy_OnResetUser, %function
|
||||
|
||||
Cy_OnResetUser:
|
||||
bx lr
|
||||
.size Cy_OnResetUser, . - Cy_OnResetUser
|
||||
.endfunc
|
||||
|
||||
/* Reset handler */
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
|
||||
Reset_Handler:
|
||||
bl Cy_OnResetUser
|
||||
/*
|
||||
#ifndef TARGET_MBED_SPM
|
||||
cpsid i
|
||||
#endif
|
||||
*/
|
||||
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
blt .L_loop0_0_done
|
||||
ldr r0, [r1, r3]
|
||||
str r0, [r2, r3]
|
||||
b .L_loop0_0
|
||||
|
||||
.L_loop0_0_done:
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
subs r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
blt .L_loop2_0_done
|
||||
str r0, [r1, r2]
|
||||
b .L_loop2_0
|
||||
.L_loop2_0_done:
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Update Vector Table Offset Register. */
|
||||
ldr r0, =__ramVectors
|
||||
ldr r1, =CY_CPU_VTOR_ADDR
|
||||
str r0, [r1]
|
||||
dsb 0xF
|
||||
|
||||
/*
|
||||
#ifndef TARGET_MBED_SPM
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
bl main
|
||||
#elif
|
||||
*/
|
||||
bl _start
|
||||
/*
|
||||
#endif
|
||||
*/
|
||||
|
||||
/* Should never get here */
|
||||
b .
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
.weak Cy_SysLib_FaultHandler
|
||||
.type Cy_SysLib_FaultHandler, %function
|
||||
|
||||
Cy_SysLib_FaultHandler:
|
||||
b .
|
||||
.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
|
||||
.type Fault_Handler, %function
|
||||
|
||||
Fault_Handler:
|
||||
/* Storing LR content for Creator call stack trace */
|
||||
push {LR}
|
||||
movs r0, #4
|
||||
mov r1, LR
|
||||
tst r0, r1
|
||||
beq .L_MSP
|
||||
mrs r0, PSP
|
||||
b .L_API_call
|
||||
.L_MSP:
|
||||
mrs r0, MSP
|
||||
.L_API_call:
|
||||
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
|
||||
adds r0, r0, #4
|
||||
bl Cy_SysLib_FaultHandler
|
||||
b .
|
||||
.size Fault_Handler, . - Fault_Handler
|
||||
|
||||
.macro def_fault_Handler fault_handler_name
|
||||
.weak \fault_handler_name
|
||||
.set \fault_handler_name, Fault_Handler
|
||||
.endm
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
|
||||
def_fault_Handler HardFault_Handler
|
||||
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
|
||||
def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */
|
||||
def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */
|
||||
def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */
|
||||
def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */
|
||||
def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */
|
||||
def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */
|
||||
def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */
|
||||
def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */
|
||||
def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */
|
||||
def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */
|
||||
def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */
|
||||
def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */
|
||||
def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */
|
||||
def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */
|
||||
def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */
|
||||
def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */
|
||||
def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */
|
||||
def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */
|
||||
def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */
|
||||
def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */
|
||||
def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */
|
||||
def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */
|
||||
def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */
|
||||
def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */
|
||||
def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */
|
||||
def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */
|
||||
def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */
|
||||
def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */
|
||||
def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */
|
||||
def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */
|
||||
def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */
|
||||
def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */
|
||||
|
||||
.end
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy8c6xx7_cm4_dual.icf
|
||||
* \file cy8c6xx7_cm0plus.icf
|
||||
* \version 2.30
|
||||
*
|
||||
* Linker file for the IAR compiler.
|
||||
|
|
@ -42,42 +42,47 @@
|
|||
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
|
||||
if (!isdefinedsymbol(MBED_ROM_START)) {
|
||||
define symbol MBED_ROM_START = 0x10002000;
|
||||
define symbol MBED_ROM_START = 0x10000000;
|
||||
}
|
||||
|
||||
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
|
||||
define symbol MBED_ROM_SIZE = 0x000FE000;
|
||||
define symbol MBED_ROM_SIZE = 0x80000;
|
||||
}
|
||||
|
||||
if (!isdefinedsymbol(MBED_RAM_START)) {
|
||||
define symbol MBED_RAM_START = 0x08002000;
|
||||
define symbol MBED_RAM_START = 0x08000000;
|
||||
}
|
||||
|
||||
if (!isdefinedsymbol(MBED_RAM_SIZE)) {
|
||||
define symbol MBED_RAM_SIZE = 0x00045800;
|
||||
define symbol MBED_RAM_SIZE = 0x10000;
|
||||
}
|
||||
|
||||
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) {
|
||||
define symbol MBED_PUBLIC_RAM_START = 0x08047600;
|
||||
}
|
||||
|
||||
if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) {
|
||||
define symbol MBED_PUBLIC_RAM_SIZE = 0x200;
|
||||
}
|
||||
|
||||
/* The symbols below define the location and size of blocks of memory in the target.
|
||||
* Use these symbols to specify the memory regions available for allocation.
|
||||
*/
|
||||
|
||||
/* The following symbols control RAM and flash memory allocation for the CM4 core.
|
||||
/* The following symbols control RAM and flash memory allocation for the CM0+ core.
|
||||
* You can change the memory allocation by editing RAM and Flash symbols.
|
||||
* Note that 2 KB of RAM (at the end of the RAM section) are reserved for system use.
|
||||
* Using this memory region for other purposes will lead to unexpected behavior.
|
||||
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
|
||||
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
|
||||
* Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
|
||||
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
|
||||
*/
|
||||
/* RAM */
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
|
||||
/* Public RAM */
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE);
|
||||
/* Flash */
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = MBED_ROM_START;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_ROM_START + MBED_ROM_SIZE);
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_ROM_START + MBED_ROM_SIZE - 0x8000);
|
||||
|
||||
/* The following symbols define a 32K flash region used for EEPROM emulation.
|
||||
* This region can also be used as the general purpose flash.
|
||||
|
|
@ -123,8 +128,8 @@ define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
|||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
|
||||
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
|
||||
/*define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;*/
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
|
|
@ -132,19 +137,26 @@ define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
|||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
/*-Sizes-*/
|
||||
|
||||
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
|
||||
define symbol MBED_BOOT_STACK_SIZE = 0x400;
|
||||
}
|
||||
|
||||
if (!isdefinedsymbol(__STACK_SIZE)) {
|
||||
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
|
||||
} else {
|
||||
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
|
||||
}
|
||||
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
if (!isdefinedsymbol(__HEAP_SIZE)) {
|
||||
define symbol __ICFEDIT_size_heap__ = 0x20000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x4000;
|
||||
} else {
|
||||
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
|
||||
}
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
|
||||
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
|
|
@ -156,27 +168,24 @@ define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFED
|
|||
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
|
||||
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
|
||||
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
|
||||
define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block RAM_DATA {readwrite section .data};
|
||||
define block RAM_OTHER {readwrite section * };
|
||||
define block RAM_NOINIT {readwrite section .noinit};
|
||||
define block RAM_BSS {readwrite section .bss};
|
||||
define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
|
||||
define block RO {first section .intvec, readonly};
|
||||
|
||||
/*-Initializations-*/
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit, section .intvec_ram };
|
||||
|
||||
|
||||
/*-Placement-*/
|
||||
|
||||
/* Flash */
|
||||
place at start of IROM1_region { block RO };
|
||||
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
|
||||
".cy_app_header" : place at start of IROM1_region { section .cy_app_header };
|
||||
place in IROM1_region { block RO };
|
||||
|
||||
/* Emulated EEPROM Flash area */
|
||||
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
|
||||
|
|
@ -204,15 +213,18 @@ place at start of IROM1_region { block RO };
|
|||
|
||||
/* RAM */
|
||||
place at start of IRAM1_region { readwrite section .intvec_ram};
|
||||
place in IRAM1_region { block RAM};
|
||||
place in IRAM1_region { block HEAP};
|
||||
place at end of IRAM1_region { block CSTACK };
|
||||
place in IRAM1_region { readwrite };
|
||||
place in IRAM1_region { readwrite section .cy_ramfunc };
|
||||
place at end of IRAM1_region { block HSTACK };
|
||||
|
||||
/* Public RAM */
|
||||
place at start of IRAM2_region { section .cy_pub_ram };
|
||||
|
||||
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
|
||||
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
|
||||
|
||||
|
||||
keep { section .cy_app_signature,
|
||||
keep { section .cy_app_header,
|
||||
section .cy_em_eeprom,
|
||||
section .cy_sflash_user_data,
|
||||
section .cy_sflash_nar,
|
||||
|
|
@ -0,0 +1,423 @@
|
|||
;/**************************************************************************//**
|
||||
; * @file startup_psoc6_01_cm0plus.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM0plus Device Series
|
||||
; * @version V5.00
|
||||
; * @date 08. March 2016
|
||||
; ******************************************************************************/
|
||||
;/*
|
||||
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; * not use this file except in compliance with the License.
|
||||
; * You may obtain a copy of the License at
|
||||
; *
|
||||
; * www.apache.org/licenses/LICENSE-2.0
|
||||
; *
|
||||
; * Unless required by applicable law or agreed to in writing, software
|
||||
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; * See the License for the specific language governing permissions and
|
||||
; * limitations under the License.
|
||||
; */
|
||||
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
SECTION .intvec_ram:DATA:NOROOT(2)
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
EXTERN __iar_data_init3
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __vector_table_0x1c
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
PUBLIC __ramVectors
|
||||
|
||||
DATA
|
||||
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler
|
||||
|
||||
DCD 0x0000000D ; NMI_Handler is defined in ROM code
|
||||
DCD HardFault_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
__vector_table_0x1c
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD SVC_Handler
|
||||
DCD 0
|
||||
DCD 0
|
||||
DCD PendSV_Handler
|
||||
DCD SysTick_Handler
|
||||
|
||||
; External interrupts Power Mode Description
|
||||
DCD NvicMux0_IRQHandler ; CM0+ NVIC Mux input 0
|
||||
DCD NvicMux1_IRQHandler ; CM0+ NVIC Mux input 1
|
||||
DCD NvicMux2_IRQHandler ; CM0+ NVIC Mux input 2
|
||||
DCD NvicMux3_IRQHandler ; CM0+ NVIC Mux input 3
|
||||
DCD NvicMux4_IRQHandler ; CM0+ NVIC Mux input 4
|
||||
DCD NvicMux5_IRQHandler ; CM0+ NVIC Mux input 5
|
||||
DCD NvicMux6_IRQHandler ; CM0+ NVIC Mux input 6
|
||||
DCD NvicMux7_IRQHandler ; CM0+ NVIC Mux input 7
|
||||
DCD NvicMux8_IRQHandler ; CM0+ NVIC Mux input 8
|
||||
DCD NvicMux9_IRQHandler ; CM0+ NVIC Mux input 9
|
||||
DCD NvicMux10_IRQHandler ; CM0+ NVIC Mux input 10
|
||||
DCD NvicMux11_IRQHandler ; CM0+ NVIC Mux input 11
|
||||
DCD NvicMux12_IRQHandler ; CM0+ NVIC Mux input 12
|
||||
DCD NvicMux13_IRQHandler ; CM0+ NVIC Mux input 13
|
||||
DCD NvicMux14_IRQHandler ; CM0+ NVIC Mux input 14
|
||||
DCD NvicMux15_IRQHandler ; CM0+ NVIC Mux input 15
|
||||
DCD NvicMux16_IRQHandler ; CM0+ NVIC Mux input 16
|
||||
DCD NvicMux17_IRQHandler ; CM0+ NVIC Mux input 17
|
||||
DCD NvicMux18_IRQHandler ; CM0+ NVIC Mux input 18
|
||||
DCD NvicMux19_IRQHandler ; CM0+ NVIC Mux input 19
|
||||
DCD NvicMux20_IRQHandler ; CM0+ NVIC Mux input 20
|
||||
DCD NvicMux21_IRQHandler ; CM0+ NVIC Mux input 21
|
||||
DCD NvicMux22_IRQHandler ; CM0+ NVIC Mux input 22
|
||||
DCD NvicMux23_IRQHandler ; CM0+ NVIC Mux input 23
|
||||
DCD NvicMux24_IRQHandler ; CM0+ NVIC Mux input 24
|
||||
DCD NvicMux25_IRQHandler ; CM0+ NVIC Mux input 25
|
||||
DCD NvicMux26_IRQHandler ; CM0+ NVIC Mux input 26
|
||||
DCD NvicMux27_IRQHandler ; CM0+ NVIC Mux input 27
|
||||
DCD NvicMux28_IRQHandler ; CM0+ NVIC Mux input 28
|
||||
DCD NvicMux29_IRQHandler ; CM0+ NVIC Mux input 29
|
||||
DCD NvicMux30_IRQHandler ; CM0+ NVIC Mux input 30
|
||||
DCD NvicMux31_IRQHandler ; CM0+ NVIC Mux input 31
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
|
||||
__ramVectors
|
||||
DS32 __Vectors_Size
|
||||
|
||||
|
||||
THUMB
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default handlers
|
||||
;;
|
||||
PUBWEAK Default_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Default_Handler
|
||||
B Default_Handler
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Weak function for startup customization
|
||||
;;
|
||||
;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
|
||||
;; because this function is executed as the first instruction in the ResetHandler.
|
||||
;; The PDL is also not initialized to use the proper register offsets.
|
||||
;; The user of this function is responsible for initializing the PDL and resources before using them.
|
||||
;;
|
||||
PUBWEAK Cy_OnResetUser
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Cy_OnResetUser
|
||||
BX LR
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Define strong version to return zero for
|
||||
;; __iar_program_start to skip data sections
|
||||
;; initialization.
|
||||
;;
|
||||
PUBLIC __low_level_init
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
__low_level_init
|
||||
MOVS R0, #0
|
||||
BX LR
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
|
||||
; Define strong function for startup customization
|
||||
LDR R0, =Cy_OnResetUser
|
||||
BLX R0
|
||||
|
||||
; Disable global interrupts
|
||||
;CPSID I
|
||||
|
||||
; Copy vectors from ROM to RAM
|
||||
LDR r1, =__vector_table
|
||||
LDR r0, =__ramVectors
|
||||
LDR r2, =__Vectors_Size
|
||||
intvec_copy
|
||||
LDR r3, [r1]
|
||||
STR r3, [r0]
|
||||
ADDS r0, r0, #4
|
||||
ADDS r1, r1, #4
|
||||
SUBS r2, r2, #1
|
||||
CMP r2, #0
|
||||
BNE intvec_copy
|
||||
|
||||
; Update Vector Table Offset Register
|
||||
LDR r0, =__ramVectors
|
||||
LDR r1, =0xE000ED08
|
||||
STR r0, [r1]
|
||||
dsb
|
||||
|
||||
; Initialize data sections
|
||||
;LDR R0, =__iar_data_init3
|
||||
;BLX R0
|
||||
|
||||
;LDR R0, =SystemInit
|
||||
;BLX R0
|
||||
|
||||
LDR R0, =__iar_program_start
|
||||
BLX R0
|
||||
|
||||
; Should never get here
|
||||
Cy_Main_Exited
|
||||
B Cy_Main_Exited
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
|
||||
PUBWEAK Cy_SysLib_FaultHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
Cy_SysLib_FaultHandler
|
||||
B Cy_SysLib_FaultHandler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
IMPORT Cy_SysLib_FaultHandler
|
||||
movs r0, #4
|
||||
mov r1, LR
|
||||
tst r0, r1
|
||||
beq L_MSP
|
||||
mrs r0, PSP
|
||||
b L_API_call
|
||||
L_MSP
|
||||
mrs r0, MSP
|
||||
L_API_call
|
||||
; Storing LR content for Creator call stack trace
|
||||
push {LR}
|
||||
bl Cy_SysLib_FaultHandler
|
||||
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
|
||||
; External interrupts
|
||||
PUBWEAK NvicMux0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux0_IRQHandler
|
||||
B NvicMux0_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux1_IRQHandler
|
||||
B NvicMux1_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux2_IRQHandler
|
||||
B NvicMux2_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux3_IRQHandler
|
||||
B NvicMux3_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux4_IRQHandler
|
||||
B NvicMux4_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux5_IRQHandler
|
||||
B NvicMux5_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux6_IRQHandler
|
||||
B NvicMux6_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux7_IRQHandler
|
||||
B NvicMux7_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux8_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux8_IRQHandler
|
||||
B NvicMux8_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux9_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux9_IRQHandler
|
||||
B NvicMux9_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux10_IRQHandler
|
||||
B NvicMux10_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux11_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux11_IRQHandler
|
||||
B NvicMux11_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux12_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux12_IRQHandler
|
||||
B NvicMux12_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux13_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux13_IRQHandler
|
||||
B NvicMux13_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux14_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux14_IRQHandler
|
||||
B NvicMux14_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux15_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux15_IRQHandler
|
||||
B NvicMux15_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux16_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux16_IRQHandler
|
||||
B NvicMux16_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux17_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux17_IRQHandler
|
||||
B NvicMux17_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux18_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux18_IRQHandler
|
||||
B NvicMux18_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux19_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux19_IRQHandler
|
||||
B NvicMux19_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux20_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux20_IRQHandler
|
||||
B NvicMux20_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux21_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux21_IRQHandler
|
||||
B NvicMux21_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux22_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux22_IRQHandler
|
||||
B NvicMux22_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux23_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux23_IRQHandler
|
||||
B NvicMux23_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux24_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux24_IRQHandler
|
||||
B NvicMux24_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux25_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux25_IRQHandler
|
||||
B NvicMux25_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux26_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux26_IRQHandler
|
||||
B NvicMux26_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux27_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux27_IRQHandler
|
||||
B NvicMux27_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux28_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux28_IRQHandler
|
||||
B NvicMux28_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux29_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux29_IRQHandler
|
||||
B NvicMux29_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux30_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux30_IRQHandler
|
||||
B NvicMux30_IRQHandler
|
||||
|
||||
PUBWEAK NvicMux31_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NvicMux31_IRQHandler
|
||||
B NvicMux31_IRQHandler
|
||||
|
||||
|
||||
END
|
||||
|
||||
|
||||
; [] END OF FILE
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/***************************************************************************//**
|
||||
* \file system_psoc6_cm4.c
|
||||
* \file system_psoc6_cm0plus.c
|
||||
* \version 2.30
|
||||
*
|
||||
* The device system-source file.
|
||||
|
|
@ -22,16 +22,14 @@
|
|||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "cy_device.h"
|
||||
#include "device.h"
|
||||
#include "system_psoc6.h"
|
||||
#include "cy_device.h"
|
||||
#include "cy_device_headers.h"
|
||||
#include "psoc6_utils.h"
|
||||
#include "cy_syslib.h"
|
||||
#include "cy_wdt.h"
|
||||
#include "cycfg.h"
|
||||
#include "system_psoc6_cm0plus_flash_init.h"
|
||||
#include "psoc6_utils.h"
|
||||
|
||||
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
|
||||
#include "cy_ipc_sema.h"
|
||||
|
|
@ -41,6 +39,7 @@
|
|||
#if defined(CY_DEVICE_PSOC6ABLE2)
|
||||
#include "cy_flash.h"
|
||||
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
|
||||
|
||||
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
|
||||
|
||||
|
||||
|
|
@ -55,7 +54,7 @@
|
|||
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
|
||||
|
||||
/** Default SlowClk system core frequency in Hz */
|
||||
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
|
||||
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
|
||||
|
||||
/** IMO frequency in Hz */
|
||||
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
|
||||
|
|
@ -100,9 +99,6 @@ uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
|
|||
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
|
||||
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
|
||||
|
||||
/* SCB->CPACR */
|
||||
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* SystemInit()
|
||||
|
|
@ -155,60 +151,96 @@ uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
|
|||
#endif /* (SRSS_PILO_PRESENT == 1U) */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
|
||||
*******************************************************************************/
|
||||
#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL)
|
||||
#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
|
||||
#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL)
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: mbed_sdk_init
|
||||
****************************************************************************//**
|
||||
*
|
||||
* Mbed's post-memory-initialization function.
|
||||
* Used here to initialize common parts of the Cypress libraries.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void mbed_sdk_init(void)
|
||||
{
|
||||
/* Initialize shared resource manager */
|
||||
cy_srm_initialize();
|
||||
/* Initialize system and clocks. */
|
||||
/* Placed here as it must be done after proper LIBC initialization. */
|
||||
SystemInit();
|
||||
}
|
||||
|
||||
#if defined(COMPONENT_SPM_MAILBOX)
|
||||
void mailbox_init(void);
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SystemInit
|
||||
****************************************************************************//**
|
||||
* \cond
|
||||
*
|
||||
* Initializes the system:
|
||||
* - Restores FLL registers to the default state for single core devices.
|
||||
* - Restores FLL registers to the default state.
|
||||
* - Unlocks and disables WDT.
|
||||
* - Calls Cy_PDL_Init() function to define the driver library.
|
||||
* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
|
||||
* - Calls \ref SystemCoreClockUpdate().
|
||||
* \endcond
|
||||
*
|
||||
*******************************************************************************/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Workaround to avoid twice SystemInit() call when ARMC5 compiler is used */
|
||||
static uint32_t temp_var = 0;
|
||||
|
||||
if (temp_var == 0)
|
||||
{
|
||||
temp_var = 1;
|
||||
|
||||
Cy_PDL_Init(CY_DEVICE_CFG);
|
||||
|
||||
#ifdef __CM0P_PRESENT
|
||||
#if (__CM0P_PRESENT == 0)
|
||||
/* Restore FLL registers to the default state as they are not restored by the ROM code */
|
||||
uint32_t copy = SRSS->CLK_FLL_CONFIG;
|
||||
copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
|
||||
SRSS->CLK_FLL_CONFIG = copy;
|
||||
/* Restore FLL registers to the default state as they are not restored by the ROM code */
|
||||
uint32_t copy = SRSS->CLK_FLL_CONFIG;
|
||||
copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
|
||||
SRSS->CLK_FLL_CONFIG = copy;
|
||||
|
||||
copy = SRSS->CLK_ROOT_SELECT[0u];
|
||||
copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
|
||||
SRSS->CLK_ROOT_SELECT[0u] = copy;
|
||||
copy = SRSS->CLK_ROOT_SELECT[0u];
|
||||
copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
|
||||
SRSS->CLK_ROOT_SELECT[0u] = copy;
|
||||
|
||||
SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
|
||||
SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
|
||||
SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
|
||||
SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
|
||||
SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
|
||||
SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
|
||||
SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
|
||||
SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
|
||||
|
||||
/* Unlock and disable WDT */
|
||||
Cy_WDT_Unlock();
|
||||
Cy_WDT_Disable();
|
||||
#endif /* (__CM0P_PRESENT == 0) */
|
||||
#endif /* __CM0P_PRESENT */
|
||||
/* Unlock and disable WDT */
|
||||
Cy_WDT_Unlock();
|
||||
Cy_WDT_Disable();
|
||||
|
||||
Cy_SystemInit();
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
|
||||
#if defined(COMPONENT_SPM_MAILBOX)
|
||||
mailbox_init();
|
||||
#endif
|
||||
#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE)
|
||||
if (CY_SYSLIB_DEVICE_REV_0A == Cy_SysLib_GetDeviceRevision())
|
||||
{
|
||||
/* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
|
||||
IPC_STRUCT7->DATA = 0UL;
|
||||
/* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
|
||||
IPC_STRUCT7->RELEASE = 0UL;
|
||||
}
|
||||
#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CY_PSOC6ABLE2_REV_0A_SUPPORT_DISABLE) */
|
||||
|
||||
#ifdef __CM0P_PRESENT
|
||||
#if (__CM0P_PRESENT == 0)
|
||||
/* Allocate and initialize semaphores for the system operations. */
|
||||
static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
|
||||
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
|
||||
#else
|
||||
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
|
||||
#endif /* (__CM0P_PRESENT) */
|
||||
#else
|
||||
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
|
||||
#endif /* __CM0P_PRESENT */
|
||||
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
|
||||
/* Allocate and initialize semaphores for the system operations. */
|
||||
static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
|
||||
|
||||
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
|
||||
|
||||
|
||||
/********************************************************************************
|
||||
|
|
@ -224,6 +256,7 @@ void SystemInit(void)
|
|||
* -# Cy_Flash_Init()
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/* Create an array of endpoint structures */
|
||||
static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
|
||||
|
||||
|
|
@ -231,7 +264,7 @@ void SystemInit(void)
|
|||
|
||||
static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
|
||||
|
||||
static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
|
||||
static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
|
||||
{
|
||||
/* .ep0ConfigData */
|
||||
{
|
||||
|
|
@ -251,48 +284,26 @@ void SystemInit(void)
|
|||
},
|
||||
/* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
|
||||
/* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
|
||||
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
|
||||
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
|
||||
};
|
||||
|
||||
if (cy_device->flashPipeRequired != 0u)
|
||||
{
|
||||
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
|
||||
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
|
||||
}
|
||||
|
||||
#if defined(CY_DEVICE_PSOC6ABLE2)
|
||||
Cy_Flash_Init();
|
||||
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
|
||||
|
||||
#else/* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
|
||||
Cy_SemaIpcFlashInit();
|
||||
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: mbed_sdk_init
|
||||
****************************************************************************//**
|
||||
*
|
||||
* Mbed's post-memory-initialization function.
|
||||
* Used here to initialize common parts of the Cypress libraries.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void mbed_sdk_init(void)
|
||||
{
|
||||
/* Initialize shared resource manager */
|
||||
cy_srm_initialize();
|
||||
|
||||
/* Initialize system and clocks. */
|
||||
/* Placed here as it must be done after proper LIBC initialization. */
|
||||
SystemInit();
|
||||
|
||||
/* Set up the device based on configurator selections */
|
||||
init_cycfg_all();
|
||||
|
||||
/* Enable global interrupts */
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SystemInit
|
||||
****************************************************************************//**
|
||||
|
|
@ -330,7 +341,7 @@ void SystemCoreClockUpdate (void)
|
|||
{
|
||||
uint32_t srcFreqHz;
|
||||
uint32_t pathFreqHz;
|
||||
uint32_t fastClkDiv;
|
||||
uint32_t slowClkDiv;
|
||||
uint32_t periClkDiv;
|
||||
uint32_t rootPath;
|
||||
uint32_t srcClk;
|
||||
|
|
@ -461,14 +472,15 @@ void SystemCoreClockUpdate (void)
|
|||
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
|
||||
cy_Hfclk0FreqHz = pathFreqHz;
|
||||
|
||||
/* Fast Clock Divider */
|
||||
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
|
||||
/* Slow Clock Divider */
|
||||
slowClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV, CPUSS->CM0_CLOCK_CTL);
|
||||
|
||||
/* Peripheral Clock Divider */
|
||||
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
|
||||
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
|
||||
|
||||
pathFreqHz = pathFreqHz / fastClkDiv;
|
||||
pathFreqHz = pathFreqHz / periClkDiv;
|
||||
cy_PeriClkFreqHz = pathFreqHz;
|
||||
pathFreqHz = pathFreqHz / slowClkDiv;
|
||||
SystemCoreClock = pathFreqHz;
|
||||
|
||||
/* Sets clock frequency for Delay API */
|
||||
|
|
@ -479,37 +491,188 @@ void SystemCoreClockUpdate (void)
|
|||
}
|
||||
|
||||
|
||||
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SystemInitFpuEnable
|
||||
* Function Name: Cy_SysGetCM4Status
|
||||
****************************************************************************//**
|
||||
*
|
||||
* Enables the FPU if it is used. The function is called from the startup file.
|
||||
* Returns the Cortex-M4 core power mode.
|
||||
*
|
||||
* \return \ref group_system_config_cm4_status_macro
|
||||
*
|
||||
*******************************************************************************/
|
||||
void Cy_SystemInitFpuEnable(void)
|
||||
uint32_t Cy_SysGetCM4Status(void)
|
||||
{
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U)
|
||||
uint32_t interruptState;
|
||||
interruptState = Cy_SysLib_EnterCriticalSection();
|
||||
SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
|
||||
__DSB();
|
||||
__ISB();
|
||||
Cy_SysLib_ExitCriticalSection(interruptState);
|
||||
#endif /* (__FPU_USED) && (__FPU_USED == 1U) */
|
||||
uint32_t regValue;
|
||||
|
||||
/* Get current power mode */
|
||||
regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
|
||||
|
||||
return (regValue);
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SysEnableCM4
|
||||
****************************************************************************//**
|
||||
*
|
||||
* Sets vector table base address and enables the Cortex-M4 core.
|
||||
*
|
||||
* \note If the CPU is already enabled, it is reset and then enabled.
|
||||
*
|
||||
* \param vectorTableOffset The offset of the vector table base address from
|
||||
* memory address 0x00000000. The offset should be multiple to 1024 bytes.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void Cy_SysEnableCM4(uint32_t vectorTableOffset)
|
||||
{
|
||||
uint32_t regValue;
|
||||
uint32_t interruptState;
|
||||
uint32_t cpuState;
|
||||
|
||||
CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
|
||||
|
||||
interruptState = Cy_SysLib_EnterCriticalSection();
|
||||
|
||||
cpuState = Cy_SysGetCM4Status();
|
||||
if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
|
||||
{
|
||||
Cy_SysResetCM4();
|
||||
}
|
||||
|
||||
CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
|
||||
|
||||
regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
|
||||
regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
|
||||
regValue |= CY_SYS_CM4_STATUS_ENABLED;
|
||||
CPUSS->CM4_PWR_CTL = regValue;
|
||||
|
||||
while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
|
||||
{
|
||||
/* Wait for the power mode to take effect */
|
||||
}
|
||||
|
||||
Cy_SysLib_ExitCriticalSection(interruptState);
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SysDisableCM4
|
||||
****************************************************************************//**
|
||||
*
|
||||
* Disables the Cortex-M4 core and waits for the mode to take the effect.
|
||||
*
|
||||
* \warning Do not call the function while the Cortex-M4 is executing because
|
||||
* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
|
||||
* unexpected behavior in the system including a deadlock. Call the function
|
||||
* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
|
||||
* the \ref group_syspm Power Management (syspm) API to put the CPU into the
|
||||
* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
|
||||
* CPU.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void Cy_SysDisableCM4(void)
|
||||
{
|
||||
uint32_t interruptState;
|
||||
uint32_t regValue;
|
||||
|
||||
interruptState = Cy_SysLib_EnterCriticalSection();
|
||||
|
||||
regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
|
||||
regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
|
||||
regValue |= CY_SYS_CM4_STATUS_DISABLED;
|
||||
CPUSS->CM4_PWR_CTL = regValue;
|
||||
|
||||
while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
|
||||
{
|
||||
/* Wait for the power mode to take effect */
|
||||
}
|
||||
|
||||
Cy_SysLib_ExitCriticalSection(interruptState);
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SysRetainCM4
|
||||
****************************************************************************//**
|
||||
*
|
||||
* Retains the Cortex-M4 core and exists without waiting for the mode to take
|
||||
* effect.
|
||||
*
|
||||
* \note The retained mode can be entered only from the enabled mode.
|
||||
*
|
||||
* \warning Do not call the function while the Cortex-M4 is executing because
|
||||
* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
|
||||
* unexpected behavior in the system including a deadlock. Call the function
|
||||
* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
|
||||
* the \ref group_syspm Power Management (syspm) API to put the CPU into the
|
||||
* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void Cy_SysRetainCM4(void)
|
||||
{
|
||||
uint32_t interruptState;
|
||||
uint32_t regValue;
|
||||
|
||||
interruptState = Cy_SysLib_EnterCriticalSection();
|
||||
|
||||
regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
|
||||
regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
|
||||
regValue |= CY_SYS_CM4_STATUS_RETAINED;
|
||||
CPUSS->CM4_PWR_CTL = regValue;
|
||||
|
||||
Cy_SysLib_ExitCriticalSection(interruptState);
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SysResetCM4
|
||||
****************************************************************************//**
|
||||
*
|
||||
* Resets the Cortex-M4 core and waits for the mode to take the effect.
|
||||
*
|
||||
* \note The reset mode can not be entered from the retained mode.
|
||||
*
|
||||
* \warning Do not call the function while the Cortex-M4 is executing because
|
||||
* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
|
||||
* unexpected behavior in the system including a deadlock. Call the function
|
||||
* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
|
||||
* the \ref group_syspm Power Management (syspm) API to put the CPU into the
|
||||
* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void Cy_SysResetCM4(void)
|
||||
{
|
||||
uint32_t interruptState;
|
||||
uint32_t regValue;
|
||||
|
||||
interruptState = Cy_SysLib_EnterCriticalSection();
|
||||
|
||||
regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
|
||||
regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
|
||||
regValue |= CY_SYS_CM4_STATUS_RESET;
|
||||
CPUSS->CM4_PWR_CTL = regValue;
|
||||
|
||||
while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
|
||||
{
|
||||
/* Wait for the power mode to take effect */
|
||||
}
|
||||
|
||||
Cy_SysLib_ExitCriticalSection(interruptState);
|
||||
}
|
||||
#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
|
||||
|
||||
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SysIpcPipeIsrCm4
|
||||
* Function Name: Cy_SysIpcPipeIsrCm0
|
||||
****************************************************************************//**
|
||||
*
|
||||
* This is the interrupt service routine for the system pipe.
|
||||
*
|
||||
*******************************************************************************/
|
||||
void Cy_SysIpcPipeIsrCm4(void)
|
||||
void Cy_SysIpcPipeIsrCm0(void)
|
||||
{
|
||||
Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
|
||||
Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -550,6 +713,7 @@ __asm void Cy_MemorySymbols(void)
|
|||
EXPORT __cy_memory_4_length
|
||||
EXPORT __cy_memory_4_row_size
|
||||
|
||||
|
||||
/* Flash */
|
||||
__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
|
||||
__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
|
||||
|
|
@ -575,7 +739,6 @@ __cy_memory_4_start EQU __cpp(0x90700000)
|
|||
__cy_memory_4_length EQU __cpp(0x100000)
|
||||
__cy_memory_4_row_size EQU __cpp(1)
|
||||
}
|
||||
|
||||
#endif /* defined (__ARMCC_VERSION) */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,129 @@
|
|||
/***************************************************************************//**
|
||||
* \file system_psoc6_cm0plus_flash_init.c
|
||||
* \version 2.30
|
||||
*
|
||||
* The source for Flash initialization function.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
#include "system_psoc6.h"
|
||||
#include "cy_ipc_sema.h"
|
||||
#include "cy_ipc_pipe.h"
|
||||
#include "cy_flash.h"
|
||||
|
||||
#include "system_psoc6_cm0plus_flash_init.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: Cy_SysIpcPipeIsrCm0Local
|
||||
****************************************************************************//**
|
||||
*
|
||||
* This is the interrupt service routine for the system pipe.
|
||||
* Copy of Cy_SysIpcPipeIsrCm0
|
||||
*
|
||||
*******************************************************************************/
|
||||
static void Cy_SysIpcPipeIsrCm0Local(void)
|
||||
{
|
||||
Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
|
||||
}
|
||||
|
||||
/* Structure containing semaphores control data */
|
||||
__attribute__((section(".cy_pub_ram"))) static cy_stc_ipc_sema_t cy_semaData;
|
||||
|
||||
static cy_en_ipcsema_status_t Cy_IPC_SemaInitLocal(uint32_t ipcChannel,
|
||||
uint32_t count, uint32_t memPtr[])
|
||||
{
|
||||
cy_en_ipcsema_status_t retStatus = CY_IPC_SEMA_BAD_PARAM;
|
||||
|
||||
/* Check for non Null pointers and count value */
|
||||
if ((NULL != memPtr) && (0u != count))
|
||||
{
|
||||
cy_semaData.maxSema = count;
|
||||
cy_semaData.arrayPtr = memPtr;
|
||||
|
||||
retStatus = Cy_IPC_Sema_InitExt(ipcChannel, &cy_semaData);
|
||||
}
|
||||
else
|
||||
{
|
||||
retStatus = CY_IPC_SEMA_BAD_PARAM;
|
||||
}
|
||||
|
||||
return(retStatus);
|
||||
}
|
||||
|
||||
__attribute__((section(".cy_pub_ram")))
|
||||
static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
|
||||
__attribute__((section(".cy_pub_ram")))
|
||||
static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
|
||||
__attribute__((section(".cy_pub_ram")))
|
||||
static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
|
||||
__attribute__((section(".cy_pub_ram")))
|
||||
CY_ALIGN(4) static cy_stc_flash_notify_t ipcWaitMessageStc;
|
||||
|
||||
void Cy_PubRamVariablesInit(void)
|
||||
{
|
||||
memset(&cy_semaData, 0, sizeof(cy_semaData));
|
||||
memset(&ipcSemaArray, 0, sizeof(ipcSemaArray));
|
||||
memset(&systemIpcPipeEpArray, 0, sizeof(systemIpcPipeEpArray));
|
||||
memset(&systemIpcPipeSysCbArray, 0, sizeof(systemIpcPipeSysCbArray));
|
||||
memset(&ipcWaitMessageStc, 0, sizeof(ipcWaitMessageStc));
|
||||
}
|
||||
|
||||
void Cy_SemaIpcFlashInit(void)
|
||||
{
|
||||
/* Initialize cy_pub_ram section variables */
|
||||
Cy_PubRamVariablesInit();
|
||||
|
||||
/* Allocate and initialize semaphores for the system operations. */
|
||||
(void) Cy_IPC_SemaInitLocal(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
|
||||
|
||||
/* Create an array of endpoint structures */
|
||||
Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
|
||||
|
||||
static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
|
||||
{
|
||||
/* .ep0ConfigData */
|
||||
{
|
||||
/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
|
||||
/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
|
||||
/* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
|
||||
/* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
|
||||
/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
|
||||
},
|
||||
/* .ep1ConfigData */
|
||||
{
|
||||
/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
|
||||
/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
|
||||
/* .ipcNotifierMuxNumber */ 0u,
|
||||
/* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
|
||||
/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
|
||||
},
|
||||
/* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
|
||||
/* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
|
||||
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0Local
|
||||
};
|
||||
|
||||
if (cy_device->flashPipeRequired != 0u)
|
||||
{
|
||||
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
|
||||
}
|
||||
|
||||
Cy_Flash_InitExt(&ipcWaitMessageStc);
|
||||
}
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/***************************************************************************//**
|
||||
* \file system_psoc6_cm0plus_flash_init.c
|
||||
* \version 2.30
|
||||
*
|
||||
* The header for Flash initialization function.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _SYSTEM_PSOC6_CM0PLUS_FLASH_INIT_H_
|
||||
#define _SYSTEM_PSOC6_CM0PLUS_FLASH_INIT_H_
|
||||
|
||||
void Cy_SemaIpcFlashInit(void);
|
||||
|
||||
#endif /* _SYSTEM_PSOC6_CM0PLUS_FLASH_INIT_H_ */
|
||||
|
|
@ -154,6 +154,9 @@ uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
|
|||
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
|
||||
#endif /* (SRSS_PILO_PRESENT == 1U) */
|
||||
|
||||
#if defined(COMPONENT_SPM_MAILBOX)
|
||||
void mailbox_init(void);
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Function Name: SystemInit
|
||||
|
|
@ -264,6 +267,10 @@ void SystemInit(void)
|
|||
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
|
||||
|
||||
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
|
||||
|
||||
#if defined(COMPONENT_SPM_MAILBOX)
|
||||
mailbox_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
README for PSoC 6 Cortex M0+ PSA target
|
||||
=======================================
|
||||
|
||||
Please note that this is still in active development, and that a bootloader
|
||||
component is still planned to be added. Because of that when using it refrain
|
||||
from using 256KB at the Flash end to allow for room for the additional
|
||||
components to be added in the future.
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,166 @@
|
|||
/* mbed Microcontroller Library
|
||||
*
|
||||
* \copyright
|
||||
|
||||
* (c) 2018, Cypress Semiconductor Corporation
|
||||
* or a subsidiary of Cypress Semiconductor Corporation. All rights
|
||||
* reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _CYPROTECTION_H_
|
||||
#define _CYPROTECTION_H_
|
||||
|
||||
#include "cy_prot.h"
|
||||
|
||||
#define MPU_SMPU_SUBREGIONS_NUMB (8u)
|
||||
/* MPU is not used yet */
|
||||
#define CPUSS_PROT_MPU_STRUCT_NR (0u)
|
||||
|
||||
#define CPUSS_PROT_PPU_GR_STRUCT_NR (16u)
|
||||
#define CPUSS_PROT_PPU_PROG_STRUCT_NR (16u)
|
||||
#define CPUSS_PROT_PPU_FX_SL_STRUCT_NR (16u)
|
||||
#define CPUSS_PROT_PPU_FX_RG_STRUCT_NR (29u)
|
||||
|
||||
#define CPUSS_PROT_PPU_FX_RG_START_ADDR (0x40201000UL)
|
||||
|
||||
#define PRIVILEGED_MODE (1u)
|
||||
#define UNPRIVILEGED_MODE (0u)
|
||||
#define NONSECURE_MODE (1u)
|
||||
#define SECURE_MODE (0u)
|
||||
|
||||
/* PPU Group existing bitmask - 11001011111 */
|
||||
#define PERI_PPU_GR_MMIO_EXIST_BITMASK 0x65F
|
||||
/* PPU MMIO1 Group Fixed Region existing bitmask - 10 */
|
||||
#define PERI_PPU_GR_MMIO1_EXIST_BITMASK 0x2
|
||||
/* PPU MMIO2 Group Fixed Region existing bitmask - 11001111111111 */
|
||||
#define PERI_PPU_GR_MMIO2_EXIST_BITMASK 0x33FF
|
||||
/* PPU MMIO3 Group Fixed Region existing bitmask - 1111101111111 */
|
||||
#define PERI_PPU_GR_MMIO3_EXIST_BITMASK 0x1F7F
|
||||
/* PPU MMIO4 Group Fixed Region existing bitmask - 101 */
|
||||
#define PERI_PPU_GR_MMIO4_EXIST_BITMASK 0x5
|
||||
/* PPU MMIO6 Group Fixed Region existing bitmask - 1111111111 */
|
||||
#define PERI_PPU_GR_MMIO6_EXIST_BITMASK 0x3FF
|
||||
/* PPU MMIO9 Group Fixed Region existing bitmask - 11 */
|
||||
#define PERI_PPU_GR_MMIO9_EXIST_BITMASK 0x3
|
||||
/* PPU MMIO10 Group Fixed Region existing bitmask - 111 */
|
||||
#define PERI_PPU_GR_MMIO10_EXIST_BITMASK 0x7
|
||||
|
||||
|
||||
/* TODO: There is no SWPU configuration part */
|
||||
typedef struct {
|
||||
uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */
|
||||
cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */
|
||||
uint8_t subregions; /**< Mask of the 8 subregions to disable (Only applicable to slave) */
|
||||
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
|
||||
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
|
||||
bool secure; /**< Non Secure = 0, Secure = 1 */
|
||||
bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
|
||||
uint16_t pcMask; /**< Mask of allowed protection context(s) */
|
||||
PROT_SMPU_SMPU_STRUCT_Type* prot_region; /* protection region */
|
||||
cy_en_prot_perm_t userMstPermission; /**< User permissions for the region */
|
||||
cy_en_prot_perm_t privMstPermission; /**< Privileged permissions for the region */
|
||||
uint16_t pcMstMask; /**< Master Mask of allowed protection context(s) */
|
||||
} cy_smpu_region_config_t;
|
||||
|
||||
/*
|
||||
* See Cy_Prot_ConfigBusMaster function description for parameters meaning
|
||||
*
|
||||
* act_pcMask specifies active PC for Cy_Prot_SetActivePC function
|
||||
*/
|
||||
typedef struct {
|
||||
en_prot_master_t busMaster;
|
||||
bool privileged;
|
||||
bool secure;
|
||||
uint32_t pcMask;
|
||||
uint32_t act_pc;
|
||||
} cy_bus_master_config_t;
|
||||
|
||||
/** Configuration structure for Fixed Group (GR) PPU (PPU_GR) struct initialization */
|
||||
typedef struct
|
||||
{
|
||||
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
|
||||
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
|
||||
bool secure; /**< Non Secure = 0, Secure = 1 */
|
||||
bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
|
||||
uint16_t pcMask; /**< Mask of allowed protection context(s) */
|
||||
cy_en_prot_perm_t userMstPermission; /**< Master User permissions for the region */
|
||||
cy_en_prot_perm_t privMstPermission; /**< Master Privileged permissions for the region */
|
||||
bool secureMst; /**< Non Secure = 0, Secure = 1 Master */
|
||||
uint16_t pcMstMask; /**< Master Mask of allowed protection context(s) */
|
||||
PERI_PPU_GR_Type *pPpuStr; /**< Ppu structure address */
|
||||
} cy_ppu_fixed_gr_cfg_t;
|
||||
/** Configuration structure for Fixed Region (RG) PPU (PPU_RG) struct initialization */
|
||||
typedef struct
|
||||
{
|
||||
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
|
||||
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
|
||||
bool secure; /**< Non Secure = 0, Secure = 1 */
|
||||
bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
|
||||
uint16_t pcMask; /**< Mask of allowed protection context(s) */
|
||||
cy_en_prot_perm_t userMstPermission; /**< Master User permissions for the region */
|
||||
cy_en_prot_perm_t privMstPermission; /**< Master Privileged permissions for the region */
|
||||
bool secureMst; /**< Non Secure = 0, Secure = 1 Master */
|
||||
uint16_t pcMstMask; /**< Master Mask of allowed protection context(s) */
|
||||
PERI_GR_PPU_RG_Type *pPpuStr; /**< Ppu structure address */
|
||||
} cy_ppu_fixed_rg_cfg_t;
|
||||
/** Configuration structure for Fixed Slave (SL) PPU (PPU_SL) struct initialization */
|
||||
typedef struct
|
||||
{
|
||||
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
|
||||
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
|
||||
bool secure; /**< Non Secure = 0, Secure = 1 */
|
||||
bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
|
||||
uint16_t pcMask; /**< Mask of allowed protection context(s) */
|
||||
cy_en_prot_perm_t userMstPermission; /**< Master User permissions for the region */
|
||||
cy_en_prot_perm_t privMstPermission; /**< Master Privileged permissions for the region */
|
||||
bool secureMst; /**< Non Secure = 0, Secure = 1 Master */
|
||||
uint16_t pcMstMask; /**< Master Mask of allowed protection context(s) */
|
||||
PERI_GR_PPU_SL_Type *pPpuStr; /**< Ppu structure address */
|
||||
} cy_ppu_fixed_sl_cfg_t;
|
||||
|
||||
/** Configuration structure for Programmable (PROG) PPU (PPU_PR) struct initialization */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */
|
||||
cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */
|
||||
uint8_t subregions; /**< Mask of the 8 subregions to disable (Only applicable to slave) */
|
||||
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
|
||||
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
|
||||
bool secure; /**< Non Secure = 0, Secure = 1 */
|
||||
bool pcMatch; /**< Access evaluation = 0, Matching = 1 */
|
||||
uint16_t pcMask; /**< Mask of allowed protection context(s) */
|
||||
cy_en_prot_perm_t userMstPermission; /**< Master User permissions for the region */
|
||||
cy_en_prot_perm_t privMstPermission; /**< Master Privileged permissions for the region */
|
||||
bool secureMst; /**< Non Secure = 0, Secure = 1 Master */
|
||||
uint16_t pcMstMask; /**< Master Mask of allowed protection context(s) */
|
||||
PERI_PPU_PR_Type *pPpuStr; /**< Ppu structure address */
|
||||
} cy_ppu_prog_cfg_t;
|
||||
|
||||
cy_en_prot_status_t smpu_protect(cy_smpu_region_config_t smpu_config_arr[], uint32_t arr_length);
|
||||
cy_en_prot_status_t smpu_config_unprotected(const cy_stc_smpu_cfg_t *smpu_config);
|
||||
cy_en_prot_status_t ppu_fixed_rg_protect(cy_ppu_fixed_rg_cfg_t ppu_config_arr[], uint32_t arr_length);
|
||||
cy_en_prot_status_t ppu_fixed_sl_protect(cy_ppu_fixed_sl_cfg_t ppu_config_arr[], uint32_t arr_length);
|
||||
cy_en_prot_status_t ppu_prog_protect(cy_ppu_prog_cfg_t ppu_config_arr[], uint32_t arr_length);
|
||||
cy_en_prot_status_t ppu_fixed_gr_protect(cy_ppu_fixed_gr_cfg_t ppu_config_arr[], uint32_t arr_length);
|
||||
cy_en_prot_status_t bus_masters_protect(cy_bus_master_config_t bus_masters_config_arr[], uint32_t arr_length);
|
||||
|
||||
uint8_t isPeripheralAccessAllowed(uint32_t perStartAddr, uint32_t perSize,
|
||||
uint8_t privModeFlag, uint8_t nsecureFlag, enum cy_en_prot_pc_t protectionCtx, cy_en_prot_perm_t accessType);
|
||||
uint8_t isMemoryAccessAllowed(uint32_t memStartAddr, uint32_t memSize,
|
||||
uint8_t privModeFlag, uint8_t nsecureFlag, enum cy_en_prot_pc_t protectionCtx, cy_en_prot_perm_t accessType);
|
||||
|
||||
#endif /* _CYPROTECTION_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,99 @@
|
|||
/* Copyright (c) 2017-2018 ARM Limited
|
||||
* Copyright 2018-2019 Cypress Semiconductor Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
/* -------------------------------------- Includes ----------------------------------- */
|
||||
|
||||
#include "cy_sysint.h"
|
||||
#include "spm_internal.h"
|
||||
|
||||
#ifdef PU_ENABLE
|
||||
#include "cyprotection_config.h"
|
||||
#endif // PU_ENABLE
|
||||
|
||||
|
||||
/* -------------------------------------- HAL API ------------------------------------ */
|
||||
|
||||
// These implementations are meant to be used only for SPM running on PSoC6 M0+ core.
|
||||
|
||||
void spm_hal_start_nspe(void)
|
||||
{
|
||||
Cy_SysEnableCM4(PSA_NON_SECURE_ROM_START);
|
||||
}
|
||||
|
||||
void spm_hal_memory_protection_init(void)
|
||||
{
|
||||
#ifdef PU_ENABLE
|
||||
cy_en_prot_status_t status = CY_PROT_SUCCESS;
|
||||
|
||||
/* smpu */
|
||||
status = smpu_protect((cy_smpu_region_config_t *)flash_spm_smpu_config, sizeof(flash_spm_smpu_config) / sizeof(flash_spm_smpu_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
status = smpu_protect((cy_smpu_region_config_t *)sram_spm_smpu_config, sizeof(sram_spm_smpu_config) / sizeof(sram_spm_smpu_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
status = smpu_config_unprotected(&default_smpu_master_config);
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
|
||||
/* fixed region ppu */
|
||||
#ifndef INITIAL_ROT_PROTECTION_AVAILABLE
|
||||
status = ppu_fixed_rg_protect((cy_ppu_fixed_rg_cfg_t *)fixed_rg_pc0_ppu_config, sizeof(fixed_rg_pc0_ppu_config) / sizeof(fixed_rg_pc0_ppu_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
#endif /* INITIAL_ROT_PROTECTION_AVAILABLE */
|
||||
#ifndef INITIAL_PROTECTION_AVAILABLE
|
||||
status = ppu_fixed_rg_protect((cy_ppu_fixed_rg_cfg_t *)fixed_rg_spm_ppu_config, sizeof(fixed_rg_spm_ppu_config) / sizeof(fixed_rg_spm_ppu_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
#endif /* INITIAL_PROTECTION_AVAILABLE */
|
||||
status = ppu_fixed_rg_protect((cy_ppu_fixed_rg_cfg_t *)fixed_rg_any_ppu_config, sizeof(fixed_rg_any_ppu_config) / sizeof(fixed_rg_any_ppu_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
/* fixed slave ppu */
|
||||
#ifndef INITIAL_ROT_PROTECTION_AVAILABLE
|
||||
status = ppu_fixed_sl_protect((cy_ppu_fixed_sl_cfg_t *)fixed_sl_pc0_ppu_config, sizeof(fixed_sl_pc0_ppu_config) / sizeof(fixed_sl_pc0_ppu_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
#endif /* INITIAL_ROT_PROTECTION_AVAILABLE */
|
||||
#ifndef INITIAL_PROTECTION_AVAILABLE
|
||||
status = ppu_fixed_sl_protect((cy_ppu_fixed_sl_cfg_t *)fixed_sl_spm_ppu_config, sizeof(fixed_sl_spm_ppu_config) / sizeof(fixed_sl_spm_ppu_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
#endif /* INITIAL_PROTECTION_AVAILABLE */
|
||||
status = ppu_fixed_sl_protect((cy_ppu_fixed_sl_cfg_t *)fixed_sl_any_ppu_config, sizeof(fixed_sl_any_ppu_config) / sizeof(fixed_sl_any_ppu_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
/* programmable ppu */
|
||||
#ifndef INITIAL_ROT_PROTECTION_AVAILABLE
|
||||
status = ppu_prog_protect((cy_ppu_prog_cfg_t *)prog_pc0_ppu_config, sizeof(prog_pc0_ppu_config) / sizeof(prog_pc0_ppu_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
#endif /* INITIAL_ROT_PROTECTION_AVAILABLE */
|
||||
#ifndef INITIAL_PROTECTION_AVAILABLE
|
||||
status = ppu_prog_protect((cy_ppu_prog_cfg_t *)prog_spm_ppu_config, sizeof(prog_spm_ppu_config) / sizeof(prog_spm_ppu_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
#endif /* INITIAL_PROTECTION_AVAILABLE */
|
||||
/* fixed group ppu */
|
||||
#ifndef INITIAL_ROT_PROTECTION_AVAILABLE
|
||||
status = ppu_fixed_gr_protect((cy_ppu_fixed_gr_cfg_t *)fixed_gr_pc0_ppu_config, sizeof(fixed_gr_pc0_ppu_config) / sizeof(fixed_gr_pc0_ppu_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
#endif /* INITIAL_ROT_PROTECTION_AVAILABLE */
|
||||
#ifndef INITIAL_PROTECTION_AVAILABLE
|
||||
status = ppu_fixed_gr_protect((cy_ppu_fixed_gr_cfg_t *)fixed_gr_spm_ppu_config, sizeof(fixed_gr_spm_ppu_config) / sizeof(fixed_gr_spm_ppu_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
#endif /* INITIAL_PROTECTION_AVAILABLE */
|
||||
|
||||
/* bus masters */
|
||||
#ifndef INITIAL_ROT_PROTECTION_AVAILABLE
|
||||
status = bus_masters_protect((cy_bus_master_config_t *)bus_masters_config, sizeof(bus_masters_config) / sizeof(bus_masters_config[0]));
|
||||
CY_ASSERT(status == CY_PROT_SUCCESS); // TODO: Panic instead
|
||||
#endif /* INITIAL_PROTECTION_AVAILABLE */
|
||||
#endif /* PU_ENABLE */
|
||||
}
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
/* Copyright (c) 2017-2018 ARM Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
/* -------------------------------------- Includes ----------------------------------- */
|
||||
|
||||
#include "spm_api.h"
|
||||
|
||||
#include "device.h"
|
||||
#include "cyip_ipc.h"
|
||||
#include "cy_ipc_drv.h"
|
||||
#include "cy_syslib.h"
|
||||
#include "cy_sysint.h"
|
||||
#include "psoc6_utils.h"
|
||||
#include "mbed_error.h"
|
||||
|
||||
|
||||
/* ------------------------------------ Definitions ---------------------------------- */
|
||||
|
||||
#define SPM_IPC_CHANNEL 8u
|
||||
#define SPM_IPC_NOTIFY_CM0P_INTR (CY_IPC_INTR_SPARE + 2) // CM4 to CM0+ notify interrupt number
|
||||
#define SPM_IPC_NOTIFY_CM4_INTR (CY_IPC_INTR_SPARE + 1) // CM0+ to CM4 notify interrupt number
|
||||
|
||||
|
||||
|
||||
/* ---------------------------------- Static Globals --------------------------------- */
|
||||
|
||||
static IPC_STRUCT_Type *ipc_channel_handle;
|
||||
static IPC_INTR_STRUCT_Type *ipc_interrupt_ptr;
|
||||
|
||||
|
||||
|
||||
/* ------------------------ Platform's Functions Implementation ---------------------- */
|
||||
|
||||
void ipc_interrupt_handler(void)
|
||||
{
|
||||
// Call ARM's interrupt handler
|
||||
spm_mailbox_irq_callback();
|
||||
|
||||
// Clear the interrupt and make a dummy read to avoid double interrupt occurrence:
|
||||
// - The double interrupt’s triggering is caused by buffered write operations on bus
|
||||
// - The dummy read of the status register is indeed required to make sure previous write completed before leaving ISR
|
||||
// Note: This is a direct clear using the IPC interrupt register and not clear of an NVIC register
|
||||
Cy_IPC_Drv_ClearInterrupt(ipc_interrupt_ptr, CY_IPC_NO_NOTIFICATION, (1uL << SPM_IPC_CHANNEL));
|
||||
}
|
||||
|
||||
void mailbox_init(void)
|
||||
{
|
||||
// Interrupts configuration for CM0+
|
||||
// * See ce216795_common.h for occupied interrupts
|
||||
// -----------------------------------------------
|
||||
|
||||
// Configure interrupts ISR / MUX and priority
|
||||
cy_stc_sysint_t ipc_intr_Config;
|
||||
ipc_intr_Config.intrSrc = CY_M0_CORE_IRQ_CHANNEL_PSA_MAILBOX;
|
||||
ipc_intr_Config.cm0pSrc = (cy_en_intr_t)cpuss_interrupts_ipc_0_IRQn + SPM_IPC_NOTIFY_CM0P_INTR; // Must match the interrupt we trigger using NOTIFY on CM4
|
||||
ipc_intr_Config.intrPriority = 1;
|
||||
if (cy_m0_nvic_reserve_channel(CY_M0_CORE_IRQ_CHANNEL_PSA_MAILBOX, CY_PSA_MAILBOX_IRQN_ID) == (IRQn_Type)(-1)) {
|
||||
error("PSA SPM Mailbox NVIC channel reservation conflict.");
|
||||
}
|
||||
(void)Cy_SysInt_Init(&ipc_intr_Config, ipc_interrupt_handler);
|
||||
|
||||
// Set specific NOTIFY interrupt mask only.
|
||||
// Only the interrupt sources with their masks enabled can trigger the interrupt.
|
||||
ipc_interrupt_ptr = Cy_IPC_Drv_GetIntrBaseAddr(SPM_IPC_NOTIFY_CM0P_INTR);
|
||||
CY_ASSERT(ipc_interrupt_ptr != NULL);
|
||||
Cy_IPC_Drv_SetInterruptMask(ipc_interrupt_ptr, 0x0, 1 << SPM_IPC_CHANNEL);
|
||||
|
||||
// Enable the interrupt
|
||||
NVIC_EnableIRQ(ipc_intr_Config.intrSrc);
|
||||
|
||||
ipc_channel_handle = Cy_IPC_Drv_GetIpcBaseAddress(SPM_IPC_CHANNEL);
|
||||
CY_ASSERT(ipc_channel_handle != NULL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* -------------------------------------- HAL API ------------------------------------ */
|
||||
|
||||
void spm_hal_mailbox_notify(void)
|
||||
{
|
||||
CY_ASSERT(ipc_channel_handle != NULL);
|
||||
Cy_IPC_Drv_AcquireNotify(ipc_channel_handle, (1uL << SPM_IPC_NOTIFY_CM4_INTR));
|
||||
}
|
||||
|
|
@ -1,8 +1,6 @@
|
|||
Copyright (c) 2018-2019 Cypress Semiconductor Corporation
|
||||
|
||||
Permissive Binary License
|
||||
|
||||
Version 1.0, September 2015
|
||||
Version 1.0, December 2018
|
||||
|
||||
Redistribution. Redistribution and use in binary form, without
|
||||
modification, are permitted provided that the following conditions are
|
||||
|
|
@ -17,12 +15,12 @@ met:
|
|||
permitted.
|
||||
|
||||
3) Redistribution as part of a software development kit must include the
|
||||
accompanying file named "DEPENDENCIES" and any dependencies listed in
|
||||
accompanying file named DEPENDENCIES and any dependencies listed in
|
||||
that file.
|
||||
|
||||
4) Neither the name of the copyright holder nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
this software without specific prior written permission.
|
||||
|
||||
Limited patent license. The copyright holders (and contributors) grant a
|
||||
worldwide, non-exclusive, no-charge, royalty-free patent license to
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
|
||||
This directory tree contains Secure images released under Permissive Binary License.
|
||||
|
||||
Build by mbed-cli using GNU Arm Embedded - version 6.3.1
|
||||
|
||||
These images were compiled by the following command:
|
||||
|
||||
```
|
||||
mbed compile -m CY8CKIT_062_WIFI_BT_M0_PSA -t GCC_ARM --profile release -N psa_release_1.0
|
||||
mbed test --compile -m CY8CKIT_062_WIFI_BT_M0_PSA -t GCC_ARM --profile debug -n *psa-spm*,*psa-crypto_access_control
|
||||
```
|
||||
|
||||
To update the prebuilt binaries run the previous commands.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,93 @@
|
|||
/* Copyright (c) 2017-2018 ARM Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
/* -------------------------------------- Includes ----------------------------------- */
|
||||
|
||||
#include "spm_api.h"
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "cyip_ipc.h"
|
||||
#include "cy_ipc_drv.h"
|
||||
#include "cy_syslib.h"
|
||||
#include "cy_sysint.h"
|
||||
|
||||
|
||||
|
||||
/* ------------------------------------ Definitions ---------------------------------- */
|
||||
|
||||
#define SPM_IPC_CHANNEL 8u
|
||||
#define SPM_IPC_NOTIFY_CM0P_INTR (CY_IPC_INTR_SPARE + 2) // CM4 to CM0+ notify interrupt number
|
||||
#define SPM_IPC_NOTIFY_CM4_INTR (CY_IPC_INTR_SPARE + 1) // CM0+ to CM4 notify interrupt number
|
||||
|
||||
|
||||
|
||||
/* ---------------------------------- Static Globals --------------------------------- */
|
||||
|
||||
static IPC_STRUCT_Type *ipc_channel_handle;
|
||||
static IPC_INTR_STRUCT_Type *ipc_interrupt_ptr;
|
||||
|
||||
|
||||
|
||||
/* ------------------------ Platform's Functions Implementation ---------------------- */
|
||||
|
||||
void ipc_interrupt_handler(void)
|
||||
{
|
||||
// Call ARM's interrupt handler
|
||||
spm_mailbox_irq_callback();
|
||||
|
||||
// Clear the interrupt and make a dummy read to avoid double interrupt occurrence:
|
||||
// - The double interrupt’s triggering is caused by buffered write operations on bus
|
||||
// - The dummy read of the status register is indeed required to make sure previous write completed before leaving ISR
|
||||
// Note: This is a direct clear using the IPC interrupt register and not clear of an NVIC register
|
||||
Cy_IPC_Drv_ClearInterrupt(ipc_interrupt_ptr, CY_IPC_NO_NOTIFICATION, (1uL << SPM_IPC_CHANNEL));
|
||||
}
|
||||
|
||||
void mailbox_init(void)
|
||||
{
|
||||
// Interrupts configuration for CM4
|
||||
// * See ce216795_common.h for occupied interrupts
|
||||
// -----------------------------------------------
|
||||
|
||||
// Configure interrupts ISR / MUX and priority
|
||||
cy_stc_sysint_t ipc_intr_Config;
|
||||
ipc_intr_Config.intrSrc = (IRQn_Type)cpuss_interrupts_ipc_0_IRQn + SPM_IPC_NOTIFY_CM4_INTR;
|
||||
ipc_intr_Config.intrPriority = 1;
|
||||
(void)Cy_SysInt_Init(&ipc_intr_Config, ipc_interrupt_handler);
|
||||
|
||||
// Set specific NOTIFY interrupt mask only.
|
||||
// Only the interrupt sources with their masks enabled can trigger the interrupt.
|
||||
ipc_interrupt_ptr = Cy_IPC_Drv_GetIntrBaseAddr(SPM_IPC_NOTIFY_CM4_INTR);
|
||||
CY_ASSERT(ipc_interrupt_ptr != NULL);
|
||||
Cy_IPC_Drv_SetInterruptMask(ipc_interrupt_ptr, 0x0, 1 << SPM_IPC_CHANNEL);
|
||||
|
||||
// Enable the interrupt
|
||||
NVIC_EnableIRQ(ipc_intr_Config.intrSrc);
|
||||
|
||||
ipc_channel_handle = Cy_IPC_Drv_GetIpcBaseAddress(SPM_IPC_CHANNEL);
|
||||
CY_ASSERT(ipc_channel_handle != NULL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* -------------------------------------- HAL API ------------------------------------ */
|
||||
|
||||
void spm_hal_mailbox_notify(void)
|
||||
{
|
||||
CY_ASSERT(ipc_channel_handle != NULL);
|
||||
Cy_IPC_Drv_AcquireNotify(ipc_channel_handle, (1uL << SPM_IPC_NOTIFY_CM0P_INTR));
|
||||
}
|
||||
|
|
@ -1,113 +0,0 @@
|
|||
/*
|
||||
* mbed Microcontroller Library
|
||||
* Copyright (c) 2017-2018 Future Electronics
|
||||
* Copyright (c) 2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef MBED_PERIPHERALNAMES_H
|
||||
#define MBED_PERIPHERALNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PinNames.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
UART_0 = (int)SCB0_BASE,
|
||||
UART_1 = (int)SCB1_BASE,
|
||||
UART_2 = (int)SCB2_BASE,
|
||||
UART_3 = (int)SCB3_BASE,
|
||||
UART_4 = (int)SCB4_BASE,
|
||||
UART_5 = (int)SCB5_BASE,
|
||||
UART_6 = (int)SCB6_BASE,
|
||||
UART_7 = (int)SCB7_BASE,
|
||||
} UARTName;
|
||||
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = (int)SCB0_BASE,
|
||||
SPI_1 = (int)SCB1_BASE,
|
||||
SPI_2 = (int)SCB2_BASE,
|
||||
SPI_3 = (int)SCB3_BASE,
|
||||
SPI_4 = (int)SCB4_BASE,
|
||||
SPI_5 = (int)SCB5_BASE,
|
||||
SPI_6 = (int)SCB6_BASE,
|
||||
SPI_7 = (int)SCB7_BASE,
|
||||
SPI_8 = (int)SCB8_BASE,
|
||||
} SPIName;
|
||||
|
||||
typedef enum {
|
||||
I2C_0 = (int)SCB0_BASE,
|
||||
I2C_1 = (int)SCB1_BASE,
|
||||
I2C_2 = (int)SCB2_BASE,
|
||||
I2C_3 = (int)SCB3_BASE,
|
||||
I2C_4 = (int)SCB4_BASE,
|
||||
I2C_5 = (int)SCB5_BASE,
|
||||
I2C_6 = (int)SCB6_BASE,
|
||||
I2C_7 = (int)SCB7_BASE,
|
||||
I2C_8 = (int)SCB8_BASE,
|
||||
} I2CName;
|
||||
|
||||
typedef enum {
|
||||
PWM_32b_0 = TCPWM0_BASE,
|
||||
PWM_32b_1,
|
||||
PWM_32b_2,
|
||||
PWM_32b_3,
|
||||
PWM_32b_4,
|
||||
PWM_32b_5,
|
||||
PWM_32b_6,
|
||||
PWM_32b_7,
|
||||
PWM_16b_0 = TCPWM1_BASE,
|
||||
PWM_16b_1,
|
||||
PWM_16b_2,
|
||||
PWM_16b_3,
|
||||
PWM_16b_4,
|
||||
PWM_16b_5,
|
||||
PWM_16b_6,
|
||||
PWM_16b_7,
|
||||
PWM_16b_8,
|
||||
PWM_16b_9,
|
||||
PWM_16b_10,
|
||||
PWM_16b_11,
|
||||
PWM_16b_12,
|
||||
PWM_16b_13,
|
||||
PWM_16b_14,
|
||||
PWM_16b_15,
|
||||
PWM_16b_16,
|
||||
PWM_16b_17,
|
||||
PWM_16b_18,
|
||||
PWM_16b_19,
|
||||
PWM_16b_20,
|
||||
PWM_16b_21,
|
||||
PWM_16b_22,
|
||||
PWM_16b_23,
|
||||
} PWMName;
|
||||
|
||||
typedef enum {
|
||||
ADC_0 = (int)SAR_BASE,
|
||||
} ADCName;
|
||||
|
||||
typedef enum {
|
||||
DAC_0 = (int)CTDAC0_BASE,
|
||||
} DACName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -1,435 +0,0 @@
|
|||
/*
|
||||
* mbed Microcontroller Library
|
||||
* Copyright (c) 2017-2018 Future Electronics
|
||||
* Copyright (c) 2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "PeripheralNames.h"
|
||||
#include "PeripheralPins.h"
|
||||
#include "pinmap.h"
|
||||
|
||||
#if DEVICE_SERIAL
|
||||
//*** SERIAL ***
|
||||
const PinMap PinMap_UART_RX[] = {
|
||||
{P0_2, UART_0, CY_PIN_IN_FUNCTION( P0_2_SCB0_UART_RX, PCLK_SCB0_CLOCK)},
|
||||
{P1_0, UART_7, CY_PIN_IN_FUNCTION( P1_0_SCB7_UART_RX, PCLK_SCB7_CLOCK)},
|
||||
{P2_0, UART_1, CY_PIN_IN_FUNCTION( P2_0_SCB1_UART_RX, PCLK_SCB1_CLOCK)},
|
||||
{P3_0, UART_2, CY_PIN_IN_FUNCTION( P3_0_SCB2_UART_RX, PCLK_SCB2_CLOCK)},
|
||||
{P4_0, UART_7, CY_PIN_IN_FUNCTION( P4_0_SCB7_UART_RX, PCLK_SCB7_CLOCK)},
|
||||
{P5_0, UART_5, CY_PIN_IN_FUNCTION( P5_0_SCB5_UART_RX, PCLK_SCB5_CLOCK)},
|
||||
{P6_0, UART_3, CY_PIN_IN_FUNCTION( P6_0_SCB3_UART_RX, PCLK_SCB3_CLOCK)},
|
||||
{P6_4, UART_6, CY_PIN_IN_FUNCTION( P6_4_SCB6_UART_RX, PCLK_SCB6_CLOCK)},
|
||||
{P7_0, UART_4, CY_PIN_IN_FUNCTION( P7_0_SCB4_UART_RX, PCLK_SCB4_CLOCK)},
|
||||
{P8_0, UART_4, CY_PIN_IN_FUNCTION( P8_0_SCB4_UART_RX, PCLK_SCB4_CLOCK)},
|
||||
{P9_0, UART_2, CY_PIN_IN_FUNCTION( P9_0_SCB2_UART_RX, PCLK_SCB2_CLOCK)},
|
||||
{P10_0, UART_1, CY_PIN_IN_FUNCTION( P10_0_SCB1_UART_RX, PCLK_SCB1_CLOCK)},
|
||||
{P11_0, UART_5, CY_PIN_IN_FUNCTION( P11_0_SCB5_UART_RX, PCLK_SCB5_CLOCK)},
|
||||
{P12_0, UART_6, CY_PIN_IN_FUNCTION( P12_0_SCB6_UART_RX, PCLK_SCB6_CLOCK)},
|
||||
{P13_0, UART_6, CY_PIN_IN_FUNCTION( P13_0_SCB6_UART_RX, PCLK_SCB6_CLOCK)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_UART_TX[] = {
|
||||
{P0_3, UART_0, CY_PIN_OUT_FUNCTION( P0_3_SCB0_UART_TX, PCLK_SCB0_CLOCK)},
|
||||
{P1_1, UART_7, CY_PIN_OUT_FUNCTION( P1_1_SCB7_UART_TX, PCLK_SCB7_CLOCK)},
|
||||
{P2_1, UART_1, CY_PIN_OUT_FUNCTION( P2_1_SCB1_UART_TX, PCLK_SCB1_CLOCK)},
|
||||
{P3_1, UART_2, CY_PIN_OUT_FUNCTION( P3_1_SCB2_UART_TX, PCLK_SCB2_CLOCK)},
|
||||
{P4_1, UART_7, CY_PIN_OUT_FUNCTION( P4_1_SCB7_UART_TX, PCLK_SCB7_CLOCK)},
|
||||
{P5_1, UART_5, CY_PIN_OUT_FUNCTION( P5_1_SCB5_UART_TX, PCLK_SCB5_CLOCK)},
|
||||
{P6_1, UART_3, CY_PIN_OUT_FUNCTION( P6_1_SCB3_UART_TX, PCLK_SCB3_CLOCK)},
|
||||
{P6_5, UART_6, CY_PIN_OUT_FUNCTION( P6_5_SCB6_UART_TX, PCLK_SCB6_CLOCK)},
|
||||
{P7_1, UART_4, CY_PIN_OUT_FUNCTION( P7_1_SCB4_UART_TX, PCLK_SCB4_CLOCK)},
|
||||
{P8_1, UART_4, CY_PIN_OUT_FUNCTION( P8_1_SCB4_UART_TX, PCLK_SCB4_CLOCK)},
|
||||
{P9_1, UART_2, CY_PIN_OUT_FUNCTION( P9_1_SCB2_UART_TX, PCLK_SCB2_CLOCK)},
|
||||
{P10_1, UART_1, CY_PIN_OUT_FUNCTION( P10_1_SCB1_UART_TX, PCLK_SCB1_CLOCK)},
|
||||
{P11_1, UART_5, CY_PIN_OUT_FUNCTION( P11_1_SCB5_UART_TX, PCLK_SCB5_CLOCK)},
|
||||
{P12_1, UART_6, CY_PIN_OUT_FUNCTION( P12_1_SCB6_UART_TX, PCLK_SCB6_CLOCK)},
|
||||
{P13_1, UART_6, CY_PIN_OUT_FUNCTION( P13_1_SCB6_UART_TX, PCLK_SCB6_CLOCK)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_UART_RTS[] = {
|
||||
{P0_4, UART_0, CY_PIN_OUT_FUNCTION( P0_4_SCB0_UART_RTS, PCLK_SCB0_CLOCK)},
|
||||
{P1_2, UART_7, CY_PIN_OUT_FUNCTION( P1_2_SCB7_UART_RTS, PCLK_SCB7_CLOCK)},
|
||||
{P2_2, UART_1, CY_PIN_OUT_FUNCTION( P2_2_SCB1_UART_RTS, PCLK_SCB1_CLOCK)},
|
||||
{P3_2, UART_2, CY_PIN_OUT_FUNCTION( P3_2_SCB2_UART_RTS, PCLK_SCB2_CLOCK)},
|
||||
{P5_2, UART_5, CY_PIN_OUT_FUNCTION( P5_2_SCB5_UART_RTS, PCLK_SCB5_CLOCK)},
|
||||
{P6_2, UART_3, CY_PIN_OUT_FUNCTION( P6_2_SCB3_UART_RTS, PCLK_SCB3_CLOCK)},
|
||||
{P6_6, UART_6, CY_PIN_OUT_FUNCTION( P6_6_SCB6_UART_RTS, PCLK_SCB6_CLOCK)},
|
||||
{P7_2, UART_4, CY_PIN_OUT_FUNCTION( P7_2_SCB4_UART_RTS, PCLK_SCB4_CLOCK)},
|
||||
{P8_2, UART_4, CY_PIN_OUT_FUNCTION( P8_2_SCB4_UART_RTS, PCLK_SCB4_CLOCK)},
|
||||
{P9_2, UART_2, CY_PIN_OUT_FUNCTION( P9_2_SCB2_UART_RTS, PCLK_SCB2_CLOCK)},
|
||||
{P10_2, UART_1, CY_PIN_OUT_FUNCTION( P10_2_SCB1_UART_RTS, PCLK_SCB1_CLOCK)},
|
||||
{P11_2, UART_5, CY_PIN_OUT_FUNCTION( P11_2_SCB5_UART_RTS, PCLK_SCB5_CLOCK)},
|
||||
{P12_2, UART_6, CY_PIN_OUT_FUNCTION( P12_2_SCB6_UART_RTS, PCLK_SCB6_CLOCK)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_UART_CTS[] = {
|
||||
{P0_5, UART_0, CY_PIN_IN_FUNCTION( P0_5_SCB0_UART_CTS, PCLK_SCB0_CLOCK)},
|
||||
{P1_3, UART_7, CY_PIN_IN_FUNCTION( P1_3_SCB7_UART_CTS, PCLK_SCB7_CLOCK)},
|
||||
{P2_3, UART_1, CY_PIN_IN_FUNCTION( P2_3_SCB1_UART_CTS, PCLK_SCB1_CLOCK)},
|
||||
{P3_3, UART_2, CY_PIN_IN_FUNCTION( P3_3_SCB2_UART_CTS, PCLK_SCB2_CLOCK)},
|
||||
{P5_3, UART_5, CY_PIN_IN_FUNCTION( P5_3_SCB5_UART_CTS, PCLK_SCB5_CLOCK)},
|
||||
{P6_3, UART_3, CY_PIN_IN_FUNCTION( P6_3_SCB3_UART_CTS, PCLK_SCB3_CLOCK)},
|
||||
{P6_7, UART_6, CY_PIN_IN_FUNCTION( P6_7_SCB6_UART_CTS, PCLK_SCB6_CLOCK)},
|
||||
{P7_3, UART_4, CY_PIN_IN_FUNCTION( P7_3_SCB4_UART_CTS, PCLK_SCB4_CLOCK)},
|
||||
{P8_3, UART_4, CY_PIN_IN_FUNCTION( P8_3_SCB4_UART_CTS, PCLK_SCB4_CLOCK)},
|
||||
{P9_3, UART_2, CY_PIN_IN_FUNCTION( P9_3_SCB2_UART_CTS, PCLK_SCB2_CLOCK)},
|
||||
{P10_3, UART_1, CY_PIN_IN_FUNCTION( P10_3_SCB1_UART_CTS, PCLK_SCB1_CLOCK)},
|
||||
{P11_3, UART_5, CY_PIN_IN_FUNCTION( P11_3_SCB5_UART_CTS, PCLK_SCB5_CLOCK)},
|
||||
{P12_3, UART_6, CY_PIN_IN_FUNCTION( P12_3_SCB6_UART_CTS, PCLK_SCB6_CLOCK)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
#endif // DEVICE_SERIAL
|
||||
|
||||
|
||||
#if DEVICE_I2C
|
||||
//*** I2C ***
|
||||
const PinMap PinMap_I2C_SCL[] = {
|
||||
{P0_2, I2C_0, CY_PIN_OD_FUNCTION( P0_2_SCB0_I2C_SCL, PCLK_SCB0_CLOCK)},
|
||||
{P1_0, I2C_7, CY_PIN_OD_FUNCTION( P1_0_SCB7_I2C_SCL, PCLK_SCB7_CLOCK)},
|
||||
{P2_0, I2C_1, CY_PIN_OD_FUNCTION( P2_0_SCB1_I2C_SCL, PCLK_SCB1_CLOCK)},
|
||||
{P3_0, I2C_2, CY_PIN_OD_FUNCTION( P3_0_SCB2_I2C_SCL, PCLK_SCB2_CLOCK)},
|
||||
{P4_0, I2C_7, CY_PIN_OD_FUNCTION( P4_0_SCB7_I2C_SCL, PCLK_SCB7_CLOCK)},
|
||||
{P5_0, I2C_5, CY_PIN_OD_FUNCTION( P5_0_SCB5_I2C_SCL, PCLK_SCB5_CLOCK)},
|
||||
{P6_0, I2C_3, CY_PIN_OD_FUNCTION( P6_0_SCB3_I2C_SCL, PCLK_SCB3_CLOCK)},
|
||||
{P6_4, I2C_6, CY_PIN_OD_FUNCTION( P6_4_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)},
|
||||
{P7_0, I2C_4, CY_PIN_OD_FUNCTION( P7_0_SCB4_I2C_SCL, PCLK_SCB4_CLOCK)},
|
||||
{P8_0, I2C_4, CY_PIN_OD_FUNCTION( P8_0_SCB4_I2C_SCL, PCLK_SCB4_CLOCK)},
|
||||
{P9_0, I2C_2, CY_PIN_OD_FUNCTION( P9_0_SCB2_I2C_SCL, PCLK_SCB2_CLOCK)},
|
||||
{P10_0, I2C_1, CY_PIN_OD_FUNCTION( P10_0_SCB1_I2C_SCL, PCLK_SCB1_CLOCK)},
|
||||
{P11_0, I2C_5, CY_PIN_OD_FUNCTION( P11_0_SCB5_I2C_SCL, PCLK_SCB5_CLOCK)},
|
||||
{P12_0, I2C_6, CY_PIN_OD_FUNCTION( P12_0_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)},
|
||||
{P13_0, I2C_6, CY_PIN_OD_FUNCTION( P13_0_SCB6_I2C_SCL, PCLK_SCB6_CLOCK)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_I2C_SDA[] = {
|
||||
{P0_3, I2C_0, CY_PIN_OD_FUNCTION( P0_3_SCB0_I2C_SDA, PCLK_SCB0_CLOCK)},
|
||||
{P1_1, I2C_7, CY_PIN_OD_FUNCTION( P1_1_SCB7_I2C_SDA, PCLK_SCB7_CLOCK)},
|
||||
{P2_1, I2C_1, CY_PIN_OD_FUNCTION( P2_1_SCB1_I2C_SDA, PCLK_SCB1_CLOCK)},
|
||||
{P3_1, I2C_2, CY_PIN_OD_FUNCTION( P3_1_SCB2_I2C_SDA, PCLK_SCB2_CLOCK)},
|
||||
{P4_1, I2C_7, CY_PIN_OD_FUNCTION( P4_1_SCB7_I2C_SDA, PCLK_SCB7_CLOCK)},
|
||||
{P5_1, I2C_5, CY_PIN_OD_FUNCTION( P5_1_SCB5_I2C_SDA, PCLK_SCB5_CLOCK)},
|
||||
{P6_1, I2C_3, CY_PIN_OD_FUNCTION( P6_1_SCB3_I2C_SDA, PCLK_SCB3_CLOCK)},
|
||||
{P6_5, I2C_6, CY_PIN_OD_FUNCTION( P6_5_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)},
|
||||
{P7_1, I2C_4, CY_PIN_OD_FUNCTION( P7_1_SCB4_I2C_SDA, PCLK_SCB4_CLOCK)},
|
||||
{P8_1, I2C_4, CY_PIN_OD_FUNCTION( P8_1_SCB4_I2C_SDA, PCLK_SCB4_CLOCK)},
|
||||
{P9_1, I2C_2, CY_PIN_OD_FUNCTION( P9_1_SCB2_I2C_SDA, PCLK_SCB2_CLOCK)},
|
||||
{P10_1, I2C_1, CY_PIN_OD_FUNCTION( P10_1_SCB1_I2C_SDA, PCLK_SCB1_CLOCK)},
|
||||
{P11_1, I2C_5, CY_PIN_OD_FUNCTION( P11_1_SCB5_I2C_SDA, PCLK_SCB5_CLOCK)},
|
||||
{P12_1, I2C_6, CY_PIN_OD_FUNCTION( P12_1_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)},
|
||||
{P13_1, I2C_6, CY_PIN_OD_FUNCTION( P13_1_SCB6_I2C_SDA, PCLK_SCB6_CLOCK)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
#endif // DEVICE_I2C
|
||||
|
||||
#if DEVICE_SPI
|
||||
//*** SPI ***
|
||||
const PinMap PinMap_SPI_MOSI[] = {
|
||||
{P0_2, SPI_0, CY_PIN_OUT_FUNCTION( P0_2_SCB0_SPI_MOSI, PCLK_SCB0_CLOCK)},
|
||||
{P1_0, SPI_7, CY_PIN_OUT_FUNCTION( P1_0_SCB7_SPI_MOSI, PCLK_SCB7_CLOCK)},
|
||||
{P2_0, SPI_1, CY_PIN_OUT_FUNCTION( P2_0_SCB1_SPI_MOSI, PCLK_SCB1_CLOCK)},
|
||||
{P3_0, SPI_2, CY_PIN_OUT_FUNCTION( P3_0_SCB2_SPI_MOSI, PCLK_SCB2_CLOCK)},
|
||||
{P4_0, SPI_7, CY_PIN_OUT_FUNCTION( P4_0_SCB7_SPI_MOSI, PCLK_SCB7_CLOCK)},
|
||||
{P5_0, SPI_5, CY_PIN_OUT_FUNCTION( P5_0_SCB5_SPI_MOSI, PCLK_SCB5_CLOCK)},
|
||||
{P6_0, SPI_3, CY_PIN_OUT_FUNCTION( P6_0_SCB3_SPI_MOSI, PCLK_SCB3_CLOCK)},
|
||||
{P6_4, SPI_6, CY_PIN_OUT_FUNCTION( P6_4_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)},
|
||||
{P7_0, SPI_4, CY_PIN_OUT_FUNCTION( P7_0_SCB4_SPI_MOSI, PCLK_SCB4_CLOCK)},
|
||||
{P8_0, SPI_4, CY_PIN_OUT_FUNCTION( P8_0_SCB4_SPI_MOSI, PCLK_SCB4_CLOCK)},
|
||||
{P9_0, SPI_2, CY_PIN_OUT_FUNCTION( P9_0_SCB2_SPI_MOSI, PCLK_SCB2_CLOCK)},
|
||||
{P10_0, SPI_1, CY_PIN_OUT_FUNCTION( P10_0_SCB1_SPI_MOSI, PCLK_SCB1_CLOCK)},
|
||||
{P11_0, SPI_5, CY_PIN_OUT_FUNCTION( P11_0_SCB5_SPI_MOSI, PCLK_SCB5_CLOCK)},
|
||||
{P12_0, SPI_6, CY_PIN_OUT_FUNCTION( P12_0_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)},
|
||||
{P13_0, SPI_6, CY_PIN_OUT_FUNCTION( P13_0_SCB6_SPI_MOSI, PCLK_SCB6_CLOCK)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_SPI_MISO[] = {
|
||||
{P0_3, SPI_0, CY_PIN_IN_FUNCTION( P0_3_SCB0_SPI_MISO, PCLK_SCB0_CLOCK)},
|
||||
{P1_1, SPI_7, CY_PIN_IN_FUNCTION( P1_1_SCB7_SPI_MISO, PCLK_SCB7_CLOCK)},
|
||||
{P2_1, SPI_1, CY_PIN_IN_FUNCTION( P2_1_SCB1_SPI_MISO, PCLK_SCB1_CLOCK)},
|
||||
{P3_1, SPI_2, CY_PIN_IN_FUNCTION( P3_1_SCB2_SPI_MISO, PCLK_SCB2_CLOCK)},
|
||||
{P4_1, SPI_7, CY_PIN_IN_FUNCTION( P4_1_SCB7_SPI_MISO, PCLK_SCB7_CLOCK)},
|
||||
{P5_1, SPI_5, CY_PIN_IN_FUNCTION( P5_1_SCB5_SPI_MISO, PCLK_SCB5_CLOCK)},
|
||||
{P6_1, SPI_3, CY_PIN_IN_FUNCTION( P6_1_SCB3_SPI_MISO, PCLK_SCB3_CLOCK)},
|
||||
{P6_5, SPI_6, CY_PIN_IN_FUNCTION( P6_5_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)},
|
||||
{P7_1, SPI_4, CY_PIN_IN_FUNCTION( P7_1_SCB4_SPI_MISO, PCLK_SCB4_CLOCK)},
|
||||
{P8_1, SPI_4, CY_PIN_IN_FUNCTION( P8_1_SCB4_SPI_MISO, PCLK_SCB4_CLOCK)},
|
||||
{P9_1, SPI_2, CY_PIN_IN_FUNCTION( P9_1_SCB2_SPI_MISO, PCLK_SCB2_CLOCK)},
|
||||
{P10_1, SPI_1, CY_PIN_IN_FUNCTION( P10_1_SCB1_SPI_MISO, PCLK_SCB1_CLOCK)},
|
||||
{P11_1, SPI_5, CY_PIN_IN_FUNCTION( P11_1_SCB5_SPI_MISO, PCLK_SCB5_CLOCK)},
|
||||
{P12_1, SPI_6, CY_PIN_IN_FUNCTION( P12_1_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)},
|
||||
{P13_1, SPI_6, CY_PIN_IN_FUNCTION( P13_1_SCB6_SPI_MISO, PCLK_SCB6_CLOCK)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_SPI_SCLK[] = {
|
||||
{P0_4, SPI_0, CY_PIN_OUT_FUNCTION( P0_4_SCB0_SPI_CLK, PCLK_SCB0_CLOCK)},
|
||||
{P1_2, SPI_7, CY_PIN_OUT_FUNCTION( P1_2_SCB7_SPI_CLK, PCLK_SCB7_CLOCK)},
|
||||
{P2_2, SPI_1, CY_PIN_OUT_FUNCTION( P2_2_SCB1_SPI_CLK, PCLK_SCB1_CLOCK)},
|
||||
{P3_2, SPI_2, CY_PIN_OUT_FUNCTION( P3_2_SCB2_SPI_CLK, PCLK_SCB2_CLOCK)},
|
||||
{P5_2, SPI_5, CY_PIN_OUT_FUNCTION( P5_2_SCB5_SPI_CLK, PCLK_SCB5_CLOCK)},
|
||||
{P6_2, SPI_3, CY_PIN_OUT_FUNCTION( P6_2_SCB3_SPI_CLK, PCLK_SCB3_CLOCK)},
|
||||
{P6_6, SPI_6, CY_PIN_OUT_FUNCTION( P6_6_SCB6_SPI_CLK, PCLK_SCB6_CLOCK)},
|
||||
{P7_2, SPI_4, CY_PIN_OUT_FUNCTION( P7_2_SCB4_SPI_CLK, PCLK_SCB4_CLOCK)},
|
||||
{P8_2, SPI_4, CY_PIN_OUT_FUNCTION( P8_2_SCB4_SPI_CLK, PCLK_SCB4_CLOCK)},
|
||||
{P9_2, SPI_2, CY_PIN_OUT_FUNCTION( P9_2_SCB2_SPI_CLK, PCLK_SCB2_CLOCK)},
|
||||
{P10_2, SPI_1, CY_PIN_OUT_FUNCTION( P10_2_SCB1_SPI_CLK, PCLK_SCB1_CLOCK)},
|
||||
{P11_2, SPI_5, CY_PIN_OUT_FUNCTION( P11_2_SCB5_SPI_CLK, PCLK_SCB5_CLOCK)},
|
||||
{P12_2, SPI_6, CY_PIN_OUT_FUNCTION( P12_2_SCB6_SPI_CLK, PCLK_SCB6_CLOCK)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_SPI_SSEL[] = {
|
||||
{P0_5, SPI_0, CY_PIN_OUT_FUNCTION( P0_5_SCB0_SPI_SELECT0, PCLK_SCB0_CLOCK)},
|
||||
{P1_3, SPI_7, CY_PIN_OUT_FUNCTION( P1_3_SCB7_SPI_SELECT0, PCLK_SCB7_CLOCK)},
|
||||
{P2_3, SPI_1, CY_PIN_OUT_FUNCTION( P2_3_SCB1_SPI_SELECT0, PCLK_SCB1_CLOCK)},
|
||||
{P3_3, SPI_2, CY_PIN_OUT_FUNCTION( P3_3_SCB2_SPI_SELECT0, PCLK_SCB2_CLOCK)},
|
||||
{P5_3, SPI_5, CY_PIN_OUT_FUNCTION( P5_3_SCB5_SPI_SELECT0, PCLK_SCB5_CLOCK)},
|
||||
{P6_3, SPI_3, CY_PIN_OUT_FUNCTION( P6_3_SCB3_SPI_SELECT0, PCLK_SCB3_CLOCK)},
|
||||
{P6_7, SPI_6, CY_PIN_OUT_FUNCTION( P6_7_SCB6_SPI_SELECT0, PCLK_SCB6_CLOCK)},
|
||||
{P7_3, SPI_4, CY_PIN_OUT_FUNCTION( P7_3_SCB4_SPI_SELECT0, PCLK_SCB4_CLOCK)},
|
||||
{P8_3, SPI_4, CY_PIN_OUT_FUNCTION( P8_3_SCB4_SPI_SELECT0, PCLK_SCB4_CLOCK)},
|
||||
{P9_3, SPI_2, CY_PIN_OUT_FUNCTION( P9_3_SCB2_SPI_SELECT0, PCLK_SCB2_CLOCK)},
|
||||
{P10_3, SPI_1, CY_PIN_OUT_FUNCTION( P10_3_SCB1_SPI_SELECT0, PCLK_SCB1_CLOCK)},
|
||||
{P11_3, SPI_5, CY_PIN_OUT_FUNCTION( P11_3_SCB5_SPI_SELECT0, PCLK_SCB5_CLOCK)},
|
||||
{P12_3, SPI_6, CY_PIN_OUT_FUNCTION( P12_3_SCB6_SPI_SELECT0, PCLK_SCB6_CLOCK)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
#endif // DEVICE_SPI
|
||||
|
||||
#if DEVICE_PWMOUT
|
||||
//*** PWM ***
|
||||
const PinMap PinMap_PWM_OUT[] = {
|
||||
// 16-bit PWM outputs
|
||||
{P0_0, PWM_16b_0, CY_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)},
|
||||
{P0_2, PWM_16b_1, CY_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)},
|
||||
{P0_4, PWM_16b_2, CY_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)},
|
||||
{P1_0, PWM_16b_3, CY_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3, PCLK_TCPWM1_CLOCKS3)},
|
||||
{P1_2, PWM_16b_12, CY_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12, PCLK_TCPWM1_CLOCKS12)},
|
||||
{P1_4, PWM_16b_13, CY_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13, PCLK_TCPWM1_CLOCKS13)},
|
||||
{P2_0, PWM_16b_15, CY_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15, PCLK_TCPWM1_CLOCKS15)},
|
||||
{P2_2, PWM_16b_16, CY_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16, PCLK_TCPWM1_CLOCKS16)},
|
||||
{P2_4, PWM_16b_17, CY_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17, PCLK_TCPWM1_CLOCKS17)},
|
||||
{P2_6, PWM_16b_18, CY_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18, PCLK_TCPWM1_CLOCKS18)},
|
||||
{P3_0, PWM_16b_19, CY_PIN_OUT_FUNCTION(P3_0_TCPWM1_LINE19, PCLK_TCPWM1_CLOCKS19)},
|
||||
{P3_2, PWM_16b_20, CY_PIN_OUT_FUNCTION(P3_2_TCPWM1_LINE20, PCLK_TCPWM1_CLOCKS20)},
|
||||
{P3_4, PWM_16b_21, CY_PIN_OUT_FUNCTION(P3_4_TCPWM1_LINE21, PCLK_TCPWM1_CLOCKS21)},
|
||||
{P4_0, PWM_16b_22, CY_PIN_OUT_FUNCTION(P4_0_TCPWM1_LINE22, PCLK_TCPWM1_CLOCKS22)},
|
||||
{P5_0, PWM_16b_4, CY_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4, PCLK_TCPWM1_CLOCKS4)},
|
||||
{P5_2, PWM_16b_5, CY_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5, PCLK_TCPWM1_CLOCKS5)},
|
||||
{P5_4, PWM_16b_6, CY_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6, PCLK_TCPWM1_CLOCKS6)},
|
||||
{P5_6, PWM_16b_7, CY_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7, PCLK_TCPWM1_CLOCKS7)},
|
||||
{P6_0, PWM_16b_8, CY_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8, PCLK_TCPWM1_CLOCKS8)},
|
||||
{P6_2, PWM_16b_9, CY_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9, PCLK_TCPWM1_CLOCKS9)},
|
||||
{P6_4, PWM_16b_10, CY_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10, PCLK_TCPWM1_CLOCKS10)},
|
||||
{P6_6, PWM_16b_11, CY_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11, PCLK_TCPWM1_CLOCKS11)},
|
||||
{P7_0, PWM_16b_12, CY_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12, PCLK_TCPWM1_CLOCKS12)},
|
||||
{P7_2, PWM_16b_13, CY_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13, PCLK_TCPWM1_CLOCKS13)},
|
||||
{P7_4, PWM_16b_14, CY_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14, PCLK_TCPWM1_CLOCKS14)},
|
||||
{P7_6, PWM_16b_15, CY_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15, PCLK_TCPWM1_CLOCKS15)},
|
||||
{P8_0, PWM_16b_16, CY_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16, PCLK_TCPWM1_CLOCKS16)},
|
||||
{P8_2, PWM_16b_17, CY_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17, PCLK_TCPWM1_CLOCKS17)},
|
||||
{P8_4, PWM_16b_18, CY_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18, PCLK_TCPWM1_CLOCKS18)},
|
||||
{P8_6, PWM_16b_19, CY_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19, PCLK_TCPWM1_CLOCKS19)},
|
||||
{P9_0, PWM_16b_20, CY_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20, PCLK_TCPWM1_CLOCKS20)},
|
||||
{P9_2, PWM_16b_21, CY_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21, PCLK_TCPWM1_CLOCKS21)},
|
||||
{P9_4, PWM_16b_0, CY_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)},
|
||||
{P9_6, PWM_16b_1, CY_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)},
|
||||
{P10_0, PWM_16b_22, CY_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22, PCLK_TCPWM1_CLOCKS22)},
|
||||
{P10_2, PWM_16b_23, CY_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23, PCLK_TCPWM1_CLOCKS23)},
|
||||
{P10_4, PWM_16b_0, CY_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0, PCLK_TCPWM1_CLOCKS0)},
|
||||
{P10_6, PWM_16b_2, CY_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)},
|
||||
{P11_0, PWM_16b_1, CY_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1, PCLK_TCPWM1_CLOCKS1)},
|
||||
{P11_2, PWM_16b_2, CY_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2, PCLK_TCPWM1_CLOCKS2)},
|
||||
{P11_4, PWM_16b_3, CY_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3, PCLK_TCPWM1_CLOCKS3)},
|
||||
{P12_0, PWM_16b_4, CY_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4, PCLK_TCPWM1_CLOCKS4)},
|
||||
{P12_2, PWM_16b_5, CY_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5, PCLK_TCPWM1_CLOCKS5)},
|
||||
{P12_4, PWM_16b_6, CY_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6, PCLK_TCPWM1_CLOCKS6)},
|
||||
{P12_6, PWM_16b_7, CY_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7, PCLK_TCPWM1_CLOCKS7)},
|
||||
{P13_0, PWM_16b_8, CY_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8, PCLK_TCPWM1_CLOCKS8)},
|
||||
{P13_2, PWM_16b_9, CY_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9, PCLK_TCPWM1_CLOCKS9)},
|
||||
{P13_4, PWM_16b_10, CY_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10, PCLK_TCPWM1_CLOCKS10)},
|
||||
{P13_6, PWM_16b_11, CY_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11, PCLK_TCPWM1_CLOCKS11)},
|
||||
// 16-bit PWM inverted outputs
|
||||
{P0_1, PWM_16b_0, CY_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)},
|
||||
{P0_3, PWM_16b_1, CY_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)},
|
||||
{P0_5, PWM_16b_2, CY_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2, PCLK_TCPWM1_CLOCKS2)},
|
||||
{P1_1, PWM_16b_3, CY_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3, PCLK_TCPWM1_CLOCKS3)},
|
||||
{P1_3, PWM_16b_12, CY_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12, PCLK_TCPWM1_CLOCKS12)},
|
||||
{P1_5, PWM_16b_14, CY_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14, PCLK_TCPWM1_CLOCKS14)},
|
||||
{P2_1, PWM_16b_15, CY_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15, PCLK_TCPWM1_CLOCKS15)},
|
||||
{P2_3, PWM_16b_16, CY_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16, PCLK_TCPWM1_CLOCKS16)},
|
||||
{P2_5, PWM_16b_17, CY_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17, PCLK_TCPWM1_CLOCKS17)},
|
||||
{P2_7, PWM_16b_18, CY_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18, PCLK_TCPWM1_CLOCKS18)},
|
||||
{P3_1, PWM_16b_19, CY_PIN_OUT_FUNCTION(P3_1_TCPWM1_LINE_COMPL19, PCLK_TCPWM1_CLOCKS19)},
|
||||
{P3_3, PWM_16b_20, CY_PIN_OUT_FUNCTION(P3_3_TCPWM1_LINE_COMPL20, PCLK_TCPWM1_CLOCKS20)},
|
||||
{P3_5, PWM_16b_21, CY_PIN_OUT_FUNCTION(P3_5_TCPWM1_LINE_COMPL21, PCLK_TCPWM1_CLOCKS21)},
|
||||
{P4_1, PWM_16b_22, CY_PIN_OUT_FUNCTION(P4_1_TCPWM1_LINE_COMPL22, PCLK_TCPWM1_CLOCKS22)},
|
||||
{P5_1, PWM_16b_4, CY_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4, PCLK_TCPWM1_CLOCKS4)},
|
||||
{P5_3, PWM_16b_5, CY_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5, PCLK_TCPWM1_CLOCKS5)},
|
||||
{P5_5, PWM_16b_6, CY_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6, PCLK_TCPWM1_CLOCKS6)},
|
||||
{P5_7, PWM_16b_7, CY_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7, PCLK_TCPWM1_CLOCKS7)},
|
||||
{P6_1, PWM_16b_8, CY_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8, PCLK_TCPWM1_CLOCKS8)},
|
||||
{P6_3, PWM_16b_9, CY_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9, PCLK_TCPWM1_CLOCKS9)},
|
||||
{P6_5, PWM_16b_10, CY_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10, PCLK_TCPWM1_CLOCKS10)},
|
||||
{P6_7, PWM_16b_11, CY_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11, PCLK_TCPWM1_CLOCKS11)},
|
||||
{P7_1, PWM_16b_12, CY_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12, PCLK_TCPWM1_CLOCKS12)},
|
||||
{P7_3, PWM_16b_13, CY_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13, PCLK_TCPWM1_CLOCKS13)},
|
||||
{P7_5, PWM_16b_14, CY_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14, PCLK_TCPWM1_CLOCKS14)},
|
||||
{P7_7, PWM_16b_15, CY_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15, PCLK_TCPWM1_CLOCKS15)},
|
||||
{P8_1, PWM_16b_16, CY_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16, PCLK_TCPWM1_CLOCKS16)},
|
||||
{P8_3, PWM_16b_17, CY_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17, PCLK_TCPWM1_CLOCKS17)},
|
||||
{P8_5, PWM_16b_18, CY_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18, PCLK_TCPWM1_CLOCKS18)},
|
||||
{P8_7, PWM_16b_19, CY_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19, PCLK_TCPWM1_CLOCKS19)},
|
||||
{P9_1, PWM_16b_20, CY_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20, PCLK_TCPWM1_CLOCKS20)},
|
||||
{P9_3, PWM_16b_21, CY_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21, PCLK_TCPWM1_CLOCKS21)},
|
||||
{P9_5, PWM_16b_0, CY_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)},
|
||||
{P9_7, PWM_16b_1, CY_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)},
|
||||
{P10_1, PWM_16b_22, CY_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22, PCLK_TCPWM1_CLOCKS22)},
|
||||
{P10_3, PWM_16b_23, CY_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23, PCLK_TCPWM1_CLOCKS23)},
|
||||
{P10_5, PWM_16b_0, CY_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0, PCLK_TCPWM1_CLOCKS0)},
|
||||
{P10_7, PWM_16b_2, CY_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2, PCLK_TCPWM1_CLOCKS2)},
|
||||
{P11_1, PWM_16b_1, CY_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1, PCLK_TCPWM1_CLOCKS1)},
|
||||
{P11_3, PWM_16b_2, CY_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2, PCLK_TCPWM1_CLOCKS2)},
|
||||
{P11_5, PWM_16b_3, CY_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3, PCLK_TCPWM1_CLOCKS3)},
|
||||
{P12_1, PWM_16b_4, CY_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4, PCLK_TCPWM1_CLOCKS4)},
|
||||
{P12_3, PWM_16b_5, CY_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5, PCLK_TCPWM1_CLOCKS5)},
|
||||
{P12_5, PWM_16b_6, CY_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6, PCLK_TCPWM1_CLOCKS6)},
|
||||
{P12_7, PWM_16b_7, CY_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7, PCLK_TCPWM1_CLOCKS7)},
|
||||
{P13_1, PWM_16b_8, CY_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8, PCLK_TCPWM1_CLOCKS8)},
|
||||
{P13_3, PWM_16b_9, CY_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9, PCLK_TCPWM1_CLOCKS9)},
|
||||
{P13_5, PWM_16b_10, CY_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10, PCLK_TCPWM1_CLOCKS10)},
|
||||
{P13_7, PWM_16b_11, CY_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11, PCLK_TCPWM1_CLOCKS11)},
|
||||
// 32-bit PWM outputs
|
||||
{PWM32(P0_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P0_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P0_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
|
||||
{PWM32(P1_0), PWM_32b_3, CY_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
|
||||
{PWM32(P1_2), PWM_32b_4, CY_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
|
||||
{PWM32(P1_4), PWM_32b_5, CY_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
|
||||
{PWM32(P2_0), PWM_32b_6, CY_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
|
||||
{PWM32(P2_2), PWM_32b_7, CY_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
|
||||
{PWM32(P2_4), PWM_32b_0, CY_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P2_6), PWM_32b_1, CY_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P3_0), PWM_32b_2, CY_PIN_OUT_FUNCTION(P3_0_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
|
||||
{PWM32(P3_2), PWM_32b_3, CY_PIN_OUT_FUNCTION(P3_2_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
|
||||
{PWM32(P3_4), PWM_32b_4, CY_PIN_OUT_FUNCTION(P3_4_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
|
||||
{PWM32(P4_0), PWM_32b_5, CY_PIN_OUT_FUNCTION(P4_0_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
|
||||
{PWM32(P5_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
|
||||
{PWM32(P5_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
|
||||
{PWM32(P5_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
|
||||
{PWM32(P5_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
|
||||
{PWM32(P6_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P6_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P6_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
|
||||
{PWM32(P6_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
|
||||
{PWM32(P7_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
|
||||
{PWM32(P7_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
|
||||
{PWM32(P7_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
|
||||
{PWM32(P7_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
|
||||
{PWM32(P8_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P8_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P8_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
|
||||
{PWM32(P8_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
|
||||
{PWM32(P9_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
|
||||
{PWM32(P9_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
|
||||
{PWM32(P9_4), PWM_32b_7, CY_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
|
||||
{PWM32(P9_6), PWM_32b_0, CY_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P10_0), PWM_32b_6, CY_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
|
||||
{PWM32(P10_2), PWM_32b_7, CY_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
|
||||
{PWM32(P10_4), PWM_32b_0, CY_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P10_6), PWM_32b_1, CY_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P11_0), PWM_32b_1, CY_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P11_2), PWM_32b_2, CY_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
|
||||
{PWM32(P11_4), PWM_32b_3, CY_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
|
||||
{PWM32(P12_0), PWM_32b_4, CY_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4, PCLK_TCPWM0_CLOCKS4)},
|
||||
{PWM32(P12_2), PWM_32b_5, CY_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5, PCLK_TCPWM0_CLOCKS5)},
|
||||
{PWM32(P12_4), PWM_32b_6, CY_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6, PCLK_TCPWM0_CLOCKS6)},
|
||||
{PWM32(P12_6), PWM_32b_7, CY_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7, PCLK_TCPWM0_CLOCKS7)},
|
||||
{PWM32(P13_0), PWM_32b_0, CY_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P13_2), PWM_32b_1, CY_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P13_4), PWM_32b_2, CY_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2, PCLK_TCPWM0_CLOCKS2)},
|
||||
{PWM32(P13_6), PWM_32b_3, CY_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3, PCLK_TCPWM0_CLOCKS3)},
|
||||
// 32-bit PWM inverted outputs
|
||||
{PWM32(P0_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P0_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P0_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
|
||||
{PWM32(P1_1), PWM_32b_3, CY_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
|
||||
{PWM32(P1_3), PWM_32b_4, CY_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
|
||||
{PWM32(P1_5), PWM_32b_5, CY_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
|
||||
{PWM32(P2_1), PWM_32b_6, CY_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
|
||||
{PWM32(P2_3), PWM_32b_7, CY_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
|
||||
{PWM32(P2_5), PWM_32b_0, CY_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P2_7), PWM_32b_1, CY_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P3_1), PWM_32b_2, CY_PIN_OUT_FUNCTION(P3_1_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
|
||||
{PWM32(P3_3), PWM_32b_3, CY_PIN_OUT_FUNCTION(P3_3_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
|
||||
{PWM32(P3_5), PWM_32b_4, CY_PIN_OUT_FUNCTION(P3_5_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
|
||||
{PWM32(P4_1), PWM_32b_5, CY_PIN_OUT_FUNCTION(P4_1_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
|
||||
{PWM32(P5_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
|
||||
{PWM32(P5_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
|
||||
{PWM32(P5_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
|
||||
{PWM32(P5_7), PWM_32b_7, CY_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
|
||||
{PWM32(P6_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P6_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P6_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
|
||||
{PWM32(P6_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
|
||||
{PWM32(P7_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
|
||||
{PWM32(P7_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
|
||||
{PWM32(P7_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
|
||||
{PWM32(P7_7), PWM_32b_7, CY_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
|
||||
{PWM32(P8_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P8_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P8_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
|
||||
{PWM32(P8_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
|
||||
{PWM32(P9_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
|
||||
{PWM32(P9_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
|
||||
{PWM32(P9_5), PWM_32b_7, CY_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
|
||||
{PWM32(P9_7), PWM_32b_0, CY_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P10_1), PWM_32b_6, CY_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
|
||||
{PWM32(P10_3), PWM_32b_7, CY_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
|
||||
{PWM32(P10_5), PWM_32b_0, CY_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P10_7), PWM_32b_1, CY_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P11_1), PWM_32b_1, CY_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P11_3), PWM_32b_2, CY_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
|
||||
{PWM32(P11_5), PWM_32b_3, CY_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
|
||||
{PWM32(P12_1), PWM_32b_4, CY_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4, PCLK_TCPWM0_CLOCKS4)},
|
||||
{PWM32(P12_3), PWM_32b_5, CY_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5, PCLK_TCPWM0_CLOCKS5)},
|
||||
{PWM32(P12_5), PWM_32b_6, CY_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6, PCLK_TCPWM0_CLOCKS6)},
|
||||
{PWM32(P12_7), PWM_32b_7, CY_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7, PCLK_TCPWM0_CLOCKS7)},
|
||||
{PWM32(P13_1), PWM_32b_0, CY_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0, PCLK_TCPWM0_CLOCKS0)},
|
||||
{PWM32(P13_3), PWM_32b_1, CY_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1, PCLK_TCPWM0_CLOCKS1)},
|
||||
{PWM32(P13_5), PWM_32b_2, CY_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2, PCLK_TCPWM0_CLOCKS2)},
|
||||
{PWM32(P13_7), PWM_32b_3, CY_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3, PCLK_TCPWM0_CLOCKS3)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
#endif // DEVICE_PWMOUT
|
||||
|
||||
#if DEVICE_ANALOGIN
|
||||
const PinMap PinMap_ADC[] = {
|
||||
{P10_0, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_1, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_2, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_3, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_4, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_5, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_6, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_7, ADC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
#endif // DEVICE_ANALOGIN
|
||||
|
||||
#if DEVICE_ANALOGOUT
|
||||
const PinMap PinMap_DAC[] = {
|
||||
{P9_6, DAC_0, CY_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_CTDAC)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
#endif // DEVICE_ANALOGIN
|
||||
|
|
@ -1,696 +0,0 @@
|
|||
;/**************************************************************************//**
|
||||
; * @file startup_psoc6_01_cm4.s
|
||||
; * @brief CMSIS Core Device Startup File for
|
||||
; * ARMCM4 Device Series
|
||||
; * @version V5.00
|
||||
; * @date 02. March 2016
|
||||
; ******************************************************************************/
|
||||
;/*
|
||||
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; * not use this file except in compliance with the License.
|
||||
; * You may obtain a copy of the License at
|
||||
; *
|
||||
; * www.apache.org/licenses/LICENSE-2.0
|
||||
; *
|
||||
; * Unless required by applicable law or agreed to in writing, software
|
||||
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; * See the License for the specific language governing permissions and
|
||||
; * limitations under the License.
|
||||
; */
|
||||
|
||||
;/*
|
||||
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
|
||||
;*/
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
IF :DEF:__STACK_SIZE
|
||||
Stack_Size EQU __STACK_SIZE
|
||||
ELSE
|
||||
Stack_Size EQU 0x00000400
|
||||
ENDIF
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
IF :DEF:__HEAP_SIZE
|
||||
Heap_Size EQU __HEAP_SIZE
|
||||
ELSE
|
||||
Heap_Size EQU 0x00000400
|
||||
ENDIF
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD 0x0000000D ; NMI Handler located at ROM code
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External interrupts Power Mode Description
|
||||
DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0
|
||||
DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1
|
||||
DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2
|
||||
DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3
|
||||
DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4
|
||||
DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5
|
||||
DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6
|
||||
DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7
|
||||
DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8
|
||||
DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9
|
||||
DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10
|
||||
DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11
|
||||
DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12
|
||||
DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13
|
||||
DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14
|
||||
DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports
|
||||
DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt
|
||||
DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt
|
||||
DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable)
|
||||
DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
|
||||
DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
|
||||
DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
|
||||
DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
|
||||
DCD pass_interrupt_ctbs_IRQHandler ; CTBm Interrupt (all CTBms)
|
||||
DCD bless_interrupt_IRQHandler ; Bluetooth Radio interrupt
|
||||
DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0
|
||||
DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1
|
||||
DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2
|
||||
DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3
|
||||
DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4
|
||||
DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5
|
||||
DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6
|
||||
DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7
|
||||
DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8
|
||||
DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9
|
||||
DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10
|
||||
DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11
|
||||
DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12
|
||||
DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13
|
||||
DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14
|
||||
DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15
|
||||
DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0
|
||||
DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1
|
||||
DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2
|
||||
DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3
|
||||
DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4
|
||||
DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5
|
||||
DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6
|
||||
DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7
|
||||
DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
|
||||
DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
|
||||
DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
|
||||
DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
|
||||
DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3
|
||||
DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4
|
||||
DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5
|
||||
DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6
|
||||
DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7
|
||||
DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8
|
||||
DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9
|
||||
DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10
|
||||
DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11
|
||||
DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12
|
||||
DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13
|
||||
DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14
|
||||
DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15
|
||||
DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0
|
||||
DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1
|
||||
DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2
|
||||
DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3
|
||||
DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4
|
||||
DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5
|
||||
DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6
|
||||
DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7
|
||||
DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8
|
||||
DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9
|
||||
DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10
|
||||
DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11
|
||||
DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12
|
||||
DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13
|
||||
DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14
|
||||
DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15
|
||||
DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0
|
||||
DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1
|
||||
DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt
|
||||
DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt
|
||||
DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0
|
||||
DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1
|
||||
DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0
|
||||
DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1
|
||||
DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
|
||||
DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
|
||||
DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
|
||||
DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
|
||||
DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
|
||||
DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
|
||||
DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
|
||||
DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
|
||||
DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
|
||||
DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
|
||||
DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2
|
||||
DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3
|
||||
DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4
|
||||
DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5
|
||||
DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6
|
||||
DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7
|
||||
DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8
|
||||
DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9
|
||||
DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10
|
||||
DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11
|
||||
DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12
|
||||
DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13
|
||||
DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14
|
||||
DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15
|
||||
DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16
|
||||
DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17
|
||||
DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18
|
||||
DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19
|
||||
DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20
|
||||
DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21
|
||||
DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22
|
||||
DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23
|
||||
DCD udb_interrupts_0_IRQHandler ; UDB Interrupt #0
|
||||
DCD udb_interrupts_1_IRQHandler ; UDB Interrupt #1
|
||||
DCD udb_interrupts_2_IRQHandler ; UDB Interrupt #2
|
||||
DCD udb_interrupts_3_IRQHandler ; UDB Interrupt #3
|
||||
DCD udb_interrupts_4_IRQHandler ; UDB Interrupt #4
|
||||
DCD udb_interrupts_5_IRQHandler ; UDB Interrupt #5
|
||||
DCD udb_interrupts_6_IRQHandler ; UDB Interrupt #6
|
||||
DCD udb_interrupts_7_IRQHandler ; UDB Interrupt #7
|
||||
DCD udb_interrupts_8_IRQHandler ; UDB Interrupt #8
|
||||
DCD udb_interrupts_9_IRQHandler ; UDB Interrupt #9
|
||||
DCD udb_interrupts_10_IRQHandler ; UDB Interrupt #10
|
||||
DCD udb_interrupts_11_IRQHandler ; UDB Interrupt #11
|
||||
DCD udb_interrupts_12_IRQHandler ; UDB Interrupt #12
|
||||
DCD udb_interrupts_13_IRQHandler ; UDB Interrupt #13
|
||||
DCD udb_interrupts_14_IRQHandler ; UDB Interrupt #14
|
||||
DCD udb_interrupts_15_IRQHandler ; UDB Interrupt #15
|
||||
DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
|
||||
DCD audioss_interrupt_i2s_IRQHandler ; I2S Audio interrupt
|
||||
DCD audioss_interrupt_pdm_IRQHandler ; PDM/PCM Audio interrupt
|
||||
DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
|
||||
DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
|
||||
DCD usb_interrupt_hi_IRQHandler ; USB Interrupt
|
||||
DCD usb_interrupt_med_IRQHandler ; USB Interrupt
|
||||
DCD usb_interrupt_lo_IRQHandler ; USB Interrupt
|
||||
DCD pass_interrupt_dacs_IRQHandler ; Consolidated interrrupt for all DACs
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
EXPORT __ramVectors
|
||||
AREA RESET_RAM, READWRITE, NOINIT
|
||||
__ramVectors SPACE __Vectors_Size
|
||||
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Weak function for startup customization
|
||||
;
|
||||
; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
|
||||
; because this function is executed as the first instruction in the ResetHandler.
|
||||
; The PDL is also not initialized to use the proper register offsets.
|
||||
; The user of this function is responsible for initializing the PDL and resources before using them.
|
||||
;
|
||||
Cy_OnResetUser PROC
|
||||
EXPORT Cy_OnResetUser [WEAK]
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
|
||||
; Reset Handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT Cy_SystemInitFpuEnable
|
||||
IMPORT __main
|
||||
|
||||
; Define strong function for startup customization
|
||||
BL Cy_OnResetUser
|
||||
|
||||
; Disable global interrupts
|
||||
CPSID I
|
||||
|
||||
; Copy vectors from ROM to RAM
|
||||
LDR r1, =__Vectors
|
||||
LDR r0, =__ramVectors
|
||||
LDR r2, =__Vectors_Size
|
||||
Vectors_Copy
|
||||
LDR r3, [r1]
|
||||
STR r3, [r0]
|
||||
ADDS r0, r0, #4
|
||||
ADDS r1, r1, #4
|
||||
SUBS r2, r2, #1
|
||||
CMP r2, #0
|
||||
BNE Vectors_Copy
|
||||
|
||||
; Update Vector Table Offset Register. */
|
||||
LDR r0, =__ramVectors
|
||||
LDR r1, =0xE000ED08
|
||||
STR r0, [r1]
|
||||
dsb 0xF
|
||||
|
||||
; Enable the FPU if used
|
||||
LDR R0, =Cy_SystemInitFpuEnable
|
||||
BLX R0
|
||||
|
||||
LDR R0, =__main
|
||||
BLX R0
|
||||
|
||||
; Should never get here
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Cy_SysLib_FaultHandler PROC
|
||||
EXPORT Cy_SysLib_FaultHandler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Wrapper\
|
||||
PROC
|
||||
EXPORT HardFault_Wrapper [WEAK]
|
||||
movs r0, #4
|
||||
mov r1, LR
|
||||
tst r0, r1
|
||||
beq L_MSP
|
||||
mrs r0, PSP
|
||||
bl L_API_call
|
||||
L_MSP
|
||||
mrs r0, MSP
|
||||
L_API_call
|
||||
bl Cy_SysLib_FaultHandler
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B HardFault_Wrapper
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B HardFault_Wrapper
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B HardFault_Wrapper
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B HardFault_Wrapper
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT Default_Handler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupt_gpio_IRQHandler [WEAK]
|
||||
EXPORT ioss_interrupt_vdd_IRQHandler [WEAK]
|
||||
EXPORT lpcomp_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_8_interrupt_IRQHandler [WEAK]
|
||||
EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK]
|
||||
EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK]
|
||||
EXPORT srss_interrupt_backup_IRQHandler [WEAK]
|
||||
EXPORT srss_interrupt_IRQHandler [WEAK]
|
||||
EXPORT pass_interrupt_ctbs_IRQHandler [WEAK]
|
||||
EXPORT bless_interrupt_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK]
|
||||
EXPORT scb_0_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_1_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_2_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_3_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_4_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_5_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_6_interrupt_IRQHandler [WEAK]
|
||||
EXPORT scb_7_interrupt_IRQHandler [WEAK]
|
||||
EXPORT csd_interrupt_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupt_fm_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK]
|
||||
EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK]
|
||||
EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_0_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_1_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_2_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_3_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_4_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_5_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_6_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_7_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_8_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_9_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_10_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_11_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_12_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_13_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_14_IRQHandler [WEAK]
|
||||
EXPORT udb_interrupts_15_IRQHandler [WEAK]
|
||||
EXPORT pass_interrupt_sar_IRQHandler [WEAK]
|
||||
EXPORT audioss_interrupt_i2s_IRQHandler [WEAK]
|
||||
EXPORT audioss_interrupt_pdm_IRQHandler [WEAK]
|
||||
EXPORT profile_interrupt_IRQHandler [WEAK]
|
||||
EXPORT smif_interrupt_IRQHandler [WEAK]
|
||||
EXPORT usb_interrupt_hi_IRQHandler [WEAK]
|
||||
EXPORT usb_interrupt_med_IRQHandler [WEAK]
|
||||
EXPORT usb_interrupt_lo_IRQHandler [WEAK]
|
||||
EXPORT pass_interrupt_dacs_IRQHandler [WEAK]
|
||||
|
||||
ioss_interrupts_gpio_0_IRQHandler
|
||||
ioss_interrupts_gpio_1_IRQHandler
|
||||
ioss_interrupts_gpio_2_IRQHandler
|
||||
ioss_interrupts_gpio_3_IRQHandler
|
||||
ioss_interrupts_gpio_4_IRQHandler
|
||||
ioss_interrupts_gpio_5_IRQHandler
|
||||
ioss_interrupts_gpio_6_IRQHandler
|
||||
ioss_interrupts_gpio_7_IRQHandler
|
||||
ioss_interrupts_gpio_8_IRQHandler
|
||||
ioss_interrupts_gpio_9_IRQHandler
|
||||
ioss_interrupts_gpio_10_IRQHandler
|
||||
ioss_interrupts_gpio_11_IRQHandler
|
||||
ioss_interrupts_gpio_12_IRQHandler
|
||||
ioss_interrupts_gpio_13_IRQHandler
|
||||
ioss_interrupts_gpio_14_IRQHandler
|
||||
ioss_interrupt_gpio_IRQHandler
|
||||
ioss_interrupt_vdd_IRQHandler
|
||||
lpcomp_interrupt_IRQHandler
|
||||
scb_8_interrupt_IRQHandler
|
||||
srss_interrupt_mcwdt_0_IRQHandler
|
||||
srss_interrupt_mcwdt_1_IRQHandler
|
||||
srss_interrupt_backup_IRQHandler
|
||||
srss_interrupt_IRQHandler
|
||||
pass_interrupt_ctbs_IRQHandler
|
||||
bless_interrupt_IRQHandler
|
||||
cpuss_interrupts_ipc_0_IRQHandler
|
||||
cpuss_interrupts_ipc_1_IRQHandler
|
||||
cpuss_interrupts_ipc_2_IRQHandler
|
||||
cpuss_interrupts_ipc_3_IRQHandler
|
||||
cpuss_interrupts_ipc_4_IRQHandler
|
||||
cpuss_interrupts_ipc_5_IRQHandler
|
||||
cpuss_interrupts_ipc_6_IRQHandler
|
||||
cpuss_interrupts_ipc_7_IRQHandler
|
||||
cpuss_interrupts_ipc_8_IRQHandler
|
||||
cpuss_interrupts_ipc_9_IRQHandler
|
||||
cpuss_interrupts_ipc_10_IRQHandler
|
||||
cpuss_interrupts_ipc_11_IRQHandler
|
||||
cpuss_interrupts_ipc_12_IRQHandler
|
||||
cpuss_interrupts_ipc_13_IRQHandler
|
||||
cpuss_interrupts_ipc_14_IRQHandler
|
||||
cpuss_interrupts_ipc_15_IRQHandler
|
||||
scb_0_interrupt_IRQHandler
|
||||
scb_1_interrupt_IRQHandler
|
||||
scb_2_interrupt_IRQHandler
|
||||
scb_3_interrupt_IRQHandler
|
||||
scb_4_interrupt_IRQHandler
|
||||
scb_5_interrupt_IRQHandler
|
||||
scb_6_interrupt_IRQHandler
|
||||
scb_7_interrupt_IRQHandler
|
||||
csd_interrupt_IRQHandler
|
||||
cpuss_interrupts_dw0_0_IRQHandler
|
||||
cpuss_interrupts_dw0_1_IRQHandler
|
||||
cpuss_interrupts_dw0_2_IRQHandler
|
||||
cpuss_interrupts_dw0_3_IRQHandler
|
||||
cpuss_interrupts_dw0_4_IRQHandler
|
||||
cpuss_interrupts_dw0_5_IRQHandler
|
||||
cpuss_interrupts_dw0_6_IRQHandler
|
||||
cpuss_interrupts_dw0_7_IRQHandler
|
||||
cpuss_interrupts_dw0_8_IRQHandler
|
||||
cpuss_interrupts_dw0_9_IRQHandler
|
||||
cpuss_interrupts_dw0_10_IRQHandler
|
||||
cpuss_interrupts_dw0_11_IRQHandler
|
||||
cpuss_interrupts_dw0_12_IRQHandler
|
||||
cpuss_interrupts_dw0_13_IRQHandler
|
||||
cpuss_interrupts_dw0_14_IRQHandler
|
||||
cpuss_interrupts_dw0_15_IRQHandler
|
||||
cpuss_interrupts_dw1_0_IRQHandler
|
||||
cpuss_interrupts_dw1_1_IRQHandler
|
||||
cpuss_interrupts_dw1_2_IRQHandler
|
||||
cpuss_interrupts_dw1_3_IRQHandler
|
||||
cpuss_interrupts_dw1_4_IRQHandler
|
||||
cpuss_interrupts_dw1_5_IRQHandler
|
||||
cpuss_interrupts_dw1_6_IRQHandler
|
||||
cpuss_interrupts_dw1_7_IRQHandler
|
||||
cpuss_interrupts_dw1_8_IRQHandler
|
||||
cpuss_interrupts_dw1_9_IRQHandler
|
||||
cpuss_interrupts_dw1_10_IRQHandler
|
||||
cpuss_interrupts_dw1_11_IRQHandler
|
||||
cpuss_interrupts_dw1_12_IRQHandler
|
||||
cpuss_interrupts_dw1_13_IRQHandler
|
||||
cpuss_interrupts_dw1_14_IRQHandler
|
||||
cpuss_interrupts_dw1_15_IRQHandler
|
||||
cpuss_interrupts_fault_0_IRQHandler
|
||||
cpuss_interrupts_fault_1_IRQHandler
|
||||
cpuss_interrupt_crypto_IRQHandler
|
||||
cpuss_interrupt_fm_IRQHandler
|
||||
cpuss_interrupts_cm0_cti_0_IRQHandler
|
||||
cpuss_interrupts_cm0_cti_1_IRQHandler
|
||||
cpuss_interrupts_cm4_cti_0_IRQHandler
|
||||
cpuss_interrupts_cm4_cti_1_IRQHandler
|
||||
tcpwm_0_interrupts_0_IRQHandler
|
||||
tcpwm_0_interrupts_1_IRQHandler
|
||||
tcpwm_0_interrupts_2_IRQHandler
|
||||
tcpwm_0_interrupts_3_IRQHandler
|
||||
tcpwm_0_interrupts_4_IRQHandler
|
||||
tcpwm_0_interrupts_5_IRQHandler
|
||||
tcpwm_0_interrupts_6_IRQHandler
|
||||
tcpwm_0_interrupts_7_IRQHandler
|
||||
tcpwm_1_interrupts_0_IRQHandler
|
||||
tcpwm_1_interrupts_1_IRQHandler
|
||||
tcpwm_1_interrupts_2_IRQHandler
|
||||
tcpwm_1_interrupts_3_IRQHandler
|
||||
tcpwm_1_interrupts_4_IRQHandler
|
||||
tcpwm_1_interrupts_5_IRQHandler
|
||||
tcpwm_1_interrupts_6_IRQHandler
|
||||
tcpwm_1_interrupts_7_IRQHandler
|
||||
tcpwm_1_interrupts_8_IRQHandler
|
||||
tcpwm_1_interrupts_9_IRQHandler
|
||||
tcpwm_1_interrupts_10_IRQHandler
|
||||
tcpwm_1_interrupts_11_IRQHandler
|
||||
tcpwm_1_interrupts_12_IRQHandler
|
||||
tcpwm_1_interrupts_13_IRQHandler
|
||||
tcpwm_1_interrupts_14_IRQHandler
|
||||
tcpwm_1_interrupts_15_IRQHandler
|
||||
tcpwm_1_interrupts_16_IRQHandler
|
||||
tcpwm_1_interrupts_17_IRQHandler
|
||||
tcpwm_1_interrupts_18_IRQHandler
|
||||
tcpwm_1_interrupts_19_IRQHandler
|
||||
tcpwm_1_interrupts_20_IRQHandler
|
||||
tcpwm_1_interrupts_21_IRQHandler
|
||||
tcpwm_1_interrupts_22_IRQHandler
|
||||
tcpwm_1_interrupts_23_IRQHandler
|
||||
udb_interrupts_0_IRQHandler
|
||||
udb_interrupts_1_IRQHandler
|
||||
udb_interrupts_2_IRQHandler
|
||||
udb_interrupts_3_IRQHandler
|
||||
udb_interrupts_4_IRQHandler
|
||||
udb_interrupts_5_IRQHandler
|
||||
udb_interrupts_6_IRQHandler
|
||||
udb_interrupts_7_IRQHandler
|
||||
udb_interrupts_8_IRQHandler
|
||||
udb_interrupts_9_IRQHandler
|
||||
udb_interrupts_10_IRQHandler
|
||||
udb_interrupts_11_IRQHandler
|
||||
udb_interrupts_12_IRQHandler
|
||||
udb_interrupts_13_IRQHandler
|
||||
udb_interrupts_14_IRQHandler
|
||||
udb_interrupts_15_IRQHandler
|
||||
pass_interrupt_sar_IRQHandler
|
||||
audioss_interrupt_i2s_IRQHandler
|
||||
audioss_interrupt_pdm_IRQHandler
|
||||
profile_interrupt_IRQHandler
|
||||
smif_interrupt_IRQHandler
|
||||
usb_interrupt_hi_IRQHandler
|
||||
usb_interrupt_med_IRQHandler
|
||||
usb_interrupt_lo_IRQHandler
|
||||
pass_interrupt_dacs_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
|
||||
; [] END OF FILE
|
||||
|
|
@ -1,631 +0,0 @@
|
|||
/**************************************************************************//**
|
||||
* @file startup_psoc6_01_cm4.S
|
||||
* @brief CMSIS Core Device Startup File for
|
||||
* ARMCM4 Device Series
|
||||
* @version V5.00
|
||||
* @date 02. March 2016
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/* Address of the NMI handler */
|
||||
#define CY_NMI_HANLDER_ADDR 0x0000000D
|
||||
|
||||
/* The CPU VTOR register */
|
||||
#define CY_CPU_VTOR_ADDR 0xE000ED08
|
||||
|
||||
/* Copy flash vectors and data section to RAM */
|
||||
#define __STARTUP_COPY_MULTIPLE
|
||||
|
||||
/* Clear single BSS section */
|
||||
#define __STARTUP_CLEAR_BSS
|
||||
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0x00001000
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0x00000400
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .vectors
|
||||
.align 2
|
||||
.globl __Vectors
|
||||
__Vectors:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long CY_NMI_HANLDER_ADDR /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts Description */
|
||||
.long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
|
||||
.long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
|
||||
.long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
|
||||
.long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
|
||||
.long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
|
||||
.long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
|
||||
.long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
|
||||
.long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
|
||||
.long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
|
||||
.long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
|
||||
.long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
|
||||
.long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
|
||||
.long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
|
||||
.long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
|
||||
.long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
|
||||
.long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
|
||||
.long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
|
||||
.long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
|
||||
.long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
|
||||
.long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
|
||||
.long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
|
||||
.long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
|
||||
.long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
.long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
|
||||
.long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
|
||||
.long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
|
||||
.long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
|
||||
.long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
|
||||
.long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
|
||||
.long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
|
||||
.long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
|
||||
.long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
|
||||
.long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
|
||||
.long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
|
||||
.long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
|
||||
.long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
|
||||
.long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
|
||||
.long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
|
||||
.long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
|
||||
.long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
|
||||
.long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
|
||||
.long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
|
||||
.long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
|
||||
.long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
|
||||
.long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
|
||||
.long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
|
||||
.long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
|
||||
.long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
|
||||
.long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
|
||||
.long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
|
||||
.long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
|
||||
.long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
|
||||
.long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
|
||||
.long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
|
||||
.long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
|
||||
.long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
|
||||
.long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
|
||||
.long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
|
||||
.long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
|
||||
.long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
|
||||
.long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
|
||||
.long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
|
||||
.long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
|
||||
.long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
|
||||
.long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
|
||||
.long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
|
||||
.long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
|
||||
.long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
|
||||
.long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
|
||||
.long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
|
||||
.long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
|
||||
.long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
|
||||
.long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
|
||||
.long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
|
||||
.long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
|
||||
.long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
|
||||
.long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
|
||||
.long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
|
||||
.long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
|
||||
.long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
|
||||
.long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
|
||||
.long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
|
||||
.long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
|
||||
.long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
|
||||
.long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
|
||||
.long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
|
||||
.long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
|
||||
.long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
|
||||
.long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
|
||||
.long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
|
||||
.long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
|
||||
.long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
|
||||
.long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
|
||||
.long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
|
||||
.long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
|
||||
.long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
|
||||
.long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
|
||||
.long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
|
||||
.long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
|
||||
.long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
|
||||
.long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
|
||||
.long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
|
||||
.long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
|
||||
.long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
|
||||
.long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
|
||||
.long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
|
||||
.long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
|
||||
.long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
|
||||
.long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
|
||||
.long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
|
||||
.long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
|
||||
.long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
|
||||
.long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
|
||||
.long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
|
||||
.long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
|
||||
.long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
|
||||
.long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
|
||||
.long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
|
||||
.long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
|
||||
.long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
|
||||
.long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
|
||||
.long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
|
||||
.long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
|
||||
.long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
|
||||
.long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
|
||||
.long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
|
||||
.long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
|
||||
.long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
|
||||
.long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
|
||||
.long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
|
||||
.long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
|
||||
.long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
|
||||
.long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
|
||||
.long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
|
||||
.long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
|
||||
.long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
|
||||
.long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
|
||||
.long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
|
||||
.long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
|
||||
.long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
|
||||
.long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
|
||||
.long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
|
||||
.long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
|
||||
.long usb_interrupt_hi_IRQHandler /* USB Interrupt */
|
||||
.long usb_interrupt_med_IRQHandler /* USB Interrupt */
|
||||
.long usb_interrupt_lo_IRQHandler /* USB Interrupt */
|
||||
.long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
|
||||
|
||||
|
||||
.size __Vectors, . - __Vectors
|
||||
.equ __VectorsSize, . - __Vectors
|
||||
|
||||
.section .ram_vectors
|
||||
.align 2
|
||||
.globl __ramVectors
|
||||
__ramVectors:
|
||||
.space __VectorsSize
|
||||
.size __ramVectors, . - __ramVectors
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
|
||||
/*
|
||||
* Device startup customization
|
||||
*
|
||||
* Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
|
||||
* because this function is executed as the first instruction in the ResetHandler.
|
||||
* The PDL is also not initialized to use the proper register offsets.
|
||||
* The user of this function is responsible for initializing the PDL and resources before using them.
|
||||
*/
|
||||
.weak Cy_OnResetUser
|
||||
.func Cy_OnResetUser, Cy_OnResetUser
|
||||
.type Cy_OnResetUser, %function
|
||||
|
||||
Cy_OnResetUser:
|
||||
bx lr
|
||||
.size Cy_OnResetUser, . - Cy_OnResetUser
|
||||
.endfunc
|
||||
|
||||
/* Reset handler */
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
|
||||
Reset_Handler:
|
||||
bl Cy_OnResetUser
|
||||
cpsid i
|
||||
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
ittt ge
|
||||
ldrge r0, [r1, r3]
|
||||
strge r0, [r2, r3]
|
||||
bge .L_loop0_0
|
||||
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
.L_loop1:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .L_loop1
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
itt ge
|
||||
strge r0, [r1, r2]
|
||||
bge .L_loop2_0
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.L_loop3:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .L_loop3
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
/* Update Vector Table Offset Register. */
|
||||
ldr r0, =__ramVectors
|
||||
ldr r1, =CY_CPU_VTOR_ADDR
|
||||
str r0, [r1]
|
||||
dsb 0xF
|
||||
|
||||
/* Enable the FPU if used */
|
||||
bl Cy_SystemInitFpuEnable
|
||||
|
||||
bl _start
|
||||
|
||||
/* Should never get here */
|
||||
b .
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
|
||||
.weak Cy_SysLib_FaultHandler
|
||||
.type Cy_SysLib_FaultHandler, %function
|
||||
|
||||
Cy_SysLib_FaultHandler:
|
||||
b .
|
||||
.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
|
||||
.type Fault_Handler, %function
|
||||
|
||||
Fault_Handler:
|
||||
/* Storing LR content for Creator call stack trace */
|
||||
push {LR}
|
||||
movs r0, #4
|
||||
mov r1, LR
|
||||
tst r0, r1
|
||||
beq .L_MSP
|
||||
mrs r0, PSP
|
||||
b .L_API_call
|
||||
.L_MSP:
|
||||
mrs r0, MSP
|
||||
.L_API_call:
|
||||
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
|
||||
adds r0, r0, #4
|
||||
bl Cy_SysLib_FaultHandler
|
||||
b .
|
||||
.size Fault_Handler, . - Fault_Handler
|
||||
|
||||
.macro def_fault_Handler fault_handler_name
|
||||
.weak \fault_handler_name
|
||||
.set \fault_handler_name, Fault_Handler
|
||||
.endm
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
|
||||
def_fault_Handler HardFault_Handler
|
||||
def_fault_Handler MemManage_Handler
|
||||
def_fault_Handler BusFault_Handler
|
||||
def_fault_Handler UsageFault_Handler
|
||||
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
|
||||
def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
|
||||
def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
|
||||
def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
|
||||
def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
|
||||
def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
|
||||
def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
|
||||
def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
|
||||
def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
|
||||
def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
|
||||
def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
|
||||
def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
|
||||
def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
|
||||
def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
|
||||
def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
|
||||
def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
|
||||
def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
|
||||
def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
|
||||
def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
|
||||
def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
|
||||
def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
|
||||
def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
|
||||
def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
|
||||
def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
|
||||
def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
|
||||
def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
|
||||
def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
|
||||
def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
|
||||
def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
|
||||
def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
|
||||
def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
|
||||
def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
|
||||
def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
|
||||
def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
|
||||
def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
|
||||
def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
|
||||
def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
|
||||
def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
|
||||
def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
|
||||
def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
|
||||
def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
|
||||
def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
|
||||
def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
|
||||
def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
|
||||
def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
|
||||
def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
|
||||
def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
|
||||
def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
|
||||
def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
|
||||
def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
|
||||
def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
|
||||
def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
|
||||
def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
|
||||
def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
|
||||
def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
|
||||
def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
|
||||
def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
|
||||
def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
|
||||
def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
|
||||
def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
|
||||
def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
|
||||
def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
|
||||
def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
|
||||
def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
|
||||
def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
|
||||
def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
|
||||
def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
|
||||
def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
|
||||
def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
|
||||
def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
|
||||
def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
|
||||
def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
|
||||
def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
|
||||
def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
|
||||
def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
|
||||
def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
|
||||
def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
|
||||
def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
|
||||
def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
|
||||
def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
|
||||
def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
|
||||
def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
|
||||
def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
|
||||
def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
|
||||
def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
|
||||
def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
|
||||
def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
|
||||
def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
|
||||
def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
|
||||
def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
|
||||
def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
|
||||
def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
|
||||
def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
|
||||
def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
|
||||
def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
|
||||
def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
|
||||
def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
|
||||
def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
|
||||
def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
|
||||
def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
|
||||
def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
|
||||
def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
|
||||
def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
|
||||
def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
|
||||
def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
|
||||
def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
|
||||
def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
|
||||
def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
|
||||
def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
|
||||
def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
|
||||
def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
|
||||
def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
|
||||
def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
|
||||
def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
|
||||
def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
|
||||
def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
|
||||
def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
|
||||
def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
|
||||
def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
|
||||
def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
|
||||
def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
|
||||
def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
|
||||
def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
|
||||
def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
|
||||
def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
|
||||
def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
|
||||
def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
|
||||
def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
|
||||
def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
|
||||
def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
|
||||
def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
|
||||
def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
|
||||
def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
|
||||
def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
|
||||
def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
|
||||
def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
|
||||
def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
|
||||
def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
|
||||
def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
|
||||
def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
|
||||
def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
|
||||
def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
|
||||
def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
|
||||
def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
|
||||
def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
|
||||
def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
|
||||
def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
|
||||
|
||||
.end
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,18 +0,0 @@
|
|||
README for pre-compiled PSoC 6 Cortex M0+ core images
|
||||
=====================================================
|
||||
|
||||
This folder contains precompiled program images for the CM0+ core of the
|
||||
PSoC 6 MCU suitable for use with Mbed OS applications running on CM4 core.
|
||||
|
||||
* `psoc6_01_cm0p_sleep.hex`
|
||||
|
||||
This image starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10080000
|
||||
and puts CM0+ core into a deep sleep.
|
||||
|
||||
The images are 'bare metal' code prepared with Cypress ModusToolbox IDE
|
||||
and are toolchain agnostic, i.e. can be used with CM4 Mbed applications
|
||||
build with any supported toolchain.
|
||||
|
||||
**These images were prepared by Cypress Semiconductor Corporation
|
||||
and are made available under the conditions of Permissive Binary Licence,
|
||||
see file LICENSE.txt**
|
||||
|
|
@ -1,106 +0,0 @@
|
|||
:020000041000EA
|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
:40120000F8BC08BC9E467047F8B5C046F8BC08BC9E4670470000000001B40248844601BC604700BFA9020008030000000100000001000000000000000503600004000000C5
|
||||
:401240000100000000000000010000000604600008000000F8060008890100100000214000002540000001400000344000002440000031400000324000001F4100002340D5
|
||||
:4012800000001140010101010101010101101010800019005500F0000501053B04101C01010000000FC000000004000001010101011D3A5778960008200010120800000068
|
||||
:4012C000001F00000010000F002000023F06080E00080009000A000B24282C3034000000100000009000000088000000080000008000000004F0000000F00000400200005B
|
||||
:401300002005A000D00100018001A0012000000010000000433A2F55736572732F766D65642F4D6F647573546F6F6C626F785F312E312F6C69627261726965732F70736FB1
|
||||
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|
||||
:4013800072732F766D65642F4D6F647573546F6F6C626F785F312E312F6C69627261726965732F70736F633673772D312E312F636F6D706F6E656E74732F70736F633670B4
|
||||
:4013C000646C2F647269766572732F736F757263652F63795F6970635F6472762E6300433A2F55736572732F766D65642F4D6F647573546F6F6C626F785F312E312F6C69A3
|
||||
:40140000627261726965732F70736F633673772D312E312F636F6D706F6E656E74732F70736F633670646C2F647269766572732F736F757263652F63795F6970635F706968
|
||||
:4014400070652E6300433A2F55736572732F766D65642F4D6F647573546F6F6C626F785F312E312F6C69627261726965732F70736F633673772D312E312F636F6D706F6EF8
|
||||
:40148000656E74732F70736F633670646C2F647269766572732F736F757263652F63795F737973696E742E6300433A2F55736572732F766D65642F4D6F647573546F6F6C17
|
||||
:4014C000626F785F312E312F6C69627261726965732F70736F633673772D312E312F636F6D706F6E656E74732F70736F633670646C2F647269766572732F736F757263654A
|
||||
:401500002F63795F737973706D2E6300000000000000001000000008C000000030150010C0000008700400006C0500081002000000093D000048E80100127A0000093D0037
|
||||
:401540000000D00700093D00A00F000004000000E9000010C100001080B230B5C00020D0104B07221C682300B0331B885A43236AD31819680029FCDA3E210B4B062519606B
|
||||
:401580000A4B0B491960A3210A4BC9005D500A4958505858206A1218002050605A58002AFCDA30BD7807000804012640080126401E1F0000000026401C05000010B5437807
|
||||
:4015C000FF2B11D100F0CCF90400042000F0A8F9C3685A68012311681943116011681942FCD1200000F0C4F910BDF7B500900020019100F095F93F4D06002B681A005033B1
|
||||
:40160000B43214681B780419002B5AD000F090F9070003281BD000F0A3F9374A374B0500D358002B3EDA364A0121300000F0A8F9002837D10198FFF78FFF009B002B3ED027
|
||||
:401640002368002BFCDB00F07BF904002BE0062000F066F92B68B4331B68C0180368002B02DA284C2000FEBD002000F091F9264B9842F6D00023254A19001268012000F07E
|
||||
:4016800047F90025A842ECD1002000F081F91E4A1F4B904203D09D42E3D00135F4E79D42B9D1DEE7174C032F05D10121002000F04FF90028F9D1280000F05AF9D2E7154CF0
|
||||
:4016C000F1E700F04DF90E4A05000121300000F057F9002809D1009B002B08D02368002BFCDB00F02DF90400E5E7064CE3E7094CE1E7C04678070008000026401C0500008D
|
||||
:4017000018070008050052000101880028070008F049020001005000F7B56E4D04002A68536800931300B033198807234B43126A9B181A68002AFCDA00F0E2F82A68130024
|
||||
:40174000B033198807234B43212800D096E0116A5B180221D8680143D960D968C9072FD508208446944460461600D968C06F01911168883608183568076849190D683902BE
|
||||
:40178000FF273F040F40694689882D0A2D0639432943D960902103684F4D09012B400B430360136830681B18186805402943196013686246D26F9A18126832689B181B68F8
|
||||
:4017C000444D2A681300B033198807234B43126A9B1800225A600423404A11690B431361012C50D030BF2A681300B033198807234B43126A9B181A68002AFCDA00F080F849
|
||||
:40180000212842D1296807220B000124B0331B8800205A430B6AD318DD6825421CD0080008300D68C06F2C4E28180568DB6835401B0C1B061B0C2B4303600B0088331868DE
|
||||
:401840000B6818180B6A0568D318DB682E401B0E1B023343036020000B6A0221D218D3688B43D3601B4B1A681300B033198807234B43126A9B1800225A60FEBD126A9B181E
|
||||
:40188000174ADA609CE720BFADE70020009BFC331B698342E6D1A320124B1349134A144FC0000E681D5814680F6006271F503E20106010483E371F501F58002FFCDA009821
|
||||
:4018C0000D4FFC3007610E60A321C9005D5001201460C7E778070008FF00FFFF00ED00E0580700080000264008012640040126401E1F00001C050000AAAAAAAA000000000F
|
||||
:4019000001B40248844601BC604700BF6D0D001001B40248844601BC604700BF5D08001001B40248844601BC604700BF7105001001B40248844601BC604700BFE903001076
|
||||
:4019400001B40248844601BC604700BFA505001001B40248844601BC604700BF190B001001B40248844601BC604700BFAB04001001B40248844601BC604700BFB304001043
|
||||
:4019800001B40248844601BC604700BF7906001001B40248844601BC604700BF8D0B0010000000000000000000000000000000000000000000000000000000000000000018
|
||||
:4019C00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000E7
|
||||
:00000001FF
|
||||
|
|
@ -1,669 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file system_psoc6.h
|
||||
* \version 2.30
|
||||
*
|
||||
* \brief Device system header file.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifndef _SYSTEM_PSOC6_H_
|
||||
#define _SYSTEM_PSOC6_H_
|
||||
|
||||
/**
|
||||
* \addtogroup group_system_config
|
||||
* \{
|
||||
* Provides device startup, system configuration, and linker script files.
|
||||
* The system startup provides the followings features:
|
||||
* - See \ref group_system_config_device_initialization for the:
|
||||
* * \ref group_system_config_dual_core_device_initialization
|
||||
* * \ref group_system_config_single_core_device_initialization
|
||||
* - \ref group_system_config_device_memory_definition
|
||||
* - \ref group_system_config_heap_stack_config
|
||||
* - \ref group_system_config_merge_apps
|
||||
* - \ref group_system_config_default_handlers
|
||||
* - \ref group_system_config_device_vector_table
|
||||
* - \ref group_system_config_cm4_functions
|
||||
*
|
||||
* \section group_system_config_configuration Configuration Considerations
|
||||
*
|
||||
* \subsection group_system_config_device_memory_definition Device Memory Definition
|
||||
* The flash and RAM allocation for each CPU is defined by the linker scripts.
|
||||
* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
|
||||
* 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
|
||||
* For Single-Core devices the system reserves additional 80 bytes of RAM.
|
||||
* Using the reserved memory area for other purposes will lead to unexpected behavior.
|
||||
*
|
||||
* \note The linker files provided with the PDL are generic and handle all common
|
||||
* use cases. Your project may not use every section defined in the linker files.
|
||||
* In that case you may see warnings during the build process. To eliminate build
|
||||
* warnings in your project, you can simply comment out or remove the relevant
|
||||
* code in the linker file.
|
||||
*
|
||||
* <b>ARM GCC</b>\n
|
||||
* The flash and RAM sections for the CPU are defined in the linker files:
|
||||
* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
|
||||
* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
|
||||
* \note If the start of the Cortex-M4 application image is changed, the value
|
||||
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
|
||||
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
|
||||
* Cy_SysEnableCM4() function call.
|
||||
*
|
||||
* Change the flash and RAM sizes by editing the macros value in the
|
||||
* linker files for both CPUs:
|
||||
* - 'xx_cm0plus.ld', where 'xx' is the device group:
|
||||
* \code
|
||||
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
|
||||
* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
|
||||
* \endcode
|
||||
* - 'xx_cm4_dual.ld', where 'xx' is the device group:
|
||||
* \code
|
||||
* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
|
||||
* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
|
||||
* \endcode
|
||||
*
|
||||
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
|
||||
* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
|
||||
* by either:
|
||||
* - Passing the following commands to the compiler:\n
|
||||
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
|
||||
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
|
||||
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
|
||||
*
|
||||
* <b>ARM MDK</b>\n
|
||||
* The flash and RAM sections for the CPU are defined in the linker files:
|
||||
* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
|
||||
* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
|
||||
* \note If the start of the Cortex-M4 application image is changed, the value
|
||||
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
|
||||
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
|
||||
* Cy_SysEnableCM4() function call.
|
||||
*
|
||||
* \note The linker files provided with the PDL are generic and handle all common
|
||||
* use cases. Your project may not use every section defined in the linker files.
|
||||
* In that case you may see the warnings during the build process:
|
||||
* L6314W (no section matches pattern) and/or L6329W
|
||||
* (pattern only matches removed unused sections). In your project, you can
|
||||
* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
|
||||
* the linker. You can also comment out or remove the relevant code in the linker
|
||||
* file.
|
||||
*
|
||||
* Change the flash and RAM sizes by editing the macros value in the
|
||||
* linker files for both CPUs:
|
||||
* - 'xx_cm0plus.scat', where 'xx' is the device group:
|
||||
* \code
|
||||
* #define FLASH_START 0x10000000
|
||||
* #define FLASH_SIZE 0x00080000
|
||||
* #define RAM_START 0x08000000
|
||||
* #define RAM_SIZE 0x00024000
|
||||
* \endcode
|
||||
* - 'xx_cm4_dual.scat', where 'xx' is the device group:
|
||||
* \code
|
||||
* #define FLASH_START 0x10080000
|
||||
* #define FLASH_SIZE 0x00080000
|
||||
* #define RAM_START 0x08024000
|
||||
* #define RAM_SIZE 0x00023800
|
||||
* \endcode
|
||||
*
|
||||
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
|
||||
* value in the 'xx_cm4_dual.scat' file,
|
||||
* where 'xx' is the device group. Do this by either:
|
||||
* - Passing the following commands to the compiler:\n
|
||||
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
|
||||
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
|
||||
* 'xx' is device family:\n
|
||||
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
|
||||
*
|
||||
* <b>IAR</b>\n
|
||||
* The flash and RAM sections for the CPU are defined in the linker files:
|
||||
* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
|
||||
* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
|
||||
* \note If the start of the Cortex-M4 application image is changed, the value
|
||||
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
|
||||
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
|
||||
* Cy_SysEnableCM4() function call.
|
||||
*
|
||||
* Change the flash and RAM sizes by editing the macros value in the
|
||||
* linker files for both CPUs:
|
||||
* - 'xx_cm0plus.icf', where 'xx' is the device group:
|
||||
* \code
|
||||
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
|
||||
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
|
||||
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
|
||||
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
|
||||
* \endcode
|
||||
* - 'xx_cm4_dual.icf', where 'xx' is the device group:
|
||||
* \code
|
||||
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
|
||||
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
|
||||
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
|
||||
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
|
||||
* \endcode
|
||||
*
|
||||
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
|
||||
* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
|
||||
* is the device group. Do this by either:
|
||||
* - Passing the following commands to the compiler:\n
|
||||
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
|
||||
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
|
||||
* 'xx' is device family:\n
|
||||
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
|
||||
*
|
||||
* \subsection group_system_config_device_initialization Device Initialization
|
||||
* After a power-on-reset (POR), the boot process is handled by the boot code
|
||||
* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot
|
||||
* code passes the control to the Cortex-M0+ startup code located in flash.
|
||||
*
|
||||
* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices
|
||||
* The Cortex-M0+ startup code performs the device initialization by a call to
|
||||
* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
|
||||
* by default. Enable the core using the \ref Cy_SysEnableCM4() function.
|
||||
* See \ref group_system_config_cm4_functions for more details.
|
||||
* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
|
||||
* The function has a separate implementation on each core.
|
||||
* Both function implementations unlock and disable the WDT.
|
||||
* Therefore enable the WDT after both cores have been initialized.
|
||||
*
|
||||
* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
|
||||
* The Cortex-M0+ core is not user-accessible on these devices. In this case the
|
||||
* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
|
||||
*
|
||||
* \subsection group_system_config_heap_stack_config Heap and Stack Configuration
|
||||
* There are two ways to adjust heap and stack configurations:
|
||||
* -# Editing source code files
|
||||
* -# Specifying via command line
|
||||
*
|
||||
* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
|
||||
*
|
||||
* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
|
||||
* - <b>Editing source code files</b>\n
|
||||
* The heap and stack sizes are defined in the assembler startup files
|
||||
* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
|
||||
* Change the heap and stack sizes by modifying the following lines:\n
|
||||
* \code .equ Stack_Size, 0x00001000 \endcode
|
||||
* \code .equ Heap_Size, 0x00000400 \endcode
|
||||
*
|
||||
* - <b>Specifying via command line</b>\n
|
||||
* Change the heap and stack sizes passing the following commands to the compiler:\n
|
||||
* \code -D __STACK_SIZE=0x000000400 \endcode
|
||||
* \code -D __HEAP_SIZE=0x000000100 \endcode
|
||||
*
|
||||
* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
|
||||
* - <b>Editing source code files</b>\n
|
||||
* The heap and stack sizes are defined in the assembler startup files
|
||||
* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
|
||||
* Change the heap and stack sizes by modifying the following lines:\n
|
||||
* \code Stack_Size EQU 0x00001000 \endcode
|
||||
* \code Heap_Size EQU 0x00000400 \endcode
|
||||
*
|
||||
* - <b>Specifying via command line</b>\n
|
||||
* Change the heap and stack sizes passing the following commands to the assembler:\n
|
||||
* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
|
||||
* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
|
||||
*
|
||||
* \subsubsection group_system_config_heap_stack_config_iar IAR
|
||||
* - <b>Editing source code files</b>\n
|
||||
* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
|
||||
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
|
||||
* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
|
||||
* Change the heap and stack sizes by modifying the following lines:\n
|
||||
* \code Stack_Size EQU 0x00001000 \endcode
|
||||
* \code Heap_Size EQU 0x00000400 \endcode
|
||||
*
|
||||
* - <b>Specifying via command line</b>\n
|
||||
* Change the heap and stack sizes passing the following commands to the
|
||||
* linker (including quotation marks):\n
|
||||
* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
|
||||
* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
|
||||
*
|
||||
* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
|
||||
* The CM0+ project and linker script build the CM0+ application image. Similarly,
|
||||
* the CM4 linker script builds the CM4 application image. Each specifies
|
||||
* locations, sizes, and contents of sections in memory. See
|
||||
* \ref group_system_config_device_memory_definition for the symbols and default
|
||||
* values.
|
||||
*
|
||||
* The cymcuelftool is invoked by a post-build command. The precise project
|
||||
* setting is IDE-specific.
|
||||
*
|
||||
* The cymcuelftool combines the two executables. The tool examines the
|
||||
* executables to ensure that memory regions either do not overlap, or contain
|
||||
* identical bytes (shared). If there are no problems, it creates a new ELF file
|
||||
* with the merged image, without changing any of the addresses or data.
|
||||
*
|
||||
* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
|
||||
* The default interrupt handler functions are defined as weak functions to a dummy
|
||||
* handler in the startup file. The naming convention for the interrupt handler names
|
||||
* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
|
||||
* user code by defining the handler function using the same name. For example:
|
||||
* \code
|
||||
* void scb_0_interrupt_IRQHandler(void)
|
||||
*{
|
||||
* ...
|
||||
*}
|
||||
* \endcode
|
||||
*
|
||||
* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM
|
||||
* This process uses memory sections defined in the linker script. The startup
|
||||
* code actually defines the contents of the vector table and performs the copy.
|
||||
* \subsubsection group_system_config_device_vector_table_gcc ARM GCC
|
||||
* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
|
||||
* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
|
||||
* It defines sections and locations in memory.\n
|
||||
* Copy interrupt vectors from flash to RAM: \n
|
||||
* From: \code LONG (__Vectors) \endcode
|
||||
* To: \code LONG (__ram_vectors_start__) \endcode
|
||||
* Size: \code LONG (__Vectors_End - __Vectors) \endcode
|
||||
* The vector table address (and the vector table itself) are defined in the
|
||||
* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
|
||||
* The code in these files copies the vector table from Flash to RAM.
|
||||
* \subsubsection group_system_config_device_vector_table_mdk ARM MDK
|
||||
* The linker script file is 'xx_yy.scat', where 'xx' is the device family,
|
||||
* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
|
||||
* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
|
||||
* (RESET_RAM) shall be first in the RAM section.\n
|
||||
* RESET_RAM represents the vector table. It is defined in the assembler startup
|
||||
* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
|
||||
* The code in these files copies the vector table from Flash to RAM.
|
||||
*
|
||||
* \subsubsection group_system_config_device_vector_table_iar IAR
|
||||
* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
|
||||
* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
|
||||
* This file defines the .intvec_ram section and its location.
|
||||
* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode
|
||||
* The vector table address (and the vector table itself) are defined in the
|
||||
* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
|
||||
* The code in these files copies the vector table from Flash to RAM.
|
||||
*
|
||||
* \section group_system_config_more_information More Information
|
||||
* Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
|
||||
* more details.
|
||||
*
|
||||
* \section group_system_config_MISRA MISRA Compliance
|
||||
*
|
||||
* <table class="doxtable">
|
||||
* <tr>
|
||||
* <th>MISRA Rule</th>
|
||||
* <th>Rule Class (Required/Advisory)</th>
|
||||
* <th>Rule Description</th>
|
||||
* <th>Description of Deviation(s)</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>2.3</td>
|
||||
* <td>R</td>
|
||||
* <td>The character sequence // shall not be used within a comment.</td>
|
||||
* <td>The comments provide a useful WEB link to the documentation.</td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*
|
||||
* \section group_system_config_changelog Changelog
|
||||
* <table class="doxtable">
|
||||
* <tr>
|
||||
* <th>Version</th>
|
||||
* <th>Changes</th>
|
||||
* <th>Reason for Change</th>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td rowspan="2">2.30</td>
|
||||
* <td>Added assembler files, linker skripts for Mbed OS.</td>
|
||||
* <td>Added Arm Mbed OS embedded operating system support.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.</td>
|
||||
* <td>Enhanced PDL usability.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>2.20</td>
|
||||
* <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.</td>
|
||||
* <td>Changed the IPC driver configuration method from compile time to run time.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td rowspan="2"> 2.10</td>
|
||||
* <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
|
||||
* Removed $Sub$$main symbol for ARM MDK compiler.
|
||||
* </td>
|
||||
* <td>uVision Debugger support.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Updated description of the Startup behavior for Single-Core Devices. \n
|
||||
* Added note about WDT disabling by SystemInit() function.
|
||||
* </td>
|
||||
* <td>Documentation improvement.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td rowspan="4"> 2.0</td>
|
||||
* <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
|
||||
* Single core device support.
|
||||
* </td>
|
||||
* <td></td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
|
||||
* Renamed 'wflash' memory region to 'em_eeprom'.
|
||||
* </td>
|
||||
* <td>Linker scripts usability improvement.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
|
||||
* <td>Reserved system resources for internal operations.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
|
||||
* <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
|
||||
* </tr>
|
||||
* <tr>
|
||||
* <td>1.0</td>
|
||||
* <td>Initial version</td>
|
||||
* <td></td>
|
||||
* </tr>
|
||||
* </table>
|
||||
*
|
||||
*
|
||||
* \defgroup group_system_config_macro Macro
|
||||
* \{
|
||||
* \defgroup group_system_config_system_macro System
|
||||
* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status
|
||||
* \defgroup group_system_config_user_settings_macro User Settings
|
||||
* \}
|
||||
* \defgroup group_system_config_functions Functions
|
||||
* \{
|
||||
* \defgroup group_system_config_system_functions System
|
||||
* \defgroup group_system_config_cm4_functions Cortex-M4 Control
|
||||
* \}
|
||||
* \defgroup group_system_config_globals Global Variables
|
||||
*
|
||||
* \}
|
||||
*/
|
||||
|
||||
/**
|
||||
* \addtogroup group_system_config_system_functions
|
||||
* \{
|
||||
* \details
|
||||
* The following system functions implement CMSIS Core functions.
|
||||
* Refer to the [CMSIS documentation]
|
||||
* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
|
||||
* for more details.
|
||||
* \}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Global preprocessor symbols/macros ('define')
|
||||
*******************************************************************************/
|
||||
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
|
||||
(defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
|
||||
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)))
|
||||
#define CY_SYSTEM_CPU_CM0P 1UL
|
||||
#else
|
||||
#define CY_SYSTEM_CPU_CM0P 0UL
|
||||
#endif
|
||||
|
||||
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
|
||||
#include "cyfitter.h"
|
||||
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
|
||||
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* START OF USER SETTINGS HERE
|
||||
* ===========================
|
||||
*
|
||||
* All lines with '<<<' can be set by user.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/**
|
||||
* \addtogroup group_system_config_user_settings_macro
|
||||
* \{
|
||||
*/
|
||||
|
||||
#if defined (CYDEV_CLK_EXTCLK__HZ)
|
||||
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
|
||||
#else
|
||||
/***************************************************************************//**
|
||||
* External Clock Frequency (in Hz, [value]UL). If compiled within
|
||||
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
|
||||
* Otherwise, edit the value below.
|
||||
* <i>(USER SETTING)</i>
|
||||
*******************************************************************************/
|
||||
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
|
||||
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
|
||||
|
||||
|
||||
#if defined (CYDEV_CLK_ECO__HZ)
|
||||
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
|
||||
#else
|
||||
/***************************************************************************//**
|
||||
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
|
||||
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
|
||||
* used.
|
||||
* <i>(USER SETTING)</i>
|
||||
*******************************************************************************/
|
||||
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
|
||||
#endif /* (CYDEV_CLK_ECO__HZ) */
|
||||
|
||||
|
||||
#if defined (CYDEV_CLK_ALTHF__HZ)
|
||||
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
|
||||
#else
|
||||
/***************************************************************************//**
|
||||
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
|
||||
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
|
||||
* Otherwise, edit the value below.
|
||||
* <i>(USER SETTING)</i>
|
||||
*******************************************************************************/
|
||||
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
|
||||
#endif /* (CYDEV_CLK_ALTHF__HZ) */
|
||||
|
||||
|
||||
/***************************************************************************//**
|
||||
* \brief Start address of the Cortex-M4 application ([address]UL)
|
||||
* <i>(USER SETTING)</i>
|
||||
*******************************************************************************/
|
||||
#if !defined (CY_CORTEX_M4_APPL_ADDR)
|
||||
#define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */
|
||||
#endif /* (CY_CORTEX_M4_APPL_ADDR) */
|
||||
|
||||
|
||||
/***************************************************************************//**
|
||||
* \brief IPC Semaphores allocation ([value]UL).
|
||||
* <i>(USER SETTING)</i>
|
||||
*******************************************************************************/
|
||||
#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */
|
||||
|
||||
|
||||
/***************************************************************************//**
|
||||
* \brief IPC Pipe definitions ([value]UL).
|
||||
* <i>(USER SETTING)</i>
|
||||
*******************************************************************************/
|
||||
#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* END OF USER SETTINGS HERE
|
||||
* =========================
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/** \} group_system_config_user_settings_macro */
|
||||
|
||||
|
||||
/**
|
||||
* \addtogroup group_system_config_system_macro
|
||||
* \{
|
||||
*/
|
||||
|
||||
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
|
||||
/** The Cortex-M0+ startup driver identifier */
|
||||
#define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
|
||||
#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
|
||||
|
||||
#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
|
||||
/** The Cortex-M4 startup driver identifier */
|
||||
#define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U))
|
||||
#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
|
||||
|
||||
/** \} group_system_config_system_macro */
|
||||
|
||||
|
||||
/**
|
||||
* \addtogroup group_system_config_system_functions
|
||||
* \{
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION)
|
||||
extern void SystemInit(void) __attribute__((constructor));
|
||||
#else
|
||||
extern void SystemInit(void);
|
||||
#endif /* (__ARMCC_VERSION) */
|
||||
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/** \} group_system_config_system_functions */
|
||||
|
||||
|
||||
/**
|
||||
* \addtogroup group_system_config_cm4_functions
|
||||
* \{
|
||||
*/
|
||||
extern uint32_t Cy_SysGetCM4Status(void);
|
||||
extern void Cy_SysEnableCM4(uint32_t vectorTableOffset);
|
||||
extern void Cy_SysDisableCM4(void);
|
||||
extern void Cy_SysRetainCM4(void);
|
||||
extern void Cy_SysResetCM4(void);
|
||||
/** \} group_system_config_cm4_functions */
|
||||
|
||||
|
||||
/** \cond */
|
||||
extern void Default_Handler (void);
|
||||
|
||||
void Cy_SysIpcPipeIsrCm0(void);
|
||||
void Cy_SysIpcPipeIsrCm4(void);
|
||||
|
||||
extern void Cy_SystemInit(void);
|
||||
extern void Cy_SystemInitFpuEnable(void);
|
||||
|
||||
extern uint32_t cy_delayFreqHz;
|
||||
extern uint32_t cy_delayFreqKhz;
|
||||
extern uint8_t cy_delayFreqMhz;
|
||||
extern uint32_t cy_delay32kMs;
|
||||
/** \endcond */
|
||||
|
||||
|
||||
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
|
||||
/**
|
||||
* \addtogroup group_system_config_cm4_status_macro
|
||||
* \{
|
||||
*/
|
||||
#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */
|
||||
#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */
|
||||
#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */
|
||||
#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
|
||||
/** \} group_system_config_cm4_status_macro */
|
||||
|
||||
#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC Configuration
|
||||
* =========================
|
||||
*******************************************************************************/
|
||||
/* IPC CY_PIPE default configuration */
|
||||
#define CY_SYS_CYPIPE_CLIENT_CNT (8UL)
|
||||
|
||||
#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */
|
||||
#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */
|
||||
#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */
|
||||
|
||||
#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0)
|
||||
#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1)
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/*
|
||||
* The System pipe configuration defines the IPC channel number, interrupt
|
||||
* number, and the pipe interrupt mask for the endpoint.
|
||||
*
|
||||
* The format of the endPoint configuration
|
||||
* Bits[31:16] Interrupt Mask
|
||||
* Bits[15:8 ] IPC interrupt
|
||||
* Bits[ 7:0 ] IPC channel
|
||||
*/
|
||||
|
||||
/* System Pipe addresses */
|
||||
/* CyPipe defines */
|
||||
|
||||
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
|
||||
|
||||
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
|
||||
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
|
||||
| CY_IPC_CHAN_CYPIPE_EP0)
|
||||
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
|
||||
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
|
||||
| CY_IPC_CHAN_CYPIPE_EP1)
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
|
||||
/** \addtogroup group_system_config_globals
|
||||
* \{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock;
|
||||
extern uint32_t cy_BleEcoClockFreqHz;
|
||||
extern uint32_t cy_Hfclk0FreqHz;
|
||||
extern uint32_t cy_PeriClkFreqHz;
|
||||
|
||||
/** \} group_system_config_globals */
|
||||
|
||||
|
||||
|
||||
/** \cond INTERNAL */
|
||||
/*******************************************************************************
|
||||
* Backward compatibility macro. The following code is DEPRECATED and must
|
||||
* not be used in new projects
|
||||
*******************************************************************************/
|
||||
|
||||
/* BWC defines for functions related to enter/exit critical section */
|
||||
#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection
|
||||
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
|
||||
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
|
||||
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
|
||||
|
||||
/** \endcond */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SYSTEM_PSOC6_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,5 +1,7 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2017 ARM Limited
|
||||
* Copyright (c) 2018-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
/*
|
||||
* mbed Microcontroller Library
|
||||
* Copyright (c) 2017-2018 Future Electronics
|
||||
* Copyright (c) 2018-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
|
|
|
|||
|
|
@ -18,7 +18,55 @@
|
|||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/** Config options. */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/** ALTHF (BLE ECO) frequency in Hz */
|
||||
#define CYDEV_CLK_ALTHF__HZ ( 8000000UL)
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "objects.h"
|
||||
|
||||
/*
|
||||
* Board clocks.
|
||||
*/
|
||||
/** Default HFClk frequency in Hz */
|
||||
#ifndef CY_CLK_HFCLK0_FREQ_HZ
|
||||
#define CY_CLK_HFCLK0_FREQ_HZ (100000000UL)
|
||||
#endif
|
||||
|
||||
/** Default PeriClk frequency in Hz */
|
||||
#ifndef CY_CLK_PERICLK_FREQ_HZ
|
||||
#define CY_CLK_PERICLK_FREQ_HZ (CY_CLK_HFCLK0_FREQ_HZ / 2)
|
||||
#endif
|
||||
|
||||
/** Default SlowClk system core frequency in Hz */
|
||||
#ifndef CY_CLK_SYSTEM_FREQ_HZ
|
||||
#define CY_CLK_SYSTEM_FREQ_HZ (CY_CLK_PERICLK_FREQ_HZ)
|
||||
#endif
|
||||
|
||||
|
||||
/** Interrupt assignment for CM0+ core.
|
||||
* On PSoC6 CM0+ core physical interrupt are routed into NVIC through a programmable
|
||||
* multiplexer. This requires that we define which of the 32 NVIC channels is used
|
||||
* by which interrupt. This is done here.
|
||||
*/
|
||||
#define CY_M0_CORE_IRQ_CHANNEL_LP_TICKER ((IRQn_Type)0)
|
||||
#define CY_M0_CORE_IRQ_CHANNEL_IPC_SYS ((IRQn_Type)1)
|
||||
#define CY_M0_CORE_IRQ_CHANNEL_IPC_USR ((IRQn_Type)2)
|
||||
#define CY_M0_CORE_IRQ_CHANNEL_PSA_MAILBOX ((IRQn_Type)3)
|
||||
#define CY_M0_CORE_IRQ_CHANNEL_SERIAL ((IRQn_Type)4)
|
||||
#define CY_M0_CORE_IRQ_CHANNEL_BLE ((IRQn_Type)7)
|
||||
#define CY_M0_CORE_IRQ_CHANNEL_US_TICKER ((IRQn_Type)8)
|
||||
|
||||
/** Identifiers used in allocation of NVIC channels.
|
||||
*/
|
||||
#define CY_US_TICKER_IRQN_ID (0x100)
|
||||
#define CY_SERIAL_IRQN_ID (0x200)
|
||||
#define CY_BLE_IRQN_ID (0x300)
|
||||
#define CY_GPIO_IRQN_ID (0x400)
|
||||
#define CY_LP_TICKER_IRQN_ID (0x500)
|
||||
#define CY_PSA_MAILBOX_IRQN_ID (0x600)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -105,6 +105,16 @@
|
|||
"help": "Size in bytes of Shared RAM between Secure and Non-secure worlds",
|
||||
"value": null,
|
||||
"macro_name": "PSA_SHARED_RAM_SIZE"
|
||||
},
|
||||
"public-ram-start": {
|
||||
"help": "Starting address of Public RAM for variables accessible from Non-secure worlds",
|
||||
"value": null,
|
||||
"macro_name": "PSA_PUBLIC_RAM_START"
|
||||
},
|
||||
"public-ram-size": {
|
||||
"help": "Size in bytes of Public RAM variables accessible from Non-secure worlds",
|
||||
"value": null,
|
||||
"macro_name": "PSA_PUBLIC_RAM_SIZE"
|
||||
}
|
||||
}
|
||||
},
|
||||
|
|
@ -7897,13 +7907,21 @@
|
|||
"macros_add": ["MCU_PSOC6_M4"],
|
||||
"public": false
|
||||
},
|
||||
"CY8CKIT_062_WIFI_BT_M0": {
|
||||
"inherits": ["MCU_PSOC6_M0"],
|
||||
"supported_form_factors": ["ARDUINO"],
|
||||
"extra_labels_add": ["CY8C62XX", "CY8CKIT_062_WIFI_BT"],
|
||||
"macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"],
|
||||
"detect_code": ["1900"],
|
||||
"post_binary_hook": {
|
||||
"function": "PSOC6Code.complete"
|
||||
}
|
||||
},
|
||||
"CY8CKIT_062_WIFI_BT": {
|
||||
"inherits": ["MCU_PSOC6_M4"],
|
||||
"features": ["BLE"],
|
||||
"supported_form_factors": ["ARDUINO"],
|
||||
"supported_toolchains": ["GCC_ARM", "ARMC5", "IAR"],
|
||||
"release_versions": ["5"],
|
||||
"extra_labels_add": ["PSOC6_01", "WICED", "CYW43XXX", "CYW4343X", "CORDIO"],
|
||||
"extra_labels_add": ["PSOC6_01", "WICED", "CYW43XXX", "CYW4343X", "CORDIO", "CY8C62XX"],
|
||||
"macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"],
|
||||
"detect_code": ["1900"],
|
||||
"hex_filename": "psoc6_01_cm0p_sleep.hex",
|
||||
|
|
@ -7914,12 +7932,61 @@
|
|||
"network-default-interface-type": "WIFI"
|
||||
}
|
||||
},
|
||||
"CY8CKIT_062_WIFI_BT_M0_PSA": {
|
||||
"inherits": ["SPE_Target", "CY8CKIT_062_WIFI_BT_M0"],
|
||||
"components_add": ["SPM_MAILBOX", "FLASHIAP"],
|
||||
"extra_labels_add": ["PSA", "MBED_SPM"],
|
||||
"macros_add": [
|
||||
"MBED_TICKLESS",
|
||||
"MBEDTLS_PSA_CRYPTO_SPM",
|
||||
"MBEDTLS_PSA_CRYPTO_C",
|
||||
"MBEDTLS_ENTROPY_NV_SEED",
|
||||
"CY_IPC_DEFAULT_CFG_DISABLE",
|
||||
"PU_ENABLE"
|
||||
],
|
||||
"deliver_to_target": "CY8CKIT_062_WIFI_BT_PSA",
|
||||
"delivery_dir": "TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT_PSA/prebuilt",
|
||||
"overrides": {
|
||||
"secure-rom-start": "0x10000000",
|
||||
"secure-rom-size": "0x80000",
|
||||
"non-secure-rom-start": "0x10080000",
|
||||
"non-secure-rom-size": "0x78000",
|
||||
"secure-ram-start": "0x08000000",
|
||||
"secure-ram-size": "0x10000",
|
||||
"non-secure-ram-start": "0x08010000",
|
||||
"non-secure-ram-size": "0x37500",
|
||||
"shared-ram-start": "0x08047500",
|
||||
"shared-ram-size": "0x100",
|
||||
"public-ram-start": "0x08047600",
|
||||
"public-ram-size": "0x200"
|
||||
}
|
||||
},
|
||||
"CY8CKIT_062_WIFI_BT_PSA": {
|
||||
"inherits": ["NSPE_Target", "CY8CKIT_062_WIFI_BT"],
|
||||
"extra_labels_add": ["PSA", "MBED_SPM"],
|
||||
"components_add": ["SPM_MAILBOX", "FLASHIAP"],
|
||||
"device_has_remove": ["TRNG", "CRC"],
|
||||
"macros_add": ["MBEDTLS_PSA_CRYPTO_C"],
|
||||
"hex_filename": "psa_release_1.0.hex",
|
||||
"overrides": {
|
||||
"secure-rom-start": "0x10000000",
|
||||
"secure-rom-size": "0x80000",
|
||||
"non-secure-rom-start": "0x10080000",
|
||||
"non-secure-rom-size": "0x78000",
|
||||
"secure-ram-start": "0x08000000",
|
||||
"secure-ram-size": "0x10000",
|
||||
"non-secure-ram-start": "0x08010000",
|
||||
"non-secure-ram-size": "0x37500",
|
||||
"shared-ram-start": "0x08047500",
|
||||
"shared-ram-size": "0x100",
|
||||
"public-ram-start": "0x08047600",
|
||||
"public-ram-size": "0x200"
|
||||
}
|
||||
},
|
||||
"CY8CMOD_062_4343W": {
|
||||
"inherits": ["MCU_PSOC6_M4"],
|
||||
"features": ["BLE"],
|
||||
"device_has_remove": ["ANALOGOUT"],
|
||||
"supported_toolchains": ["GCC_ARM", "ARMC5", "IAR"],
|
||||
"release_versions": ["5"],
|
||||
"extra_labels_add": ["PSOC6_02", "WICED", "CYW43XXX", "CYW4343X", "CORDIO"],
|
||||
"macros_add": ["CY8C624ABZI_D44", "PSOC6_DYNSRM_DISABLE=1"],
|
||||
"public": false,
|
||||
|
|
@ -7948,8 +8015,6 @@
|
|||
},
|
||||
"CY8CKIT_062_4343W": {
|
||||
"inherits": ["MCU_PSOC6_M4"],
|
||||
"supported_toolchains": ["GCC_ARM", "ARMC5", "IAR"],
|
||||
"release_versions": ["5"],
|
||||
"features": ["BLE"],
|
||||
"supported_form_factors": ["ARDUINO"],
|
||||
"device_has_remove": ["ANALOGOUT"],
|
||||
|
|
@ -7964,12 +8029,18 @@
|
|||
"network-default-interface-type": "WIFI"
|
||||
}
|
||||
},
|
||||
"CYW943012P6EVB_01_M0": {
|
||||
"inherits": ["MCU_PSOC6_M0"],
|
||||
"extra_labels_add": ["CY8C62XX", "CYW943012P6EVB_01"],
|
||||
"macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"],
|
||||
"post_binary_hook": {
|
||||
"function": "PSOC6Code.complete"
|
||||
}
|
||||
},
|
||||
"CYW943012P6EVB_01": {
|
||||
"inherits": ["MCU_PSOC6_M4"],
|
||||
"features": ["BLE"],
|
||||
"supported_toolchains": ["GCC_ARM", "ARMC5", "IAR"],
|
||||
"release_versions": ["5"],
|
||||
"extra_labels_add": ["PSOC6_01", "WICED", "CYW43XXX", "CYW43012", "CORDIO"],
|
||||
"extra_labels_add": ["PSOC6_01", "WICED", "CYW43XXX", "CYW43012", "CORDIO", "CY8C62XX"],
|
||||
"macros_add": ["CY8C6247BZI_D54", "PSOC6_DYNSRM_DISABLE=1"],
|
||||
"detect_code": ["1906"],
|
||||
"hex_filename": "psoc6_01_cm0p_sleep.hex",
|
||||
|
|
|
|||
|
|
@ -135,7 +135,9 @@ class CodeBlocks(GccArm):
|
|||
'NRF51_DK_OTA': 'board/nordic_nrf51_dk.cfg',
|
||||
'NRF51_DK': 'board/nordic_nrf51_dk.cfg',
|
||||
'FUTURE_SEQUANA': 'board/cy8ckit_062_ble.cfg',
|
||||
'FUTURE_SEQUANA_M0': 'board/cy8ckit_062_ble.cfg'
|
||||
'FUTURE_SEQUANA_M0': 'board/cy8ckit_062_ble.cfg',
|
||||
'CY8CKIT_062_WIFI_BT': 'board/cy8ckit_062_ble.cfg',
|
||||
'CY8CKIT_062_WIFI_BT_M0': 'board/cy8ckit_062_ble.cfg'
|
||||
}
|
||||
|
||||
if self.target in openocd_board:
|
||||
|
|
|
|||
|
|
@ -937,7 +937,9 @@ class mbedToolchain:
|
|||
"MBED_ROM_START": "target.secure-rom-start",
|
||||
"MBED_ROM_SIZE": "target.secure-rom-size",
|
||||
"MBED_RAM_START": "target.secure-ram-start",
|
||||
"MBED_RAM_SIZE": "target.secure-ram-size"
|
||||
"MBED_RAM_SIZE": "target.secure-ram-size",
|
||||
"MBED_PUBLIC_RAM_START": "target.public-ram-start",
|
||||
"MBED_PUBLIC_RAM_SIZE": "target.public-ram-size"
|
||||
}
|
||||
|
||||
for flag, param in flags2params.items():
|
||||
|
|
|
|||
Loading…
Reference in New Issue