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Merge pull request #9870 from ChangwuShan/Re-enable_MPS2_platform 

Re-enable MPS2 platform
pull/10407/head
Martin Kojtal 2019-04-17 08:02:14 +01:00 committed by GitHub
parent 0b7d9af4dd 3d9b7df8e0
commit c961a5d834
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
33 changed files with 4286 additions and 265 deletions
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6
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct
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@ -1,7 +1,7 @@
#! armcc -E
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2016 ARM Limited
;* Copyright (c) 2006-2019 Arm Limited
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
@ -44,11 +44,11 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
*(+RO)
}
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100-Stack_Size) { ; RW data
.ANY (+RW +ZI)
*(+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x400000 EMPTY -Stack_Size { ; Stack region growing down
}

74
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD/startup_MPS2.S
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@ -1,6 +1,6 @@
; MPS2 CMSIS Library
;
; Copyright (c) 2006-2016 ARM Limited
; Copyright (c) 2006-2019 Arm Limited
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
@ -38,29 +38,27 @@
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x20400000
PRESERVE8
THUMB
@ -115,14 +113,14 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -217,22 +215,22 @@ UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
B .
ENDP

204
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_GCC_ARM/MPS2.ld Normal file
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@ -0,0 +1,204 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS MPS2.ld for GCC_ARM
*
* Linker script for AN382
*/
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00400000 /* 4MB ZBTSRAM1 */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00400000 /* 4MB ZBTSRAM2 & ZBTSRAM3 */
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x1000;
STACK_SIZE = 0x400;
/* Size of the vector table in SRAM */
NVIC_NUM_VECTORS = (16 + 48);
M_VECTOR_RAM_SIZE = NVIC_NUM_VECTORS * 4;
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(4);
} > FLASH
.text :
{
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
. = ALIGN(4);
__data_start__ = .;
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM AT > FLASH
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM
.bss :
{
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > RAM
bss_size = __bss_end__ - __bss_start__;
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
} /* End of sections */

203
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S Normal file
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@ -0,0 +1,203 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS startup_MPS2.S for GCC_ARM
*/
.syntax unified
.arch armv6-m
.section .vector_table,"a",%progbits
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long UARTRX0_Handler /* UART 0 RX Handler */
.long UARTTX0_Handler /* UART 0 TX Handler */
.long UARTRX1_Handler /* UART 1 RX Handler */
.long UARTTX1_Handler /* UART 1 TX Handler */
.long UARTRX2_Handler /* UART 2 RX Handler */
.long UARTTX2_Handler /* UART 2 TX Handler */
.long PORT0_COMB_Handler /* GPIO Port 0 Combined Handler */
.long PORT1_COMB_Handler /* GPIO Port 1 Combined Handler */
.long TIMER0_Handler /* TIMER 0 handler */
.long TIMER1_Handler /* TIMER 1 handler */
.long DUALTIMER_Handler /* Dual timer handler */
.long SPI_Handler /* SPI exceptions Handler */
.long UARTOVF_Handler /* UART 0,1,2 Overflow Handler */
.long ETHERNET_Handler /* Ethernet Overflow Handler */
.long I2S_Handler /* I2S Handler */
.long TSC_Handler /* Touch Screen handler */
.long PORT2_COMB_Handler /* GPIO Port 2 Combined Handler */
.long PORT3_COMB_Handler /* GPIO Port 3 Combined Handler */
.long UARTRX3_Handler /* UART 3 RX Handler */
.long UARTTX3_Handler /* UART 3 TX Handler */
.long UARTRX4_Handler /* UART 4 RX Handler */
.long UARTTX4_Handler /* UART 4 TX Handler */
.long ADCSPI_Handler /* SHIELD ADC SPI exceptions Handler */
.long SHIELDSPI_Handler /* SHIELD SPI exceptions Handler */
.long PORT0_0_Handler /* GPIO Port 0 pin 0 Handler */
.long PORT0_1_Handler /* GPIO Port 0 pin 1 Handler */
.long PORT0_2_Handler /* GPIO Port 0 pin 2 Handler */
.long PORT0_3_Handler /* GPIO Port 0 pin 3 Handler */
.long PORT0_4_Handler /* GPIO Port 0 pin 4 Handler */
.long PORT0_5_Handler /* GPIO Port 0 pin 5 Handler */
.long PORT0_6_Handler /* GPIO Port 0 pin 6 Handler */
.long PORT0_7_Handler /* GPIO Port 0 pin 7 Handler */
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/*
* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_loop_end
movs r4, #0
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, #4
cmp r4, r3
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
/* Initialize .bss */
init_bss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
ldr r3, =bss_size
cmp r3, #0
beq system_startup
movs r4, #0
zero:
strb r4, [r1]
adds r1, #1
subs r3, r3, #1
bne zero
system_startup:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/*
* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers
*/
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
/* External interrupts */
def_irq_default_handler UARTRX0_Handler /* 0: UART 0 RX Handler */
def_irq_default_handler UARTTX0_Handler /* 1: UART 0 TX Handler */
def_irq_default_handler UARTRX1_Handler /* 2: UART 1 RX Handler */
def_irq_default_handler UARTTX1_Handler /* 3: UART 1 TX Handler */
def_irq_default_handler UARTRX2_Handler /* 4: UART 2 RX Handler */
def_irq_default_handler UARTTX2_Handler /* 5: UART 2 TX Handler */
def_irq_default_handler PORT0_COMB_Handler /* 6: GPIO Port 0 combined Handler */
def_irq_default_handler PORT1_COMB_Handler /* 7: GPIO Port 1 combined Handler */
def_irq_default_handler TIMER0_Handler /* 8: TIMER 0 Handler */
def_irq_default_handler TIMER1_Handler /* 9: TIMER 1 Handler */
def_irq_default_handler DUALTIMER_Handler /* 10: Dual Timer Handler */
def_irq_default_handler SPI_Handler /* 11: SPI exceptions Handler */
def_irq_default_handler UARTOVF_Handler /* 12: UART 0,1,2 Overflow Handler */
def_irq_default_handler ETHERNET_Handler /* 13: Ethernet Overflow Handler */
def_irq_default_handler I2S_Handler /* 14: I2S Handler */
def_irq_default_handler TSC_Handler /* 15: Touch Screen Handler */
def_irq_default_handler PORT2_COMB_Handler /* 16: GPIO Port 2 combined Handler */
def_irq_default_handler PORT3_COMB_Handler /* 17: GPIO Port 3 combined Handler */
def_irq_default_handler UARTRX3_Handler /* 18: UART 3 RX Handler */
def_irq_default_handler UARTTX3_Handler /* 19: UART 3 TX Handler */
def_irq_default_handler UARTRX4_Handler /* 20: UART 4 RX Handler */
def_irq_default_handler UARTTX4_Handler /* 21: UART 4 TX Handler */
def_irq_default_handler ADCSPI_Handler /* 22: SHIELD ADC SPI exceptions Handlre */
def_irq_default_handler SHIELDSPI_Handler /* 23: SHIELD SPI exceptions Handlre */
def_irq_default_handler PORT0_0_Handler /* 24: GPIO Port 0 pin 0 Handler */
def_irq_default_handler PORT0_1_Handler /* 25: GPIO Port 0 pin 1 Handler */
def_irq_default_handler PORT0_2_Handler /* 26: GPIO Port 0 pin 2 Handler */
def_irq_default_handler PORT0_3_Handler /* 27: GPIO Port 0 pin 3 Handler */
def_irq_default_handler PORT0_4_Handler /* 28: GPIO Port 0 pin 4 Handler */
def_irq_default_handler PORT0_5_Handler /* 29: GPIO Port 0 pin 5 Handler */
def_irq_default_handler PORT0_6_Handler /* 30: GPIO Port 0 pin 6 Handler */
def_irq_default_handler PORT0_7_Handler /* 31: GPIO Port 0 pin 7 Handler */
.end

65
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_IAR/MPS2.icf Normal file
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@ -0,0 +1,65 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License) you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS MPS2.icf for IAR
*/
/* Code memory zones */
define symbol ZBT_SSRAM1_START = 0x00000000;
define symbol ZBT_SSRAM1_SIZE = 0x00400000; /* 4 MiB */
/* Data memory zones */
define symbol ZBT_SSRAM23_START = 0x20000000;
define symbol ZBT_SSRAM23_SIZE = 0x00400000; /* 4 MiB */
/* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = 16 + 48;
define symbol NVIC_VECTORS_SIZE = NVIC_NUM_VECTORS * 4;
/* Specials */
define symbol __ICFEDIT_intvec_start__ = ZBT_SSRAM1_START;
/* Memory Regions */
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SSRAM1_START;
define symbol __ICFEDIT_region_ROM_end__ = ZBT_SSRAM1_START + ZBT_SSRAM1_SIZE - 1;
/*
* At execution, RAM is set to be in ZBT SSRAM2 and 3, just after the vector
* table previously moved from Flash.
*/
define symbol __ICFEDIT_region_RAM_start__ = ZBT_SSRAM23_START + NVIC_VECTORS_SIZE;
define symbol __ICFEDIT_region_RAM_end__ = ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE;
/* Sizes */
/* Heap and Stack size */
define symbol __ICFEDIT_size_heap__ = 0x1000;
define symbol __ICFEDIT_size_cstack__ = 0x400;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
initialize by copy { readwrite };
do not initialize { section .noinit };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

317
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_IAR/startup_MPS2.S Normal file
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@ -0,0 +1,317 @@
;/*
; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
; * This file is derivative of mbed-os V5.10.4 CM3DS startup_MPS2.S for IAR
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UARTRX0_Handler ; UART 0 RX Handler
DCD UARTTX0_Handler ; UART 0 TX Handler
DCD UARTRX1_Handler ; UART 1 RX Handler
DCD UARTTX1_Handler ; UART 1 TX Handler
DCD UARTRX2_Handler ; UART 2 RX Handler
DCD UARTTX2_Handler ; UART 2 TX Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
DCD SPI_Handler ; SPI exceptions Handler
DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
DCD UARTRX3_Handler ; UART 3 RX Handler
DCD UARTTX3_Handler ; UART 3 TX Handler
DCD UARTRX4_Handler ; UART 4 RX Handler
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK UARTRX0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX0_Handler
B UARTRX0_Handler
PUBWEAK UARTTX0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX0_Handler
B UARTTX0_Handler
PUBWEAK UARTRX1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX1_Handler
B UARTRX1_Handler
PUBWEAK UARTTX1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX1_Handler
B UARTTX1_Handler
PUBWEAK UARTRX2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX2_Handler
B UARTRX2_Handler
PUBWEAK UARTTX2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX2_Handler
B UARTTX2_Handler
PUBWEAK PORT0_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_COMB_Handler
B PORT0_COMB_Handler
PUBWEAK PORT1_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT1_COMB_Handler
B PORT1_COMB_Handler
PUBWEAK TIMER0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER0_Handler
B TIMER0_Handler
PUBWEAK TIMER1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER1_Handler
B TIMER1_Handler
PUBWEAK DUALTIMER_HANDLER
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER_HANDLER
B DUALTIMER_HANDLER
PUBWEAK SPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI_Handler
B SPI_Handler
PUBWEAK UARTOVF_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTOVF_Handler
B UARTOVF_Handler
PUBWEAK ETHERNET_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ETHERNET_Handler
B ETHERNET_Handler
PUBWEAK I2S_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2S_Handler
B I2S_Handler
PUBWEAK TSC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TSC_Handler
B TSC_Handler
PUBWEAK PORT2_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT2_COMB_Handler
B PORT2_COMB_Handler
PUBWEAK PORT3_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT3_COMB_Handler
B PORT3_COMB_Handler
PUBWEAK UARTRX3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX3_Handler
B UARTRX3_Handler
PUBWEAK UARTTX3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX3_Handler
B UARTTX3_Handler
PUBWEAK UARTRX4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX4_Handler
B UARTRX4_Handler
PUBWEAK UARTTX4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX4_Handler
B UARTTX4_Handler
PUBWEAK ADCSPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ADCSPI_Handler
B ADCSPI_Handler
PUBWEAK SHIELDSPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SHIELDSPI_Handler
B SHIELDSPI_Handler
PUBWEAK PORT0_0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_0_Handler
B PORT0_0_Handler
PUBWEAK PORT0_1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_1_Handler
B PORT0_1_Handler
PUBWEAK PORT0_2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_2_Handler
B PORT0_2_Handler
PUBWEAK PORT0_3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_3_Handler
B PORT0_3_Handler
PUBWEAK PORT0_4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_4_Handler
B PORT0_4_Handler
PUBWEAK PORT0_5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_5_Handler
B PORT0_5_Handler
PUBWEAK PORT0_6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_6_Handler
B PORT0_6_Handler
PUBWEAK PORT0_7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_7_Handler
B PORT0_7_Handler
END

2
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/CMSDK_CM0plus.h
View File

@ -99,7 +99,7 @@ typedef enum IRQn
/* -------- Configuration of the Cortex-M0+ Processor and Core Peripherals ------ */
#define __CM0PLUS_REV 0x0000 /* Core revision r0p0 */
#define __MPU_PRESENT 1 /* MPU present or not */
#define __MPU_PRESENT 0 /* MPU present or not */
#define __VTOR_PRESENT 1 /* VTOR present or not */
#define __NVIC_PRIO_BITS 2 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */

6
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -1,7 +1,7 @@
#! armcc -E
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2016 ARM Limited
;* Copyright (c) 2006-2019 Arm Limited
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
@ -44,11 +44,11 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
*(+RO)
}
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100-Stack_Size) { ; RW data
.ANY (+RW +ZI)
*(+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x400000 EMPTY -Stack_Size { ; Stack region growing down
}

74
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD/startup_MPS2.S
View File

@ -1,6 +1,6 @@
; MPS2 CMSIS Library
;
; Copyright (c) 2006-2016 ARM Limited
; Copyright (c) 2006-2019 Arm Limited
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
@ -38,29 +38,27 @@
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x20400000
PRESERVE8
THUMB
@ -115,14 +113,14 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -217,22 +215,22 @@ UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
B .
ENDP

204
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/MPS2.ld Normal file
View File

@ -0,0 +1,204 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS MPS2.ld for GCC_ARM
*
* Linker script for AN383
*/
#include "../cmsis_nvic.h"
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00400000 /* 4MB ZBTSRAM1 */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00400000 /* 4MB ZBTSRAM2 & ZBTSRAM3 */
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x1000;
STACK_SIZE = 0x400;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = NVIC_NUM_VECTORS * 4;
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(4);
} > FLASH
.text :
{
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
. = ALIGN(4);
__data_start__ = .;
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM AT > FLASH
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM
.bss :
{
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > RAM
bss_size = __bss_end__ - __bss_start__;
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
} /* End of sections */

203
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S Normal file
View File

@ -0,0 +1,203 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS startup_MPS2.S for GCC_ARM
*/
.syntax unified
.arch armv6-m
.section .vector_table,"a",%progbits
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long UARTRX0_Handler /* UART 0 RX Handler */
.long UARTTX0_Handler /* UART 0 TX Handler */
.long UARTRX1_Handler /* UART 1 RX Handler */
.long UARTTX1_Handler /* UART 1 TX Handler */
.long UARTRX2_Handler /* UART 2 RX Handler */
.long UARTTX2_Handler /* UART 2 TX Handler */
.long PORT0_COMB_Handler /* GPIO Port 0 Combined Handler */
.long PORT1_COMB_Handler /* GPIO Port 1 Combined Handler */
.long TIMER0_Handler /* TIMER 0 handler */
.long TIMER1_Handler /* TIMER 1 handler */
.long DUALTIMER_Handler /* Dual timer handler */
.long SPI_Handler /* SPI exceptions Handler */
.long UARTOVF_Handler /* UART 0,1,2 Overflow Handler */
.long ETHERNET_Handler /* Ethernet Overflow Handler */
.long I2S_Handler /* I2S Handler */
.long TSC_Handler /* Touch Screen handler */
.long PORT2_COMB_Handler /* GPIO Port 2 Combined Handler */
.long PORT3_COMB_Handler /* GPIO Port 3 Combined Handler */
.long UARTRX3_Handler /* UART 3 RX Handler */
.long UARTTX3_Handler /* UART 3 TX Handler */
.long UARTRX4_Handler /* UART 4 RX Handler */
.long UARTTX4_Handler /* UART 4 TX Handler */
.long ADCSPI_Handler /* SHIELD ADC SPI exceptions Handler */
.long SHIELDSPI_Handler /* SHIELD SPI exceptions Handler */
.long PORT0_0_Handler /* GPIO Port 0 pin 0 Handler */
.long PORT0_1_Handler /* GPIO Port 0 pin 1 Handler */
.long PORT0_2_Handler /* GPIO Port 0 pin 2 Handler */
.long PORT0_3_Handler /* GPIO Port 0 pin 3 Handler */
.long PORT0_4_Handler /* GPIO Port 0 pin 4 Handler */
.long PORT0_5_Handler /* GPIO Port 0 pin 5 Handler */
.long PORT0_6_Handler /* GPIO Port 0 pin 6 Handler */
.long PORT0_7_Handler /* GPIO Port 0 pin 7 Handler */
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/*
* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_loop_end
movs r4, #0
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, #4
cmp r4, r3
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
/* Initialize .bss */
init_bss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
ldr r3, =bss_size
cmp r3, #0
beq system_startup
movs r4, #0
zero:
strb r4, [r1]
adds r1, #1
subs r3, r3, #1
bne zero
system_startup:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/*
* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers
*/
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
/* External interrupts */
def_irq_default_handler UARTRX0_Handler /* 0: UART 0 RX Handler */
def_irq_default_handler UARTTX0_Handler /* 1: UART 0 TX Handler */
def_irq_default_handler UARTRX1_Handler /* 2: UART 1 RX Handler */
def_irq_default_handler UARTTX1_Handler /* 3: UART 1 TX Handler */
def_irq_default_handler UARTRX2_Handler /* 4: UART 2 RX Handler */
def_irq_default_handler UARTTX2_Handler /* 5: UART 2 TX Handler */
def_irq_default_handler PORT0_COMB_Handler /* 6: GPIO Port 0 combined Handler */
def_irq_default_handler PORT1_COMB_Handler /* 7: GPIO Port 1 combined Handler */
def_irq_default_handler TIMER0_Handler /* 8: TIMER 0 Handler */
def_irq_default_handler TIMER1_Handler /* 9: TIMER 1 Handler */
def_irq_default_handler DUALTIMER_Handler /* 10: Dual Timer Handler */
def_irq_default_handler SPI_Handler /* 11: SPI exceptions Handler */
def_irq_default_handler UARTOVF_Handler /* 12: UART 0,1,2 Overflow Handler */
def_irq_default_handler ETHERNET_Handler /* 13: Ethernet Overflow Handler */
def_irq_default_handler I2S_Handler /* 14: I2S Handler */
def_irq_default_handler TSC_Handler /* 15: Touch Screen Handler */
def_irq_default_handler PORT2_COMB_Handler /* 16: GPIO Port 2 combined Handler */
def_irq_default_handler PORT3_COMB_Handler /* 17: GPIO Port 3 combined Handler */
def_irq_default_handler UARTRX3_Handler /* 18: UART 3 RX Handler */
def_irq_default_handler UARTTX3_Handler /* 19: UART 3 TX Handler */
def_irq_default_handler UARTRX4_Handler /* 20: UART 4 RX Handler */
def_irq_default_handler UARTTX4_Handler /* 21: UART 4 TX Handler */
def_irq_default_handler ADCSPI_Handler /* 22: SHIELD ADC SPI exceptions Handlre */
def_irq_default_handler SHIELDSPI_Handler /* 23: SHIELD SPI exceptions Handlre */
def_irq_default_handler PORT0_0_Handler /* 24: GPIO Port 0 pin 0 Handler */
def_irq_default_handler PORT0_1_Handler /* 25: GPIO Port 0 pin 1 Handler */
def_irq_default_handler PORT0_2_Handler /* 26: GPIO Port 0 pin 2 Handler */
def_irq_default_handler PORT0_3_Handler /* 27: GPIO Port 0 pin 3 Handler */
def_irq_default_handler PORT0_4_Handler /* 28: GPIO Port 0 pin 4 Handler */
def_irq_default_handler PORT0_5_Handler /* 29: GPIO Port 0 pin 5 Handler */
def_irq_default_handler PORT0_6_Handler /* 30: GPIO Port 0 pin 6 Handler */
def_irq_default_handler PORT0_7_Handler /* 31: GPIO Port 0 pin 7 Handler */
.end

66
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_IAR/MPS2.icf Normal file
View File

@ -0,0 +1,66 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License) you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS MPS2.icf for IAR
*/
/* Code memory zones */
define symbol ZBT_SSRAM1_START = 0x00000000;
define symbol ZBT_SSRAM1_SIZE = 0x00400000; /* 4 MiB */
/* Data memory zones */
define symbol ZBT_SSRAM23_START = 0x20000000;
define symbol ZBT_SSRAM23_SIZE = 0x00400000; /* 4 MiB */
/* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = 16 + 48;
define symbol NVIC_VECTORS_SIZE = NVIC_NUM_VECTORS * 4;
/* Specials */
define symbol __ICFEDIT_intvec_start__ = ZBT_SSRAM1_START;
/* Memory Regions */
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SSRAM1_START;
define symbol __ICFEDIT_region_ROM_end__ = ZBT_SSRAM1_START + ZBT_SSRAM1_SIZE - 1;
/*
* At execution, RAM is set to be in ZBT SSRAM2 and 3, just after the vector
* table previously moved from Flash.
*/
define symbol __ICFEDIT_region_RAM_start__ = ZBT_SSRAM23_START + NVIC_VECTORS_SIZE;
define symbol __ICFEDIT_region_RAM_end__ = ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE;
/* Sizes */
/* Heap and Stack size */
define symbol __ICFEDIT_size_heap__ = 0x1000;
define symbol __ICFEDIT_size_cstack__ = 0x400;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
initialize by copy { readwrite };
do not initialize { section .noinit };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

317
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_IAR/startup_MPS2.S Normal file
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@ -0,0 +1,317 @@
;/*
; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
; * This file is derivative of mbed-os V5.10.4 CM3DS startup_MPS2.S for IAR
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UARTRX0_Handler ; UART 0 RX Handler
DCD UARTTX0_Handler ; UART 0 TX Handler
DCD UARTRX1_Handler ; UART 1 RX Handler
DCD UARTTX1_Handler ; UART 1 TX Handler
DCD UARTRX2_Handler ; UART 2 RX Handler
DCD UARTTX2_Handler ; UART 2 TX Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
DCD SPI_Handler ; SPI exceptions Handler
DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
DCD UARTRX3_Handler ; UART 3 RX Handler
DCD UARTTX3_Handler ; UART 3 TX Handler
DCD UARTRX4_Handler ; UART 4 RX Handler
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK UARTRX0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX0_Handler
B UARTRX0_Handler
PUBWEAK UARTTX0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX0_Handler
B UARTTX0_Handler
PUBWEAK UARTRX1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX1_Handler
B UARTRX1_Handler
PUBWEAK UARTTX1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX1_Handler
B UARTTX1_Handler
PUBWEAK UARTRX2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX2_Handler
B UARTRX2_Handler
PUBWEAK UARTTX2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX2_Handler
B UARTTX2_Handler
PUBWEAK PORT0_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_COMB_Handler
B PORT0_COMB_Handler
PUBWEAK PORT1_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT1_COMB_Handler
B PORT1_COMB_Handler
PUBWEAK TIMER0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER0_Handler
B TIMER0_Handler
PUBWEAK TIMER1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER1_Handler
B TIMER1_Handler
PUBWEAK DUALTIMER_HANDLER
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER_HANDLER
B DUALTIMER_HANDLER
PUBWEAK SPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI_Handler
B SPI_Handler
PUBWEAK UARTOVF_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTOVF_Handler
B UARTOVF_Handler
PUBWEAK ETHERNET_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ETHERNET_Handler
B ETHERNET_Handler
PUBWEAK I2S_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2S_Handler
B I2S_Handler
PUBWEAK TSC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TSC_Handler
B TSC_Handler
PUBWEAK PORT2_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT2_COMB_Handler
B PORT2_COMB_Handler
PUBWEAK PORT3_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT3_COMB_Handler
B PORT3_COMB_Handler
PUBWEAK UARTRX3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX3_Handler
B UARTRX3_Handler
PUBWEAK UARTTX3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX3_Handler
B UARTTX3_Handler
PUBWEAK UARTRX4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX4_Handler
B UARTRX4_Handler
PUBWEAK UARTTX4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX4_Handler
B UARTTX4_Handler
PUBWEAK ADCSPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ADCSPI_Handler
B ADCSPI_Handler
PUBWEAK SHIELDSPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SHIELDSPI_Handler
B SHIELDSPI_Handler
PUBWEAK PORT0_0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_0_Handler
B PORT0_0_Handler
PUBWEAK PORT0_1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_1_Handler
B PORT0_1_Handler
PUBWEAK PORT0_2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_2_Handler
B PORT0_2_Handler
PUBWEAK PORT0_3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_3_Handler
B PORT0_3_Handler
PUBWEAK PORT0_4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_4_Handler
B PORT0_4_Handler
PUBWEAK PORT0_5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_5_Handler
B PORT0_5_Handler
PUBWEAK PORT0_6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_6_Handler
B PORT0_6_Handler
PUBWEAK PORT0_7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_7_Handler
B PORT0_7_Handler
END

6
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -1,7 +1,7 @@
#! armcc -E
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2016 ARM Limited
;* Copyright (c) 2006-2019 Arm Limited
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
@ -44,11 +44,11 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
*(+RO)
}
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100-Stack_Size) { ; RW data
.ANY (+RW +ZI)
*(+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x400000 EMPTY -Stack_Size { ; Stack region growing down
}

74
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD/startup_MPS2.S
View File

@ -1,6 +1,6 @@
; MPS2 CMSIS Library
;
; Copyright (c) 2006-2016 ARM Limited
; Copyright (c) 2006-2019 Arm Limited
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
@ -38,29 +38,27 @@
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x20400000
PRESERVE8
THUMB
@ -115,14 +113,14 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -237,22 +235,22 @@ UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
B .
ENDP

205
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_GCC_ARM/MPS2.ld Normal file
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@ -0,0 +1,205 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS MPS2.ld for GCC_ARM
*
* Linker script for AN385
*/
#include "../cmsis_nvic.h"
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00400000 /* 4MB ZBTSRAM1 */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00400000 /* 4MB ZBTSRAM2 & ZBTSRAM3 */
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x1000;
STACK_SIZE = 0x400;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = NVIC_NUM_VECTORS * 4;
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(4);
} > FLASH
.text :
{
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM AT > FLASH
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM
.bss :
{
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > RAM
bss_size = __bss_end__ - __bss_start__;
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
} /* End of sections */

203
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S Normal file
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@ -0,0 +1,203 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS startup_MPS2.S for GCC_ARM
*/
.syntax unified
.arch armv7-m
.section .vector_table,"a",%progbits
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long UARTRX0_Handler /* UART 0 RX Handler */
.long UARTTX0_Handler /* UART 0 TX Handler */
.long UARTRX1_Handler /* UART 1 RX Handler */
.long UARTTX1_Handler /* UART 1 TX Handler */
.long UARTRX2_Handler /* UART 2 RX Handler */
.long UARTTX2_Handler /* UART 2 TX Handler */
.long PORT0_COMB_Handler /* GPIO Port 0 Combined Handler */
.long PORT1_COMB_Handler /* GPIO Port 1 Combined Handler */
.long TIMER0_Handler /* TIMER 0 handler */
.long TIMER1_Handler /* TIMER 1 handler */
.long DUALTIMER_Handler /* Dual timer handler */
.long SPI_Handler /* SPI exceptions Handler */
.long UARTOVF_Handler /* UART 0,1,2 Overflow Handler */
.long ETHERNET_Handler /* Ethernet Overflow Handler */
.long I2S_Handler /* I2S Handler */
.long TSC_Handler /* Touch Screen handler */
.long PORT2_COMB_Handler /* GPIO Port 2 Combined Handler */
.long PORT3_COMB_Handler /* GPIO Port 3 Combined Handler */
.long UARTRX3_Handler /* UART 3 RX Handler */
.long UARTTX3_Handler /* UART 3 TX Handler */
.long UARTRX4_Handler /* UART 4 RX Handler */
.long UARTTX4_Handler /* UART 4 TX Handler */
.long ADCSPI_Handler /* SHIELD ADC SPI exceptions Handler */
.long SHIELDSPI_Handler /* SHIELD SPI exceptions Handler */
.long PORT0_0_Handler /* GPIO Port 0 pin 0 Handler */
.long PORT0_1_Handler /* GPIO Port 0 pin 1 Handler */
.long PORT0_2_Handler /* GPIO Port 0 pin 2 Handler */
.long PORT0_3_Handler /* GPIO Port 0 pin 3 Handler */
.long PORT0_4_Handler /* GPIO Port 0 pin 4 Handler */
.long PORT0_5_Handler /* GPIO Port 0 pin 5 Handler */
.long PORT0_6_Handler /* GPIO Port 0 pin 6 Handler */
.long PORT0_7_Handler /* GPIO Port 0 pin 7 Handler */
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/*
* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_loop_end
movs r4, 0
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
/* Initialize .bss */
init_bss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
ldr r3, =bss_size
cmp r3, #0
beq system_startup
mov r4, #0
zero:
strb r4, [r1], #1
subs r3, r3, #1
bne zero
system_startup:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/*
* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers
*/
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
/* External interrupts */
def_irq_default_handler UARTRX0_Handler /* 0: UART 0 RX Handler */
def_irq_default_handler UARTTX0_Handler /* 1: UART 0 TX Handler */
def_irq_default_handler UARTRX1_Handler /* 2: UART 1 RX Handler */
def_irq_default_handler UARTTX1_Handler /* 3: UART 1 TX Handler */
def_irq_default_handler UARTRX2_Handler /* 4: UART 2 RX Handler */
def_irq_default_handler UARTTX2_Handler /* 5: UART 2 TX Handler */
def_irq_default_handler PORT0_COMB_Handler /* 6: GPIO Port 0 combined Handler */
def_irq_default_handler PORT1_COMB_Handler /* 7: GPIO Port 1 combined Handler */
def_irq_default_handler TIMER0_Handler /* 8: TIMER 0 Handler */
def_irq_default_handler TIMER1_Handler /* 9: TIMER 1 Handler */
def_irq_default_handler DUALTIMER_Handler /* 10: Dual Timer Handler */
def_irq_default_handler SPI_Handler /* 11: SPI exceptions Handler */
def_irq_default_handler UARTOVF_Handler /* 12: UART 0,1,2 Overflow Handler */
def_irq_default_handler ETHERNET_Handler /* 13: Ethernet Overflow Handler */
def_irq_default_handler I2S_Handler /* 14: I2S Handler */
def_irq_default_handler TSC_Handler /* 15: Touch Screen Handler */
def_irq_default_handler PORT2_COMB_Handler /* 16: GPIO Port 2 combined Handler */
def_irq_default_handler PORT3_COMB_Handler /* 17: GPIO Port 3 combined Handler */
def_irq_default_handler UARTRX3_Handler /* 18: UART 3 RX Handler */
def_irq_default_handler UARTTX3_Handler /* 19: UART 3 TX Handler */
def_irq_default_handler UARTRX4_Handler /* 20: UART 4 RX Handler */
def_irq_default_handler UARTTX4_Handler /* 21: UART 4 TX Handler */
def_irq_default_handler ADCSPI_Handler /* 22: SHIELD ADC SPI exceptions Handlre */
def_irq_default_handler SHIELDSPI_Handler /* 23: SHIELD SPI exceptions Handlre */
def_irq_default_handler PORT0_0_Handler /* 24: GPIO Port 0 pin 0 Handler */
def_irq_default_handler PORT0_1_Handler /* 25: GPIO Port 0 pin 1 Handler */
def_irq_default_handler PORT0_2_Handler /* 26: GPIO Port 0 pin 2 Handler */
def_irq_default_handler PORT0_3_Handler /* 27: GPIO Port 0 pin 3 Handler */
def_irq_default_handler PORT0_4_Handler /* 28: GPIO Port 0 pin 4 Handler */
def_irq_default_handler PORT0_5_Handler /* 29: GPIO Port 0 pin 5 Handler */
def_irq_default_handler PORT0_6_Handler /* 30: GPIO Port 0 pin 6 Handler */
def_irq_default_handler PORT0_7_Handler /* 31: GPIO Port 0 pin 7 Handler */
.end

66
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_IAR/MPS2.icf Normal file
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@ -0,0 +1,66 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License) you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS MPS2.icf for IAR
*/
/* Code memory zones */
define symbol ZBT_SSRAM1_START = 0x00000000;
define symbol ZBT_SSRAM1_SIZE = 0x00400000; /* 4 MiB */
/* Data memory zones */
define symbol ZBT_SSRAM23_START = 0x20000000;
define symbol ZBT_SSRAM23_SIZE = 0x00400000; /* 4 MiB */
/* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = 16 + 48;
define symbol NVIC_VECTORS_SIZE = NVIC_NUM_VECTORS * 4;
/* Specials */
define symbol __ICFEDIT_intvec_start__ = ZBT_SSRAM1_START;
/* Memory Regions */
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SSRAM1_START;
define symbol __ICFEDIT_region_ROM_end__ = ZBT_SSRAM1_START + ZBT_SSRAM1_SIZE - 1;
/*
* At execution, RAM is set to be in ZBT SSRAM2 and 3, just after the vector
* table previously moved from Flash.
*/
define symbol __ICFEDIT_region_RAM_start__ = ZBT_SSRAM23_START + NVIC_VECTORS_SIZE;
define symbol __ICFEDIT_region_RAM_end__ = ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE;
/* Sizes */
/* Heap and Stack size */
define symbol __ICFEDIT_size_heap__ = 0x1000;
define symbol __ICFEDIT_size_cstack__ = 0x400;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
initialize by copy { readwrite };
do not initialize { section .noinit };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

337
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_IAR/startup_MPS2.S Normal file
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@ -0,0 +1,337 @@
;/*
; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
; * This file is derivative of mbed-os V5.10.4 startup_MPS2.S for IAR
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UARTRX0_Handler ; UART 0 RX Handler
DCD UARTTX0_Handler ; UART 0 TX Handler
DCD UARTRX1_Handler ; UART 1 RX Handler
DCD UARTTX1_Handler ; UART 1 TX Handler
DCD UARTRX2_Handler ; UART 2 RX Handler
DCD UARTTX2_Handler ; UART 2 TX Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
DCD SPI_Handler ; SPI exceptions Handler
DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
DCD UARTRX3_Handler ; UART 3 RX Handler
DCD UARTTX3_Handler ; UART 3 TX Handler
DCD UARTRX4_Handler ; UART 4 RX Handler
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK UARTRX0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX0_Handler
B UARTRX0_Handler
PUBWEAK UARTTX0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX0_Handler
B UARTTX0_Handler
PUBWEAK UARTRX1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX1_Handler
B UARTRX1_Handler
PUBWEAK UARTTX1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX1_Handler
B UARTTX1_Handler
PUBWEAK UARTRX2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX2_Handler
B UARTRX2_Handler
PUBWEAK UARTTX2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX2_Handler
B UARTTX2_Handler
PUBWEAK PORT0_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_COMB_Handler
B PORT0_COMB_Handler
PUBWEAK PORT1_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT1_COMB_Handler
B PORT1_COMB_Handler
PUBWEAK TIMER0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER0_Handler
B TIMER0_Handler
PUBWEAK TIMER1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER1_Handler
B TIMER1_Handler
PUBWEAK DUALTIMER_HANDLER
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER_HANDLER
B DUALTIMER_HANDLER
PUBWEAK SPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI_Handler
B SPI_Handler
PUBWEAK UARTOVF_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTOVF_Handler
B UARTOVF_Handler
PUBWEAK ETHERNET_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ETHERNET_Handler
B ETHERNET_Handler
PUBWEAK I2S_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2S_Handler
B I2S_Handler
PUBWEAK TSC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TSC_Handler
B TSC_Handler
PUBWEAK PORT2_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT2_COMB_Handler
B PORT2_COMB_Handler
PUBWEAK PORT3_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT3_COMB_Handler
B PORT3_COMB_Handler
PUBWEAK UARTRX3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX3_Handler
B UARTRX3_Handler
PUBWEAK UARTTX3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX3_Handler
B UARTTX3_Handler
PUBWEAK UARTRX4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX4_Handler
B UARTRX4_Handler
PUBWEAK UARTTX4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX4_Handler
B UARTTX4_Handler
PUBWEAK ADCSPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ADCSPI_Handler
B ADCSPI_Handler
PUBWEAK SHIELDSPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SHIELDSPI_Handler
B SHIELDSPI_Handler
PUBWEAK PORT0_0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_0_Handler
B PORT0_0_Handler
PUBWEAK PORT0_1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_1_Handler
B PORT0_1_Handler
PUBWEAK PORT0_2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_2_Handler
B PORT0_2_Handler
PUBWEAK PORT0_3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_3_Handler
B PORT0_3_Handler
PUBWEAK PORT0_4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_4_Handler
B PORT0_4_Handler
PUBWEAK PORT0_5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_5_Handler
B PORT0_5_Handler
PUBWEAK PORT0_6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_6_Handler
B PORT0_6_Handler
PUBWEAK PORT0_7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_7_Handler
B PORT0_7_Handler
END

6
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -2,7 +2,7 @@
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2016 ARM Limited
;* Copyright (c) 2006-2019 Arm Limited
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
@ -45,11 +45,11 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
*(+RO)
}
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100-Stack_Size) { ; RW data
.ANY (+RW +ZI)
*(+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x400000 EMPTY -Stack_Size { ; Stack region growing down
}

74
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD/startup_MPS2.S
View File

@ -1,6 +1,6 @@
; MPS2 CMSIS Library
;
; Copyright (c) 2006-2016 ARM Limited
; Copyright (c) 2006-2019 Arm Limited
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
@ -38,29 +38,27 @@
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x20400000
PRESERVE8
THUMB
@ -115,14 +113,14 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -237,22 +235,22 @@ UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
B .
ENDP

205
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_GCC_ARM/MPS2.ld Normal file
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@ -0,0 +1,205 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS MPS2.ld for GCC_ARM
*
* Linker script for AN386
*/
#include "../cmsis_nvic.h"
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00400000 /* 4MB ZBTSRAM1 */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00400000 /* 4MB ZBTSRAM2 & ZBTSRAM3 */
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x1000;
STACK_SIZE = 0x400;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = NVIC_NUM_VECTORS * 4;
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(4);
} > FLASH
.text :
{
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM AT > FLASH
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM
.bss :
{
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > RAM
bss_size = __bss_end__ - __bss_start__;
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
} /* End of sections */

203
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S Normal file
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/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS startup_MPS2.S for GCC_ARM
*/
.syntax unified
.arch armv7-m
.section .vector_table,"a",%progbits
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long UARTRX0_Handler /* UART 0 RX Handler */
.long UARTTX0_Handler /* UART 0 TX Handler */
.long UARTRX1_Handler /* UART 1 RX Handler */
.long UARTTX1_Handler /* UART 1 TX Handler */
.long UARTRX2_Handler /* UART 2 RX Handler */
.long UARTTX2_Handler /* UART 2 TX Handler */
.long PORT0_COMB_Handler /* GPIO Port 0 Combined Handler */
.long PORT1_COMB_Handler /* GPIO Port 1 Combined Handler */
.long TIMER0_Handler /* TIMER 0 handler */
.long TIMER1_Handler /* TIMER 1 handler */
.long DUALTIMER_Handler /* Dual timer handler */
.long SPI_Handler /* SPI exceptions Handler */
.long UARTOVF_Handler /* UART 0,1,2 Overflow Handler */
.long ETHERNET_Handler /* Ethernet Overflow Handler */
.long I2S_Handler /* I2S Handler */
.long TSC_Handler /* Touch Screen handler */
.long PORT2_COMB_Handler /* GPIO Port 2 Combined Handler */
.long PORT3_COMB_Handler /* GPIO Port 3 Combined Handler */
.long UARTRX3_Handler /* UART 3 RX Handler */
.long UARTTX3_Handler /* UART 3 TX Handler */
.long UARTRX4_Handler /* UART 4 RX Handler */
.long UARTTX4_Handler /* UART 4 TX Handler */
.long ADCSPI_Handler /* SHIELD ADC SPI exceptions Handler */
.long SHIELDSPI_Handler /* SHIELD SPI exceptions Handler */
.long PORT0_0_Handler /* GPIO Port 0 pin 0 Handler */
.long PORT0_1_Handler /* GPIO Port 0 pin 1 Handler */
.long PORT0_2_Handler /* GPIO Port 0 pin 2 Handler */
.long PORT0_3_Handler /* GPIO Port 0 pin 3 Handler */
.long PORT0_4_Handler /* GPIO Port 0 pin 4 Handler */
.long PORT0_5_Handler /* GPIO Port 0 pin 5 Handler */
.long PORT0_6_Handler /* GPIO Port 0 pin 6 Handler */
.long PORT0_7_Handler /* GPIO Port 0 pin 7 Handler */
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/*
* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_loop_end
movs r4, 0
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
/* Initialize .bss */
init_bss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
ldr r3, =bss_size
cmp r3, #0
beq system_startup
mov r4, #0
zero:
strb r4, [r1], #1
subs r3, r3, #1
bne zero
system_startup:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/*
* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers
*/
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
/* External interrupts */
def_irq_default_handler UARTRX0_Handler /* 0: UART 0 RX Handler */
def_irq_default_handler UARTTX0_Handler /* 1: UART 0 TX Handler */
def_irq_default_handler UARTRX1_Handler /* 2: UART 1 RX Handler */
def_irq_default_handler UARTTX1_Handler /* 3: UART 1 TX Handler */
def_irq_default_handler UARTRX2_Handler /* 4: UART 2 RX Handler */
def_irq_default_handler UARTTX2_Handler /* 5: UART 2 TX Handler */
def_irq_default_handler PORT0_COMB_Handler /* 6: GPIO Port 0 combined Handler */
def_irq_default_handler PORT1_COMB_Handler /* 7: GPIO Port 1 combined Handler */
def_irq_default_handler TIMER0_Handler /* 8: TIMER 0 Handler */
def_irq_default_handler TIMER1_Handler /* 9: TIMER 1 Handler */
def_irq_default_handler DUALTIMER_Handler /* 10: Dual Timer Handler */
def_irq_default_handler SPI_Handler /* 11: SPI exceptions Handler */
def_irq_default_handler UARTOVF_Handler /* 12: UART 0,1,2 Overflow Handler */
def_irq_default_handler ETHERNET_Handler /* 13: Ethernet Overflow Handler */
def_irq_default_handler I2S_Handler /* 14: I2S Handler */
def_irq_default_handler TSC_Handler /* 15: Touch Screen Handler */
def_irq_default_handler PORT2_COMB_Handler /* 16: GPIO Port 2 combined Handler */
def_irq_default_handler PORT3_COMB_Handler /* 17: GPIO Port 3 combined Handler */
def_irq_default_handler UARTRX3_Handler /* 18: UART 3 RX Handler */
def_irq_default_handler UARTTX3_Handler /* 19: UART 3 TX Handler */
def_irq_default_handler UARTRX4_Handler /* 20: UART 4 RX Handler */
def_irq_default_handler UARTTX4_Handler /* 21: UART 4 TX Handler */
def_irq_default_handler ADCSPI_Handler /* 22: SHIELD ADC SPI exceptions Handlre */
def_irq_default_handler SHIELDSPI_Handler /* 23: SHIELD SPI exceptions Handlre */
def_irq_default_handler PORT0_0_Handler /* 24: GPIO Port 0 pin 0 Handler */
def_irq_default_handler PORT0_1_Handler /* 25: GPIO Port 0 pin 1 Handler */
def_irq_default_handler PORT0_2_Handler /* 26: GPIO Port 0 pin 2 Handler */
def_irq_default_handler PORT0_3_Handler /* 27: GPIO Port 0 pin 3 Handler */
def_irq_default_handler PORT0_4_Handler /* 28: GPIO Port 0 pin 4 Handler */
def_irq_default_handler PORT0_5_Handler /* 29: GPIO Port 0 pin 5 Handler */
def_irq_default_handler PORT0_6_Handler /* 30: GPIO Port 0 pin 6 Handler */
def_irq_default_handler PORT0_7_Handler /* 31: GPIO Port 0 pin 7 Handler */
.end

65
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_IAR/MPS2.icf Normal file
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/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License) you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS MPS2.icf for IAR
*/
/* Code memory zones */
define symbol ZBT_SSRAM1_START = 0x00000000;
define symbol ZBT_SSRAM1_SIZE = 0x00400000; /* 4 MiB */
/* Data memory zones */
define symbol ZBT_SSRAM23_START = 0x20000000;
define symbol ZBT_SSRAM23_SIZE = 0x00400000; /* 4 MiB */
/* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = 16 + 48;
define symbol NVIC_VECTORS_SIZE = NVIC_NUM_VECTORS * 4;
/* Specials */
define symbol __ICFEDIT_intvec_start__ = ZBT_SSRAM1_START;
/* Memory Regions */
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SSRAM1_START;
define symbol __ICFEDIT_region_ROM_end__ = ZBT_SSRAM1_START + ZBT_SSRAM1_SIZE - 1;
/*
* At execution, RAM is set to be in ZBT SSRAM2 and 3, just after the vector
* table previously moved from Flash.
*/
define symbol __ICFEDIT_region_RAM_start__ = ZBT_SSRAM23_START + NVIC_VECTORS_SIZE;
define symbol __ICFEDIT_region_RAM_end__ = ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE;
/* Sizes */
/* Heap and Stack size */
define symbol __ICFEDIT_size_heap__ = 0x1000;
define symbol __ICFEDIT_size_cstack__ = 0x400;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
initialize by copy { readwrite };
do not initialize { section .noinit };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

337
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_IAR/startup_MPS2.S Normal file
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;/*
; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
; * This file is derivative of mbed-os V5.10.4 CM3DS startup_MPS2.S for IAR
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UARTRX0_Handler ; UART 0 RX Handler
DCD UARTTX0_Handler ; UART 0 TX Handler
DCD UARTRX1_Handler ; UART 1 RX Handler
DCD UARTTX1_Handler ; UART 1 TX Handler
DCD UARTRX2_Handler ; UART 2 RX Handler
DCD UARTTX2_Handler ; UART 2 TX Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
DCD SPI_Handler ; SPI exceptions Handler
DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
DCD UARTRX3_Handler ; UART 3 RX Handler
DCD UARTTX3_Handler ; UART 3 TX Handler
DCD UARTRX4_Handler ; UART 4 RX Handler
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK UARTRX0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX0_Handler
B UARTRX0_Handler
PUBWEAK UARTTX0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX0_Handler
B UARTTX0_Handler
PUBWEAK UARTRX1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX1_Handler
B UARTRX1_Handler
PUBWEAK UARTTX1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX1_Handler
B UARTTX1_Handler
PUBWEAK UARTRX2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX2_Handler
B UARTRX2_Handler
PUBWEAK UARTTX2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX2_Handler
B UARTTX2_Handler
PUBWEAK PORT0_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_COMB_Handler
B PORT0_COMB_Handler
PUBWEAK PORT1_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT1_COMB_Handler
B PORT1_COMB_Handler
PUBWEAK TIMER0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER0_Handler
B TIMER0_Handler
PUBWEAK TIMER1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER1_Handler
B TIMER1_Handler
PUBWEAK DUALTIMER_HANDLER
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER_HANDLER
B DUALTIMER_HANDLER
PUBWEAK SPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI_Handler
B SPI_Handler
PUBWEAK UARTOVF_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTOVF_Handler
B UARTOVF_Handler
PUBWEAK ETHERNET_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ETHERNET_Handler
B ETHERNET_Handler
PUBWEAK I2S_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2S_Handler
B I2S_Handler
PUBWEAK TSC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TSC_Handler
B TSC_Handler
PUBWEAK PORT2_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT2_COMB_Handler
B PORT2_COMB_Handler
PUBWEAK PORT3_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT3_COMB_Handler
B PORT3_COMB_Handler
PUBWEAK UARTRX3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX3_Handler
B UARTRX3_Handler
PUBWEAK UARTTX3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX3_Handler
B UARTTX3_Handler
PUBWEAK UARTRX4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX4_Handler
B UARTRX4_Handler
PUBWEAK UARTTX4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX4_Handler
B UARTTX4_Handler
PUBWEAK ADCSPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ADCSPI_Handler
B ADCSPI_Handler
PUBWEAK SHIELDSPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SHIELDSPI_Handler
B SHIELDSPI_Handler
PUBWEAK PORT0_0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_0_Handler
B PORT0_0_Handler
PUBWEAK PORT0_1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_1_Handler
B PORT0_1_Handler
PUBWEAK PORT0_2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_2_Handler
B PORT0_2_Handler
PUBWEAK PORT0_3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_3_Handler
B PORT0_3_Handler
PUBWEAK PORT0_4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_4_Handler
B PORT0_4_Handler
PUBWEAK PORT0_5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_5_Handler
B PORT0_5_Handler
PUBWEAK PORT0_6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_6_Handler
B PORT0_6_Handler
PUBWEAK PORT0_7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_7_Handler
B PORT0_7_Handler
END

50
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct
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@ -2,34 +2,34 @@
;* MPS2 CMSIS Library
;*
;* Copyright (c) 2006-2016 ARM Limited
;* Copyright (c) 2006-2019 Arm Limited
;* All rights reserved.
;*
;* Redistribution and use in source and binary forms, with or without
;*
;* Redistribution and use in source and binary forms, with or without
;* modification, are permitted provided that the following conditions are met:
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;*
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;*
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;*
;* 3. Neither the name of the copyright holder nor the names of its contributors
;* may be used to endorse or promote products derived from this software without
;* specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
;* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;* POSSIBILITY OF SUCH DAMAGE.
;*
; *************************************************************
; *** Scatter-Loading Description File ***
@ -45,11 +45,11 @@ LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 0x00000000 0x00400000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
*(+RO)
}
; Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (0x20000000+0x100) (0x400000-0x100-Stack_Size) { ; RW data
.ANY (+RW +ZI)
*(+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x400000 EMPTY -Stack_Size { ; Stack region growing down
}

118
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.S
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@ -1,33 +1,33 @@
; MPS2 CMSIS Library
;
; Copyright (c) 2006-2016 ARM Limited
; Copyright (c) 2006-2019 Arm Limited
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
;
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
;
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
;
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
;******************************************************************************
; @file startup_CMSDK_CM7.s
; @brief CMSIS Core Device Startup File for
@ -38,29 +38,27 @@
;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x20400000
PRESERVE8
THUMB
@ -115,14 +113,14 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
@ -237,22 +235,22 @@ UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT2_COMB_Handler
PORT3_COMB_Handler
UARTRX3_Handler
UARTTX3_Handler
UARTRX4_Handler
UARTTX4_Handler
ADCSPI_Handler
SHIELDSPI_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
B .
ENDP

205
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_GCC_ARM/MPS2.ld Normal file
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@ -0,0 +1,205 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS MPS2.ld for GCC_ARM
*
* Linker script for AN500
*/
#include "../cmsis_nvic.h"
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00400000 /* 4MB ZBTSRAM1 */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00400000 /* 4MB ZBTSRAM2 & ZBTSRAM3 */
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
HEAP_SIZE = 0x1000;
STACK_SIZE = 0x400;
/* Size of the vector table in SRAM */
M_VECTOR_RAM_SIZE = NVIC_NUM_VECTORS * 4;
SECTIONS
{
.isr_vector :
{
__vector_table = .;
KEEP(*(.vector_table))
. = ALIGN(4);
} > FLASH
.text :
{
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
.interrupts_ram :
{
. = ALIGN(4);
__VECTOR_RAM__ = .;
__interrupts_ram_start__ = .; /* Create a global symbol at data start */
. += M_VECTOR_RAM_SIZE;
. = ALIGN(4);
__interrupts_ram_end__ = .; /* Define a global symbol at data end */
} > RAM
.data :
{
PROVIDE(__etext = LOADADDR(.data));
. = ALIGN(4);
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM AT > FLASH
.uninitialized (NOLOAD):
{
. = ALIGN(32);
__uninitialized_start = .;
*(.uninitialized)
KEEP(*(.keep.uninitialized))
. = ALIGN(32);
__uninitialized_end = .;
} > RAM
.bss :
{
. = ALIGN(4);
__START_BSS = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
__END_BSS = .;
} > RAM
bss_size = __bss_end__ - __bss_start__;
.heap :
{
. = ALIGN(8);
__end__ = .;
PROVIDE(end = .);
__HeapBase = .;
. += HEAP_SIZE;
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
} /* End of sections */

203
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_GCC_ARM/startup_MPS2.S Normal file
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@ -0,0 +1,203 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS startup_MPS2.S for GCC_ARM
*/
.syntax unified
.arch armv7-m
.section .vector_table,"a",%progbits
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long UARTRX0_Handler /* UART 0 RX Handler */
.long UARTTX0_Handler /* UART 0 TX Handler */
.long UARTRX1_Handler /* UART 1 RX Handler */
.long UARTTX1_Handler /* UART 1 TX Handler */
.long UARTRX2_Handler /* UART 2 RX Handler */
.long UARTTX2_Handler /* UART 2 TX Handler */
.long PORT0_COMB_Handler /* GPIO Port 0 Combined Handler */
.long PORT1_COMB_Handler /* GPIO Port 1 Combined Handler */
.long TIMER0_Handler /* TIMER 0 handler */
.long TIMER1_Handler /* TIMER 1 handler */
.long DUALTIMER_Handler /* Dual timer handler */
.long SPI_Handler /* SPI exceptions Handler */
.long UARTOVF_Handler /* UART 0,1,2 Overflow Handler */
.long ETHERNET_Handler /* Ethernet Overflow Handler */
.long I2S_Handler /* I2S Handler */
.long TSC_Handler /* Touch Screen handler */
.long PORT2_COMB_Handler /* GPIO Port 2 Combined Handler */
.long PORT3_COMB_Handler /* GPIO Port 3 Combined Handler */
.long UARTRX3_Handler /* UART 3 RX Handler */
.long UARTTX3_Handler /* UART 3 TX Handler */
.long UARTRX4_Handler /* UART 4 RX Handler */
.long UARTTX4_Handler /* UART 4 TX Handler */
.long ADCSPI_Handler /* SHIELD ADC SPI exceptions Handler */
.long SHIELDSPI_Handler /* SHIELD SPI exceptions Handler */
.long PORT0_0_Handler /* GPIO Port 0 pin 0 Handler */
.long PORT0_1_Handler /* GPIO Port 0 pin 1 Handler */
.long PORT0_2_Handler /* GPIO Port 0 pin 2 Handler */
.long PORT0_3_Handler /* GPIO Port 0 pin 3 Handler */
.long PORT0_4_Handler /* GPIO Port 0 pin 4 Handler */
.long PORT0_5_Handler /* GPIO Port 0 pin 5 Handler */
.long PORT0_6_Handler /* GPIO Port 0 pin 6 Handler */
.long PORT0_7_Handler /* GPIO Port 0 pin 7 Handler */
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/*
* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .Lflash_to_ram_loop_end
movs r4, 0
.Lflash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .Lflash_to_ram_loop
.Lflash_to_ram_loop_end:
/* Initialize .bss */
init_bss:
ldr r1, =__bss_start__
ldr r2, =__bss_end__
ldr r3, =bss_size
cmp r3, #0
beq system_startup
mov r4, #0
zero:
strb r4, [r1], #1
subs r3, r3, #1
bne zero
system_startup:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/*
* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers
*/
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
/* External interrupts */
def_irq_default_handler UARTRX0_Handler /* 0: UART 0 RX Handler */
def_irq_default_handler UARTTX0_Handler /* 1: UART 0 TX Handler */
def_irq_default_handler UARTRX1_Handler /* 2: UART 1 RX Handler */
def_irq_default_handler UARTTX1_Handler /* 3: UART 1 TX Handler */
def_irq_default_handler UARTRX2_Handler /* 4: UART 2 RX Handler */
def_irq_default_handler UARTTX2_Handler /* 5: UART 2 TX Handler */
def_irq_default_handler PORT0_COMB_Handler /* 6: GPIO Port 0 combined Handler */
def_irq_default_handler PORT1_COMB_Handler /* 7: GPIO Port 1 combined Handler */
def_irq_default_handler TIMER0_Handler /* 8: TIMER 0 Handler */
def_irq_default_handler TIMER1_Handler /* 9: TIMER 1 Handler */
def_irq_default_handler DUALTIMER_Handler /* 10: Dual Timer Handler */
def_irq_default_handler SPI_Handler /* 11: SPI exceptions Handler */
def_irq_default_handler UARTOVF_Handler /* 12: UART 0,1,2 Overflow Handler */
def_irq_default_handler ETHERNET_Handler /* 13: Ethernet Overflow Handler */
def_irq_default_handler I2S_Handler /* 14: I2S Handler */
def_irq_default_handler TSC_Handler /* 15: Touch Screen Handler */
def_irq_default_handler PORT2_COMB_Handler /* 16: GPIO Port 2 combined Handler */
def_irq_default_handler PORT3_COMB_Handler /* 17: GPIO Port 3 combined Handler */
def_irq_default_handler UARTRX3_Handler /* 18: UART 3 RX Handler */
def_irq_default_handler UARTTX3_Handler /* 19: UART 3 TX Handler */
def_irq_default_handler UARTRX4_Handler /* 20: UART 4 RX Handler */
def_irq_default_handler UARTTX4_Handler /* 21: UART 4 TX Handler */
def_irq_default_handler ADCSPI_Handler /* 22: SHIELD ADC SPI exceptions Handlre */
def_irq_default_handler SHIELDSPI_Handler /* 23: SHIELD SPI exceptions Handlre */
def_irq_default_handler PORT0_0_Handler /* 24: GPIO Port 0 pin 0 Handler */
def_irq_default_handler PORT0_1_Handler /* 25: GPIO Port 0 pin 1 Handler */
def_irq_default_handler PORT0_2_Handler /* 26: GPIO Port 0 pin 2 Handler */
def_irq_default_handler PORT0_3_Handler /* 27: GPIO Port 0 pin 3 Handler */
def_irq_default_handler PORT0_4_Handler /* 28: GPIO Port 0 pin 4 Handler */
def_irq_default_handler PORT0_5_Handler /* 29: GPIO Port 0 pin 5 Handler */
def_irq_default_handler PORT0_6_Handler /* 30: GPIO Port 0 pin 6 Handler */
def_irq_default_handler PORT0_7_Handler /* 31: GPIO Port 0 pin 7 Handler */
.end

65
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_IAR/MPS2.icf Normal file
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@ -0,0 +1,65 @@
/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License) you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of mbed-os V5.10.4 CM3DS MPS2.icf for IAR
*/
/* Code memory zones */
define symbol ZBT_SSRAM1_START = 0x00000000;
define symbol ZBT_SSRAM1_SIZE = 0x00400000; /* 4 MiB */
/* Data memory zones */
define symbol ZBT_SSRAM23_START = 0x20000000;
define symbol ZBT_SSRAM23_SIZE = 0x00400000; /* 4 MiB */
/* NVIC vector numbers and size. */
define symbol NVIC_NUM_VECTORS = 16 + 48;
define symbol NVIC_VECTORS_SIZE = NVIC_NUM_VECTORS * 4;
/* Specials */
define symbol __ICFEDIT_intvec_start__ = ZBT_SSRAM1_START;
/* Memory Regions */
define symbol __ICFEDIT_region_ROM_start__ = ZBT_SSRAM1_START;
define symbol __ICFEDIT_region_ROM_end__ = ZBT_SSRAM1_START + ZBT_SSRAM1_SIZE - 1;
/*
* At execution, RAM is set to be in ZBT SSRAM2 and 3, just after the vector
* table previously moved from Flash.
*/
define symbol __ICFEDIT_region_RAM_start__ = ZBT_SSRAM23_START + NVIC_VECTORS_SIZE;
define symbol __ICFEDIT_region_RAM_end__ = ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE;
/* Sizes */
/* Heap and Stack size */
define symbol __ICFEDIT_size_heap__ = 0x1000;
define symbol __ICFEDIT_size_cstack__ = 0x400;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
initialize by copy { readwrite };
do not initialize { section .noinit };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

337
targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_IAR/startup_MPS2.S Normal file
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@ -0,0 +1,337 @@
;/*
; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
; * This file is derivative of mbed-os V5.10.4 CM3DS startup_MPS2.S for IAR
; */
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UARTRX0_Handler ; UART 0 RX Handler
DCD UARTTX0_Handler ; UART 0 TX Handler
DCD UARTRX1_Handler ; UART 1 RX Handler
DCD UARTTX1_Handler ; UART 1 TX Handler
DCD UARTRX2_Handler ; UART 2 RX Handler
DCD UARTTX2_Handler ; UART 2 TX Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
DCD SPI_Handler ; SPI exceptions Handler
DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler
DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler
DCD UARTRX3_Handler ; UART 3 RX Handler
DCD UARTTX3_Handler ; UART 3 TX Handler
DCD UARTRX4_Handler ; UART 4 RX Handler
DCD UARTTX4_Handler ; UART 4 TX Handler
DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler
DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK UARTRX0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX0_Handler
B UARTRX0_Handler
PUBWEAK UARTTX0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX0_Handler
B UARTTX0_Handler
PUBWEAK UARTRX1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX1_Handler
B UARTRX1_Handler
PUBWEAK UARTTX1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX1_Handler
B UARTTX1_Handler
PUBWEAK UARTRX2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX2_Handler
B UARTRX2_Handler
PUBWEAK UARTTX2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX2_Handler
B UARTTX2_Handler
PUBWEAK PORT0_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_COMB_Handler
B PORT0_COMB_Handler
PUBWEAK PORT1_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT1_COMB_Handler
B PORT1_COMB_Handler
PUBWEAK TIMER0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER0_Handler
B TIMER0_Handler
PUBWEAK TIMER1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER1_Handler
B TIMER1_Handler
PUBWEAK DUALTIMER_HANDLER
SECTION .text:CODE:REORDER:NOROOT(1)
DUALTIMER_HANDLER
B DUALTIMER_HANDLER
PUBWEAK SPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SPI_Handler
B SPI_Handler
PUBWEAK UARTOVF_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTOVF_Handler
B UARTOVF_Handler
PUBWEAK ETHERNET_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ETHERNET_Handler
B ETHERNET_Handler
PUBWEAK I2S_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
I2S_Handler
B I2S_Handler
PUBWEAK TSC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
TSC_Handler
B TSC_Handler
PUBWEAK PORT2_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT2_COMB_Handler
B PORT2_COMB_Handler
PUBWEAK PORT3_COMB_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT3_COMB_Handler
B PORT3_COMB_Handler
PUBWEAK UARTRX3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX3_Handler
B UARTRX3_Handler
PUBWEAK UARTTX3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX3_Handler
B UARTTX3_Handler
PUBWEAK UARTRX4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTRX4_Handler
B UARTRX4_Handler
PUBWEAK UARTTX4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UARTTX4_Handler
B UARTTX4_Handler
PUBWEAK ADCSPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
ADCSPI_Handler
B ADCSPI_Handler
PUBWEAK SHIELDSPI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SHIELDSPI_Handler
B SHIELDSPI_Handler
PUBWEAK PORT0_0_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_0_Handler
B PORT0_0_Handler
PUBWEAK PORT0_1_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_1_Handler
B PORT0_1_Handler
PUBWEAK PORT0_2_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_2_Handler
B PORT0_2_Handler
PUBWEAK PORT0_3_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_3_Handler
B PORT0_3_Handler
PUBWEAK PORT0_4_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_4_Handler
B PORT0_4_Handler
PUBWEAK PORT0_5_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_5_Handler
B PORT0_5_Handler
PUBWEAK PORT0_6_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_6_Handler
B PORT0_6_Handler
PUBWEAK PORT0_7_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PORT0_7_Handler
B PORT0_7_Handler
END

8
targets/TARGET_ARM_SSG/mbed_rtx.h
View File

@ -23,6 +23,14 @@
#define INITIAL_SP (0x20020000UL)
#endif
#elif defined(TARGET_MPS2_M0) || defined(TARGET_MPS2_M0P) || \
defined(TARGET_MPS2_M3) || defined(TARGET_MPS2_M4) || \
defined(TARGET_MPS2_M7)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20400000UL)
#endif
#elif defined(TARGET_CM3DS_MPS2)
#include "memory_zones.h"

43
targets/targets.json
View File

@ -5205,7 +5205,7 @@
"ARM_MPS2_M0": {
"inherits": ["ARM_MPS2_Target"],
"core": "Cortex-M0",
"supported_toolchains": ["ARM"],
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0"],
"macros": [
"CMSDK_CM0",
@ -5226,14 +5226,16 @@
"SPI",
"SPISLAVE",
"TSC",
"MPU"
"USTICKER"
],
"release_versions": ["2"]
"release_versions": ["2", "5"],
"copy_method": "mps2",
"reset_method": "reboot.txt"
},
"ARM_MPS2_M0P": {
"inherits": ["ARM_MPS2_Target"],
"core": "Cortex-M0+",
"supported_toolchains": ["ARM"],
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0P"],
"macros": ["CMSDK_CM0plus"],
"device_has": [
@ -5250,14 +5252,16 @@
"SPI",
"SPISLAVE",
"TSC",
"MPU"
"USTICKER"
],
"release_versions": ["2"]
"release_versions": ["2", "5"],
"copy_method": "mps2",
"reset_method": "reboot.txt"
},
"ARM_MPS2_M3": {
"inherits": ["ARM_MPS2_Target"],
"core": "Cortex-M3",
"supported_toolchains": ["ARM"],
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"extra_labels": ["ARM_SSG", "MPS2", "MPS2_M3"],
"macros": ["CMSDK_CM3"],
"device_has": [
@ -5274,14 +5278,17 @@
"SPI",
"SPISLAVE",
"TSC",
"MPU"
"MPU",
"USTICKER"
],
"release_versions": ["2"]
"release_versions": ["2", "5"],
"copy_method": "mps2",
"reset_method": "reboot.txt"
},
"ARM_MPS2_M4": {
"inherits": ["ARM_MPS2_Target"],
"core": "Cortex-M4F",
"supported_toolchains": ["ARM"],
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"extra_labels": ["ARM_SSG", "MPS2", "MPS2_M4"],
"macros": ["CMSDK_CM4"],
"device_has": [
@ -5298,14 +5305,17 @@
"SPI",
"SPISLAVE",
"TSC",
"MPU"
"MPU",
"USTICKER"
],
"release_versions": ["2"]
"release_versions": ["2", "5"],
"copy_method": "mps2",
"reset_method": "reboot.txt"
},
"ARM_MPS2_M7": {
"inherits": ["ARM_MPS2_Target"],
"core": "Cortex-M7",
"supported_toolchains": ["ARM"],
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"extra_labels": ["ARM_SSG", "MPS2", "MPS2_M7"],
"macros": ["CMSDK_CM7"],
"device_has": [
@ -5322,9 +5332,12 @@
"SPI",
"SPISLAVE",
"TSC",
"MPU"
"MPU",
"USTICKER"
],
"release_versions": ["2"]
"release_versions": ["2", "5"],
"copy_method": "mps2",
"reset_method": "reboot.txt"
},
"ARM_IOTSS_Target": {
"inherits": ["Target"],