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Only GCC_ARM toolchain is supported, removing legacy code

pull/9714/head
deepikabhavnani 2019-02-13 16:19:53 -06:00
parent 8f932a476f
commit 818d38b6ae
28 changed files with 3 additions and 5495 deletions
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6
platform/mbed_retarget.cpp
View File

@ -1203,7 +1203,7 @@ extern "C" WEAK void __cxa_pure_virtual(void)
// Provide implementation of _sbrk (low-level dynamic memory allocation
// routine) for GCC_ARM which compares new heap pointer with MSP instead of
// SP. This make it compatible with RTX RTOS thread stacks.
#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR)
#if defined(TOOLCHAIN_GCC_ARM)
#if defined(TARGET_CORTEX_A)
extern "C" uint32_t __HeapLimit;
@ -1255,7 +1255,7 @@ extern "C" WEAK caddr_t _sbrk(int incr)
#endif
#endif
#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR)
#if defined(TOOLCHAIN_GCC_ARM)
extern "C" void _exit(int return_code)
{
#else
@ -1285,7 +1285,7 @@ extern "C" void exit(int return_code)
while (1);
}
#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CR)
#if !defined(TOOLCHAIN_GCC_ARM)
} //namespace std
#endif

201
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld
View File

@ -1,201 +0,0 @@
/*
*****************************************************************************
**
** File : KL25Z128M4_flash.ld
**
** Default linker command file for Flash targets
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(__thumb_startup)
/* Highest address of the user mode stack */
_estack = 0x20003000; /* end of SRAM */
__SP_INIT = _estack;
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Generate a link error if heap and stack don't fit into RAM */
__heap_size = 0x400; /* required amount of heap */
__stack_size = MBED_BOOT_STACK_SIZE; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
m_interrupts (rx) : ORIGIN = 0x00000000, LENGTH = 0xC0
m_cfmprotrom (rx) : ORIGIN = 0x00000400, LENGTH = 0x10
m_text (rx) : ORIGIN = 0x00000800, LENGTH = 128K - 0x800
m_data (rwx) : ORIGIN = 0x1FFFF000, LENGTH = 16K /* SRAM */
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into Flash */
.interrupts :
{
__vector_table = .;
. = ALIGN(8);
KEEP(*(.vectortable)) /* Startup code */
. = ALIGN(8);
} > m_interrupts
.cfmprotect :
{
. = ALIGN(8);
KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */
. = ALIGN(8);
} > m_cfmprotrom
/* The program code and other data goes into Flash */
.text :
{
. = ALIGN(8);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(8);
_etext = .; /* define a global symbols at end of code */
} > m_text
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} > m_text
.ctors :
{
__CTOR_LIST__ = .;
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
/* We don't want to include the .ctor section from
from the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
} > m_text
.dtors :
{
__DTOR_LIST__ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
} > m_text
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} > m_text
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} > m_text
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
___ROM_AT = .;
} > m_text
/* reserve MTB memory at the beginning of m_data */
.mtb : /* MTB buffer address as defined by the hardware */
{
. = ALIGN(8);
_mtb_start = .;
KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
. = ALIGN(8);
_mtb_end = .;
} > m_data
/* Initialized data sections goes into RAM, load LMA copy after code */
.data : AT(___ROM_AT)
{
. = ALIGN(8);
__sinit__ = .;
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(8);
_edata = .; /* define a global symbol at data end */
} > m_data
___data_size = _edata - _sdata;
/* Uninitialized data section */
. = ALIGN(8);
.bss :
{
/* This is used by the startup in order to initialize the .bss section */
__START_BSS = .;
PROVIDE ( __bss_start__ = __START_BSS );
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(8);
__END_BSS = .;
PROVIDE ( __bss_end__ = __END_BSS );
} > m_data
_romp_at = ___ROM_AT + SIZEOF(.data);
.romp : AT(_romp_at)
{
__S_romp = _romp_at;
LONG(___ROM_AT);
LONG(_sdata);
LONG(___data_size);
LONG(0);
LONG(0);
LONG(0);
} > m_data
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
__heap_addr = .;
. = . + __heap_size;
. = . + __stack_size;
. = ALIGN(8);
} > m_data
.ARM.attributes 0 : { *(.ARM.attributes) }
}

147
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_GCC_CW_EWL/startup_MKL25Z4.c
View File

@ -1,147 +0,0 @@
#include <string.h>
#include <stdlib.h>
#include "cmsis.h"
// Linker Script
extern unsigned long _estack;
extern char __S_romp[];
extern char __START_BSS[];
extern char __END_BSS[];
// CRT0
extern void __init_registers();
extern void __copy_rom_sections_to_ram(void);
extern void __call_static_initializers(void);
extern void __init_user();
// User/mbed Defined
extern int main();
extern void mbed_exit(int return_code);
void _ExitProcess(int return_code) {
mbed_exit(return_code);
}
void __thumb_startup(void) {
// Setup registers
__init_registers();
// Disable the Watchdog because it may reset the core before entering main().
SIM->COPC = 0x0;
// zero-fill the .bss section
memset(__START_BSS, 0, (__END_BSS - __START_BSS));
if (__S_romp != 0L)
__copy_rom_sections_to_ram();
// call C++ static initializers
__call_static_initializers();
// initializations before main, user specific
__init_user();
exit(main());
// should never get here
while (1);
}
void Default_Handler() {
__asm("bkpt");
}
/* Weak definitions of handlers point to Default_Handler if not implemented */
void NMI_Handler() __attribute__ ((weak, alias("Default_Handler")));
void HardFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler() __attribute__ ((weak, alias("Default_Handler")));
void PendSV_Handler() __attribute__ ((weak, alias("Default_Handler")));
void SysTick_Handler() __attribute__ ((weak, alias("Default_Handler")));
void DMA0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void DMA1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void DMA2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void DMA3_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void MCM_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void FTFL_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void PMC_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void LLW_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void I2C0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void I2C1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void SPI0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void SPI1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void UART0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void UART1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void UART2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void ADC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void CMP0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void FTM0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void FTM1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void FTM2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void RTC_Alarm_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void RTC_Seconds_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void PIT_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void USBOTG_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void DAC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void TSI0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void MCG_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void LPTimer_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void PORTA_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
void PORTD_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
/* The Interrupt Vector Table */
void (* const InterruptVector[])() __attribute__ ((section(".vectortable"))) = {
/* Processor exceptions */
(void(*)(void)) &_estack,
__thumb_startup,
NMI_Handler,
HardFault_Handler,
0,
0,
0,
0,
0,
0,
0,
SVC_Handler,
0,
0,
PendSV_Handler,
SysTick_Handler,
/* Interrupts */
DMA0_IRQHandler, /* DMA Channel 0 Transfer Complete and Error */
DMA1_IRQHandler, /* DMA Channel 1 Transfer Complete and Error */
DMA2_IRQHandler, /* DMA Channel 2 Transfer Complete and Error */
DMA3_IRQHandler, /* DMA Channel 3 Transfer Complete and Error */
MCM_IRQHandler, /* Normal Interrupt */
FTFL_IRQHandler, /* FTFL Interrupt */
PMC_IRQHandler, /* PMC Interrupt */
LLW_IRQHandler, /* Low Leakage Wake-up */
I2C0_IRQHandler, /* I2C0 interrupt */
I2C1_IRQHandler, /* I2C1 interrupt */
SPI0_IRQHandler, /* SPI0 Interrupt */
SPI1_IRQHandler, /* SPI1 Interrupt */
UART0_IRQHandler, /* UART0 Status and Error interrupt */
UART1_IRQHandler, /* UART1 Status and Error interrupt */
UART2_IRQHandler, /* UART2 Status and Error interrupt */
ADC0_IRQHandler, /* ADC0 interrupt */
CMP0_IRQHandler, /* CMP0 interrupt */
FTM0_IRQHandler, /* FTM0 fault, overflow and channels interrupt */
FTM1_IRQHandler, /* FTM1 fault, overflow and channels interrupt */
FTM2_IRQHandler, /* FTM2 fault, overflow and channels interrupt */
RTC_Alarm_IRQHandler, /* RTC Alarm interrupt */
RTC_Seconds_IRQHandler, /* RTC Seconds interrupt */
PIT_IRQHandler, /* PIT timer all channels interrupt */
Default_Handler, /* Reserved interrupt 39/23 */
USBOTG_IRQHandler, /* USB interrupt */
DAC0_IRQHandler, /* DAC0 interrupt */
TSI0_IRQHandler, /* TSI0 Interrupt */
MCG_IRQHandler, /* MCG Interrupt */
LPTimer_IRQHandler, /* LPTimer interrupt */
Default_Handler, /* Reserved interrupt 45/29 */
PORTA_IRQHandler, /* Port A interrupt */
PORTD_IRQHandler /* Port D interrupt */
};

159
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld
View File

@ -1,159 +0,0 @@
/* Linker script for mbed LPC1768 */
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 0x3F40
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text.Reset_Handler)
*(.text.SystemInit)
/* Only vectors and code running at reset are safe to be in first 512
bytes since RAM can be mapped into this area for RAM based interrupt
vectors. */
. = 0x00000200;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(8);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
} > RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

226
targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_GCC_CW_NEWLIB/startup_MKL25Z4.S
View File

@ -1,226 +0,0 @@
/* File: startup_ARMCM0.S
* Purpose: startup file for Cortex-M0 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V1.2
* Date: 15 Nov 2011
*
* Copyright (c) 2011, ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the ARM Limited nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.syntax unified
.arch armv6-m
/* Memory Model
The HEAP starts at the end of the DATA section and grows upward.
The STACK starts at the end of the RAM and grows downward.
The HEAP and stack STACK are only checked at compile time:
(DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
This is just a check for the bare minimum for the Heap+Stack area before
aborting compilation, it is not the run time limit:
Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
*/
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x80
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x80
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
.long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
.long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
.long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
.long Reserved20_IRQHandler /* Reserved interrupt 20 */
.long FTFA_IRQHandler /* FTFA interrupt */
.long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
.long LLW_IRQHandler /* Low Leakage Wakeup */
.long I2C0_IRQHandler /* I2C0 interrupt */
.long I2C1_IRQHandler /* I2C0 interrupt 25 */
.long SPI0_IRQHandler /* SPI0 interrupt */
.long SPI1_IRQHandler /* SPI1 interrupt */
.long UART0_IRQHandler /* UART0 status/error interrupt */
.long UART1_IRQHandler /* UART1 status/error interrupt */
.long UART2_IRQHandler /* UART2 status/error interrupt */
.long ADC0_IRQHandler /* ADC0 interrupt */
.long CMP0_IRQHandler /* CMP0 interrupt */
.long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
.long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
.long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt */
.long RTC_IRQHandler /* RTC interrupt */
.long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
.long PIT_IRQHandler /* PIT timer interrupt */
.long Reserved39_IRQHandler /* Reserved interrupt 39 */
.long USB0_IRQHandler /* USB0 interrupt */
.long DAC0_IRQHandler /* DAC interrupt */
.long TSI0_IRQHandler /* TSI0 interrupt */
.long MCG_IRQHandler /* MCG interrupt */
.long LPTimer_IRQHandler /* LPTimer interrupt */
.long Reserved45_IRQHandler /* Reserved interrupt 45 */
.long PORTA_IRQHandler /* Port A interrupt */
.long PORTD_IRQHandler /* Port D interrupt */
.size __isr_vector, . - __isr_vector
.section .text.Reset_Handler
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
movs r4, 0
.flash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .flash_to_ram_loop
.flash_to_ram_loop_end:
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler SVC_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler DMA0_IRQHandler
def_default_handler DMA1_IRQHandler
def_default_handler DMA2_IRQHandler
def_default_handler DMA3_IRQHandler
def_default_handler Reserved20_IRQHandler
def_default_handler FTFA_IRQHandler
def_default_handler LVD_LVW_IRQHandler
def_default_handler LLW_IRQHandler
def_default_handler I2C0_IRQHandler
def_default_handler I2C1_IRQHandler
def_default_handler SPI0_IRQHandler
def_default_handler SPI1_IRQHandler
def_default_handler UART0_IRQHandler
def_default_handler UART1_IRQHandler
def_default_handler UART2_IRQHandler
def_default_handler ADC0_IRQHandler
def_default_handler CMP0_IRQHandler
def_default_handler TPM0_IRQHandler
def_default_handler TPM1_IRQHandler
def_default_handler TPM2_IRQHandler
def_default_handler RTC_IRQHandler
def_default_handler RTC_Seconds_IRQHandler
def_default_handler PIT_IRQHandler
def_default_handler Reserved39_IRQHandler
def_default_handler USB0_IRQHandler
def_default_handler DAC0_IRQHandler
def_default_handler TSI0_IRQHandler
def_default_handler MCG_IRQHandler
def_default_handler LPTimer_IRQHandler
def_default_handler Reserved45_IRQHandler
def_default_handler PORTA_IRQHandler
def_default_handler PORTD_IRQHandler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
.end

153
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U24/LPC11U24.ld
View File

@ -1,153 +0,0 @@
/* mbed - LPC11U24 linker script
* Based linker script generated by Code Red Technologies Red Suite 4.1
*/
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32k */
RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
}
/* Define a symbol for the top of each memory region */
__top_MFlash32 = 0x0 + 0x8000;
__top_RamLoc8 = 0x10000000 + 0x2000;
__top_RamUsb2 = 0x20004000 + 0x800;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data)) ;
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2)) ;
LONG( SIZEOF(.data_RAM2));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(8);
/* C++ constructors etc */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* End C++ */
} > MFlash32
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
.ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
__exidx_end = .;
_etext = .;
.data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamUsb2*)
. = ALIGN(8) ;
} > RamUsb2 AT>MFlash32
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc8
.data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
. = ALIGN(8) ;
_edata = .;
} > RamLoc8 AT>MFlash32
.bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamUsb2*)
. = ALIGN(8) ;
} > RamUsb2
/* MAIN BSS SECTION */
.bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > RamLoc8
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_RamLoc8 - 0);
}

155
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_401/LPC11U35.ld
View File

@ -1,155 +0,0 @@
/* mbed - LPC11U35 linker script
* Based linker script generated by Code Red Technologies Red Suite 4.1
*/
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64k */
RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
}
/* Define a symbol for the top of each memory region */
__top_MFlash32 = 0x0 + 0x10000;
__top_RamLoc8 = 0x10000000 + 0x1F40;
__top_RamUsb2 = 0x20004000 + 0x800;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
*(.text.ResetISR)
. = 0x200;
/* Global Section Table */
. = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data)) ;
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2)) ;
LONG( SIZEOF(.data_RAM2));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(8);
/* C++ constructors etc */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* End C++ */
} > MFlash32
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
.ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
__exidx_end = .;
_etext = .;
.data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamUsb2*)
. = ALIGN(8) ;
} > RamUsb2 AT>MFlash32
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc8
.data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
. = ALIGN(8) ;
_edata = .;
} > RamLoc8 AT>MFlash32
.bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamUsb2*)
. = ALIGN(8) ;
} > RamUsb2
/* MAIN BSS SECTION */
.bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > RamLoc8
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_RamLoc8 - 0);
}

155
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U35_501/LPC11U35.ld
View File

@ -1,155 +0,0 @@
/* mbed - LPC11U35 linker script
* Based linker script generated by Code Red Technologies Red Suite 4.1
*/
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64k */
RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
}
/* Define a symbol for the top of each memory region */
__top_MFlash32 = 0x0 + 0x10000;
__top_RamLoc8 = 0x10000000 + 0x1F40;
__top_RamUsb2 = 0x20004000 + 0x800;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
*(.text.ResetISR)
. = 0x200;
/* Global Section Table */
. = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data)) ;
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2)) ;
LONG( SIZEOF(.data_RAM2));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(8);
/* C++ constructors etc */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* End C++ */
} > MFlash32
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
.ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
__exidx_end = .;
_etext = .;
.data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamUsb2*)
. = ALIGN(8) ;
} > RamUsb2 AT>MFlash32
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc8
.data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
. = ALIGN(8) ;
_edata = .;
} > RamLoc8 AT>MFlash32
.bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamUsb2*)
. = ALIGN(8) ;
} > RamUsb2
/* MAIN BSS SECTION */
.bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > RamLoc8
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_RamLoc8 - 0);
}

157
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U37H_401/LPC11U37.ld
View File

@ -1,157 +0,0 @@
/* mbed - LPC11U35 linker script
* Based linker script generated by Code Red Technologies Red Suite 4.1
*/
GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128k */
RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
RamIo1 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2k */
RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
}
/* Define a symbol for the top of each memory region */
__top_MFlash32 = 0x0 + 0x10000;
__top_RamLoc8 = 0x10000000 + 0x1F40;
__top_RamIo1 = 0x20000000 + 0x800;
__top_RamUsb2 = 0x20004000 + 0x800;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
*(.text.ResetISR)
. = 0x200;
/* Global Section Table */
. = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data)) ;
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2)) ;
LONG( SIZEOF(.data_RAM2));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(8);
/* C++ constructors etc */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* End C++ */
} > MFlash32
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
.ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
__exidx_end = .;
_etext = .;
.data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamUsb2*)
. = ALIGN(8) ;
} > RamUsb2 AT>MFlash32
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc8
.data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
. = ALIGN(8) ;
_edata = .;
} > RamLoc8 AT>MFlash32
.bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamUsb2*)
. = ALIGN(8) ;
} > RamUsb2
/* MAIN BSS SECTION */
.bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > RamLoc8
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_RamLoc8 - 0);
}

155
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11U37_501/LPC11U37.ld
View File

@ -1,155 +0,0 @@
/* mbed - LPC11U35 linker script
* Based linker script generated by Code Red Technologies Red Suite 4.1
*/
GROUP(libgcc.a libc_s.a libstdc++_s.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128k */
RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40 /* 8k */
RamUsb2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2k */
}
/* Define a symbol for the top of each memory region */
__top_MFlash32 = 0x0 + 0x10000;
__top_RamLoc8 = 0x10000000 + 0x1F40;
__top_RamUsb2 = 0x20004000 + 0x800;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
*(.text.ResetISR)
. = 0x200;
/* Global Section Table */
. = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data)) ;
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2)) ;
LONG( SIZEOF(.data_RAM2));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(8);
/* C++ constructors etc */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* End C++ */
} > MFlash32
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
.ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
__exidx_end = .;
_etext = .;
.data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamUsb2*)
. = ALIGN(8) ;
} > RamUsb2 AT>MFlash32
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc8
.data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
. = ALIGN(8) ;
_edata = .;
} > RamLoc8 AT>MFlash32
.bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamUsb2*)
. = ALIGN(8) ;
} > RamUsb2
/* MAIN BSS SECTION */
.bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > RamLoc8
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_RamLoc8 - 0);
}

161
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CR/startup_LPC11xx.cpp
View File

@ -1,161 +0,0 @@
extern "C" {
#include "LPC11Uxx.h"
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))
void ResetISR (void);
WEAK void NMI_Handler (void);
WEAK void HardFault_Handler (void);
WEAK void SVC_Handler (void);
WEAK void PendSV_Handler (void);
WEAK void SysTick_Handler (void);
WEAK void IntDefaultHandler (void);
void FLEX_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER16_0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER16_1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER32_0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER32_1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
void UART_IRQHandler (void) ALIAS(IntDefaultHandler);
void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler (void) ALIAS(IntDefaultHandler);
void WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler (void) ALIAS(IntDefaultHandler);
void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
extern void __libc_init_array(void);
extern int main(void);
extern void _vStackTop(void);
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
&_vStackTop,
ResetISR,
NMI_Handler,
HardFault_Handler,
0,
0,
0,
0,
0,
0,
0,
SVC_Handler,
0,
0,
PendSV_Handler,
SysTick_Handler,
FLEX_INT0_IRQHandler,
FLEX_INT1_IRQHandler,
FLEX_INT2_IRQHandler,
FLEX_INT3_IRQHandler,
FLEX_INT4_IRQHandler,
FLEX_INT5_IRQHandler,
FLEX_INT6_IRQHandler,
FLEX_INT7_IRQHandler,
GINT0_IRQHandler,
GINT1_IRQHandler,
0,
0,
0,
0,
SSP1_IRQHandler,
I2C_IRQHandler,
TIMER16_0_IRQHandler,
TIMER16_1_IRQHandler,
TIMER32_0_IRQHandler,
TIMER32_1_IRQHandler,
SSP0_IRQHandler,
UART_IRQHandler,
USB_IRQHandler,
USB_FIQHandler,
ADC_IRQHandler,
WDT_IRQHandler,
BOD_IRQHandler,
FMC_IRQHandler,
0,
0,
USBWakeup_IRQHandler,
0,
};
AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
}
AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
}
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table_end;
extern "C" void software_init_hook(void);
extern "C" void pre_main(void) __attribute__((weak));
AFTER_VECTORS void ResetISR(void) {
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Data Init
SectionTableAddr = &__data_section_table;
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// BSS Init
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
SystemInit();
if (pre_main) { // give control to the RTOS
software_init_hook(); // this will also call __libc_init_array
}
else { // for BareMetal (non-RTOS) build
__libc_init_array();
main();
}
while (1) {;}
}
AFTER_VECTORS void NMI_Handler (void) {while(1){}}
AFTER_VECTORS void HardFault_Handler(void) {while(1){}}
AFTER_VECTORS void SVC_Handler (void) {while(1){}}
AFTER_VECTORS void PendSV_Handler (void) {while(1){}}
AFTER_VECTORS void SysTick_Handler (void) {while(1){}}
AFTER_VECTORS void IntDefaultHandler(void) {while(1){}}
int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {
return 0;
}
}

207
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CS/LPC11U24.ld
View File

@ -1,207 +0,0 @@
/* Linker script for mbed LPC1768
*
* Version:CodeSourcery Sourcery G++ Lite 2007q3-53
* BugURL:https://support.codesourcery.com/GNUToolchain/
*
* Copyright 2007 CodeSourcery.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply. */
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
ENTRY(__cs3_reset_cortex_m)
SEARCH_DIR(.)
/*
ram ORIGIN: 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
ram LENGTH: 8KB - 0xC0 = 0xF40
*/
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 32K
ram (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
usb_ram (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800
}
/* These force the linker to search for particular symbols from
* the start of the link process and thus ensure the user's
* overrides are picked up
*/
EXTERN(__cs3_reset_cortex_m)
EXTERN(__cs3_interrupt_vector_cortex_m)
EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
PROVIDE(__cs3_heap_start = _end);
PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
SECTIONS
{
.text :
{
CREATE_OBJECT_SYMBOLS
__cs3_region_start_rom = .;
*(.cs3.region-head.rom)
__cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
*(.cs3.interrupt_vector)
/* Make sure we pulled in an interrupt vector. */
ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
*(.rom)
*(.rom.b)
__cs3_reset = __cs3_reset_cortex_m;
*(.cs3.reset)
/* Make sure we pulled in some reset code. */
ASSERT (. != __cs3_reset, "No reset code");
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
*(.gnu.warning)
*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(8);
KEEP(*(.fini))
. = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(8);
__cs3_regions = .;
LONG (0)
LONG (__cs3_region_init_ram)
LONG (__cs3_region_start_ram)
LONG (__cs3_region_init_size_ram)
LONG (__cs3_region_zero_size_ram)
}
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >rom
__exidx_end = .;
.text.align :
{
. = ALIGN(8);
_etext = .;
} >rom
__cs3_region_size_rom = LENGTH(rom);
__cs3_region_num = 1;
.data :
{
__cs3_region_start_ram = .;
*(.cs3.region-head.ram)
KEEP(*(.jcr))
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
*(.ram)
. = ALIGN (8);
_edata = .;
} >ram AT>rom
.bss :
{
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
*(.ram.b)
. = ALIGN (8);
_end = .;
__end = .;
} >ram AT>rom
.heap (NOLOAD) :
{
*(.heap)
} >ram
.stack (__cs3_stack - __cs3_stack_size) (NOLOAD):
{
*(.stack)
_estack = .;
PROVIDE(estack = .);
} >ram
__cs3_region_init_ram = LOADADDR (.data);
__cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
__cs3_region_zero_size_ram = _end - _edata;
__cs3_region_size_ram = LENGTH(ram);
__cs3_region_num = 1;
.stab 0 (NOLOAD) : { *(.stab) }
.stabstr 0 (NOLOAD) : { *(.stabstr) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) }
}

112
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_GCC_CS/startup_LPC11xx.S
View File

@ -1,112 +0,0 @@
.equ Stack_Size, 0x80
.section ".stack", "w"
.align 3
.globl __cs3_stack_mem
.globl __cs3_stack_size
__cs3_stack_mem:
.if Stack_Size
.space Stack_Size
.endif
.size __cs3_stack_mem, . - __cs3_stack_mem
.set __cs3_stack_size, . - __cs3_stack_mem
.equ Heap_Size, 0x80
.section ".heap", "w"
.align 3
.globl __cs3_heap_start
.globl __cs3_heap_end
__cs3_heap_start:
.if Heap_Size
.space Heap_Size
.endif
__cs3_heap_end:
.section ".cs3.interrupt_vector"
.globl __cs3_interrupt_vector_cortex_m
.type __cs3_interrupt_vector_cortex_m, %object
__cs3_interrupt_vector_cortex_m:
.long __cs3_stack
.long __cs3_reset
.long NMI_Handler
.long HardFault_Handler
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long SVC_Handler
.long 0
.long 0
.long PendSV_Handler
.long SysTick_Handler
.long DEF_IRQHandler
.size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
.thumb
.section .cs3.reset,"x",%progbits
.thumb_func
.globl __cs3_reset_cortex_m
.type __cs3_reset_cortex_m, %function
__cs3_reset_cortex_m:
.fnstart
LDR R0, =SystemInit
BLX R0
LDR R0,=__cs3_start_c
BX R0
.pool
.cantunwind
.fnend
.size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
.section ".text"
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
B .
.size NMI_Handler, . - NMI_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
B .
.size HardFault_Handler, . - HardFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
B .
.size SVC_Handler, . - SVC_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
B .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
B .
.size SysTick_Handler, . - SysTick_Handler
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
B .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ DEF_IRQHandler
.end

136
targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/LPC1114.ld
View File

@ -1,136 +0,0 @@
/* mbed - LPC1114 linker script
* Based linker script generated by Code Red Technologies Red Suite 4.1
*/
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32k */
RamLoc8 (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x0F40 /* 4k */
}
/* Define a symbol for the top of each memory region */
__top_MFlash32 = 0x0 + 0x8000;
__top_RamLoc8 = 0x10000000 + 0x0F40;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
*(.text.ResetISR)
*(.text.SystemInit)
. = 0x200;
/* Global Section Table */
. = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data)) ;
LONG( SIZEOF(.data));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(8);
/* C++ constructors etc */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* End C++ */
} > MFlash32
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
.ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
__exidx_end = .;
_etext = .;
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc8
.data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
. = ALIGN(8) ;
_edata = .;
} > RamLoc8 AT>MFlash32
/* MAIN BSS SECTION */
.bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > RamLoc8
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_RamLoc8 - 0);
}

161
targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_GCC_CR/TARGET_LPC11XX/startup_LPC11xx.cpp
View File

@ -1,161 +0,0 @@
extern "C" {
#include "LPC11xx.h"
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))
void ResetISR (void);
WEAK void NMI_Handler (void);
WEAK void HardFault_Handler (void);
WEAK void SVC_Handler (void);
WEAK void PendSV_Handler (void);
WEAK void SysTick_Handler (void);
WEAK void IntDefaultHandler (void);
void FLEX_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLEX_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER16_0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER16_1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER32_0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER32_1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
void UART_IRQHandler (void) ALIAS(IntDefaultHandler);
void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler (void) ALIAS(IntDefaultHandler);
void WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler (void) ALIAS(IntDefaultHandler);
void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
extern void __libc_init_array(void);
extern int main(void);
extern void _vStackTop(void);
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
&_vStackTop,
ResetISR,
NMI_Handler,
HardFault_Handler,
0,
0,
0,
0,
0,
0,
0,
SVC_Handler,
0,
0,
PendSV_Handler,
SysTick_Handler,
FLEX_INT0_IRQHandler,
FLEX_INT1_IRQHandler,
FLEX_INT2_IRQHandler,
FLEX_INT3_IRQHandler,
FLEX_INT4_IRQHandler,
FLEX_INT5_IRQHandler,
FLEX_INT6_IRQHandler,
FLEX_INT7_IRQHandler,
GINT0_IRQHandler,
GINT1_IRQHandler,
0,
0,
0,
0,
SSP1_IRQHandler,
I2C_IRQHandler,
TIMER16_0_IRQHandler,
TIMER16_1_IRQHandler,
TIMER32_0_IRQHandler,
TIMER32_1_IRQHandler,
SSP0_IRQHandler,
UART_IRQHandler,
USB_IRQHandler,
USB_FIQHandler,
ADC_IRQHandler,
WDT_IRQHandler,
BOD_IRQHandler,
FMC_IRQHandler,
0,
0,
USBWakeup_IRQHandler,
0,
};
AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
}
AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
}
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table_end;
extern "C" void software_init_hook(void);
extern "C" void pre_main(void) __attribute__((weak));
AFTER_VECTORS void ResetISR(void) {
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Data Init
SectionTableAddr = &__data_section_table;
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// BSS Init
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
SystemInit();
if (pre_main) { // give control to the RTOS
software_init_hook(); // this will also call __libc_init_array
}
else { // for BareMetal (non-RTOS) build
__libc_init_array();
main();
}
while (1) {;}
}
AFTER_VECTORS void NMI_Handler (void) {while(1){}}
AFTER_VECTORS void HardFault_Handler(void) {while(1){}}
AFTER_VECTORS void SVC_Handler (void) {while(1){}}
AFTER_VECTORS void PendSV_Handler (void) {while(1){}}
AFTER_VECTORS void SysTick_Handler (void) {while(1){}}
AFTER_VECTORS void IntDefaultHandler(void) {while(1){}}
int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {
return 0;
}
}

112
targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_GCC_CS/startup_LPC11xx.S
View File

@ -1,112 +0,0 @@
.equ Stack_Size, 0x80
.section ".stack", "w"
.align 3
.globl __cs3_stack_mem
.globl __cs3_stack_size
__cs3_stack_mem:
.if Stack_Size
.space Stack_Size
.endif
.size __cs3_stack_mem, . - __cs3_stack_mem
.set __cs3_stack_size, . - __cs3_stack_mem
.equ Heap_Size, 0x80
.section ".heap", "w"
.align 3
.globl __cs3_heap_start
.globl __cs3_heap_end
__cs3_heap_start:
.if Heap_Size
.space Heap_Size
.endif
__cs3_heap_end:
.section ".cs3.interrupt_vector"
.globl __cs3_interrupt_vector_cortex_m
.type __cs3_interrupt_vector_cortex_m, %object
__cs3_interrupt_vector_cortex_m:
.long __cs3_stack
.long __cs3_reset
.long NMI_Handler
.long HardFault_Handler
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long SVC_Handler
.long 0
.long 0
.long PendSV_Handler
.long SysTick_Handler
.long DEF_IRQHandler
.size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
.thumb
.section .cs3.reset,"x",%progbits
.thumb_func
.globl __cs3_reset_cortex_m
.type __cs3_reset_cortex_m, %function
__cs3_reset_cortex_m:
.fnstart
LDR R0, =SystemInit
BLX R0
LDR R0,=__cs3_start_c
BX R0
.pool
.cantunwind
.fnend
.size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
.section ".text"
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
B .
.size NMI_Handler, . - NMI_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
B .
.size HardFault_Handler, . - HardFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
B .
.size SVC_Handler, . - SVC_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
B .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
B .
.size SysTick_Handler, . - SysTick_Handler
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
B .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ DEF_IRQHandler
.end

214
targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_CR/LPC1549.ld
View File

@ -1,214 +0,0 @@
/*Based on following file*/
/*
* GENERATED FILE - DO NOT EDIT
* (c) Code Red Technologies Ltd, 2008-13
* (c) NXP Semiconductors 2013-2014
* Generated linker script file for LPC1549
* Created from generic_c.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))
* By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Tue Jun 10 00:20:53 JST 2014
*/
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */
Ram0_16 (rwx) : ORIGIN = 0x2000000+0x100, LENGTH = 0x4000-0x100 /* 16K bytes */
Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes */
Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes */
}
/* Define a symbol for the top of each memory region */
__top_MFlash256 = 0x0 + 0x40000;
__top_Ram0_16 = 0x2000000 + 0x4000;
__top_Ram1_16 = 0x2004000 + 0x4000;
__top_Ram2_4 = 0x2008000 + 0x1000;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
LONG(LOADADDR(.data_RAM3));
LONG( ADDR(.data_RAM3));
LONG( SIZEOF(.data_RAM3));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
LONG( ADDR(.bss_RAM3));
LONG( SIZEOF(.bss_RAM3));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(8);
/* C++ constructors etc */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
} > MFlash256
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash256
__exidx_start = .;
.ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash256
__exidx_end = .;
_etext = .;
/* DATA section for Ram1_16 */
.data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM2)
*(.ramfunc.$Ram1_16)
*(.data.$RAM2*)
*(.data.$Ram1_16*)
. = ALIGN(8) ;
} > Ram1_16 AT>MFlash256
/* DATA section for Ram2_4 */
.data_RAM3 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM3)
*(.ramfunc.$Ram2_4)
*(.data.$RAM3*)
*(.data.$Ram2_4*)
. = ALIGN(8) ;
} > Ram2_4 AT>MFlash256
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
. = ALIGN(8) ;
_end_uninit_RESERVED = .;
} > Ram0_16
/* Main DATA section (Ram0_16) */
.data : ALIGN(8)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
. = ALIGN(8) ;
_edata = . ;
} > Ram0_16 AT>MFlash256
/* BSS section for Ram1_16 */
.bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$Ram1_16*)
. = ALIGN(8) ;
} > Ram1_16
/* BSS section for Ram2_4 */
.bss_RAM3 : ALIGN(8)
{
*(.bss.$RAM3*)
*(.bss.$Ram2_4*)
. = ALIGN(8) ;
} > Ram2_4
/* MAIN BSS SECTION */
.bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > Ram0_16
/* NOINIT section for Ram1_16 */
.noinit_RAM2 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM2*)
*(.noinit.$Ram1_16*)
. = ALIGN(8) ;
} > Ram1_16
/* NOINIT section for Ram2_4 */
.noinit_RAM3 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM3*)
*(.noinit.$Ram2_4*)
. = ALIGN(8) ;
} > Ram2_4
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(8)
{
_noinit = .;
*(.noinit*)
. = ALIGN(8) ;
_end_noinit = .;
} > Ram0_16
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_Ram0_16 - 0);
}

213
targets/TARGET_NXP/TARGET_LPC15XX/device/TOOLCHAIN_GCC_CR/startup_LPC15xx.cpp
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@ -1,213 +0,0 @@
extern "C" {
#include "LPC15xx.h"
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void);
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
extern void __libc_init_array(void);
extern int main(void);
extern void _vStackTop(void);
extern void (* const g_pfnVectors[])(void);
void ResetISR (void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void FMC_IRQHandler(void) ALIAS(IntDefaultHandler);
void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void SCT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SCT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SCT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void SCT3_IRQHandler(void) ALIAS(IntDefaultHandler);
void MRT_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI1_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_FIQHandler(void) ALIAS(IntDefaultHandler);
void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0A_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0B_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0_OVR_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1A_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1B_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1_OVR_IRQHandler(void) ALIAS(IntDefaultHandler);
void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
void ACMP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void ACMP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void ACMP2_IRQHandler(void) ALIAS(IntDefaultHandler);
void ACMP3_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_ALARM_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_WAKE_IRQHandler(void) ALIAS(IntDefaultHandler);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC15xx
WDT_IRQHandler, // 0 - Windowed watchdog timer
BOD_IRQHandler, // 1 - BOD
FMC_IRQHandler, // 2 - Flash controller
EEPROM_IRQHandler, // 3 - EEPROM controller
DMA_IRQHandler, // 4 - DMA
GINT0_IRQHandler, // 5 - GINT0
GINT1_IRQHandler, // 6 - GINT1
PIN_INT0_IRQHandler, // 7 - PIO INT0
PIN_INT1_IRQHandler, // 8 - PIO INT1
PIN_INT2_IRQHandler, // 9 - PIO INT2
PIN_INT3_IRQHandler, // 10 - PIO INT3
PIN_INT4_IRQHandler, // 11 - PIO INT4
PIN_INT5_IRQHandler, // 12 - PIO INT5
PIN_INT6_IRQHandler, // 13 - PIO INT6
PIN_INT7_IRQHandler, // 14 - PIO INT7
RIT_IRQHandler, // 15 - RIT
SCT0_IRQHandler, // 16 - State configurable timer
SCT1_IRQHandler, // 17 - State configurable timer
SCT2_IRQHandler, // 18 - State configurable timer
SCT3_IRQHandler, // 19 - State configurable timer
MRT_IRQHandler, // 20 - Multi-Rate Timer
UART0_IRQHandler, // 21 - UART0
UART1_IRQHandler, // 22 - UART1
UART2_IRQHandler, // 23 - UART2
I2C0_IRQHandler, // 24 - I2C0 controller
SPI0_IRQHandler, // 25 - SPI0 controller
SPI1_IRQHandler, // 26 - SPI1 controller
CAN_IRQHandler, // 27 - C_CAN0
USB_IRQHandler, // 28 - USB IRQ
USB_FIQHandler, // 29 - USB FIQ
USBWakeup_IRQHandler, // 30 - USB wake-up
ADC0A_IRQHandler, // 31 - ADC0 sequence A completion
ADC0B_IRQHandler, // 32 - ADC0 sequence B completion
ADC0_THCMP_IRQHandler, // 33 - ADC0 threshold compare
ADC0_OVR_IRQHandler, // 34 - ADC0 overrun
ADC1A_IRQHandler, // 35 - ADC1 sequence A completion
ADC1B_IRQHandler, // 36 - ADC1 sequence B completion
ADC1_THCMP_IRQHandler, // 37 - ADC1 threshold compare
ADC1_OVR_IRQHandler, // 38 - ADC1 overrun
DAC_IRQHandler, // 39 - DAC
ACMP0_IRQHandler, // 40 - Analog Comparator 0
ACMP1_IRQHandler, // 41 - Analog Comparator 1
ACMP2_IRQHandler, // 42 - Analog Comparator 2
ACMP3_IRQHandler, // 43 - Analog Comparator 3
QEI_IRQHandler, // 44 - QEI
RTC_ALARM_IRQHandler, // 45 - RTC alarm
RTC_WAKE_IRQHandler, // 46 - RTC wake-up
};
/* End Vector */
AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
}
AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
}
/* Reset entry point*/
extern "C" void software_init_hook(void);
extern "C" void pre_main(void) __attribute__((weak));
AFTER_VECTORS void ResetISR(void) {
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
SectionTableAddr = &__data_section_table;
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
SystemInit();
if (pre_main) { // give control to the RTOS
software_init_hook(); // this will also call __libc_init_array
}
else { // for BareMetal (non-RTOS) build
__libc_init_array();
main();
}
while (1) {;}
}
AFTER_VECTORS void NMI_Handler (void) {}
AFTER_VECTORS void HardFault_Handler (void) {}
AFTER_VECTORS void MemManage_Handler (void) {}
AFTER_VECTORS void BusFault_Handler (void) {}
AFTER_VECTORS void UsageFault_Handler(void) {}
AFTER_VECTORS void SVC_Handler (void) {}
AFTER_VECTORS void DebugMon_Handler (void) {}
AFTER_VECTORS void PendSV_Handler (void) {}
AFTER_VECTORS void SysTick_Handler (void) {}
AFTER_VECTORS void IntDefaultHandler (void) {}
int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
}

161
targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_CR/LPC1768.ld
View File

@ -1,161 +0,0 @@
/* mbed - LPC1768 linker script
* Based linker script generated by Code Red Technologies Red Suite 4.1
*/
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F18 /* 32k (topmost 32 bytes used by IAP functions) */
RamAHB_USB (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x4000 /* 16k */
RamAHB_Eth (rwx) : ORIGIN = 0x20080000, LENGTH = 0x4000 /* 16k */
}
/* Define a symbol for the top of each memory region */
__top_MFlash512 = 0x0 + 0x80000;
__top_RamLoc32 = 0x10000000 + 0x8000;
__top_RamAHB32 = 0x2007c000 + 0x8000;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data)) ;
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2)) ;
LONG( SIZEOF(.data_RAM2));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(8);
/* C++ constructors etc */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(0x4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* End C++ */
} > MFlash512
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash512
__exidx_start = .;
.ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash512
__exidx_end = .;
_etext = .;
.data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamAHB32*)
. = ALIGN(8) ;
} > RamAHB_USB AT>MFlash512
/* MAIN DATA SECTION */
.uninit_RESERVED(NOLOAD) : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc32
.data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
. = ALIGN(8) ;
_edata = .;
} > RamLoc32 AT>MFlash512
.bss_RAM2(NOLOAD) : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamAHB32*)
*(AHBSRAM0)
. = ALIGN(8) ;
} > RamAHB_USB
.bss_RAM3(NOLOAD) : ALIGN(8)
{
*(AHBSRAM1)
. = ALIGN(8) ;
} > RamAHB_Eth
/* MAIN BSS SECTION */
.bss(NOLOAD) : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > RamLoc32
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_RamLoc32 - 0);
}

177
targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_CR/startup_LPC17xx.cpp
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@ -1,177 +0,0 @@
extern "C" {
#include "LPC17xx.h"
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
extern void __libc_init_array(void);
extern int main(void);
extern void _vStackTop(void);
extern void (* const g_pfnVectors[])(void);
void ResetISR (void);
WEAK void NMI_Handler (void);
WEAK void HardFault_Handler (void);
WEAK void MemManage_Handler (void);
WEAK void BusFault_Handler (void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler (void);
WEAK void DebugMon_Handler (void);
WEAK void PendSV_Handler (void);
WEAK void SysTick_Handler (void);
WEAK void IntDefaultHandler (void);
void WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER0_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler (void) ALIAS(IntDefaultHandler);
void TIMER3_IRQHandler (void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler (void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler (void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler (void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler (void) ALIAS(IntDefaultHandler);
void PWM1_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C2_IRQHandler (void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler (void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
void PLL0_IRQHandler (void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler (void) ALIAS(IntDefaultHandler);
void EINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
void EINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
void EINT2_IRQHandler (void) ALIAS(IntDefaultHandler);
void EINT3_IRQHandler (void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler (void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler (void) ALIAS(IntDefaultHandler);
void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
void CAN_IRQHandler (void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2S_IRQHandler (void) ALIAS(IntDefaultHandler);
void ENET_IRQHandler (void) ALIAS(IntDefaultHandler);
void RIT_IRQHandler (void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler (void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler (void) ALIAS(IntDefaultHandler);
void PLL1_IRQHandler (void) ALIAS(IntDefaultHandler);
void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
&_vStackTop, ResetISR, NMI_Handler,
HardFault_Handler,
MemManage_Handler,
BusFault_Handler,
UsageFault_Handler,
0,
0,
0,
0,
SVC_Handler,
DebugMon_Handler,
0,
PendSV_Handler,
SysTick_Handler,
WDT_IRQHandler,
TIMER0_IRQHandler,
TIMER1_IRQHandler,
TIMER2_IRQHandler,
TIMER3_IRQHandler,
UART0_IRQHandler,
UART1_IRQHandler,
UART2_IRQHandler,
UART3_IRQHandler,
PWM1_IRQHandler,
I2C0_IRQHandler,
I2C1_IRQHandler,
I2C2_IRQHandler,
SPI_IRQHandler,
SSP0_IRQHandler,
SSP1_IRQHandler,
PLL0_IRQHandler,
RTC_IRQHandler,
EINT0_IRQHandler,
EINT1_IRQHandler,
EINT2_IRQHandler,
EINT3_IRQHandler,
ADC_IRQHandler,
BOD_IRQHandler,
USB_IRQHandler,
CAN_IRQHandler,
DMA_IRQHandler,
I2S_IRQHandler,
ENET_IRQHandler,
RIT_IRQHandler,
MCPWM_IRQHandler,
QEI_IRQHandler,
PLL1_IRQHandler,
USBActivity_IRQHandler,
CANActivity_IRQHandler,
};
AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
}
AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
}
extern "C" void software_init_hook(void);
extern "C" void pre_main(void) __attribute__((weak));
AFTER_VECTORS void ResetISR(void) {
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
SectionTableAddr = &__data_section_table;
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
SystemInit();
if (pre_main) { // give control to the RTOS
software_init_hook(); // this will also call __libc_init_array
}
else { // for BareMetal (non-RTOS) build
__libc_init_array();
main();
}
while (1) {;}
}
AFTER_VECTORS void NMI_Handler (void) {}
AFTER_VECTORS void HardFault_Handler (void) {}
AFTER_VECTORS void MemManage_Handler (void) {}
AFTER_VECTORS void BusFault_Handler (void) {}
AFTER_VECTORS void UsageFault_Handler(void) {}
AFTER_VECTORS void SVC_Handler (void) {}
AFTER_VECTORS void DebugMon_Handler (void) {}
AFTER_VECTORS void PendSV_Handler (void) {}
AFTER_VECTORS void SysTick_Handler (void) {}
AFTER_VECTORS void IntDefaultHandler (void) {}
int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
}

212
targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_CS/LPC1768.ld
View File

@ -1,212 +0,0 @@
/* Linker script for mbed LPC1768
*
* Version:CodeSourcery Sourcery G++ Lite 2007q3-53
* BugURL:https://support.codesourcery.com/GNUToolchain/
*
* Copyright 2007 CodeSourcery.
*
* The authors hereby grant permission to use, copy, modify, distribute,
* and license this software and its documentation for any purpose, provided
* that existing copyright notices are retained in all copies and that this
* notice is included verbatim in any distributions. No written agreement,
* license, or royalty fee is required for any of the authorized uses.
* Modifications to this software may be copyrighted by their authors
* and need not follow the licensing terms described here, provided that
* the new terms are clearly indicated on the first page of each file where
* they apply. */
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
ENTRY(__cs3_reset_cortex_m)
SEARCH_DIR(.)
/*
ram ORIGIN: 8_byte_aligned(49 vect * 4 bytes) = 8_byte_aligned(0xC4) = 0xC8
ram LENGTH: 32KB (RAM size) - 0xC8 (NIVT) - 32 (topmost 32 bytes used by IAP functions) = 0x7F18
*/
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 512K
ram (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F18
ram1(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
ram2(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
}
/* These force the linker to search for particular symbols from
* the start of the link process and thus ensure the user's
* overrides are picked up
*/
EXTERN(__cs3_reset_cortex_m)
EXTERN(__cs3_interrupt_vector_cortex_m)
EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
PROVIDE(__cs3_heap_start = _end);
PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
SECTIONS
{
.text :
{
CREATE_OBJECT_SYMBOLS
__cs3_region_start_rom = .;
*(.cs3.region-head.rom)
__cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
*(.cs3.interrupt_vector)
/* Make sure we pulled in an interrupt vector. */
ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
*(.rom)
*(.rom.b)
__cs3_reset = __cs3_reset_cortex_m;
*(.cs3.reset)
/* Make sure we pulled in some reset code. */
ASSERT (. != __cs3_reset, "No reset code");
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
*(.gnu.warning)
*(.glue_7t) *(.glue_7) *(.vfp11_veneer)
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
*(.gcc_except_table)
*(.eh_frame_hdr)
*(.eh_frame)
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(0x4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(8);
KEEP(*(.fini))
. = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(8);
__cs3_regions = .;
LONG (0)
LONG (__cs3_region_init_ram)
LONG (__cs3_region_start_ram)
LONG (__cs3_region_init_size_ram)
LONG (__cs3_region_zero_size_ram)
}
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} >rom
__exidx_end = .;
.text.align :
{
. = ALIGN(8);
_etext = .;
} >rom
__cs3_region_size_rom = LENGTH(rom);
__cs3_region_num = 1;
.data :
{
__cs3_region_start_ram = .;
*(.cs3.region-head.ram)
KEEP(*(.jcr))
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
*(.ram)
. = ALIGN (8);
_edata = .;
} >ram AT>rom
.bss :
{
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
*(.ram.b)
. = ALIGN (8);
_end = .;
__end = .;
} >ram AT>rom
/* This used for USB RAM section */
.usb_ram (NOLOAD):
{
*.o (USB_RAM)
} > ram2
.heap (NOLOAD) :
{
*(.heap)
} >ram
.stack (__cs3_stack - __cs3_stack_size) (NOLOAD):
{
*(.stack)
_estack = .;
PROVIDE(estack = .);
} >ram
__cs3_region_init_ram = LOADADDR (.data);
__cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
__cs3_region_zero_size_ram = _end - _edata;
__cs3_region_size_ram = LENGTH(ram);
__cs3_region_num = 1;
.stab 0 (NOLOAD) : { *(.stab) }
.stabstr 0 (NOLOAD) : { *(.stabstr) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
.ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) }
}

204
targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_GCC_CS/startup_LPC17xx.S
View File

@ -1,204 +0,0 @@
.equ Stack_Size, 0x1024
.section ".stack", "w"
.align 3
.globl __cs3_stack_mem
.globl __cs3_stack_size
__cs3_stack_mem:
.if Stack_Size
.space Stack_Size
.endif
.size __cs3_stack_mem, . - __cs3_stack_mem
.set __cs3_stack_size, . - __cs3_stack_mem
.equ Heap_Size, 0x8000
.section ".heap", "w"
.align 3
.globl __cs3_heap_start
.globl __cs3_heap_end
__cs3_heap_start:
.if Heap_Size
.space Heap_Size
.endif
__cs3_heap_end:
.section ".cs3.interrupt_vector"
.globl __cs3_interrupt_vector_cortex_m
.type __cs3_interrupt_vector_cortex_m, %object
__cs3_interrupt_vector_cortex_m:
.long __cs3_stack
.long __cs3_reset
.long NMI_Handler
.long HardFault_Handler
.long MemManage_Handler
.long BusFault_Handler
.long UsageFault_Handler
.long 0
.long 0
.long 0
.long 0
.long SVC_Handler
.long DebugMon_Handler
.long 0
.long PendSV_Handler
.long SysTick_Handler
.long WDT_IRQHandler
.long TIMER0_IRQHandler
.long TIMER1_IRQHandler
.long TIMER2_IRQHandler
.long TIMER3_IRQHandler
.long UART0_IRQHandler
.long UART1_IRQHandler
.long UART2_IRQHandler
.long UART3_IRQHandler
.long PWM1_IRQHandler
.long I2C0_IRQHandler
.long I2C1_IRQHandler
.long I2C2_IRQHandler
.long SPI_IRQHandler
.long SSP0_IRQHandler
.long SSP1_IRQHandler
.long PLL0_IRQHandler
.long RTC_IRQHandler
.long EINT0_IRQHandler
.long EINT1_IRQHandler
.long EINT2_IRQHandler
.long EINT3_IRQHandler
.long ADC_IRQHandler
.long BOD_IRQHandler
.long USB_IRQHandler
.long CAN_IRQHandler
.long DMA_IRQHandler
.long I2S_IRQHandler
.long ENET_IRQHandler
.long RIT_IRQHandler
.long MCPWM_IRQHandler
.long QEI_IRQHandler
.long PLL1_IRQHandler
.long USBActivity_IRQHandler
.long CANActivity_IRQHandler
.size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
.thumb
.section .cs3.reset,"x",%progbits
.thumb_func
.globl __cs3_reset_cortex_m
.type __cs3_reset_cortex_m, %function
__cs3_reset_cortex_m:
.fnstart
LDR R0, =SystemInit
BLX R0
LDR R0, =__cs3_start_c
BX R0
.pool
.cantunwind
.fnend
.size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
.section ".text"
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
B .
.size NMI_Handler, . - NMI_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
B .
.size HardFault_Handler, . - HardFault_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
B .
.size MemManage_Handler, . - MemManage_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
B .
.size BusFault_Handler, . - BusFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
B .
.size UsageFault_Handler, . - UsageFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
B .
.size SVC_Handler, . - SVC_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
B .
.size DebugMon_Handler, . - DebugMon_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
B .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
B .
.size SysTick_Handler, . - SysTick_Handler
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
B .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ WDT_IRQHandler
IRQ TIMER0_IRQHandler
IRQ TIMER1_IRQHandler
IRQ TIMER2_IRQHandler
IRQ TIMER3_IRQHandler
IRQ UART0_IRQHandler
IRQ UART1_IRQHandler
IRQ UART2_IRQHandler
IRQ UART3_IRQHandler
IRQ PWM1_IRQHandler
IRQ I2C0_IRQHandler
IRQ I2C1_IRQHandler
IRQ I2C2_IRQHandler
IRQ SPI_IRQHandler
IRQ SSP0_IRQHandler
IRQ SSP1_IRQHandler
IRQ PLL0_IRQHandler
IRQ RTC_IRQHandler
IRQ EINT0_IRQHandler
IRQ EINT1_IRQHandler
IRQ EINT2_IRQHandler
IRQ EINT3_IRQHandler
IRQ ADC_IRQHandler
IRQ BOD_IRQHandler
IRQ USB_IRQHandler
IRQ CAN_IRQHandler
IRQ DMA_IRQHandler
IRQ I2S_IRQHandler
IRQ ENET_IRQHandler
IRQ RIT_IRQHandler
IRQ MCPWM_IRQHandler
IRQ QEI_IRQHandler
IRQ PLL1_IRQHandler
IRQ USBActivity_IRQHandler
IRQ CANActivity_IRQHandler
.end

181
targets/TARGET_NXP/TARGET_LPC408X/device/TOOLCHAIN_GCC_CR/LPC407x_8x.ld
View File

@ -1,181 +0,0 @@
/*
* GENERATED FILE - DO NOT EDIT
* (C) Code Red Technologies Ltd, 2008-2013
* Generated linker script file for LPC4088
* Created from generic_c.ld (vLPCXpresso v5.1 (2 [Build 2065] [2013-02-20] ))
* By LPCXpresso v5.1.2 [Build 2065] [2013-02-20] on Wed Apr 17 14:50:07 CEST 2013
*/
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
RamLoc64 (rwx) : ORIGIN = 0x100000E8, LENGTH = 0xFF18 /* 64k */
RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32k */
}
/* Define a symbol for the top of each memory region */
__top_MFlash512 = 0x0 + 0x80000;
__top_RamLoc64 = 0x10000000 + 0x10000;
__top_RamPeriph32 = 0x20000000 + 0x8000;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(8)
{
FILL(0xff)
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data)) ;
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2)) ;
LONG( SIZEOF(.data_RAM2));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
*(.text*)
*(.rodata .rodata.*)
. = ALIGN(8);
/* C++ constructors etc */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(8);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* End C++ */
} > MFlash512
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash512
__exidx_start = .;
.ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash512
__exidx_end = .;
_etext = .;
/* DATA section for RamPeriph32 */
.data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.data.$RAM2*)
*(.data.$RamPeriph32*)
. = ALIGN(8) ;
} > RamPeriph32 AT>MFlash512
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
. = ALIGN(8) ;
_end_uninit_RESERVED = .;
} > RamLoc64
.data : ALIGN(8)
{
FILL(0xff)
_data = .;
*(vtable)
*(.data*)
. = ALIGN(8) ;
_edata = .;
} > RamLoc64 AT>MFlash512
/* BSS section for RamPeriph32 */
.bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamPeriph32*)
. = ALIGN(8) ;
} > RamPeriph32
/* MAIN BSS SECTION */
.bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
__end__ = .;
} > RamLoc64
/* NOINIT section for RamPeriph32 */
.noinit_RAM2 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM2*)
*(.noinit.$RamPeriph32*)
. = ALIGN(8) ;
} > RamPeriph32
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(8)
{
_noinit = .;
*(.noinit*)
. = ALIGN(8) ;
_end_noinit = .;
} > RamLoc64
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_RamLoc64 - 0);
}

420
targets/TARGET_NXP/TARGET_LPC408X/device/TOOLCHAIN_GCC_CR/startup_lpc407x_8x.cpp
View File

@ -1,420 +0,0 @@
//*****************************************************************************
// +--+
// | ++----+
// +-++ |
// | |
// +-+--+ |
// | +--+--+
// +----+ Copyright (c) 2012 Code Red Technologies Ltd.
//
// LPC407x_8x Microcontroller Startup code for use with Red Suite
//
// Version : 120624
//
// Software License Agreement
//
// The software is owned by Code Red Technologies and/or its suppliers, and is
// protected under applicable copyright laws. All rights are reserved. Any
// use in violation of the foregoing restrictions may subject the user to criminal
// sanctions under applicable laws, as well as to civil liability for the breach
// of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
// CODE RED TECHNOLOGIES LTD.
//
//*****************************************************************************
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
//#if defined (__USE_CMSIS)
#include "LPC407x_8x_177x_8x.h"
//#endif
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCI_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART4_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP2_IRQHandler(void) ALIAS(IntDefaultHandler);
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void PWM0_IRQHandler(void) ALIAS(IntDefaultHandler);
void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM3
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC17
WDT_IRQHandler, // 16, 0x40 - WDT
TIMER0_IRQHandler, // 17, 0x44 - TIMER0
TIMER1_IRQHandler, // 18, 0x48 - TIMER1
TIMER2_IRQHandler, // 19, 0x4c - TIMER2
TIMER3_IRQHandler, // 20, 0x50 - TIMER3
UART0_IRQHandler, // 21, 0x54 - UART0
UART1_IRQHandler, // 22, 0x58 - UART1
UART2_IRQHandler, // 23, 0x5c - UART2
UART3_IRQHandler, // 24, 0x60 - UART3
PWM1_IRQHandler, // 25, 0x64 - PWM1
I2C0_IRQHandler, // 26, 0x68 - I2C0
I2C1_IRQHandler, // 27, 0x6c - I2C1
I2C2_IRQHandler, // 28, 0x70 - I2C2
IntDefaultHandler, // 29, Not used
SSP0_IRQHandler, // 30, 0x78 - SSP0
SSP1_IRQHandler, // 31, 0x7c - SSP1
PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
RTC_IRQHandler, // 33, 0x84 - RTC
EINT0_IRQHandler, // 34, 0x88 - EINT0
EINT1_IRQHandler, // 35, 0x8c - EINT1
EINT2_IRQHandler, // 36, 0x90 - EINT2
EINT3_IRQHandler, // 37, 0x94 - EINT3
ADC_IRQHandler, // 38, 0x98 - ADC
BOD_IRQHandler, // 39, 0x9c - BOD
USB_IRQHandler, // 40, 0xA0 - USB
CAN_IRQHandler, // 41, 0xa4 - CAN
DMA_IRQHandler, // 42, 0xa8 - GP DMA
I2S_IRQHandler, // 43, 0xac - I2S
ENET_IRQHandler, // 44, 0xb0 - Ethernet
MCI_IRQHandler, // 45, 0xb4 - SD/MMC card I/F
MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
UART4_IRQHandler, // 51, 0xcc - UART4
SSP2_IRQHandler, // 52, 0xd0 - SSP2
LCD_IRQHandler, // 53, 0xd4 - LCD
GPIO_IRQHandler, // 54, 0xd8 - GPIO
PWM0_IRQHandler, // 55, 0xdc - PWM0
EEPROM_IRQHandler, // 56, 0xe0 - EEPROM
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
extern "C" void software_init_hook(void);
extern "C" void pre_main(void) __attribute__((weak));
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
/*
* Code to enable the Cortex-M4 FPU only included
* if appropriate build options have been selected.
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
*/
// Read CPACR (located at address 0xE000ED88)
// Set bits 20-23 to enable CP10 and CP11 coprocessors
// Write back the modified value to the CPACR
asm volatile ("LDR.W R0, =0xE000ED88\n\t"
"LDR R1, [R0]\n\t"
"ORR R1, R1, #(0xF << 20)\n\t"
"STR R1, [R0]");
#endif // (__VFP_FP__) && !(__SOFTFP__)
// Check to see if we are running the code from a non-zero
// address (eg RAM, external flash), in which case we need
// to modify the VTOR register to tell the CPU that the
// vector table is located at a non-0x0 address.
// Note that we do not use the CMSIS register access mechanism,
// as there is no guarantee that the project has been configured
// to use CMSIS.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
// CMSIS : SCB->VTOR = <address of vector table>
*pSCB_VTOR = (unsigned int)g_pfnVectors;
}
SystemInit();
if (pre_main) { // give control to the RTOS
software_init_hook(); // this will also call __libc_init_array
}
else { // for BareMetal (non-RTOS) build
__libc_init_array();
main();
#endif
}
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void SysTick_Handler(void)
{
while(1)
{
}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{
while(1)
{
}
}

281
targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_GCC_CR/LPC43xx.ld
View File

@ -1,281 +0,0 @@
/* mbed - LPC4330_M4 linker script
* Based linker script generated by Code Red Technologies Red Suite 7.0
*/
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
MEMORY
{
/* Define each memory region */
RamLoc128 (rwx) : ORIGIN = 0x10000118, LENGTH = 0x1FEE8 /* 128K bytes */
RamLoc72 (rwx) : ORIGIN = 0x10080000, LENGTH = 0x12000 /* 72K bytes */
RamAHB32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes */
RamAHB16 (rwx) : ORIGIN = 0x20008000, LENGTH = 0x4000 /* 16K bytes */
RamAHB_ETB16 (rwx) : ORIGIN = 0x2000c000, LENGTH = 0x4000 /* 16K bytes */
SPIFI (rx) : ORIGIN = 0x14000000, LENGTH = 0x400000 /* 4M bytes */
}
/* Define a symbol for the top of each memory region */
__top_RamLoc128 = 0x10000000 + 0x20000;
__top_RamLoc72 = 0x10080000 + 0x12000;
__top_RamAHB32 = 0x20000000 + 0x8000;
__top_RamAHB16 = 0x20008000 + 0x4000;
__top_RamAHB_ETB16 = 0x2000c000 + 0x4000;
__top_SPIFI = 0x14000000 + 0x400000;
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(8)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
LONG(LOADADDR(.data_RAM2));
LONG( ADDR(.data_RAM2));
LONG( SIZEOF(.data_RAM2));
LONG(LOADADDR(.data_RAM3));
LONG( ADDR(.data_RAM3));
LONG( SIZEOF(.data_RAM3));
LONG(LOADADDR(.data_RAM4));
LONG( ADDR(.data_RAM4));
LONG( SIZEOF(.data_RAM4));
LONG(LOADADDR(.data_RAM5));
LONG( ADDR(.data_RAM5));
LONG( SIZEOF(.data_RAM5));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
LONG( ADDR(.bss_RAM2));
LONG( SIZEOF(.bss_RAM2));
LONG( ADDR(.bss_RAM3));
LONG( SIZEOF(.bss_RAM3));
LONG( ADDR(.bss_RAM4));
LONG( SIZEOF(.bss_RAM4));
LONG( ADDR(.bss_RAM5));
LONG( SIZEOF(.bss_RAM5));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
} >SPIFI
.text : ALIGN(8)
{
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
. = ALIGN(8);
/* C++ constructors etc */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(8);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
/* End C++ */
} > SPIFI
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > SPIFI
__exidx_start = .;
.ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > SPIFI
__exidx_end = .;
_etext = .;
/* DATA section for RamLoc72 */
.data_RAM2 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM2)
*(.ramfunc.$RamLoc72)
*(.data.$RAM2*)
*(.data.$RamLoc72*)
. = ALIGN(8) ;
} > RamLoc72 AT>SPIFI
/* DATA section for RamAHB32 */
.data_RAM3 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM3)
*(.ramfunc.$RamAHB32)
*(.data.$RAM3*)
*(.data.$RamAHB32*)
. = ALIGN(8) ;
} > RamAHB32 AT>SPIFI
/* DATA section for RamAHB16 */
.data_RAM4 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM4)
*(.ramfunc.$RamAHB16)
*(.data.$RAM4*)
*(.data.$RamAHB16*)
. = ALIGN(8) ;
} > RamAHB16 AT>SPIFI
/* DATA section for RamAHB_ETB16 */
.data_RAM5 : ALIGN(8)
{
FILL(0xff)
*(.ramfunc.$RAM5)
*(.ramfunc.$RamAHB_ETB16)
*(.data.$RAM5*)
*(.data.$RamAHB_ETB16*)
. = ALIGN(8) ;
} > RamAHB_ETB16 AT>SPIFI
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
. = ALIGN(8) ;
_end_uninit_RESERVED = .;
} > RamLoc128
/* Main DATA section (RamLoc128) */
.data : ALIGN(8)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
. = ALIGN(8) ;
_edata = . ;
} > RamLoc128 AT>SPIFI
/* BSS section for RamLoc72 */
.bss_RAM2 : ALIGN(8)
{
*(.bss.$RAM2*)
*(.bss.$RamLoc72*)
. = ALIGN(8) ;
} > RamLoc72
/* BSS section for RamAHB32 */
.bss_RAM3 : ALIGN(8)
{
*(.bss.$RAM3*)
*(.bss.$RamAHB32*)
. = ALIGN(8) ;
} > RamAHB32
/* BSS section for RamAHB16 */
.bss_RAM4 : ALIGN(8)
{
*(.bss.$RAM4*)
*(.bss.$RamAHB16*)
. = ALIGN(8) ;
} > RamAHB16
/* BSS section for RamAHB_ETB16 */
.bss_RAM5 : ALIGN(8)
{
*(.bss.$RAM5*)
*(.bss.$RamAHB_ETB16*)
. = ALIGN(8) ;
} > RamAHB_ETB16
/* MAIN BSS SECTION */
.bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
} > RamLoc128
/* NOINIT section for RamLoc72 */
.noinit_RAM2 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM2*)
*(.noinit.$RamLoc72*)
. = ALIGN(8) ;
} > RamLoc72
/* NOINIT section for RamAHB32 */
.noinit_RAM3 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM3*)
*(.noinit.$RamAHB32*)
. = ALIGN(8) ;
} > RamAHB32
/* NOINIT section for RamAHB16 */
.noinit_RAM4 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM4*)
*(.noinit.$RamAHB16*)
. = ALIGN(8) ;
} > RamAHB16
/* NOINIT section for RamAHB_ETB16 */
.noinit_RAM5 (NOLOAD) : ALIGN(8)
{
*(.noinit.$RAM5*)
*(.noinit.$RamAHB_ETB16*)
. = ALIGN(8) ;
} > RamAHB_ETB16
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(8)
{
_noinit = .;
*(.noinit*)
. = ALIGN(8) ;
_end_noinit = .;
} > RamLoc128
PROVIDE(_pvHeapStart = .);
PROVIDE(_vStackTop = __top_RamLoc128 - 0);
}

500
targets/TARGET_NXP/TARGET_LPC43XX/device/TOOLCHAIN_GCC_CR/startup_LPC43xx.cpp
View File

@ -1,500 +0,0 @@
//*****************************************************************************
// +--+
// | ++----+
// +-++ |
// | |
// +-+--+ |
// | +--+--+
// +----+ Copyright (c) 2011-12 Code Red Technologies Ltd.
//
// LPC43xx Microcontroller Startup code for use with Red Suite
//
// Version : 120430
//
// Software License Agreement
//
// The software is owned by Code Red Technologies and/or its suppliers, and is
// protected under applicable copyright laws. All rights are reserved. Any
// use in violation of the foregoing restrictions may subject the user to criminal
// sanctions under applicable laws, as well as to civil liability for the breach
// of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
// CODE RED TECHNOLOGIES LTD.
//
//*****************************************************************************
#if defined (__cplusplus)
#ifdef __REDLIB__
#error Redlib does not support C++
#else
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
// Code Red - if CMSIS is being used, then SystemInit() routine
// will be called by startup code rather than in application's main()
#if defined (__USE_CMSIS)
#include "LPC43xx.h"
#endif
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void MemManage_Handler(void);
WEAK void BusFault_Handler(void);
WEAK void UsageFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void DebugMon_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
void M0CORE_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void EZH_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLASH_EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB0_IRQHandler(void) ALIAS(IntDefaultHandler);
void USB1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI_IRQHandler (void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S0_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2S1_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPIFI_IRQHandler(void) ALIAS(IntDefaultHandler);
void SGPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO0_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO1_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO2_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO3_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO4_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO5_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO6_IRQHandler(void) ALIAS(IntDefaultHandler);
void GPIO7_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void EVRT_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN1_IRQHandler(void) ALIAS(IntDefaultHandler);
void VADC_IRQHandler(void) ALIAS(IntDefaultHandler);
void ATIMER_IRQHandler(void) ALIAS(IntDefaultHandler);
void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void M0s_IRQHandler(void) ALIAS(IntDefaultHandler);
void CAN0_IRQHandler(void) ALIAS(IntDefaultHandler);
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// __main() is the entry point for Redlib based applications
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
#if defined (__REDLIB__)
extern void __main(void);
#endif
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM4
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
MemManage_Handler, // The MPU fault handler
BusFault_Handler, // The bus fault handler
UsageFault_Handler, // The usage fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
DebugMon_Handler, // Debug monitor handler
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC43
DAC_IRQHandler, // 16
M0CORE_IRQHandler, // 17
DMA_IRQHandler, // 18
EZH_IRQHandler, // 19
FLASH_EEPROM_IRQHandler, // 20
ETH_IRQHandler, // 21
SDIO_IRQHandler, // 22
LCD_IRQHandler, // 23
USB0_IRQHandler, // 24
USB1_IRQHandler, // 25
SCT_IRQHandler, // 26
RIT_IRQHandler, // 27
TIMER0_IRQHandler, // 28
TIMER1_IRQHandler, // 29
TIMER2_IRQHandler, // 30
TIMER3_IRQHandler, // 31
MCPWM_IRQHandler, // 32
ADC0_IRQHandler, // 33
I2C0_IRQHandler, // 34
I2C1_IRQHandler, // 35
SPI_IRQHandler, // 36
ADC1_IRQHandler, // 37
SSP0_IRQHandler, // 38
SSP1_IRQHandler, // 39
UART0_IRQHandler, // 40
UART1_IRQHandler, // 41
UART2_IRQHandler, // 42
UART3_IRQHandler, // 43
I2S0_IRQHandler, // 44
I2S1_IRQHandler, // 45
SPIFI_IRQHandler, // 46
SGPIO_IRQHandler, // 47
GPIO0_IRQHandler, // 48
GPIO1_IRQHandler, // 49
GPIO2_IRQHandler, // 50
GPIO3_IRQHandler, // 51
GPIO4_IRQHandler, // 52
GPIO5_IRQHandler, // 53
GPIO6_IRQHandler, // 54
GPIO7_IRQHandler, // 55
GINT0_IRQHandler, // 56
GINT1_IRQHandler, // 57
EVRT_IRQHandler, // 58
CAN1_IRQHandler, // 59
0, // 60
VADC_IRQHandler, // 61
ATIMER_IRQHandler, // 62
RTC_IRQHandler, // 63
0, // 64
WDT_IRQHandler, // 65
M0s_IRQHandler, // 66
CAN0_IRQHandler, // 67
QEI_IRQHandler, // 68
};
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//
//*****************************************************************************
void
ResetISR(void) {
// *************************************************************
// The following conditional block of code manually resets as
// much of the peripheral set of the LPC43 as possible. This is
// done because the LPC43 does not provide a means of triggering
// a full system reset under debugger control, which can cause
// problems in certain circumstances when debugging.
//
// You can prevent this code block being included if you require
// (for example when creating a final executable which you will
// not debug) by setting the define 'DONT_RESET_ON_RESTART'.
//
#ifndef DONT_RESET_ON_RESTART
// Disable interrupts
__asm volatile ("cpsid i");
// equivalent to CMSIS '__disable_irq()' function
unsigned int *RESET_CONTROL = (unsigned int *) 0x40053100;
// LPC_RGU->RESET_CTRL0 @ 0x40053100
// LPC_RGU->RESET_CTRL1 @ 0x40053104
// Note that we do not use the CMSIS register access mechanism,
// as there is no guarantee that the project has been configured
// to use CMSIS.
// Write to LPC_RGU->RESET_CTRL0
*(RESET_CONTROL+0) = 0x10DF0000;
// GPIO_RST|AES_RST|ETHERNET_RST|SDIO_RST|DMA_RST|
// USB1_RST|USB0_RST|LCD_RST
// Write to LPC_RGU->RESET_CTRL1
*(RESET_CONTROL+1) = 0x01DFF7FF;
// M0APP_RST|CAN0_RST|CAN1_RST|I2S_RST|SSP1_RST|SSP0_RST|
// I2C1_RST|I2C0_RST|UART3_RST|UART1_RST|UART1_RST|UART0_RST|
// DAC_RST|ADC1_RST|ADC0_RST|QEI_RST|MOTOCONPWM_RST|SCT_RST|
// RITIMER_RST|TIMER3_RST|TIMER2_RST|TIMER1_RST|TIMER0_RST
// Clear all pending interrupts in the NVIC
volatile unsigned int *NVIC_ICPR = (unsigned int *) 0xE000E280;
unsigned int irqpendloop;
for (irqpendloop = 0; irqpendloop < 8; irqpendloop++) {
*(NVIC_ICPR+irqpendloop)= 0xFFFFFFFF;
}
// Reenable interrupts
__asm volatile ("cpsie i");
// equivalent to CMSIS '__enable_irq()' function
#endif // ifndef DONT_RESET_ON_RESTART
// *************************************************************
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
/*
* Code to enable the Cortex-M4 FPU only included
* if appropriate build options have been selected.
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
*/
// CPACR is located at address 0xE000ED88
asm("LDR.W R0, =0xE000ED88");
// Read CPACR
asm("LDR R1, [R0]");
// Set bits 20-23 to enable CP10 and CP11 coprocessors
asm(" ORR R1, R1, #(0xF << 20)");
// Write back the modified value to the CPACR
asm("STR R1, [R0]");
#endif // (__VFP_FP__) && !(__SOFTFP__)
// ******************************
// Check to see if we are running the code from a non-zero
// address (eg RAM, external flash), in which case we need
// to modify the VTOR register to tell the CPU that the
// vector table is located at a non-0x0 address.
// Note that we do not use the CMSIS register access mechanism,
// as there is no guarantee that the project has been configured
// to use CMSIS.
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
// CMSIS : SCB->VTOR = <address of vector table>
*pSCB_VTOR = (unsigned int)g_pfnVectors;
}
#ifdef __USE_CMSIS
SystemInit();
#endif
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
#if defined (__REDLIB__)
// Call the Redlib library, which in turn calls main()
__main() ;
#else
main();
#endif
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void MemManage_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void BusFault_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void UsageFault_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void DebugMon_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{
while(1)
{
}
}
__attribute__ ((section(".after_vectors")))
void SysTick_Handler(void)
{
while(1)
{
}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{
while(1)
{
}
}

199
targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_CR/LPC824.ld
View File

@ -1,199 +0,0 @@
/*Based on following file
* (c) Code Red Technologies Ltd, 2008-13
* (c) NXP Semiconductors 2013-2015
* Generated linker script file for LPC824
* Created from generic_c.ld (LPCXpresso v7.4 (0 [Build 229] [2014-09-16] ))
* By LPCXpresso v7.4.0 [Build 229] [2014-09-16] on Fri Jan 02 03:36:48 JST 2015
*/
/* Linker script to configure memory regions. */
MEMORY
{
/* Define each memory region */
MFlash32 (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */
RamLoc8 (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */
}
/* Define a symbol for the top of each memory region */
__top_MFlash32 = 0x0 + 0x8000;
__top_RamLoc8 = 0x10000000 + 0x2000;
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
/*GROUP(libcr_nohost.a libcr_c.a libcr_eabihelpers.a libm.a)*/
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(ResetISR)
SECTIONS
{
/* MAIN TEXT SECTION */
.text : ALIGN(8)
{
FILL(0xff)
__vectors_start__ = ABSOLUTE(.) ;
KEEP(*(.isr_vector))
/* Global Section Table */
. = ALIGN(8) ;
__section_table_start = .;
__data_section_table = .;
LONG(LOADADDR(.data));
LONG( ADDR(.data));
LONG( SIZEOF(.data));
__data_section_table_end = .;
__bss_section_table = .;
LONG( ADDR(.bss));
LONG( SIZEOF(.bss));
__bss_section_table_end = .;
__section_table_end = . ;
/* End of Global Section Table */
*(.after_vectors*)
} >MFlash32
.text : ALIGN(8)
{
*(.text*)
*(.rodata .rodata.* .constdata .constdata.*)
. = ALIGN(8);
/* C++ constructors etc */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
KEEP(*(.fini));
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > MFlash32
/*
* for exception handling/unwind - some Newlib functions (in common
* with C++ and STDC++) use this.
*/
.ARM.extab : ALIGN(8)
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > MFlash32
__exidx_start = .;
.ARM.exidx : ALIGN(8)
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > MFlash32
__exidx_end = .;
_etext = .;
/* MAIN DATA SECTION */
/* Default MTB section */
.mtb_buffer_default (NOLOAD) :
{
KEEP(*(.mtb*))
} > RamLoc8
.uninit_RESERVED : ALIGN(8)
{
KEEP(*(.bss.$RESERVED*))
. = ALIGN(8) ;
_end_uninit_RESERVED = .;
} > RamLoc8
/* Main DATA section (RamLoc8) */
.data : ALIGN(8)
{
FILL(0xff)
_data = . ;
*(vtable)
*(.ramfunc*)
*(.data*)
. = ALIGN(8) ;
_edata = . ;
} > RamLoc8 AT>MFlash32
/* MAIN BSS SECTION */
.bss : ALIGN(8)
{
_bss = .;
*(.bss*)
*(COMMON)
. = ALIGN(8) ;
_ebss = .;
PROVIDE(end = .);
} > RamLoc8
/* DEFAULT NOINIT SECTION */
.noinit (NOLOAD): ALIGN(8)
{
_noinit = .;
*(.noinit*)
. = ALIGN(8) ;
_end_noinit = .;
} > RamLoc8
PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc8 - 0);
}

333
targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_CR/startup_LPC824_CR.cpp
View File

@ -1,333 +0,0 @@
//*****************************************************************************
// LPC82x Microcontroller Startup code for use with LPCXpresso IDE
//
// Version : 140901
//*****************************************************************************
//
// Copyright(C) NXP Semiconductors, 2014
// All rights reserved.
//
// Software that is described herein is for illustrative purposes only
// which provides customers with programming information regarding the
// LPC products. This software is supplied "AS IS" without any warranties of
// any kind, and NXP Semiconductors and its licensor disclaim any and
// all warranties, express or implied, including all implied warranties of
// merchantability, fitness for a particular purpose and non-infringement of
// intellectual property rights. NXP Semiconductors assumes no responsibility
// or liability for the use of the software, conveys no license or rights under any
// patent, copyright, mask work right, or any other intellectual property rights in
// or to any products. NXP Semiconductors reserves the right to make changes
// in the software without notification. NXP Semiconductors also makes no
// representation or warranty that such application will be suitable for the
// specified use without further testing or modification.
//
// Permission to use, copy, modify, and distribute this software and its
// documentation is hereby granted, under NXP Semiconductors' and its
// licensor's relevant copyrights in the software, without fee, provided that it
// is used in conjunction with NXP Semiconductors microcontrollers. This
// copyright, permission, and disclaimer notice must appear in all copies of
// this code.
//*****************************************************************************
#if defined (__cplusplus)
//*****************************************************************************
//
// The entry point for the C++ library startup
//
//*****************************************************************************
extern "C" {
extern void __libc_init_array(void);
}
#endif
#define WEAK __attribute__ ((weak))
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
//*****************************************************************************
#if defined (__cplusplus)
extern "C" {
#endif
//*****************************************************************************
// Declaration of external SystemInit function
extern void SystemInit(void);
// Patch the AEABI integer divide functions to use MCU's romdivide library
#ifdef __USE_ROMDIVIDE
// Location in memory that holds the address of the ROM Driver table
#define PTR_ROM_DRIVER_TABLE ((unsigned int *)(0x1FFF1FF8))
// Variables to store addresses of idiv and udiv functions within MCU ROM
unsigned int *pDivRom_idiv;
unsigned int *pDivRom_uidiv;
#endif
//*****************************************************************************
//
// Forward declaration of the default handlers. These are aliased.
// When the application defines a handler (with the same name), this will
// automatically take precedence over these weak definitions
//
//*****************************************************************************
void ResetISR(void);
WEAK void NMI_Handler(void);
WEAK void HardFault_Handler(void);
WEAK void SVC_Handler(void);
WEAK void PendSV_Handler(void);
WEAK void SysTick_Handler(void);
WEAK void IntDefaultHandler(void);
//*****************************************************************************
//
// Forward declaration of the specific IRQ handlers. These are aliased
// to the IntDefaultHandler, which is a 'forever' loop. When the application
// defines a handler (with the same name), this will automatically take
// precedence over these weak definitions
//
//*****************************************************************************
void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SPI1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
void SCT_IRQHandler(void) ALIAS(IntDefaultHandler);
void MRT_IRQHandler(void) ALIAS(IntDefaultHandler);
void CMP_IRQHandler(void) ALIAS(IntDefaultHandler);
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
void FLASH_IRQHandler(void) ALIAS(IntDefaultHandler);
void WKT_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_SEQA_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_SEQB_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
void ADC_OVR_IRQHandler(void) ALIAS(IntDefaultHandler);
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
void I2C3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
//*****************************************************************************
//
// The entry point for the application.
// main() is the entry point for Newlib based applications
//
//*****************************************************************************
extern int main(void);
//*****************************************************************************
//
// External declaration for the pointer to the stack top from the Linker Script
//
//*****************************************************************************
extern void _vStackTop(void);
//*****************************************************************************
#if defined (__cplusplus)
} // extern "C"
#endif
//*****************************************************************************
//
// The vector table.
// This relies on the linker script to place at correct location in memory.
//
//*****************************************************************************
extern void (* const g_pfnVectors[])(void);
__attribute__ ((section(".isr_vector")))
void (* const g_pfnVectors[])(void) = {
// Core Level - CM0plus
&_vStackTop, // The initial stack pointer
ResetISR, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
0, // Reserved
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
// Chip Level - LPC82x
SPI0_IRQHandler, // SPI0 controller
SPI1_IRQHandler, // SPI1 controller
0, // Reserved
UART0_IRQHandler, // UART0
UART1_IRQHandler, // UART1
UART2_IRQHandler, // UART2
0, // Reserved
I2C1_IRQHandler, // I2C1 controller
I2C0_IRQHandler, // I2C0 controller
SCT_IRQHandler, // Smart Counter Timer
MRT_IRQHandler, // Multi-Rate Timer
CMP_IRQHandler, // Comparator
WDT_IRQHandler, // Watchdog
BOD_IRQHandler, // Brown Out Detect
FLASH_IRQHandler, // Flash Interrupt
WKT_IRQHandler, // Wakeup timer
ADC_SEQA_IRQHandler, // ADC sequence A completion
ADC_SEQB_IRQHandler, // ADC sequence B completion
ADC_THCMP_IRQHandler, // ADC threshold compare
ADC_OVR_IRQHandler, // ADC overrun
DMA_IRQHandler, // DMA
I2C2_IRQHandler, // I2C2 controller
I2C3_IRQHandler, // I2C3 controller
0, // Reserved
PIN_INT0_IRQHandler, // PIO INT0
PIN_INT1_IRQHandler, // PIO INT1
PIN_INT2_IRQHandler, // PIO INT2
PIN_INT3_IRQHandler, // PIO INT3
PIN_INT4_IRQHandler, // PIO INT4
PIN_INT5_IRQHandler, // PIO INT5
PIN_INT6_IRQHandler, // PIO INT6
PIN_INT7_IRQHandler, // PIO INT7
}; /* End of g_pfnVectors */
//*****************************************************************************
// Functions to carry out the initialization of RW and BSS data sections. These
// are written as separate functions rather than being inlined within the
// ResetISR() function in order to cope with MCUs with multiple banks of
// memory.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int *pulSrc = (unsigned int*) romstart;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = *pulSrc++;
}
__attribute__ ((section(".after_vectors")))
void bss_init(unsigned int start, unsigned int len) {
unsigned int *pulDest = (unsigned int*) start;
unsigned int loop;
for (loop = 0; loop < len; loop = loop + 4)
*pulDest++ = 0;
}
//*****************************************************************************
// The following symbols are constructs generated by the linker, indicating
// the location of various points in the "Global Section Table". This table is
// created by the linker via the Code Red managed linker script mechanism. It
// contains the load address, execution address and length of each RW data
// section and the execution and length of each BSS (zero initialized) section.
//*****************************************************************************
extern unsigned int __data_section_table;
extern unsigned int __data_section_table_end;
extern unsigned int __bss_section_table;
extern unsigned int __bss_section_table_end;
//*****************************************************************************
// Reset entry point for your code.
// Sets up a simple runtime environment and initializes the C/C++
// library.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void
ResetISR(void) {
//
// Copy the data sections from flash to SRAM.
//
unsigned int LoadAddr, ExeAddr, SectionLen;
unsigned int *SectionTableAddr;
// Load base address of Global Section Table
SectionTableAddr = &__data_section_table;
// Copy the data sections from flash to SRAM.
while (SectionTableAddr < &__data_section_table_end) {
LoadAddr = *SectionTableAddr++;
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
data_init(LoadAddr, ExeAddr, SectionLen);
}
// At this point, SectionTableAddr = &__bss_section_table;
// Zero fill the bss segment
while (SectionTableAddr < &__bss_section_table_end) {
ExeAddr = *SectionTableAddr++;
SectionLen = *SectionTableAddr++;
bss_init(ExeAddr, SectionLen);
}
// Patch the AEABI integer divide functions to use MCU's romdivide library
#ifdef __USE_ROMDIVIDE
// Get address of Integer division routines function table in ROM
unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4];
// Get addresses of integer divide routines in ROM
// These address are then used by the code in aeabi_romdiv_patch.s
pDivRom_idiv = (unsigned int *)div_ptr[0];
pDivRom_uidiv = (unsigned int *)div_ptr[1];
#endif
SystemInit();
#if defined (__cplusplus)
//
// Call C++ library initialisation
//
__libc_init_array();
#endif
main();
//
// main() shouldn't return, but if it does, we'll just enter an infinite loop
//
while (1) {
;
}
}
//*****************************************************************************
// Default exception handlers. Override the ones here by defining your own
// handler routines in your application code.
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void NMI_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void HardFault_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void SVC_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void PendSV_Handler(void)
{ while(1) {}
}
__attribute__ ((section(".after_vectors")))
void SysTick_Handler(void)
{ while(1) {}
}
//*****************************************************************************
//
// Processor ends up here if an unexpected interrupt occurs or a specific
// handler is not present in the application code.
//
//*****************************************************************************
__attribute__ ((section(".after_vectors")))
void IntDefaultHandler(void)
{ while(1) {}
}