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Addressed review comments to correct size values

pull/9766/head
deepikabhavnani 2019-02-21 22:12:32 -06:00 committed by Deepika
parent 0ff2d42143
commit 75040535ed
2 changed files with 6 additions and 4 deletions
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9
targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_MICRO/NANO130.sct
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@ -9,7 +9,7 @@
#define MBED_APP_SIZE 0x00020000
#endif
; 64 KB SRAM (internal)
; 16 KB SRAM (internal)
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
@ -23,7 +23,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define VECTOR_SIZE (4*(16 + 142))
; Does not support vector table relocation
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
@ -43,5 +43,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) ; 512 KB APROM
ScatterAssert(ImageLimit(RW_IRAM1) <= (MBED_RAM_START + MBED_RAM_SIZE)) ; 64 KB SRAM (internal)
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) ; 128 KB APROM
ScatterAssert(ImageLimit(RW_IRAM1) <= (MBED_RAM_START + MBED_RAM_SIZE)) ; 16 KB SRAM (internal)

1
targets/TARGET_NXP/TARGET_LPC11U6X/device/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/startup_LPC11U6x.S
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@ -234,6 +234,7 @@ USBWAKEUP_IRQHandler
ALIGN
; User Initial Stack & Heap
EXPORT __initial_sp