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Add PWM pin for GR-LYCHEE

pull/9952/head
d-kato 2019-03-07 12:26:53 +09:00
parent 9c8d263b4e
commit c5b01bf429
5 changed files with 31 additions and 3 deletions
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2
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralNames.h
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@ -51,7 +51,9 @@ typedef enum {
PWM_TIOC0A = 0x20,
PWM_TIOC0C,
PWM_TIOC1A,
PWM_TIOC1B,
PWM_TIOC2A,
PWM_TIOC2B,
PWM_TIOC3A,
PWM_TIOC3C,
PWM_TIOC4A,

8
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/PeripheralPins.c
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@ -246,6 +246,14 @@ const PinMap PinMap_PWM[] = {
{P7_9 , PWM_TIOC1A, 6},
{P9_2 , PWM_TIOC1A, 5}, /* for 208QFP */
{P2_7 , PWM_TIOC1A, 3},
{P9_3 , PWM_TIOC1B, 5}, /* for 208QFP */
{P4_0 , PWM_TIOC1B, 3},
{P2_6 , PWM_TIOC2A, 3},
{P5_14 , PWM_TIOC2A, 4},
{P7_0 , PWM_TIOC2A, 5},
{P9_4 , PWM_TIOC2A, 5}, /* for 208QFP */
{P9_5 , PWM_TIOC2B, 5}, /* for 208QFP */
{P4_1 , PWM_TIOC2B, 3},
{P6_7 , PWM_TIOC3A, 5},
{P2_5 , PWM_TIOC3A, 3},
{P3_11 , PWM_TIOC3A, 3},

2
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralNames.h
View File

@ -54,7 +54,9 @@ typedef enum {
PWM_TIOC0A = 0x20,
PWM_TIOC0C,
PWM_TIOC1A,
PWM_TIOC1B,
PWM_TIOC2A,
PWM_TIOC2B,
PWM_TIOC3A,
PWM_TIOC3C,
PWM_TIOC4A,

2
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h
View File

@ -54,7 +54,9 @@ typedef enum {
PWM_TIOC0A = 0x20,
PWM_TIOC0C,
PWM_TIOC1A,
PWM_TIOC1B,
PWM_TIOC2A,
PWM_TIOC2B,
PWM_TIOC3A,
PWM_TIOC3C,
PWM_TIOC4A,

20
targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c
View File

@ -125,7 +125,9 @@ static st_mtu2_ctrl_t mtu2_ctl[] = {
{ TIOC0A, &MTU2TGRA_0, &MTU2TGRC_0, &MTU2TGRB_0, &MTU2TGRD_0, &MTU2TIORH_0, &MTU2TCR_0, &MTU2TMDR_0, 125000 }, // PWM_TIOC0A
{ TIOC0C, &MTU2TGRC_0, &MTU2TGRA_0, &MTU2TGRB_0, &MTU2TGRD_0, &MTU2TIORL_0, &MTU2TCR_0, &MTU2TMDR_0, 125000 }, // PWM_TIOC0C
{ TIOC1A, &MTU2TGRA_1, NULL , &MTU2TGRB_1, NULL , &MTU2TIOR_1 , &MTU2TCR_1, &MTU2TMDR_1, 503000 }, // PWM_TIOC1A
{ TIOC1B, &MTU2TGRB_1, NULL , &MTU2TGRA_1, NULL , &MTU2TIOR_1 , &MTU2TCR_1, &MTU2TMDR_1, 503000 }, // PWM_TIOC1B
{ TIOC2A, &MTU2TGRA_2, NULL , &MTU2TGRB_2, NULL , &MTU2TIOR_2 , &MTU2TCR_2, &MTU2TMDR_2, 2000000 }, // PWM_TIOC2A
{ TIOC2B, &MTU2TGRB_2, NULL , &MTU2TGRA_2, NULL , &MTU2TIOR_2 , &MTU2TCR_2, &MTU2TMDR_2, 2000000 }, // PWM_TIOC2B
{ TIOC3A, &MTU2TGRA_3, &MTU2TGRC_3, &MTU2TGRB_3, &MTU2TGRD_3, &MTU2TIORH_3, &MTU2TCR_3, &MTU2TMDR_3, 2000000 }, // PWM_TIOC3A
{ TIOC3C, &MTU2TGRC_3, &MTU2TGRA_3, &MTU2TGRB_3, &MTU2TGRD_3, &MTU2TIORL_3, &MTU2TCR_3, &MTU2TMDR_3, 2000000 }, // PWM_TIOC3C
{ TIOC4A, &MTU2TGRA_4, &MTU2TGRC_4, &MTU2TGRB_4, &MTU2TGRD_4, &MTU2TIORH_4, &MTU2TCR_4, &MTU2TMDR_4, 2000000 }, // PWM_TIOC4A
@ -250,7 +252,11 @@ void pwmout_write(pwmout_t* obj, float value) {
} else {
if ((wk_pulse == wk_cycle) || (wk_pulse == 0)) {
MTU2TSTR &= ~tmp_tstr_st;
*p_mtu2_ctl->tior = 0x65;
if (((uint8_t)p_mtu2_ctl->port & 0x0F) == 0x01) {
*p_mtu2_ctl->tior = 0x56;
} else {
*p_mtu2_ctl->tior = 0x65;
}
}
}
*p_mtu2_ctl->pulse1 = (uint16_t)((float)wk_cycle * value);
@ -392,7 +398,11 @@ void pwmout_period_us(pwmout_t* obj, int us) {
}
wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000);
tmp_tcr_up = 0x40;
if (((uint8_t)p_mtu2_ctl->port & 0x0F) == 0x01) {
tmp_tcr_up = 0x20;
} else {
tmp_tcr_up = 0x40;
}
if ((obj->ch == 4) || (obj->ch == 3)) {
tmp_tstr_st = (1 << (obj->ch + 3));
} else {
@ -414,7 +424,11 @@ void pwmout_period_us(pwmout_t* obj, int us) {
set_mtu2_duty_again(p_mtu2_ctl->pulse2, wk_last_cycle, wk_cycle);
}
// Set mode
*p_mtu2_ctl->tmdr = 0x02; // PWM mode 1
if (((uint8_t)p_mtu2_ctl->port & 0x0F) == 0x01) {
*p_mtu2_ctl->tmdr = 0x03; // PWM mode 2
} else {
*p_mtu2_ctl->tmdr = 0x02; // PWM mode 1
}
// Counter Start
MTU2TSTR |= tmp_tstr_st;
// Save for future use