mirror of https://github.com/ARMmbed/mbed-os.git
STM32WB: update deep sleep sequence
Review HSE clock initialization to match with latest CUBE firmware. Also there is no need to set the full clock tree again after deep sleep exit. With this change we get a stable deep sleep mode (when allowed by CORDIO stack).pull/9814/head
Laurent Meunier
parent
b21110d6b8
commit
718b16545c
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@ -34,6 +34,8 @@
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#include "stm32wbxx.h"
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#include "mbed_error.h"
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#include "stm32wbxx_ll_hsem.h"
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#include "stm32wbxx_ll_hsem.h"
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#include "otp.h"
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#include "hw_conf.h" /* Common BLE file where BLE shared resources are defined */
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// Clock source is selected with CLOCK_SOURCE in json config
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@ -56,7 +58,59 @@ uint8_t SetSysClock_PLL_HSI(void);
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uint8_t SetSysClock_PLL_MSI(void);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
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void Configure_RF_Clock_Sources(void);
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static void Configure_RF_Clock_Sources(void)
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{
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static uint8_t RF_ON = 0;
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if ( !RF_ON ) {
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// Reset backup domain
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if ((LL_RCC_IsActiveFlag_PINRST()) && (!LL_RCC_IsActiveFlag_SFTRST())) {
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// Write twice the value to flush the APB-AHB bridge
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// This bit shall be written in the register before writing the next one
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HAL_PWR_EnableBkUpAccess();
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HAL_PWR_EnableBkUpAccess();
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__HAL_RCC_BACKUPRESET_FORCE();
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__HAL_RCC_BACKUPRESET_RELEASE();
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}
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/**
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* Select LSE clock
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*/
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LL_RCC_LSE_Enable();
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while (!LL_RCC_LSE_IsReady());
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/**
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* Select wakeup source of BLE RF
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*/
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LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE);
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/**
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* Switch OFF LSI
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*/
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LL_RCC_LSI1_Disable();
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RF_ON = 1;
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}
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return;
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}
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static void Config_HSE(void)
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{
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OTP_ID0_t * p_otp;
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/**
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* Read HSE_Tuning from OTP
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*/
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p_otp = (OTP_ID0_t *) OTP_Read(0);
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if (p_otp)
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{
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LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
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}
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return;
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}
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers
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@ -112,43 +166,69 @@ void SetSysClock(void)
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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{
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LL_RCC_HSE_Enable();
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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/**
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* Switch to HSE as Sys clok source
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* All Peripehrals (HCLK, HCLK2, HCLK4, PCLK1, PCLK2) will be clocked
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* @ 32MHZ. This is not optimal but a stable setting for enter and exit
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* deep sleep mode (STOP mode).
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*
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*/
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while(!LL_RCC_HSE_IsReady());
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LL_RCC_SetSysClkSource( LL_RCC_SYS_CLKSOURCE_HSE );
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
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Config_HSE();
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/**
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* Set RNG on HSI48
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*/
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LL_RCC_HSI48_Enable();
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while (!LL_RCC_HSI48_IsReady());
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LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_HSI48);
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/** Configure the main internal regulator output voltage
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*/
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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/** Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI1
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|RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.LSIState = RCC_LSI_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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return 0; // FAIL
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}
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/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
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|RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
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/**
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* Switch OFF MSI and HSI
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*/
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LL_RCC_MSI_Disable();
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LL_RCC_HSI_Disable();
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
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{
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return 0; // FAIL
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}
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/** Initializes the peripherals clocks
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*/
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS|RCC_PERIPHCLK_RFWAKEUP
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|RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_USART1
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|RCC_PERIPHCLK_LPUART1;
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PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
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PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
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PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSI;
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PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
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PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
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// Output clock on MCO1 pin(PA8) for debugging purpose
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#if DEBUG_MCO == 2
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if (bypass == 0) {
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HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_4); // 8 MHz
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} else {
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HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
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}
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#endif
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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{
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return 0; // FAIL
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}
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return 1;
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/**
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* Select HSI as system clock source after Wake Up from Stop mode
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*/
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LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
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return 1;
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}
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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@ -271,33 +351,3 @@ uint8_t SetSysClock_PLL_MSI(void)
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}
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#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
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void Configure_RF_Clock_Sources(void)
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{
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// Reset backup domain
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if ((LL_RCC_IsActiveFlag_PINRST()) && (!LL_RCC_IsActiveFlag_SFTRST())) {
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// Write twice the value to flush the APB-AHB bridge
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// This bit shall be written in the register before writing the next one
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HAL_PWR_EnableBkUpAccess();
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HAL_PWR_EnableBkUpAccess();
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__HAL_RCC_BACKUPRESET_FORCE();
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__HAL_RCC_BACKUPRESET_RELEASE();
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}
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/**
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* Select LSE clock
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*/
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LL_RCC_LSE_Enable();
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while (!LL_RCC_LSE_IsReady());
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/**
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* Select wakeup source of BLE RF
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*/
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LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE);
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/**
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* Switch OFF LSI
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*/
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LL_RCC_LSI1_Disable();
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return;
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}
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@ -191,55 +191,53 @@ void SystemInit(void)
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{
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OTP_ID0_t * p_otp;
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/* FPU settings ------------------------------------------------------------*/
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL))); /* set CP10 and CP11 Full Access */
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#endif
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/**
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* Read HSE_Tuning from OTP
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*/
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p_otp = (OTP_ID0_t *) OTP_Read(0);
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if (p_otp)
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{
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LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
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}
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/* Reset the RCC clock configuration to the default reset state ------------*/
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LL_RCC_HSE_Enable();
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/* Set MSION bit */
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RCC->CR |= RCC_CR_MSION;
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/**
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* Set FLASH latency to 1WS
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*/
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LL_FLASH_SetLatency( LL_FLASH_LATENCY_1 );
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while( LL_FLASH_GetLatency() != LL_FLASH_LATENCY_1 );
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/* Reset CFGR register */
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RCC->CFGR = 0x00070000U;
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/**
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* Switch to HSE
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*
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*/
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while(!LL_RCC_HSE_IsReady());
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LL_RCC_SetSysClkSource( LL_RCC_SYS_CLKSOURCE_HSE );
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
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/* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
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RCC->CR &= (uint32_t)0xFAF6FEFBU;
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/**
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* Switch OFF MSI
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*/
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LL_RCC_MSI_Disable();
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/*!< Reset LSI1 and LSI2 bits */
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RCC->CSR &= (uint32_t)0xFFFFFFFAU;
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/*!< Reset HSI48ON bit */
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RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x22041000U;
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/* Reset PLLSAI1CFGR register */
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RCC->PLLSAI1CFGR = 0x22041000U;
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/* Reset HSEBYP bit */
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RCC->CR &= 0xFFFBFFFFU;
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/* Disable all interrupts */
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RCC->CIER = 0x00000000;
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef CORE_CM0PLUS
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/* program in SRAM2A */
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#if defined(VECT_TAB_SRAM)
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SCB->VTOR = RAM2A_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM2A for CPU2 */
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#elif defined(VECT_TAB_SRAM2B)
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#elif defined(VECT_TAB_SRAM2B)
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/* program in SRAM2B */
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SCB->VTOR = RAM2B_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM2B for CPU2 */
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#else
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#else
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/* program in FLASH */
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SCB->VTOR = VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif /* Program memory type */
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#else
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#endif /* Program memory type */
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#else
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#if defined(VECT_TAB_SRAM)
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/* program in SRAM1 */
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SCB->VTOR = RAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM1 for CPU1 */
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@ -294,78 +292,68 @@ void SystemInit(void)
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
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uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
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/* Get MSI Range frequency--------------------------------------------------*/
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/* Get MSI Range frequency--------------------------------------------------*/
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/*MSI frequency range in Hz*/
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msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
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/*MSI frequency range in Hz*/
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msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
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/*SystemCoreClock=HAL_RCC_GetSysClockFreq();*/
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS)
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{
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case 0x00: /* MSI used as system clock source */
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SystemCoreClock = msirange;
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break;
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS)
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{
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case 0x00: /* MSI used as system clock source */
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SystemCoreClock = msirange;
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break;
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case 0x04: /* HSI used as system clock source */
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/* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSI used as system clock source */
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/* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x08: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x0C: /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
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case 0x0C: /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
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SYSCLK = PLL_VCO / PLLR
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
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pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1 ;
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
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pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
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switch (pllsource)
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{
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case 0x02: /* HSI used as PLL clock source */
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pllvco = (HSI_VALUE / pllm);
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break;
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if(pllsource == 0x02UL) /* HSI used as PLL clock source */
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{
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pllvco = (HSI_VALUE / pllm);
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}
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else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
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{
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pllvco = (HSE_VALUE / pllm);
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}
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else /* MSI used as PLL clock source */
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{
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pllvco = (msirange / pllm);
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}
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pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
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pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
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SystemCoreClock = pllvco/pllr;
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break;
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case 0x03: /* HSE used as PLL clock source */
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pllvco = (HSE_VALUE / pllm);
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break;
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default: /* MSI used as PLL clock source */
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pllvco = (msirange / pllm);
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break;
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}
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pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
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pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1);
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SystemCoreClock = pllvco/pllr;
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break;
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default:
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SystemCoreClock = msirange;
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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#ifdef CORE_CM0PLUS
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/* Get HCLK2 prescaler */
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tmp = AHBPrescTable[((RCC->EXTCFGR & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos)];
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#else
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/* Get HCLK1 prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
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#endif
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/* HCLK clock frequency */
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SystemCoreClock = SystemCoreClock / tmp;
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default:
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SystemCoreClock = msirange;
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK1 prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
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/* HCLK clock frequency */
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SystemCoreClock = SystemCoreClock / tmp;
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}
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/**
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* @}
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*/
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@ -43,7 +43,6 @@ extern void save_timer_ctx(void);
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extern void restore_timer_ctx(void);
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extern int serial_is_tx_ongoing(void);
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extern int mbed_sdk_inited;
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extern void SetSysClock(void);
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static void Switch_On_HSI( void )
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{
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@ -63,6 +62,11 @@ static void LPM_EnterStopMode(void)
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while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
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/**
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* Select HSI as system clock source after Wake Up from Stop mode
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*/
|
||||
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
|
||||
|
||||
if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
|
||||
{
|
||||
if( LL_PWR_IsActiveFlag_C2DS() )
|
||||
|
|
@ -173,9 +177,6 @@ void hal_deepsleep(void)
|
|||
HW_LPM_StopMode();
|
||||
LPM_ExitStopMode();
|
||||
|
||||
/* After wake-up from STOP reconfigure the whole clock tree */
|
||||
SetSysClock();
|
||||
|
||||
restore_timer_ctx();
|
||||
|
||||
/* us_ticker context restored, allow HAL_GetTick() to read the us_ticker
|
||||
|
|
|
|||
Loading…
Reference in New Issue