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Merge pull request from NXPmicro/Add_LPC55S96_Exporter_Support 

LPC55S69: Add IAR and uvision exporter support
pull/10118/head
Martin Kojtal 2019-03-15 09:32:40 +01:00 committed by GitHub
parent 0e37fc206c 3da7c6f3c0
commit cde7d0be58
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 116 additions and 3 deletions
tools
arm_pack_manager
export

1
targets/targets.json
View File

@ -2052,6 +2052,7 @@
"LPC"
],
"detect_code": ["0236"],
"device_name": "LPC55S69JBD100",
"release_versions": ["5"]
},
"LPC55S69_NS": {

104
tools/arm_pack_manager/index.json
View File

@ -157016,6 +157016,110 @@
],
"vendor": "NXP:11"
},
"LPC55S69JBD100": {
"algorithms": [
{
"default": false,
"file_name": "arm/LPC55XX_640.FLM",
"ram_size": 4096,
"ram_start": 536870912,
"size": 622592,
"start": 0
}
],
"from_pack": {
"pack": "LPC55S69_DFP",
"url": "http://mcuxpresso.nxp.com/cmsis_pack/repo/",
"vendor": "NXP",
"version": "11.0.0"
},
"memories": {
"PROGRAM_FLASH": {
"access": {
"execute": true,
"non_secure": false,
"non_secure_callable": false,
"peripheral": false,
"read": true,
"secure": false,
"write": false
},
"default": true,
"size": 622592,
"start": 0,
"startup": true
},
"SRAMX": {
"access": {
"execute": false,
"non_secure": false,
"non_secure_callable": false,
"peripheral": false,
"read": true,
"secure": false,
"write": true
},
"default": false,
"size": 32768,
"start": 67108864,
"startup": false
},
"SRAM": {
"access": {
"execute": false,
"non_secure": false,
"non_secure_callable": false,
"peripheral": false,
"read": true,
"secure": false,
"write": true
},
"default": true,
"size": 278528,
"start": 536870912,
"startup": false
},
"USB_RAM": {
"access": {
"execute": false,
"non_secure": false,
"non_secure_callable": false,
"peripheral": false,
"read": true,
"secure": false,
"write": true
},
"default": false,
"size": 16384,
"start": 1074790400,
"startup": false
}
},
"name": "LPC55S69JBD100",
"processor": {
"Asymmetric": {
"cm33_core0": {
"core": "CortexM33",
"fpu": "SinglePrecision",
"mpu": "Present",
"units": 1
},
"cm33_core1": {
"core": "CortexM33",
"fpu": "None",
"mpu": "NotPresent",
"units": 1
}
}
},
"sectors": [
[
0,
32768
]
],
"vendor": "NXP:11"
},
"LPC802M001JDH16": {
"algorithms": [
{

8
tools/export/cmsis/__init__.py
View File

@ -51,10 +51,14 @@ class DeviceCMSIS():
try:
self.dfpu = target_info['processor']['Symmetric']['fpu']
except KeyError:
cmsis_core = self.core.replace("F", "").replace("-", "")
for proc in target_info['processor']['Asymmetric'].values():
# TODO: refactor this into a "base_core_for" function
cmsis_core = self.core.replace("F", "").replace("-", "").replace("E", "")
cmsis_core = cmsis_core.replace("NS", "")
for core_name, proc in target_info['processor']['Asymmetric'].items():
if proc['core'] == cmsis_core:
self.dfpu = proc['fpu']
self.dname = '{}:{}'.format(self.dname, core_name)
break
self.debug, self.dvendor = self.vendor_debug(
target_info.get('vendor') or target_info['from_pack']['vendor']
)

3
tools/export/iar/iar_definitions.json
View File

@ -96,6 +96,9 @@
"LPC54628J512ET180": {
"OGChipSelectEditMenu": "LPC54618J512\tNXP LPC54618J512"
},
"LPC55S69JBD100": {
"OGChipSelectEditMenu": "LPC55S69_core0\tNXP LPC55S69_core0"
},
"STM32F072RB": {
"OGChipSelectEditMenu": "STM32F072RB\tST STM32F072RB"
},

3
tools/export/uvision/__init__.py
View File

@ -137,7 +137,8 @@ class Uvision(Exporter):
"LPC4088Code.binary_hook",
"MTSCode.combine_bins_mts_dot",
"MTSCode.combine_bins_mts_dragonfly",
"NCS36510TargetCode.ncs36510_addfib"
"NCS36510TargetCode.ncs36510_addfib",
"LPC55S69Code.binary_hook"
])
# File associations within .uvprojx file