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Workaround(recommended by compiler team) for FVP_MPS2 targets to use ARM Compiler 6

pull/9888/head
Senthil Ramakrishnan 2019-03-01 13:40:42 -06:00
parent e1e4456c47
commit 45c727ee6f
6 changed files with 11 additions and 11 deletions
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4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -53,11 +53,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections)
.ANY (+RO)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE) { ; RW data
.ANY (+RW +ZI)
*(+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections)
.ANY (+RO)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
.ANY (+RW +ZI)
*(+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections)
.ANY (+RO)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
.ANY (+RW +ZI)
*(+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections)
.ANY (+RO)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
.ANY (+RW +ZI)
*(+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}

4
targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct
View File

@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {
LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region
ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address
*(InRoot$$Sections)
.ANY (+RO)
*(+RO)
}
; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data
.ANY (+RW +ZI)
*(+RW +ZI)
}
ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
}

2
targets/targets.json
View File

@ -7654,7 +7654,7 @@
"FVP_MPS2": {
"inherits": ["ARM_FM"],
"public": false,
"supported_toolchains": ["GCC_ARM", "ARMC5", "IAR"],
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
"OUTPUT_EXT": "elf",
"device_has": [
"AACI",