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Refactoring system clock driver

pull/10213/head
d-kato 2019-03-25 20:24:22 +09:00
parent 2509ea82fd
commit e96c6334f7
6 changed files with 27 additions and 51 deletions
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10
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/os_tick_ostm.c
View File

@ -26,10 +26,7 @@
#include "os_tick.h"
#include "irq_ctrl.h"
#include <MBRZA1LU.h>
#include <cmsis.h>
#include "cmsis.h"
#include "mbed_drv_cfg.h"
@ -145,7 +142,8 @@ void OS_Tick_Enable (void)
}
/// Disable OS Tick.
void OS_Tick_Disable (void) {
void OS_Tick_Disable (void)
{
// Stop the OSTM counter
OSTM.OSTMnTT = 0x01U;
@ -157,7 +155,7 @@ void OS_Tick_Disable (void) {
}
// Acknowledge OS Tick IRQ.
void OS_Tick_AcknowledgeIRQ (void)
void OS_Tick_AcknowledgeIRQ (void)
{
IRQ_ClearPending (OSTM_IRQn);
}

18
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/system_RZ_A1LU.c
View File

@ -26,16 +26,11 @@
* limitations under the License.
*/
#include <RZ_A1LU.h>
#include "RZ_A1LU.h"
#include "RZ_A1_Init.h"
#include "irq_ctrl.h"
#include "mbed_drv_cfg.h"
#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
/*
Port 0 (P0) MD pin assignment
P0_0: MD_BOOT0
@ -66,12 +61,11 @@ void SystemCoreClockUpdate (void)
if (ifc == 0x03U) {
/* Division ratio is 1/3 */
freq = (freq / 3U);
}
else {
if (ifc == 0x01U) {
/* Division ratio is 2/3 */
freq = (freq * 2U) / 3U;
}
} else if (ifc == 0x01U) {
/* Division ratio is 2/3 */
freq = (freq * 2U) / 3U;
} else {
/* do nothing */
}
SystemCoreClock = freq;

5
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/os_tick_ostm.c
View File

@ -26,10 +26,7 @@
#include "os_tick.h"
#include "irq_ctrl.h"
#include <MBRZA1H.h>
#include <cmsis.h>
#include "cmsis.h"
#include "mbed_drv_cfg.h"

17
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c
View File

@ -26,15 +26,11 @@
* limitations under the License.
*/
#include <RZ_A1H.h>
#include "RZ_A1H.h"
#include "RZ_A1_Init.h"
#include "irq_ctrl.h"
#include "mbed_drv_cfg.h"
#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
/*
Port 0 (P0) MD pin assignment
P0_0: MD_BOOT0
@ -65,12 +61,11 @@ void SystemCoreClockUpdate (void)
if (ifc == 0x03U) {
/* Division ratio is 1/3 */
freq = (freq / 3U);
}
else {
if (ifc == 0x01U) {
/* Division ratio is 2/3 */
freq = (freq * 2U) / 3U;
}
} else if (ifc == 0x01U) {
/* Division ratio is 2/3 */
freq = (freq * 2U) / 3U;
} else {
/* do nothing */
}
SystemCoreClock = freq;

5
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c
View File

@ -26,10 +26,7 @@
#include "os_tick.h"
#include "irq_ctrl.h"
#include <VKRZA1H.h>
#include <cmsis.h>
#include "cmsis.h"
#include "mbed_drv_cfg.h"

23
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c
View File

@ -26,15 +26,11 @@
* limitations under the License.
*/
#include <VK_RZ_A1H.h>
#include "VK_RZ_A1H.h"
#include "RZ_A1_Init.h"
#include "irq_ctrl.h"
#include "mbed_drv_cfg.h"
#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
/*
Port 0 (P0) MD pin assignment
P0_0: MD_BOOT0
@ -52,7 +48,7 @@ uint32_t SystemCoreClock = RENESAS_RZ_A1_SYS_CLK;
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
{
uint32_t freq;
uint16_t ifc;
@ -60,21 +56,20 @@ void SystemCoreClockUpdate (void)
/* Get CPG.FRQCR[IFC] bits */
ifc = (CPG.FRQCR >> 8U) & 0x03U;
/* Determine Divider 2 output clock */
if (ifc == 0x03U) {
/* Division ratio is 1/3 */
freq = (freq / 3U);
} else if (ifc == 0x01U) {
/* Division ratio is 2/3 */
freq = (freq * 2U) / 3U;
} else {
/* do nothing */
}
else {
if (ifc == 0x01U) {
/* Division ratio is 2/3 */
freq = (freq * 2U) / 3U;
}
}
SystemCoreClock = freq;
}
}
/*----------------------------------------------------------------------------
IRQ Handler Register/Unregister