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Removed clock mode decision of "SystemCoreClockUpdate()" 

Since GPIO.PPR0 can not check clock mode, I changed it to set a fixed value for each board.
pull/10213/head
d-kato 2019-03-25 20:19:28 +09:00
parent cb31d11319
commit 2509ea82fd
3 changed files with 3 additions and 42 deletions
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15
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/system_RZ_A1LU.c
View File

@ -55,22 +55,9 @@ uint32_t SystemCoreClock = RENESAS_RZ_A1_SYS_CLK;
void SystemCoreClockUpdate (void)
{
uint32_t freq;
uint16_t mode;
uint16_t ifc;
mode = (GPIO.PPR0 >> 2U) & 0x01U;
if (mode == 0) {
/* Clock Mode 0 */
/* CLKIN is between 10MHz and 13.33MHz */
/* Divider 1 uses 1/1 ratio, PLL x30 is ON */
freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
} else {
/* Clock Mode 1 */
/* CLKIN is 48MHz */
/* Divider 1 uses 1/4 ratio, PLL x32 is ON */
freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
}
freq = RENESAS_RZ_A1_SYS_CLK;
/* Get CPG.FRQCR[IFC] bits */
ifc = (CPG.FRQCR >> 8U) & 0x03U;

15
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/system_RZ_A1H.c
View File

@ -54,22 +54,9 @@ uint32_t SystemCoreClock = RENESAS_RZ_A1_SYS_CLK;
void SystemCoreClockUpdate (void)
{
uint32_t freq;
uint16_t mode;
uint16_t ifc;
mode = (GPIO.PPR0 >> 2U) & 0x01U;
if (mode == 0) {
/* Clock Mode 0 */
/* CLKIN is between 10MHz and 13.33MHz */
/* Divider 1 uses 1/1 ratio, PLL x30 is ON */
freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
} else {
/* Clock Mode 1 */
/* CLKIN is 48MHz */
/* Divider 1 uses 1/4 ratio, PLL x32 is ON */
freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
}
freq = RENESAS_RZ_A1_SYS_CLK;
/* Get CPG.FRQCR[IFC] bits */
ifc = (CPG.FRQCR >> 8U) & 0x03U;

15
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c
View File

@ -54,23 +54,10 @@ uint32_t SystemCoreClock = RENESAS_RZ_A1_SYS_CLK;
void SystemCoreClockUpdate (void)
{
uint32_t freq;
uint16_t mode;
uint16_t ifc;
mode = (GPIO.PPR0 >> 2U) & 0x01U;
freq = RENESAS_RZ_A1_SYS_CLK;
if (mode == 0) {
/* Clock Mode 0 */
/* CLKIN is between 10MHz and 13.33MHz */
/* Divider 1 uses 1/1 ratio, PLL x30 is ON */
freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
} else {
/* Clock Mode 1 */
/* CLKIN is 48MHz */
/* Divider 1 uses 1/4 ratio, PLL x32 is ON */
freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
}
/* Get CPG.FRQCR[IFC] bits */
ifc = (CPG.FRQCR >> 8U) & 0x03U;