ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

uARM - Move heap region after IRAM1 

ARM_LIB_HEAP start is aligned to IRAM1 end, hence should be placed next to
RW_IRAM1 i.e. no other region in between.
pull/10019/head
Deepika 2019-03-08 15:06:49 -06:00
parent 6dbc00dd8a
commit 36c7b2de86
17 changed files with 54 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_301/LPC11U24.sct
View File

@ -40,11 +40,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack

6
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U24_401/LPC11U24.sct
View File

@ -40,11 +40,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack

8
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U34_421/LPC11U34.sct
View File

@ -39,14 +39,14 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

8
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U35_401/LPC11U35.sct
View File

@ -39,14 +39,14 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

6
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37H_401/LPC11U37.sct
View File

@ -40,6 +40,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
.ANY (IOHANDLER_RAM)
}
@ -48,9 +51,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (USBRAM)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

6
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11U37_501/LPC11U37.sct
View File

@ -40,6 +40,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
.ANY (IOHANDLER_RAM)
}
@ -48,9 +51,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (USBRAM)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

6
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_MCU_LPC11U35_501/LPC11U35.sct
View File

@ -40,6 +40,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
.ANY (IOHANDLER_RAM)
}
@ -48,9 +51,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (USBRAM)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

6
targets/TARGET_NXP/TARGET_LPC11UXX/device/TOOLCHAIN_ARM_MICRO/TARGET_OC_MBUINO/LPC11U24.sct
View File

@ -40,11 +40,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack

6
targets/TARGET_NXP/TARGET_LPC11XX_11CXX/device/TOOLCHAIN_ARM_MICRO/TARGET_LPC11CXX/LPC11C24.sct
View File

@ -40,13 +40,13 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
RW_IRAM2 0x20004000 0x800 { ; RW data, USB RAM
.ANY (USBRAM)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

6
targets/TARGET_NXP/TARGET_LPC13XX/device/TOOLCHAIN_ARM_MICRO/LPC1347.sct
View File

@ -40,6 +40,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
RW_IRAM2 0x20000000 0x800 { ; RW data, I/O Handler RAM
.ANY (AHBSRAM0)
}
@ -48,9 +51,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (AHBSRAM1)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

6
targets/TARGET_NXP/TARGET_LPC176X/device/TOOLCHAIN_ARM_MICRO/LPC1768.sct
View File

@ -49,6 +49,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
RW_IRAM2 0x2007C000 0x4000 { ; RW data, USB RAM
.ANY (AHBSRAM0)
}
@ -61,9 +64,6 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (CANRAM)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_ARM_MICRO/STM32F407xx.sct
View File

@ -43,11 +43,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
RW_IRAM2 MBED_RAM2_START MBED_RAM2_SIZE { ; CCM
.ANY (CCMRAM)
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
RW_IRAM2 MBED_RAM2_START MBED_RAM2_SIZE { ; CCM
.ANY (CCMRAM)
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack

6
targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/stm32f439xx.sct
View File

@ -79,11 +79,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
RW_IRAM2 MBED_RAM2_START MBED_RAM2_SIZE {
.ANY (+RW +ZI)
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
RW_IRAM2 MBED_RAM2_START MBED_RAM2_SIZE {
.ANY (+RW +ZI)
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack

8
targets/TARGET_STM/TARGET_STM32L4/TARGET_MTS_DRAGONFLY_L471QG/device/TOOLCHAIN_ARM_MICRO/stm32l471xx.sct
View File

@ -73,14 +73,14 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
RW_IRAM1 MBED_RAM_START MBED_RAM_SIZE {
.ANY (+RW +ZI)
}
RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_START-MBED_RAM2_SIZE) {
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_START-MBED_RAM2_SIZE) {
.ANY (+RW +ZI)
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

6
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO/stm32l475xx.sct
View File

@ -79,11 +79,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_SIZE-VECTOR_SIZE) {
.ANY (+RW +ZI)
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_SIZE-VECTOR_SIZE) {
.ANY (+RW +ZI)
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack

6
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_ARM_MICRO/stm32l476xx.sct
View File

@ -79,11 +79,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_SIZE-VECTOR_SIZE) {
.ANY (+RW +ZI)
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_SIZE-VECTOR_SIZE) {
.ANY (+RW +ZI)
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack

6
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_ARM_MICRO/stm32l486xx.sct
View File

@ -79,11 +79,11 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
.ANY (+RW +ZI)
}
RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_SIZE-VECTOR_SIZE) {
.ANY (+RW +ZI)
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
RW_IRAM2 (MBED_RAM2_START+VECTOR_SIZE) (MBED_RAM2_SIZE-VECTOR_SIZE) {
.ANY (+RW +ZI)
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack