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STM32 astyle updates

pull/10570/head
jeromecoutant 2019-05-10 15:32:05 +02:00
parent 2f1338b89f
commit 0352bbbd5b
9 changed files with 172 additions and 183 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
targets/TARGET_STM/TARGET_STM32F7/flash_api.c
View File

@ -284,7 +284,7 @@ static uint32_t GetSectorBase(uint32_t SectorId)
int i = 0;
uint32_t address_sector = FLASH_BASE;
for(i=0;i<SectorId;i++){
for (i = 0; i < SectorId; i++) {
address_sector += GetSectorSize(i);
}
return address_sector;

24
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TARGET_NUCLEO_WB55RG/PeripheralPins.c
View File

@ -141,38 +141,38 @@ MBED_WEAK const PinMap PinMap_PWM[] = {
//*** SERIAL ***
MBED_WEAK const PinMap PinMap_UART_TX[] = {
{PA_2, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_5, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD1 [Blue Led]
{PB_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD1 [Blue Led]
{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX
{PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RX[] = {
{PA_3, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PA_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_DP
{PA_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_DP
{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX
{PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_RTS[] = {
{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP
{PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD3 [Red Led]
{PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD3 [Red Led]
{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to JTDO
{PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{NC, NC, 0}
};
MBED_WEAK const PinMap PinMap_UART_CTS[] = {
{PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM
{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
{PB_13, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{PB_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
{NC, NC, 0}
};

128
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TARGET_NUCLEO_WB55RG/system_clock.c
View File

@ -62,7 +62,7 @@ static void Configure_RF_Clock_Sources(void)
{
static uint8_t RF_ON = 0;
if ( !RF_ON ) {
if (!RF_ON) {
// Reset backup domain
if ((LL_RCC_IsActiveFlag_PINRST()) && (!LL_RCC_IsActiveFlag_SFTRST())) {
// Write twice the value to flush the APB-AHB bridge
@ -97,18 +97,17 @@ static void Configure_RF_Clock_Sources(void)
static void Config_HSE(void)
{
OTP_ID0_t * p_otp;
OTP_ID0_t *p_otp;
/**
* Read HSE_Tuning from OTP
*/
p_otp = (OTP_ID0_t *) OTP_Read(0);
if (p_otp)
{
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
}
/**
* Read HSE_Tuning from OTP
*/
p_otp = (OTP_ID0_t *) OTP_Read(0);
if (p_otp) {
LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning);
}
return;
return;
}
@ -122,7 +121,7 @@ static void Config_HSE(void)
void SetSysClock(void)
{
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
/* 1- Try to start with HSE and external clock */
if (SetSysClock_PLL_HSE(1) == 0)
@ -157,7 +156,7 @@ void SetSysClock(void)
#if DEBUG_MCO == 1
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 64 MHz
#endif
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
}
#if (((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC))
@ -166,66 +165,63 @@ void SetSysClock(void)
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
Config_HSE();
Config_HSE();
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
return 0; // FAIL
}
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4|RCC_CLOCKTYPE_HCLK2
|RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
/** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2
| RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
return 0; // FAIL
}
/** Initializes the peripherals clocks
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
return 0; // FAIL
}
/** Initializes the peripherals clocks
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS;
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;
PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE0;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
return 0; // FAIL
}
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
return 0; // FAIL
}
/**
* Select HSI as system clock source after Wake Up from Stop mode
*/
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
/**
* Select HSI as system clock source after Wake Up from Stop mode
*/
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
/**
* Set RNG on HSI48
*/
LL_RCC_HSI48_Enable();
while(!LL_RCC_HSI48_IsReady());
LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_HSI48);
/**
* Set RNG on HSI48
*/
LL_RCC_HSI48_Enable();
while (!LL_RCC_HSI48_IsReady());
LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_HSI48);
return 1;
return 1;
}
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */

8
targets/TARGET_STM/TARGET_STM32WB/flash_api.c
View File

@ -77,7 +77,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
#if defined(CFG_HW_FLASH_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
while( LL_HSEM_1StepLock( HSEM, CFG_HW_FLASH_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID));
#endif
/* Unlock the Flash to enable the flash control register access */
@ -109,7 +109,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
HAL_FLASH_Lock();
#if defined(CFG_HW_FLASH_SEMID)
LL_HSEM_ReleaseLock( HSEM, CFG_HW_FLASH_SEMID, 0 );
LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, 0);
#endif
return status;
@ -141,7 +141,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
#if defined(CFG_HW_FLASH_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
while( LL_HSEM_1StepLock( HSEM, CFG_HW_FLASH_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID));
#endif
/* Unlock the Flash to enable the flash control register access */
@ -182,7 +182,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
HAL_FLASH_Lock();
#if defined(CFG_HW_FLASH_SEMID)
LL_HSEM_ReleaseLock( HSEM, CFG_HW_FLASH_SEMID, 0 );
LL_HSEM_ReleaseLock(HSEM, CFG_HW_FLASH_SEMID, 0);
#endif
return status;

120
targets/TARGET_STM/TARGET_STM32WB/wb_sleep.c
View File

@ -44,103 +44,95 @@ extern void restore_timer_ctx(void);
extern int serial_is_tx_ongoing(void);
extern int mbed_sdk_inited;
static void Switch_On_HSI( void )
static void Switch_On_HSI(void)
{
LL_RCC_HSI_Enable();
while(!LL_RCC_HSI_IsReady());
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
LL_RCC_HSI_Enable();
while (!LL_RCC_HSI_IsReady());
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI);
return;
return;
}
static void LPM_EnterStopMode(void)
{
/**
* This function is called from CRITICAL SECTION
*/
/**
* This function is called from CRITICAL SECTION
*/
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
/**
* Select HSI as system clock source after Wake Up from Stop mode
*/
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
/**
* Select HSI as system clock source after Wake Up from Stop mode
*/
LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI);
if ( ! LL_HSEM_1StepLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID ) )
{
if( LL_PWR_IsActiveFlag_C2DS() )
{
/* Release ENTRY_STOP_MODE semaphore */
LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
if (! LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID)) {
if (LL_PWR_IsActiveFlag_C2DS()) {
/* Release ENTRY_STOP_MODE semaphore */
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
Switch_On_HSI();
Switch_On_HSI();
}
} else {
Switch_On_HSI();
}
}
else
{
Switch_On_HSI();
}
/* Release RCC semaphore */
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
/* Release RCC semaphore */
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
return;
return;
}
static void LPM_ExitStopMode(void)
{
/**
* This function is called from CRITICAL SECTION
*/
/**
* This function is called from CRITICAL SECTION
*/
/* Release ENTRY_STOP_MODE semaphore */
LL_HSEM_ReleaseLock( HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0 );
/* Release ENTRY_STOP_MODE semaphore */
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
if( (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI) || (LL_PWR_IsActiveFlag_C1STOP() != 0) )
{
LL_PWR_ClearFlag_C1STOP_C1STB();
if ((LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI) || (LL_PWR_IsActiveFlag_C1STOP() != 0)) {
LL_PWR_ClearFlag_C1STOP_C1STB();
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RCC_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
if(LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
{
LL_RCC_HSE_Enable();
while(!LL_RCC_HSE_IsReady());
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
}
else
{
/**
* As long as the current application is fine with HSE as system clock source,
* there is nothing to do here
*/
if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
LL_RCC_HSE_Enable();
while (!LL_RCC_HSE_IsReady());
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE);
} else {
/**
* As long as the current application is fine with HSE as system clock source,
* there is nothing to do here
*/
}
/* Release RCC semaphore */
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0);
}
/* Release RCC semaphore */
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RCC_SEMID, 0 );
}
return;
return;
}
void HW_LPM_StopMode(void)
{
LL_PWR_SetPowerMode(LL_PWR_MODE_STOP2);
LL_PWR_SetPowerMode(LL_PWR_MODE_STOP2);
LL_LPM_EnableDeepSleep(); /**< Set SLEEPDEEP bit of Cortex System Control Register */
LL_LPM_EnableDeepSleep(); /**< Set SLEEPDEEP bit of Cortex System Control Register */
/**
* This option is used to ensure that store operations are completed
*/
/**
* This option is used to ensure that store operations are completed
*/
#if defined ( __CC_ARM)
__force_stores();
__force_stores();
#endif
__WFI();
__WFI();
return;
return;
}
/* STM32WB has very specific needs to handling STOP mode.

48
targets/TARGET_STM/mbed_crc_api.c
View File

@ -25,7 +25,7 @@ static uint32_t crc_mask;
+-------------------------+---------------------------------------+---------------+
| Polynomial coefficients | Fixed to 0x4C11DB7 | Programmable |
+-------------------------+---------------------------------------+---------------+
#1 The STM32F0 series which supported polynomial in 7, 8, 16, 32 bits as below list:
STM32F071xB
STM32F072xB
@ -77,24 +77,23 @@ void hal_crc_compute_partial_start(const crc_mbed_config_t *config)
current_state.Init.InitValue = config->initial_xor;
current_state.Init.GeneratingPolynomial = config->polynomial;
switch (config->width)
{
case HAL_CRC_LENGTH_32B:
current_state.Init.CRCLength = CRC_POLYLENGTH_32B;
break;
case HAL_CRC_LENGTH_16B:
current_state.Init.CRCLength = CRC_POLYLENGTH_16B;
break;
case HAL_CRC_LENGTH_8B:
current_state.Init.CRCLength = CRC_POLYLENGTH_8B;
break;
case HAL_CRC_LENGTH_7B:
current_state.Init.CRCLength = CRC_POLYLENGTH_7B;
break;
default:
MBED_ASSERT(false);
break;
}
switch (config->width) {
case HAL_CRC_LENGTH_32B:
current_state.Init.CRCLength = CRC_POLYLENGTH_32B;
break;
case HAL_CRC_LENGTH_16B:
current_state.Init.CRCLength = CRC_POLYLENGTH_16B;
break;
case HAL_CRC_LENGTH_8B:
current_state.Init.CRCLength = CRC_POLYLENGTH_8B;
break;
case HAL_CRC_LENGTH_7B:
current_state.Init.CRCLength = CRC_POLYLENGTH_7B;
break;
default:
MBED_ASSERT(false);
break;
}
current_state.Init.InputDataInversionMode =
config->reflect_in ? CRC_INPUTDATA_INVERSION_BYTE
@ -104,7 +103,7 @@ void hal_crc_compute_partial_start(const crc_mbed_config_t *config)
: CRC_OUTPUTDATA_INVERSION_DISABLE;
#endif
if (HAL_CRC_Init(&current_state) != HAL_OK) {
if (HAL_CRC_Init(&current_state) != HAL_OK) {
MBED_ASSERT(false);
}
}
@ -124,21 +123,22 @@ uint32_t hal_crc_get_result(void)
/* The CRC-7 SD needs to shift left by 1 bit after obtaining the result, but the output
* inversion of CRC peripheral will convert the result before shift left by 1 bit, so
* the result seems to have shifted after the conversion.
*
*
* Example:
* [Gerenal setps]
* 1. Before output inversion: 0x75 (0111 0101)
* 2. Left shift by 1 bit: 0xEA (1110 1010)
* 3. After output inversion: 0x57 (0101 0111)
*
*
* [STM32 CRC peripheral steps]
* 1. Before output inversion: 0x75 (0111 0101)
* 2. After output inversion: 0x57 (0101 0111) <= no needs shift again
*/
if (current_state.Init.CRCLength == CRC_POLYLENGTH_7B &&
current_state.Init.GeneratingPolynomial == POLY_7BIT_SD &&
current_state.Init.OutputDataInversionMode == CRC_OUTPUTDATA_INVERSION_DISABLE)
current_state.Init.GeneratingPolynomial == POLY_7BIT_SD &&
current_state.Init.OutputDataInversionMode == CRC_OUTPUTDATA_INVERSION_DISABLE) {
result = result << 1;
}
#endif
return (result ^ final_xor) & crc_mask;
}

8
targets/TARGET_STM/mbed_rtx.h
View File

@ -141,10 +141,10 @@
#if (defined(TARGET_STM32L475VG) || defined(TARGET_STM32L443RC))
#if defined(__ARMCC_VERSION)
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[];
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[];
#define HEAP_START Image$$ARM_LIB_HEAP$$ZI$$Base
#define HEAP_SIZE Image$$ARM_LIB_HEAP$$ZI$$Length
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[];
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[];
#define HEAP_START Image$$ARM_LIB_HEAP$$ZI$$Base
#define HEAP_SIZE Image$$ARM_LIB_HEAP$$ZI$$Length
#endif
#endif

3
targets/TARGET_STM/stm_spi_api.c
View File

@ -92,7 +92,8 @@ void init_spi(spi_t *obj)
}
}
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk) {
SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName sclk)
{
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);

14
targets/TARGET_STM/trng_api.c
View File

@ -43,7 +43,7 @@ void trng_init(trng_t *obj)
}
#if !defined(TARGET_STM32WB)
/* Because M0 core of WB also needs RG RNG is already clocked by default */
/* Because M0 core of WB also needs RG RNG is already clocked by default */
#if defined(RCC_PERIPHCLK_RNG)
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
@ -70,7 +70,7 @@ void trng_init(trng_t *obj)
#if defined(CFG_HW_RNG_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RNG_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RNG_SEMID));
#endif
HAL_RNG_Init(&obj->handle);
@ -78,7 +78,7 @@ void trng_init(trng_t *obj)
HAL_RNG_GenerateRandomNumber(&obj->handle, &dummy);
#if defined(CFG_HW_RNG_SEMID)
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RNG_SEMID, 0 );
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RNG_SEMID, 0);
#endif
}
@ -86,14 +86,14 @@ void trng_free(trng_t *obj)
{
#if defined(CFG_HW_RNG_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RNG_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RNG_SEMID));
#endif
/*Disable the RNG peripheral */
HAL_RNG_DeInit(&obj->handle);
#if defined(CFG_HW_RNG_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RNG_SEMID, 0 );
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RNG_SEMID, 0);
#else
/* RNG Peripheral clock disable - assume we're the only users of RNG */
__HAL_RCC_RNG_CLK_DISABLE();
@ -110,7 +110,7 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l
#if defined(CFG_HW_RNG_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
while( LL_HSEM_1StepLock( HSEM, CFG_HW_RNG_SEMID ) );
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RNG_SEMID));
#endif
/* Get Random byte */
@ -133,7 +133,7 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l
#if defined(CFG_HW_RNG_SEMID)
/* In case RNG is a shared ressource, get the HW semaphore first */
LL_HSEM_ReleaseLock( HSEM, CFG_HW_RNG_SEMID, 0 );
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RNG_SEMID, 0);
#endif
return (ret);