mirror of https://github.com/ARMmbed/mbed-os.git
NUCLEO_WB55RG: add SDK files
- Contains files from STM32Cube_FW_WB_V1.0.0pull/9814/head
bcostm
Laurent Meunier
parent
0a088a6f4d
commit
81f985433f
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_PERIPHERALNAMES_H
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#define MBED_PERIPHERALNAMES_H
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#include "cmsis.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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ADC_1 = (int)ADC1_BASE
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} ADCName;
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typedef enum {
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UART_1 = (int)USART1_BASE,
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LPUART_1 = (int)LPUART1_BASE
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} UARTName;
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typedef enum {
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SPI_1 = (int)SPI1_BASE,
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SPI_2 = (int)SPI2_BASE
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} SPIName;
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typedef enum {
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I2C_1 = (int)I2C1_BASE,
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I2C_3 = (int)I2C3_BASE
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} I2CName;
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typedef enum {
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PWM_1 = (int)TIM1_BASE,
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PWM_2 = (int)TIM2_BASE,
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PWM_16 = (int)TIM16_BASE,
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PWM_17 = (int)TIM17_BASE
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} PWMName;
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typedef enum {
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QSPI_1 = QUADSPI_BASE
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} QSPIName;
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#ifdef __cplusplus
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}
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#endif
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#endif
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/* mbed Microcontroller Library
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*******************************************************************************
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* Copyright (c) 2018, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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*
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* Automatically generated from STM32WB55RGVx.xml
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*/
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#include "PeripheralPins.h"
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#include "mbed_toolchain.h"
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//==============================================================================
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// Notes
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//
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// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
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// HW peripheral instances. You can use them the same way as any other "normal"
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// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
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// pinout image on mbed.org.
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//
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// - The pins which are connected to other components present on the board have
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// the comment "Connected to xxx". The pin function may not work properly in this
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// case. These pins may not be displayed on the board pinout image on mbed.org.
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// Please read the board reference manual and schematic for more information.
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//
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// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented
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// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
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//
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//==============================================================================
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//*** ADC ***
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MBED_WEAK const PinMap PinMap_ADC[] = {
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{PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
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{PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
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{PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
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{PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
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{PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
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{PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
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{PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
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{PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
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{PA_8, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
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{PA_9, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
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{PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
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{PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
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{PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
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{PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
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{PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 // Connected to B1 [Push Button]
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{PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
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{ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
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{ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)},
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{ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
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{NC, NC, 0}
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};
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//*** I2C ***
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MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
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{PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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{PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
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// {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_RX
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{PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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{PB_11, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
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{PB_14, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
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{PC_1, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
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{PA_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
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{PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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// {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_TX
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{PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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{PB_10, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
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{PB_13, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
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{PC_0, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
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{NC, NC, 0}
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};
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//*** PWM ***
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// TIM16 cannot be used because already used by the us_ticker
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MBED_WEAK const PinMap PinMap_PWM[] = {
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{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
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{PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
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{PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
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{PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
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{PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
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// {PA_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
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{PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
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{PA_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
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{PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
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{PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
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{PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
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{PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 // Connected to USB_DM
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{PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
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{PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to JTDO
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// {PB_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N // Connected to STDIO_UART_TX
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// {PB_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N // Connected to STDIO_UART_RX
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{PB_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
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// {PB_8, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
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{PB_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
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{PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
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{PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
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{PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
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{PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
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{PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
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{PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
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{NC, NC, 0}
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};
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//*** SERIAL ***
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MBED_WEAK const PinMap PinMap_UART_TX[] = {
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{PA_2, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
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{PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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{PB_5, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD1 [Blue Led]
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{PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX
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{PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
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{PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_UART_RX[] = {
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{PA_3, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
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{PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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{PA_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to USB_DP
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{PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX
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{PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
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{PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_UART_RTS[] = {
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{PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DP
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{PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD3 [Red Led]
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{PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to JTDO
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{PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_UART_CTS[] = {
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{PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
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{PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_DM
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{PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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{PB_13, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
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{NC, NC, 0}
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};
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//*** SPI ***
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MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
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{PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
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{PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to USB_DP
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{PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LD1 [Blue Led]
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{PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
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{PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_SPI2)},
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{PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
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{PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
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{PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to USB_DM
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{PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
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{PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
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{PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
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{PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
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{PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
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{PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
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{PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to JTDO
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{PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
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{PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
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{PD_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to B3 [Push Button]
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
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{PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PB_2, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
|
||||
{PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
|
||||
{PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
|
||||
{PD_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to B2 [Push Button]
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
//*** QUADSPI ***
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
|
||||
{PB_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
|
||||
{PB_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
|
||||
{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO2
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
|
||||
{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO3
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
|
||||
{PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
|
||||
{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_CLK
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
|
||||
{PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
|
||||
{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
|
@ -0,0 +1,185 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PinNamesTypes.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
ALT0 = 0x100,
|
||||
ALT1 = 0x200,
|
||||
ALT2 = 0x300,
|
||||
ALT3 = 0x400
|
||||
} ALTx;
|
||||
|
||||
typedef enum {
|
||||
PA_0 = 0x00,
|
||||
PA_1 = 0x01,
|
||||
PA_2 = 0x02,
|
||||
PA_3 = 0x03,
|
||||
PA_4 = 0x04,
|
||||
PA_5 = 0x05,
|
||||
PA_6 = 0x06,
|
||||
PA_7 = 0x07,
|
||||
PA_7_ALT0 = PA_7|ALT0,
|
||||
PA_8 = 0x08,
|
||||
PA_9 = 0x09,
|
||||
PA_10 = 0x0A,
|
||||
PA_11 = 0x0B,
|
||||
PA_12 = 0x0C,
|
||||
PA_13 = 0x0D,
|
||||
PA_14 = 0x0E,
|
||||
PA_15 = 0x0F,
|
||||
|
||||
PB_0 = 0x10,
|
||||
PB_1 = 0x11,
|
||||
PB_2 = 0x12,
|
||||
PB_3 = 0x13,
|
||||
PB_4 = 0x14,
|
||||
PB_5 = 0x15,
|
||||
PB_6 = 0x16,
|
||||
PB_7 = 0x17,
|
||||
PB_8 = 0x18,
|
||||
PB_9 = 0x19,
|
||||
PB_9_ALT0 = PB_9|ALT0,
|
||||
PB_10 = 0x1A,
|
||||
PB_11 = 0x1B,
|
||||
PB_12 = 0x1C,
|
||||
PB_13 = 0x1D,
|
||||
PB_14 = 0x1E,
|
||||
PB_15 = 0x1F,
|
||||
|
||||
PC_0 = 0x20,
|
||||
PC_1 = 0x21,
|
||||
PC_2 = 0x22,
|
||||
PC_3 = 0x23,
|
||||
PC_4 = 0x24,
|
||||
PC_5 = 0x25,
|
||||
PC_6 = 0x26,
|
||||
PC_10 = 0x2A,
|
||||
PC_11 = 0x2B,
|
||||
PC_12 = 0x2C,
|
||||
PC_13 = 0x2D,
|
||||
PC_14 = 0x2E,
|
||||
PC_15 = 0x2F,
|
||||
|
||||
PD_0 = 0x30,
|
||||
PD_1 = 0x31,
|
||||
|
||||
PH_3 = 0x73,
|
||||
|
||||
// ADC internal channels
|
||||
ADC_TEMP = 0xF0,
|
||||
ADC_VREF = 0xF1,
|
||||
ADC_VBAT = 0xF2,
|
||||
|
||||
// Arduino connector
|
||||
A0 = PC_0,
|
||||
A1 = PC_1,
|
||||
A2 = PA_1,
|
||||
A3 = PA_0,
|
||||
A4 = PC_3,
|
||||
A5 = PC_2,
|
||||
D0 = PA_3,
|
||||
D1 = PA_2,
|
||||
D2 = PC_6,
|
||||
D3 = PA_10,
|
||||
D4 = PC_10,
|
||||
D5 = PA_15,
|
||||
D6 = PA_8,
|
||||
D7 = PC_13,
|
||||
D8 = PC_12,
|
||||
D9 = PA_9,
|
||||
D10 = PA_4,
|
||||
D11 = PA_7,
|
||||
D12 = PA_6,
|
||||
D13 = PA_5,
|
||||
D14 = PB_9,
|
||||
D15 = PB_8,
|
||||
|
||||
// STDIO for console print
|
||||
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
|
||||
STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
|
||||
#else
|
||||
STDIO_UART_TX = PB_6,
|
||||
#endif
|
||||
#ifdef MBED_CONF_TARGET_STDIO_UART_RX
|
||||
STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
|
||||
#else
|
||||
STDIO_UART_RX = PB_7,
|
||||
#endif
|
||||
|
||||
// Generic signals namings
|
||||
LED1 = PB_5, // Blue LED1
|
||||
LED2 = PB_0, // Green LED2
|
||||
LED3 = PB_1, // Red LED3
|
||||
LED4 = LED1,
|
||||
BUTTON1 = PC_4, // SW1
|
||||
BUTTON2 = PD_0, // SW2
|
||||
BUTTON3 = PD_1, // SW3
|
||||
BUTTON4 = BUTTON1,
|
||||
BUTTON5 = BUTTON1,
|
||||
USER_BUTTON = BUTTON1,
|
||||
SERIAL_TX = STDIO_UART_TX,
|
||||
SERIAL_RX = STDIO_UART_RX,
|
||||
USBTX = STDIO_UART_TX,
|
||||
USBRX = STDIO_UART_RX,
|
||||
I2C_SCL = D15,
|
||||
I2C_SDA = D14,
|
||||
SPI_MOSI = D11,
|
||||
SPI_MISO = D12,
|
||||
SPI_SCK = D13,
|
||||
SPI_CS = D10,
|
||||
PWM_OUT = D9,
|
||||
|
||||
/**** USB pins ****/
|
||||
USB_DM = PA_11,
|
||||
USB_DP = PA_12,
|
||||
USB_NOE = PA_13,
|
||||
|
||||
/**** OSCILLATOR pins ****/
|
||||
RCC_OSC32_IN = PC_14,
|
||||
RCC_OSC32_OUT = PC_15,
|
||||
|
||||
/**** DEBUG pins ****/
|
||||
SYS_JTCK_SWCLK = PA_14,
|
||||
SYS_JTDI = PA_15,
|
||||
SYS_JTDO_SWO = PB_3,
|
||||
SYS_JTMS_SWDIO = PA_13,
|
||||
SYS_JTRST = PB_4,
|
||||
SYS_PVD_IN = PB_7,
|
||||
SYS_TRACED1 = PC_10,
|
||||
SYS_TRACED3 = PC_12,
|
||||
SYS_WKUP1 = PA_0,
|
||||
SYS_WKUP2 = PC_13,
|
||||
SYS_WKUP3 = PC_12,
|
||||
SYS_WKUP4 = PA_2,
|
||||
SYS_WKUP5 = PC_5,
|
||||
|
||||
// Not connected
|
||||
NC = (int)0xFFFFFFFF
|
||||
} PinName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2017 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "stm32wbxx.h"
|
||||
#include "mbed_assert.h"
|
||||
|
||||
// Clock source is selected with CLOCK_SOURCE in json config
|
||||
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (not available)
|
||||
#define USE_PLL_HSE_XTAL 0x4 // Use external 32 MHz xtal (X1 on board + need HW patch)
|
||||
#define USE_PLL_HSI 0x2 // Use HSI 16MHz internal clock
|
||||
#define USE_PLL_MSI 0x1 // Use MSI 4MHz internal clock (default)
|
||||
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
|
||||
#if (((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC))
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
||||
void Configure_RF_Clock_Sources(void);
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SetSysClock(void)
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/* 3- If fail start with HSI clock */
|
||||
if (SetSysClock_PLL_HSI()==0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/* 4- If fail start with MSI clock */
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
while(1) {
|
||||
MBED_ASSERT(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Configure_RF_Clock_Sources();
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 64 MHz
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC))
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
if (bypass == 0) {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 32 MHz xtal on OSC_IN/OSC_OUT
|
||||
} else {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 32 MHz clock on OSC_IN
|
||||
}
|
||||
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLN = 16;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
|
||||
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
|
||||
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV4;
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
|
||||
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2; // 32 MHz
|
||||
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1; // 64 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 64 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
|
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0)
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // xx MHz
|
||||
else
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // xx MHz
|
||||
#endif
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLN = 16;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
|
||||
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
|
||||
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
|
||||
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2; // 32 MHz
|
||||
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1; // 64 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 64 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
|
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
|
||||
// Enable MSI Oscillator and activate PLL with MSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV1;
|
||||
RCC_OscInitStruct.PLL.PLLN = 32;
|
||||
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
||||
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV5;
|
||||
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
|
||||
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV2; // 32 MHz
|
||||
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1; // 64 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 64 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
|
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Calibrate MSI
|
||||
LL_PWR_EnableBkUpAccess();
|
||||
LL_RCC_ForceBackupDomainReset();
|
||||
LL_RCC_ReleaseBackupDomainReset();
|
||||
LL_RCC_LSE_Enable();
|
||||
while (LL_RCC_LSE_IsReady() != 1) {}
|
||||
LL_RCC_MSI_EnablePLLMode();
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_1); // 4 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
||||
void Configure_RF_Clock_Sources(void)
|
||||
{
|
||||
/**
|
||||
* Select LSE clock
|
||||
*/
|
||||
LL_RCC_LSE_Enable();
|
||||
while(!LL_RCC_LSE_IsReady());
|
||||
|
||||
/**
|
||||
* Select wakeup source of BLE RF
|
||||
*/
|
||||
LL_RCC_SetRFWKPClockSource(LL_RCC_RFWKP_CLKSOURCE_LSE);
|
||||
|
||||
/**
|
||||
* Switch OFF LSI
|
||||
*/
|
||||
LL_RCC_LSI1_Disable();
|
||||
|
||||
/**
|
||||
* Set RNG on HSI48
|
||||
*/
|
||||
LL_RCC_HSI48_Enable();
|
||||
while(!LL_RCC_HSI48_IsReady());
|
||||
LL_RCC_SetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE_HSI48);
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,347 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32wbxx.c
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex Device Peripheral Access Layer System Source File
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32wbxx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the MSI (4 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32wbxx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32WBxx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32WBxx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32wbxx.h"
|
||||
#include "nvic_addr.h" // MBED patch
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)32000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE ((uint32_t)32000) /*!< Value of LSI in Hz*/
|
||||
#endif /* LSI_VALUE */
|
||||
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE ((uint32_t)32768) /*!< Value of LSE in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
#ifdef CORE_CM0PLUS
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x100. */
|
||||
|
||||
#define VECT_TAB_BASE_ADDRESS RAM2A_BASE /*!< Vector Table base address field.
|
||||
This value must be a multiple of 0x100. */
|
||||
#else
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x0U /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
|
||||
#define VECT_TAB_BASE_ADDRESS RAM1_BASE /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 4000000; /*CPU1: M4 on MSI clock after startup (4MHz)*/
|
||||
|
||||
const uint32_t AHBPrescTable[16] = {1, 3, 5, 1, 1, 6, 10, 32, 2, 4, 8, 16, 64, 128, 256, 512}; /* eqv. division factor used for Dory*/
|
||||
/* index=[0,...15]*/
|
||||
const uint32_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
|
||||
|
||||
const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
|
||||
4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
|
||||
|
||||
const uint32_t SmpsPrescalerTable[4][6]={{1,3,2,2,1,2}, \
|
||||
{2,6,4,3,2,4}, \
|
||||
{4,12,8,6,4,8}, \
|
||||
{4,12,8,6,4,8}};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef CORE_CM0PLUS
|
||||
#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)
|
||||
/* program in SRAMx */
|
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAMx for CPU2 */
|
||||
#else
|
||||
/* program in FLASH */
|
||||
SCB->VTOR = VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif /* Program memory type */
|
||||
#else
|
||||
#if defined(VECT_TAB_SRAM) && defined(VECT_TAB_BASE_ADDRESS)
|
||||
/* program in SRAMx */
|
||||
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAMx for CPU1 */
|
||||
#else /* program in FLASH */
|
||||
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH - MBED patch */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR |= RCC_CR_MSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00070000U;
|
||||
|
||||
/* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFAF6FEFBU;
|
||||
|
||||
/*!< Reset LSI1 and LSI2 bits */
|
||||
RCC->CSR &= (uint32_t)0xFFFFFFFAU;
|
||||
|
||||
/*!< Reset HSI48ON bit */
|
||||
RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x22041000U;
|
||||
|
||||
/* Reset PLLSAI1CFGR register */
|
||||
RCC->PLLSAI1CFGR = 0x22041000U;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) MSI_VALUE is a constant defined in stm32wbxx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32wbxx_hal_conf.h file (default value
|
||||
* 32 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get MSI Range frequency--------------------------------------------------*/
|
||||
|
||||
/*MSI frequency range in Hz*/
|
||||
msirange = MSIRangeTable[(RCC->CR & RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos];
|
||||
|
||||
/*SystemCoreClock=HAL_RCC_GetSysClockFreq();*/
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock source */
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
|
||||
case 0x04: /* HSI used as system clock source */
|
||||
/* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x08: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x0C: /* PLL used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
||||
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1 ;
|
||||
|
||||
switch (pllsource)
|
||||
{
|
||||
case 0x02: /* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm);
|
||||
break;
|
||||
|
||||
case 0x03: /* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm);
|
||||
break;
|
||||
|
||||
default: /* MSI used as PLL clock source */
|
||||
pllvco = (msirange / pllm);
|
||||
break;
|
||||
}
|
||||
|
||||
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
|
||||
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1);
|
||||
|
||||
SystemCoreClock = pllvco/pllr;
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
#ifdef CORE_CM0PLUS
|
||||
/* Get HCLK2 prescaler */
|
||||
tmp = AHBPrescTable[((RCC->EXTCFGR & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos)];
|
||||
|
||||
#else
|
||||
/* Get HCLK1 prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
|
||||
#endif
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock = SystemCoreClock / tmp;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,345 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb55xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WB55xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __initial_sp
|
||||
|
||||
Stack_Mem SPACE Stack_Size
|
||||
|
||||
__initial_sp EQU 0x20030000 ; Top of SRAM1 (192KB)
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit EQU (__initial_sp - Stack_Size)
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD USB_HP_IRQHandler ; USB High Priority Interrupt
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD SAI1_IRQHandler ; SAI Interrupt
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD CRS_IRQHandler ; CRS interrupt
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD LCD_IRQHandler ; LCD Interrupt
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI Interrupt
|
||||
DCD AES1_IRQHandler ; AES1 Interrupt
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_IRQHandler [WEAK]
|
||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT TSC_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||
EXPORT AES1_IRQHandler [WEAK]
|
||||
EXPORT AES2_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
COMP_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
PKA_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
TSC_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
CRS_IRQHandler
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
IPCC_C1_RX_IRQHandler
|
||||
IPCC_C1_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
LCD_IRQHandler
|
||||
QUADSPI_IRQHandler
|
||||
AES1_IRQHandler
|
||||
AES2_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
DMA2_Channel6_IRQHandler
|
||||
DMA2_Channel7_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
#! armcc -E
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; mbed Microcontroller Library
|
||||
; Copyright (c) 2006-2013 ARM Limited
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the "License");
|
||||
; you may not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; http://www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an "AS IS" BASIS,
|
||||
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START 0x08000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
; 512KB FLASH
|
||||
#define MBED_APP_SIZE 0x80000
|
||||
#endif
|
||||
|
||||
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
|
||||
|
||||
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; SRAM1 192KB (0x30000)
|
||||
; Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM
|
||||
RW_IRAM1 (0x20000000+0x13C) (0x30000-0x13C) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,318 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb55xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : STM32WB55xx devices vector table for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == Reset_Handler
|
||||
;* - Set the vector table entries with the exceptions ISR address
|
||||
;* - Branches to __main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the CortexM4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;*
|
||||
;******************************************************************************
|
||||
|
||||
__initial_sp EQU 0x20030000 ; Top of SRAM1 (192KB)
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM detector
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper and TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD USB_HP_IRQHandler ; USB High Priority Interrupt
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD SAI1_IRQHandler ; SAI Interrupt
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD CRS_IRQHandler ; CRS interrupt
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD LCD_IRQHandler ; LCD Interrupt
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI Interrupt
|
||||
DCD AES1_IRQHandler ; AES1 Interrupt
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMP_STAMP_LSECSS_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT USB_HP_IRQHandler [WEAK]
|
||||
EXPORT USB_LP_IRQHandler [WEAK]
|
||||
EXPORT C2SEV_PWR_C2H_IRQHandler [WEAK]
|
||||
EXPORT COMP_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT PKA_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT LPUART1_IRQHandler [WEAK]
|
||||
EXPORT SAI1_IRQHandler [WEAK]
|
||||
EXPORT TSC_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT CRS_IRQHandler [WEAK]
|
||||
EXPORT PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_RX_IRQHandler [WEAK]
|
||||
EXPORT IPCC_C1_TX_IRQHandler [WEAK]
|
||||
EXPORT HSEM_IRQHandler [WEAK]
|
||||
EXPORT LPTIM1_IRQHandler [WEAK]
|
||||
EXPORT LPTIM2_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT QUADSPI_IRQHandler [WEAK]
|
||||
EXPORT AES1_IRQHandler [WEAK]
|
||||
EXPORT AES2_IRQHandler [WEAK]
|
||||
EXPORT RNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel7_IRQHandler [WEAK]
|
||||
EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_PVM_IRQHandler
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
USB_HP_IRQHandler
|
||||
USB_LP_IRQHandler
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
COMP_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
PKA_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
I2C3_EV_IRQHandler
|
||||
I2C3_ER_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
USART1_IRQHandler
|
||||
LPUART1_IRQHandler
|
||||
SAI1_IRQHandler
|
||||
TSC_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
CRS_IRQHandler
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
IPCC_C1_RX_IRQHandler
|
||||
IPCC_C1_TX_IRQHandler
|
||||
HSEM_IRQHandler
|
||||
LPTIM1_IRQHandler
|
||||
LPTIM2_IRQHandler
|
||||
LCD_IRQHandler
|
||||
QUADSPI_IRQHandler
|
||||
AES1_IRQHandler
|
||||
AES2_IRQHandler
|
||||
RNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
DMA2_Channel6_IRQHandler
|
||||
DMA2_Channel7_IRQHandler
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
END
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
#! armcc -E
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
; mbed Microcontroller Library
|
||||
; Copyright (c) 2006-2013 ARM Limited
|
||||
;
|
||||
; Licensed under the Apache License, Version 2.0 (the "License");
|
||||
; you may not use this file except in compliance with the License.
|
||||
; You may obtain a copy of the License at
|
||||
;
|
||||
; http://www.apache.org/licenses/LICENSE-2.0
|
||||
;
|
||||
; Unless required by applicable law or agreed to in writing, software
|
||||
; distributed under the License is distributed on an "AS IS" BASIS,
|
||||
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; See the License for the specific language governing permissions and
|
||||
; limitations under the License.
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START 0x08000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
; 512KB FLASH
|
||||
#define MBED_APP_SIZE 0x80000
|
||||
#endif
|
||||
|
||||
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
|
||||
|
||||
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
; SRAM1 192KB (0x30000)
|
||||
; Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM
|
||||
RW_IRAM1 (0x20000000+0x13C) (0x30000-0x13C) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,431 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32wb55xx_cm4.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32WB55xx devices vector table GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
ldr r2, =_sidata
|
||||
movs r3, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r4, [r2, r3]
|
||||
str r4, [r0, r3]
|
||||
adds r3, r3, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
adds r4, r0, r3
|
||||
cmp r4, r1
|
||||
bcc CopyDataInit
|
||||
|
||||
/* Zero fill the bss segment. */
|
||||
ldr r2, =_sbss
|
||||
ldr r4, =_ebss
|
||||
movs r3, #0
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
cmp r2, r4
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
|
||||
/* Call static constructors */
|
||||
// MBED >>>
|
||||
//bl __libc_init_array
|
||||
/* Call the application s entry point.*/
|
||||
//bl main
|
||||
//LoopForever:
|
||||
// b LoopForever
|
||||
bl _start
|
||||
bx lr
|
||||
// <<< MBED
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex-M4. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
.word WWDG_IRQHandler
|
||||
.word PVD_PVM_IRQHandler
|
||||
.word TAMP_STAMP_LSECSS_IRQHandler
|
||||
.word RTC_WKUP_IRQHandler
|
||||
.word FLASH_IRQHandler
|
||||
.word RCC_IRQHandler
|
||||
.word EXTI0_IRQHandler
|
||||
.word EXTI1_IRQHandler
|
||||
.word EXTI2_IRQHandler
|
||||
.word EXTI3_IRQHandler
|
||||
.word EXTI4_IRQHandler
|
||||
.word DMA1_Channel1_IRQHandler
|
||||
.word DMA1_Channel2_IRQHandler
|
||||
.word DMA1_Channel3_IRQHandler
|
||||
.word DMA1_Channel4_IRQHandler
|
||||
.word DMA1_Channel5_IRQHandler
|
||||
.word DMA1_Channel6_IRQHandler
|
||||
.word DMA1_Channel7_IRQHandler
|
||||
.word ADC1_IRQHandler
|
||||
.word USB_HP_IRQHandler
|
||||
.word USB_LP_IRQHandler
|
||||
.word C2SEV_PWR_C2H_IRQHandler
|
||||
.word COMP_IRQHandler
|
||||
.word EXTI9_5_IRQHandler
|
||||
.word TIM1_BRK_IRQHandler
|
||||
.word TIM1_UP_TIM16_IRQHandler
|
||||
.word TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.word TIM1_CC_IRQHandler
|
||||
.word TIM2_IRQHandler
|
||||
.word PKA_IRQHandler
|
||||
.word I2C1_EV_IRQHandler
|
||||
.word I2C1_ER_IRQHandler
|
||||
.word I2C3_EV_IRQHandler
|
||||
.word I2C3_ER_IRQHandler
|
||||
.word SPI1_IRQHandler
|
||||
.word SPI2_IRQHandler
|
||||
.word USART1_IRQHandler
|
||||
.word LPUART1_IRQHandler
|
||||
.word SAI1_IRQHandler
|
||||
.word TSC_IRQHandler
|
||||
.word EXTI15_10_IRQHandler
|
||||
.word RTC_Alarm_IRQHandler
|
||||
.word CRS_IRQHandler
|
||||
.word PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.word IPCC_C1_RX_IRQHandler
|
||||
.word IPCC_C1_TX_IRQHandler
|
||||
.word HSEM_IRQHandler
|
||||
.word LPTIM1_IRQHandler
|
||||
.word LPTIM2_IRQHandler
|
||||
.word LCD_IRQHandler
|
||||
.word QUADSPI_IRQHandler
|
||||
.word AES1_IRQHandler
|
||||
.word AES2_IRQHandler
|
||||
.word RNG_IRQHandler
|
||||
.word FPU_IRQHandler
|
||||
.word DMA2_Channel1_IRQHandler
|
||||
.word DMA2_Channel2_IRQHandler
|
||||
.word DMA2_Channel3_IRQHandler
|
||||
.word DMA2_Channel4_IRQHandler
|
||||
.word DMA2_Channel5_IRQHandler
|
||||
.word DMA2_Channel6_IRQHandler
|
||||
.word DMA2_Channel7_IRQHandler
|
||||
.word DMAMUX1_OVR_IRQHandler
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_PVM_IRQHandler
|
||||
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_LSECSS_IRQHandler
|
||||
.thumb_set TAMP_STAMP_LSECSS_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_IRQHandler
|
||||
.thumb_set ADC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_HP_IRQHandler
|
||||
.thumb_set USB_HP_IRQHandler,Default_Handler
|
||||
|
||||
.weak USB_LP_IRQHandler
|
||||
.thumb_set USB_LP_IRQHandler,Default_Handler
|
||||
|
||||
.weak C2SEV_PWR_C2H_IRQHandler
|
||||
.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP_IRQHandler
|
||||
.thumb_set COMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM16_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM17_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak PKA_IRQHandler
|
||||
.thumb_set PKA_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TSC_IRQHandler
|
||||
.thumb_set TSC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
.thumb_set PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_RX_IRQHandler
|
||||
.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPCC_C1_TX_IRQHandler
|
||||
.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM_IRQHandler
|
||||
.thumb_set HSEM_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LCD_IRQHandler
|
||||
.thumb_set LCD_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES1_IRQHandler
|
||||
.thumb_set AES1_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES2_IRQHandler
|
||||
.thumb_set AES2_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_IRQHandler
|
||||
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel5_IRQHandler
|
||||
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel6_IRQHandler
|
||||
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel7_IRQHandler
|
||||
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,161 @@
|
|||
#if !defined(MBED_APP_START)
|
||||
#define MBED_APP_START 0x08000000
|
||||
#endif
|
||||
|
||||
#if !defined(MBED_APP_SIZE)
|
||||
#define MBED_APP_SIZE 512K
|
||||
#endif
|
||||
|
||||
/* Linker script to configure memory regions. */
|
||||
/* Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM1 (192K) */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
|
||||
RAM1 (rwx) : ORIGIN = 0x2000013C, LENGTH = 192K - 0x13C
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
* _estack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
__etext = .;
|
||||
_sidata = .;
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
_sdata = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
_edata = .;
|
||||
|
||||
} > RAM1
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
_sbss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
_ebss = .;
|
||||
} > RAM1
|
||||
|
||||
.heap (COPY):
|
||||
{
|
||||
__end__ = .;
|
||||
end = __end__;
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM1
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (COPY):
|
||||
{
|
||||
*(.stack*)
|
||||
} > RAM1
|
||||
|
||||
/* Set stack top to end of RAM1, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM1) + LENGTH(RAM1);
|
||||
_estack = __StackTop;
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM1 limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM1 overflowed with stack")
|
||||
}
|
||||
|
|
@ -0,0 +1,517 @@
|
|||
;******************************************************************************
|
||||
;* File Name : startup_stm32wb55xx_cm4.s
|
||||
;* Author : MCD Application Team
|
||||
;* Description : M4 core vector table of the STM32WB55xx devices for the
|
||||
;* IAR (EWARM) toolchain.
|
||||
;*
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
;* - Set the initial PC == _iar_program_start,
|
||||
;* - Set the vector table entries with the exceptions ISR
|
||||
;* address.
|
||||
;* - Branches to main in the C library (which eventually
|
||||
;* calls main()).
|
||||
;* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;******************************************************************************
|
||||
;* @attention
|
||||
;*
|
||||
;* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
;* All rights reserved.</center></h2>
|
||||
;*
|
||||
;* This software component is licensed by ST under BSD 3-Clause license,
|
||||
;* the "License"; You may not use this file except in compliance with the
|
||||
;* License. You may obtain a copy of the License at:
|
||||
;* opensource.org/licenses/BSD-3-Clause
|
||||
;*
|
||||
;******************************************************************************
|
||||
;
|
||||
;
|
||||
; The modules in this file are included in the libraries, and may be replaced
|
||||
; by any user-defined modules that define the PUBLIC symbol _program_start or
|
||||
; a user defined start symbol.
|
||||
; To override the cstartup defined in the library, simply add your modified
|
||||
; version to the workbench project.
|
||||
;
|
||||
; The vector table is normally located at address 0.
|
||||
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
|
||||
; The name "__vector_table" has special meaning for C-SPY:
|
||||
; it is where the SP start value is found, and the NVIC vector
|
||||
; table register (VTOR) is initialized to this address if != 0.
|
||||
;
|
||||
; Cortex-M version
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDG_IRQHandler ; Window WatchDog
|
||||
DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt
|
||||
DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts
|
||||
DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt
|
||||
DCD FLASH_IRQHandler ; FLASH global Interrupt
|
||||
DCD RCC_IRQHandler ; RCC Interrupt
|
||||
DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt
|
||||
DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt
|
||||
DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt
|
||||
DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup
|
||||
DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt
|
||||
DCD ADC1_IRQHandler ; ADC1 Interrupt
|
||||
DCD USB_HP_IRQHandler ; USB High Priority Interrupt
|
||||
DCD USB_LP_IRQHandler ; USB Low Priority Interrupt
|
||||
DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt
|
||||
DCD COMP_IRQHandler ; COMP1 and COMP2 Interrupts
|
||||
DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt
|
||||
DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt
|
||||
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 global Interrupts
|
||||
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Communication and TIM17 global Interrupts
|
||||
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt
|
||||
DCD TIM2_IRQHandler ; TIM2 Global Interrupt
|
||||
DCD PKA_IRQHandler ; PKA Interrupt
|
||||
DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt
|
||||
DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt
|
||||
DCD I2C3_EV_IRQHandler ; I2C3 Event Interrupt
|
||||
DCD I2C3_ER_IRQHandler ; I2C3 Error Interrupt
|
||||
DCD SPI1_IRQHandler ; SPI1 Interrupt
|
||||
DCD SPI2_IRQHandler ; SPI2 Interrupt
|
||||
DCD USART1_IRQHandler ; USART1 Interrupt
|
||||
DCD LPUART1_IRQHandler ; LPUART1 Interrupt
|
||||
DCD SAI1_IRQHandler ; SAI Interrupt
|
||||
DCD TSC_IRQHandler ; TSC Interrupt
|
||||
DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts
|
||||
DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt
|
||||
DCD CRS_IRQHandler ; CRS interrupt
|
||||
DCD PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR
|
||||
DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt
|
||||
DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt
|
||||
DCD HSEM_IRQHandler ; HSEM0 Interrupt
|
||||
DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt
|
||||
DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt
|
||||
DCD LCD_IRQHandler ; LCD Interrupt
|
||||
DCD QUADSPI_IRQHandler ; QUADSPI Interrupt
|
||||
DCD AES1_IRQHandler ; AES1 Interrupt
|
||||
DCD AES2_IRQHandler ; AES2 Interrupt
|
||||
DCD RNG_IRQHandler ; RNG1 Interrupt
|
||||
DCD FPU_IRQHandler ; FPU Interrupt
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 Interrupt
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 Interrupt
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 Interrupt
|
||||
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 Interrupt
|
||||
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 Interrupt
|
||||
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6 Interrupt
|
||||
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7 Interrupt
|
||||
DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDG_IRQHandler
|
||||
B WWDG_IRQHandler
|
||||
|
||||
PUBWEAK PVD_PVM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PVD_PVM_IRQHandler
|
||||
B PVD_PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMP_STAMP_LSECSS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMP_STAMP_LSECSS_IRQHandler
|
||||
B TAMP_STAMP_LSECSS_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK RCC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCC_IRQHandler
|
||||
B RCC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC1_IRQHandler
|
||||
B ADC1_IRQHandler
|
||||
|
||||
PUBWEAK USB_HP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_HP_IRQHandler
|
||||
B USB_HP_IRQHandler
|
||||
|
||||
PUBWEAK USB_LP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USB_LP_IRQHandler
|
||||
B USB_LP_IRQHandler
|
||||
|
||||
PUBWEAK C2SEV_PWR_C2H_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
C2SEV_PWR_C2H_IRQHandler
|
||||
B C2SEV_PWR_C2H_IRQHandler
|
||||
|
||||
PUBWEAK COMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
COMP_IRQHandler
|
||||
B COMP_IRQHandler
|
||||
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI9_5_IRQHandler
|
||||
B EXTI9_5_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_BRK_IRQHandler
|
||||
B TIM1_BRK_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_UP_TIM16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_UP_TIM16_IRQHandler
|
||||
B TIM1_UP_TIM16_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_TRG_COM_TIM17_IRQHandler
|
||||
B TIM1_TRG_COM_TIM17_IRQHandler
|
||||
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM1_CC_IRQHandler
|
||||
B TIM1_CC_IRQHandler
|
||||
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIM2_IRQHandler
|
||||
B TIM2_IRQHandler
|
||||
|
||||
PUBWEAK PKA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PKA_IRQHandler
|
||||
B PKA_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_EV_IRQHandler
|
||||
B I2C3_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C3_ER_IRQHandler
|
||||
B I2C3_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK LPUART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPUART1_IRQHandler
|
||||
B LPUART1_IRQHandler
|
||||
|
||||
PUBWEAK SAI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SAI1_IRQHandler
|
||||
B SAI1_IRQHandler
|
||||
|
||||
PUBWEAK TSC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TSC_IRQHandler
|
||||
B TSC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI15_10_IRQHandler
|
||||
B EXTI15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK CRS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CRS_IRQHandler
|
||||
B CRS_IRQHandler
|
||||
|
||||
PUBWEAK PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
B PWR_SOTF_BLEACT_802ACT_RFPHASE_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_RX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_RX_IRQHandler
|
||||
B IPCC_C1_RX_IRQHandler
|
||||
|
||||
PUBWEAK IPCC_C1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPCC_C1_TX_IRQHandler
|
||||
B IPCC_C1_TX_IRQHandler
|
||||
|
||||
PUBWEAK HSEM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HSEM_IRQHandler
|
||||
B HSEM_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM1_IRQHandler
|
||||
B LPTIM1_IRQHandler
|
||||
|
||||
PUBWEAK LPTIM2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LPTIM2_IRQHandler
|
||||
B LPTIM2_IRQHandler
|
||||
|
||||
PUBWEAK LCD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LCD_IRQHandler
|
||||
B LCD_IRQHandler
|
||||
|
||||
PUBWEAK QUADSPI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
QUADSPI_IRQHandler
|
||||
B QUADSPI_IRQHandler
|
||||
|
||||
PUBWEAK AES1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES1_IRQHandler
|
||||
B AES1_IRQHandler
|
||||
|
||||
PUBWEAK AES2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
AES2_IRQHandler
|
||||
B AES2_IRQHandler
|
||||
|
||||
PUBWEAK RNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RNG_IRQHandler
|
||||
B RNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel4_IRQHandler
|
||||
B DMA2_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel5_IRQHandler
|
||||
B DMA2_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel6_IRQHandler
|
||||
B DMA2_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA2_Channel7_IRQHandler
|
||||
B DMA2_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK DMAMUX1_OVR_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMAMUX1_OVR_IRQHandler
|
||||
B DMAMUX1_OVR_IRQHandler
|
||||
|
||||
END
|
||||
|
||||
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
|
||||
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x80000; }
|
||||
|
||||
/* [ROM = 512kb = 0x80000] */
|
||||
define symbol __intvec_start__ = MBED_APP_START;
|
||||
define symbol __region_ROM_start__ = MBED_APP_START;
|
||||
define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE;
|
||||
|
||||
/* [RAM1 = 192kb = 0x30000] */
|
||||
/* Total: 79 vectors = 316 bytes (0x13C) to be reserved in RAM */
|
||||
define symbol __NVIC_start__ = 0x20000000;
|
||||
define symbol __NVIC_end__ = 0x2000013F;
|
||||
define symbol __region_RAM_start__ = 0x20000140; /* Aligned on 8 bytes */
|
||||
define symbol __region_RAM_end__ = 0x2002FFFF;
|
||||
/* [RAM2aRet = 10kb = 0x2800] */
|
||||
define symbol __ICFEDIT_region_RAM2aRet_SHARED_start__ = 0x20030000;
|
||||
define symbol __ICFEDIT_region_RAM2aRet_SHARED_end__ = 0x200327FF;
|
||||
/* [RAM2bRet = 20kb = 0x5000] */
|
||||
define symbol __ICFEDIT_region_RAM2b_SHARED_start__ = 0x20038000;
|
||||
define symbol __ICFEDIT_region_RAM2b_SHARED_end__ = 0x2003CFFF;
|
||||
|
||||
/* Memory regions */
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
|
||||
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
|
||||
define region RAM2aRet_SHARED_region = mem:[from __ICFEDIT_region_RAM2aRet_SHARED_start__ to __ICFEDIT_region_RAM2aRet_SHARED_end__];
|
||||
define region RAM2b_SHARED_region = mem:[from __ICFEDIT_region_RAM2b_SHARED_start__ to __ICFEDIT_region_RAM2b_SHARED_end__];
|
||||
|
||||
/* Stack and Heap */
|
||||
define symbol __size_cstack__ = 0x8000;
|
||||
define symbol __size_heap__ = 0x10000;
|
||||
define block CSTACK with alignment = 8, size = __size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __size_heap__ { };
|
||||
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
|
||||
|
||||
initialize by copy with packing = zeros { readwrite };
|
||||
do not initialize { section .noinit,
|
||||
section MAPPING_TABLE,
|
||||
section MB_MEM1 };
|
||||
|
||||
place at address mem:__intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite, block STACKHEAP };
|
||||
|
||||
place in RAM2aRet_SHARED_region { first section MAPPING_TABLE};
|
||||
place in RAM2aRet_SHARED_region { section MB_MEM1};
|
||||
place in RAM2b_SHARED_region { section MB_MEM2};
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_CMSIS_H
|
||||
#define MBED_CMSIS_H
|
||||
|
||||
#include "stm32wbxx.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_CMSIS_NVIC_H
|
||||
#define MBED_CMSIS_NVIC_H
|
||||
|
||||
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
|
||||
// MCU Peripherals: 63 vectors = 252 bytes from 0x40 to 0x13B
|
||||
// Total: 16+63=79 vectors = 316 bytes (0x13C) to be reserved in RAM
|
||||
#define NVIC_NUM_VECTORS 79
|
||||
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/* mbed Microcontroller Library
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2016, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef MBED_FLASH_DATA_H
|
||||
#define MBED_FLASH_DATA_H
|
||||
|
||||
#if DEVICE_FLASH
|
||||
|
||||
#ifdef FLASH_SIZE
|
||||
#undef FLASH_SIZE
|
||||
#endif
|
||||
|
||||
// Only the first 128 pages are accessible when security is enabled
|
||||
#define FLASH_SIZE ((uint32_t)0x80000) // 128 pages x 4 Kbytes = 512 Kbytes
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2013 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef MBED_OBJECTS_H
|
||||
#define MBED_OBJECTS_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PortNames.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "PinNames.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct gpio_irq_s {
|
||||
IRQn_Type irq_n;
|
||||
uint32_t irq_index;
|
||||
uint32_t event;
|
||||
PinName pin;
|
||||
};
|
||||
|
||||
struct port_s {
|
||||
PortName port;
|
||||
uint32_t mask;
|
||||
PinDirection direction;
|
||||
__IO uint32_t *reg_in;
|
||||
__IO uint32_t *reg_out;
|
||||
};
|
||||
|
||||
struct trng_s {
|
||||
RNG_HandleTypeDef handle;
|
||||
};
|
||||
|
||||
#include "common_objects.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,167 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32WBxx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32WBxx device used in the target application
|
||||
* - To use or not the peripheral’s drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral’s registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32wbxx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __STM32WBxx_H
|
||||
#define __STM32WBxx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32 Family
|
||||
*/
|
||||
#if !defined (STM32WB)
|
||||
#define STM32WB
|
||||
#endif /* STM32WB */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
#if !defined (USE_HAL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/
|
||||
/*#define USE_HAL_DRIVER */
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number
|
||||
*/
|
||||
#define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
|
||||
#define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
|
||||
#define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32WBxx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__STM32WBxx_CMSIS_VERSION_SUB2 << 8 )\
|
||||
|(__STM32WBxx_CMSIS_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32WB55xx)
|
||||
#include "stm32wb55xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32WBxx device used in your application, for instance xxx (in stm32wbxx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SUCCESS = 0,
|
||||
ERROR = !SUCCESS
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Exported_macros
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
|
||||
#include "stm32wbxx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32WBxx_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32wbxx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex Device System Source File for STM32WBxx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32wbxx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32WBXX_H
|
||||
#define __SYSTEM_STM32WBXX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency */
|
||||
|
||||
extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */
|
||||
extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
|
||||
extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */
|
||||
|
||||
extern const uint32_t SmpsPrescalerTable[4][6]; /*!< SMPS factor ranges table values */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32WBxx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32WBXX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2018 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef __US_TICKER_DATA_H
|
||||
#define __US_TICKER_DATA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "stm32wbxx.h"
|
||||
#include "stm32wbxx_ll_tim.h"
|
||||
#include "cmsis_nvic.h"
|
||||
|
||||
#define TIM_MST TIM16
|
||||
#define TIM_MST_IRQ TIM1_UP_TIM16_IRQn
|
||||
#define TIM_MST_RCC __HAL_RCC_TIM16_CLK_ENABLE()
|
||||
#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM16()
|
||||
|
||||
#define TIM_MST_RESET_ON __HAL_RCC_TIM16_FORCE_RESET()
|
||||
#define TIM_MST_RESET_OFF __HAL_RCC_TIM16_RELEASE_RESET()
|
||||
|
||||
#define TIM_MST_BIT_WIDTH 16 // 16 or 32
|
||||
|
||||
#define TIM_MST_PCLK 2 // Select the peripheral clock number (1 or 2)
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __US_TICKER_DATA_H
|
||||
|
||||
|
|
@ -0,0 +1,207 @@
|
|||
/* mbed Microcontroller Library
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2019, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#if DEVICE_ANALOGIN
|
||||
|
||||
#include "analogin_api.h"
|
||||
#include "mbed_assert.h"
|
||||
#include "mbed_error.h"
|
||||
#include "mbed_debug.h"
|
||||
#include "mbed_wait_api.h"
|
||||
#include "cmsis.h"
|
||||
#include "pinmap.h"
|
||||
#include "PeripheralPins.h"
|
||||
|
||||
void analogin_init(analogin_t *obj, PinName pin)
|
||||
{
|
||||
uint32_t function = (uint32_t)NC;
|
||||
|
||||
// ADC Internal Channels "pins" (Temperature, Vref, Vbat, ...)
|
||||
// are described in PinNames.h and PeripheralPins.c
|
||||
// Pin value must be between 0xF0 and 0xFF
|
||||
if ((pin < 0xF0) || (pin >= 0x100)) {
|
||||
// Normal channels
|
||||
// Get the peripheral name from the pin and assign it to the object
|
||||
obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC);
|
||||
// Get the functions (adc channel) from the pin and assign it to the object
|
||||
function = pinmap_function(pin, PinMap_ADC);
|
||||
// Configure GPIO
|
||||
pinmap_pinout(pin, PinMap_ADC);
|
||||
} else {
|
||||
// Internal channels
|
||||
obj->handle.Instance = (ADC_TypeDef *)pinmap_peripheral(pin, PinMap_ADC_Internal);
|
||||
function = pinmap_function(pin, PinMap_ADC_Internal);
|
||||
// No GPIO configuration for internal channels
|
||||
}
|
||||
MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC);
|
||||
MBED_ASSERT(function != (uint32_t)NC);
|
||||
|
||||
obj->channel = STM_PIN_CHANNEL(function);
|
||||
|
||||
// Save pin number for the read function
|
||||
obj->pin = pin;
|
||||
|
||||
// Configure ADC object structures
|
||||
obj->handle.State = HAL_ADC_STATE_RESET;
|
||||
obj->handle.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2; // Asynchronous clock mode, input ADC clock
|
||||
obj->handle.Init.Resolution = ADC_RESOLUTION_12B;
|
||||
obj->handle.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
||||
obj->handle.Init.ScanConvMode = ADC_SCAN_DISABLE; // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1)
|
||||
obj->handle.Init.EOCSelection = ADC_EOC_SINGLE_CONV; // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example).
|
||||
obj->handle.Init.LowPowerAutoWait = DISABLE;
|
||||
obj->handle.Init.ContinuousConvMode = DISABLE; // Continuous mode disabled to have only 1 conversion at each conversion trig
|
||||
obj->handle.Init.NbrOfConversion = 1; // Parameter discarded because sequencer is disabled
|
||||
obj->handle.Init.DiscontinuousConvMode = DISABLE; // Parameter discarded because sequencer is disabled
|
||||
obj->handle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled
|
||||
obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; // Software start to trig the 1st conversion manually, without external event
|
||||
obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
|
||||
obj->handle.Init.DMAContinuousRequests = DISABLE;
|
||||
obj->handle.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; // DR register is overwritten with the last conversion result in case of overrun
|
||||
obj->handle.Init.OversamplingMode = DISABLE; // No oversampling
|
||||
|
||||
// Enable ADC core clock
|
||||
__HAL_RCC_ADC_CLK_ENABLE();
|
||||
|
||||
// Enable ADC conversion clock.
|
||||
// Only necessary with asynchronous clock source
|
||||
__HAL_RCC_ADC_CONFIG(RCC_ADCCLKSOURCE_SYSCLK);
|
||||
|
||||
if (HAL_ADC_Init(&obj->handle) != HAL_OK) {
|
||||
error("ADC initialization failed\r\n");
|
||||
}
|
||||
|
||||
// ADC calibration is done only once
|
||||
if (!HAL_ADCEx_Calibration_GetValue(&obj->handle, ADC_SINGLE_ENDED)) {
|
||||
HAL_ADCEx_Calibration_Start(&obj->handle, ADC_SINGLE_ENDED);
|
||||
}
|
||||
}
|
||||
|
||||
uint16_t adc_read(analogin_t *obj)
|
||||
{
|
||||
ADC_ChannelConfTypeDef sConfig = {0};
|
||||
|
||||
// Configure ADC channel
|
||||
sConfig.Rank = ADC_REGULAR_RANK_1;
|
||||
sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5;
|
||||
sConfig.SingleDiff = ADC_SINGLE_ENDED;
|
||||
sConfig.OffsetNumber = ADC_OFFSET_NONE;
|
||||
sConfig.Offset = 0;
|
||||
|
||||
switch (obj->channel) {
|
||||
case 0:
|
||||
sConfig.Channel = ADC_CHANNEL_VREFINT;
|
||||
sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; // Minimum ADC sampling time when reading the internal reference voltage is 4us
|
||||
break;
|
||||
case 1:
|
||||
sConfig.Channel = ADC_CHANNEL_1;
|
||||
break;
|
||||
case 2:
|
||||
sConfig.Channel = ADC_CHANNEL_2;
|
||||
break;
|
||||
case 3:
|
||||
sConfig.Channel = ADC_CHANNEL_3;
|
||||
break;
|
||||
case 4:
|
||||
sConfig.Channel = ADC_CHANNEL_4;
|
||||
break;
|
||||
case 5:
|
||||
sConfig.Channel = ADC_CHANNEL_5;
|
||||
break;
|
||||
case 6:
|
||||
sConfig.Channel = ADC_CHANNEL_6;
|
||||
break;
|
||||
case 7:
|
||||
sConfig.Channel = ADC_CHANNEL_7;
|
||||
break;
|
||||
case 8:
|
||||
sConfig.Channel = ADC_CHANNEL_8;
|
||||
break;
|
||||
case 9:
|
||||
sConfig.Channel = ADC_CHANNEL_9;
|
||||
break;
|
||||
case 10:
|
||||
sConfig.Channel = ADC_CHANNEL_10;
|
||||
break;
|
||||
case 11:
|
||||
sConfig.Channel = ADC_CHANNEL_11;
|
||||
break;
|
||||
case 12:
|
||||
sConfig.Channel = ADC_CHANNEL_12;
|
||||
break;
|
||||
case 13:
|
||||
sConfig.Channel = ADC_CHANNEL_13;
|
||||
break;
|
||||
case 14:
|
||||
sConfig.Channel = ADC_CHANNEL_14;
|
||||
break;
|
||||
case 15:
|
||||
sConfig.Channel = ADC_CHANNEL_15;
|
||||
break;
|
||||
case 16:
|
||||
sConfig.Channel = ADC_CHANNEL_16;
|
||||
break;
|
||||
case 17:
|
||||
sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
|
||||
sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; // Minimum ADC sampling time when reading the temperature is 5us
|
||||
break;
|
||||
case 18:
|
||||
sConfig.Channel = ADC_CHANNEL_VBAT;
|
||||
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5; // Minimum ADC sampling time when reading the VBAT is 12us
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (HAL_ADC_ConfigChannel(&obj->handle, &sConfig) != HAL_OK) {
|
||||
debug("ADC channel configuration failed\r\n");
|
||||
}
|
||||
|
||||
// Start conversion
|
||||
if (HAL_ADC_Start(&obj->handle) != HAL_OK) {
|
||||
debug("ADC start of conversion failed\r\n");
|
||||
}
|
||||
|
||||
// Wait end of conversion and get value
|
||||
if (HAL_ADC_PollForConversion(&obj->handle, 10) == HAL_OK) {
|
||||
|
||||
/* Ref Manual: To prevent any unwanted consumption on the battery,
|
||||
it is recommended to enable the bridge divider only when needed for ADC conversion */
|
||||
if (sConfig.Channel == ADC_CHANNEL_VBAT) {
|
||||
CLEAR_BIT(__LL_ADC_COMMON_INSTANCE(obj->handle.Instance)->CCR, LL_ADC_PATH_INTERNAL_VBAT);
|
||||
}
|
||||
|
||||
return (uint16_t)HAL_ADC_GetValue(&obj->handle);
|
||||
} else {
|
||||
debug("ADC conversion failed. Returned 0.\r\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
/* mbed Microcontroller Library
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2019, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_COMMON_OBJECTS_H
|
||||
#define MBED_COMMON_OBJECTS_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PortNames.h"
|
||||
#include "PeripheralNames.h"
|
||||
#include "PinNames.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct pwmout_s {
|
||||
PWMName pwm;
|
||||
PinName pin;
|
||||
uint32_t prescaler;
|
||||
uint32_t period;
|
||||
uint32_t pulse;
|
||||
uint8_t channel;
|
||||
uint8_t inverted;
|
||||
};
|
||||
|
||||
struct spi_s {
|
||||
SPI_HandleTypeDef handle;
|
||||
IRQn_Type spiIRQ;
|
||||
SPIName spi;
|
||||
PinName pin_miso;
|
||||
PinName pin_mosi;
|
||||
PinName pin_sclk;
|
||||
PinName pin_ssel;
|
||||
#if DEVICE_SPI_ASYNCH
|
||||
uint32_t event;
|
||||
uint8_t transfer_type;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct serial_s {
|
||||
UARTName uart;
|
||||
int index; // Used by irq
|
||||
uint32_t baudrate;
|
||||
uint32_t databits;
|
||||
uint32_t stopbits;
|
||||
uint32_t parity;
|
||||
PinName pin_tx;
|
||||
PinName pin_rx;
|
||||
#if DEVICE_SERIAL_ASYNCH
|
||||
uint32_t events;
|
||||
#endif
|
||||
#if DEVICE_SERIAL_FC
|
||||
uint32_t hw_flow_ctl;
|
||||
PinName pin_rts;
|
||||
PinName pin_cts;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct i2c_s {
|
||||
/* The 1st 2 members I2CName i2c
|
||||
* and I2C_HandleTypeDef handle should
|
||||
* be kept as the first members of this struct
|
||||
* to ensure i2c_get_obj to work as expected
|
||||
*/
|
||||
I2CName i2c;
|
||||
I2C_HandleTypeDef handle;
|
||||
uint8_t index;
|
||||
int hz;
|
||||
PinName sda;
|
||||
PinName scl;
|
||||
IRQn_Type event_i2cIRQ;
|
||||
IRQn_Type error_i2cIRQ;
|
||||
uint32_t XferOperation;
|
||||
volatile uint8_t event;
|
||||
volatile int pending_start;
|
||||
#if DEVICE_I2CSLAVE
|
||||
uint8_t slave;
|
||||
volatile uint8_t pending_slave_tx_master_rx;
|
||||
volatile uint8_t pending_slave_rx_maxter_tx;
|
||||
#endif
|
||||
#if DEVICE_I2C_ASYNCH
|
||||
uint32_t address;
|
||||
uint8_t stop;
|
||||
uint8_t available_events;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct flash_s {
|
||||
/* nothing to be stored for now */
|
||||
uint32_t dummy;
|
||||
};
|
||||
|
||||
struct analogin_s {
|
||||
ADC_HandleTypeDef handle;
|
||||
PinName pin;
|
||||
uint8_t channel;
|
||||
};
|
||||
|
||||
#include "gpio_object.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/* STM32WB HAL doesn't provide this API called in sleep.c */
|
||||
#define __HAL_RCC_PWR_CLK_DISABLE()
|
||||
#define __HAL_RCC_PWR_CLK_ENABLE()
|
||||
#define __HAL_RCC_PWR_IS_CLK_ENABLED() 1
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/* mbed Microcontroller Library
|
||||
*******************************************************************************
|
||||
* Copyright (c) 2019, STMicroelectronics
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef MBED_DEVICE_H
|
||||
#define MBED_DEVICE_H
|
||||
|
||||
#define DEVICE_ID_LENGTH 24
|
||||
|
||||
#include "objects.h"
|
||||
/* WORKAROUND waiting for mbed-os issue 4408 to be addressed */
|
||||
#include "stm32wbxx_ll_usart.h"
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,57 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32_assert.h
|
||||
* @author MCD Application Team
|
||||
* @brief STM32 assert template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32_assert.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32_ASSERT_H
|
||||
#define STM32_ASSERT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32_ASSERT_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,812 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal.c
|
||||
* @author MCD Application Team
|
||||
* @brief HAL module driver.
|
||||
* This is the common part of the HAL initialization
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The common HAL driver contains a set of generic and common APIs that can be
|
||||
used by the PPP peripheral drivers and the user to start using the HAL.
|
||||
[..]
|
||||
The HAL contains two APIs' categories:
|
||||
(+) Common HAL APIs
|
||||
(+) Services HAL APIs
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL
|
||||
* @brief HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Private_Constants HAL Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief STM32WBxx HAL Driver version number
|
||||
*/
|
||||
#define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32WBxx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
|
||||
#define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
|
||||
#define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
|
||||
|(__STM32WBxx_HAL_VERSION_SUB1 << 16U)\
|
||||
|(__STM32WBxx_HAL_VERSION_SUB2 << 8U )\
|
||||
|(__STM32WBxx_HAL_VERSION_RC))
|
||||
|
||||
#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Exported variables ---------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Variables HAL Exported Variables
|
||||
* @{
|
||||
*/
|
||||
__IO uint32_t uwTick;
|
||||
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
|
||||
uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group1
|
||||
* @brief HAL Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the Flash interface the NVIC allocation and initial time base
|
||||
clock configuration.
|
||||
(+) De-initialize common part of the HAL.
|
||||
(+) Configure the time base source to have 1ms time base with a dedicated
|
||||
Tick interrupt priority.
|
||||
(++) SysTick timer is used by default as source of time base, but user
|
||||
can eventually implement his proper time base source (a general purpose
|
||||
timer for example or other time source), keeping in mind that Time base
|
||||
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
|
||||
handled in milliseconds basis.
|
||||
(++) Time base configuration function (HAL_InitTick ()) is called automatically
|
||||
at the beginning of the program after reset by HAL_Init() or at any time
|
||||
when clock is configured, by HAL_RCC_ClockConfig().
|
||||
(++) Source of time base is configured to generate interrupts at regular
|
||||
time intervals. Care must be taken if HAL_Delay() is called from a
|
||||
peripheral ISR process, the Tick interrupt line must have higher priority
|
||||
(numerically lower) than the peripheral interrupt. Otherwise the caller
|
||||
ISR process will be blocked.
|
||||
(++) functions affecting time base configurations are declared as __weak
|
||||
to make override possible in case of other implementations in user file.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function is used to initialize the HAL Library; it must be the first
|
||||
* instruction to be executed in the main program (before to call any other
|
||||
* HAL function), it performs the following:
|
||||
* Configure the Flash prefetch, instruction and Data caches.
|
||||
* Configures the SysTick to generate an interrupt each 1 millisecond,
|
||||
* which is clocked by the MSI (at this stage, the clock is not yet
|
||||
* configured and thus the system is running from the internal MSI at 4 MHz).
|
||||
* Set NVIC Group Priority to 4.
|
||||
* Calls the HAL_MspInit() callback function defined in user file
|
||||
* "stm32wbxx_hal_msp.c" to do the global low level hardware initialization
|
||||
*
|
||||
* @note SysTick is used as time base for the HAL_Delay() function, the application
|
||||
* need to ensure that the SysTick time base is always set to 1 millisecond
|
||||
* to have correct HAL operation.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_Init(void)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
/* Configure Flash prefetch, Instruction cache, Data cache */
|
||||
/* Default configuration at reset is: */
|
||||
/* - Prefetch disabled */
|
||||
/* - Instruction cache enabled */
|
||||
/* - Data cache enabled */
|
||||
#if (INSTRUCTION_CACHE_ENABLE == 0U)
|
||||
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
|
||||
#endif /* INSTRUCTION_CACHE_ENABLE */
|
||||
|
||||
#if (DATA_CACHE_ENABLE == 0U)
|
||||
__HAL_FLASH_DATA_CACHE_DISABLE();
|
||||
#endif /* DATA_CACHE_ENABLE */
|
||||
|
||||
#if (PREFETCH_ENABLE != 0U)
|
||||
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
||||
#endif /* PREFETCH_ENABLE */
|
||||
|
||||
/* Set Interrupt Group Priority */
|
||||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
|
||||
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
||||
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Init the low level hardware */
|
||||
HAL_MspInit();
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function de-Initializes common part of the HAL and stops the source of time base.
|
||||
* @note This function is optional.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DeInit(void)
|
||||
{
|
||||
/* Reset of all peripherals */
|
||||
__HAL_RCC_APB1_FORCE_RESET();
|
||||
__HAL_RCC_APB1_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_APB2_FORCE_RESET();
|
||||
__HAL_RCC_APB2_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_APB3_FORCE_RESET();
|
||||
__HAL_RCC_APB3_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB1_FORCE_RESET();
|
||||
__HAL_RCC_AHB1_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB2_FORCE_RESET();
|
||||
__HAL_RCC_AHB2_RELEASE_RESET();
|
||||
|
||||
__HAL_RCC_AHB3_FORCE_RESET();
|
||||
__HAL_RCC_AHB3_RELEASE_RESET();
|
||||
|
||||
/* De-Init the low level hardware */
|
||||
HAL_MspDeInit();
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the MSP.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspInit(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the MSP.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_MspDeInit(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configures the source of the time base:
|
||||
* The time source is configured to have 1ms time base with a dedicated
|
||||
* Tick interrupt priority.
|
||||
* @note This function is called automatically at the beginning of program after
|
||||
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
|
||||
* @note In the default implementation, SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals.
|
||||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
|
||||
* The SysTick interrupt must have higher priority (numerically lower)
|
||||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
|
||||
* The function is declared as __weak to be overwritten in case of other
|
||||
* implementation in user file.
|
||||
* @param TickPriority Tick interrupt priority.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (uwTickFreq != 0U)
|
||||
{
|
||||
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
||||
if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/ (1000U /uwTickFreq)) == 0U)
|
||||
{
|
||||
/* Configure the SysTick IRQ priority */
|
||||
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
||||
{
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
||||
uwTickPrio = TickPriority;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group2
|
||||
* @brief HAL Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Provide a tick value in millisecond
|
||||
(+) Provide a blocking delay in millisecond
|
||||
(+) Suspend the time base source interrupt
|
||||
(+) Resume the time base source interrupt
|
||||
(+) Get the HAL API driver version
|
||||
(+) Get the device revision identifier
|
||||
(+) Get the device identifier
|
||||
(+) Get the unique device identifier
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function is called to increment a global variable "uwTick"
|
||||
* used as application time base.
|
||||
* @note In the default implementation, this variable is incremented each 1ms
|
||||
* in SysTick ISR.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IncTick(void)
|
||||
{
|
||||
uwTick += (uint32_t)uwTickFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Provides a tick value in millisecond.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval tick value
|
||||
*/
|
||||
__weak uint32_t HAL_GetTick(void)
|
||||
{
|
||||
return uwTick;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function returns a tick priority.
|
||||
* @retval tick priority
|
||||
*/
|
||||
uint32_t HAL_GetTickPrio(void)
|
||||
{
|
||||
return uwTickPrio;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set new tick Freq.
|
||||
* @retval Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
assert_param(IS_TICKFREQ(Freq));
|
||||
|
||||
if (uwTickFreq != Freq)
|
||||
{
|
||||
uwTickFreq = Freq;
|
||||
|
||||
/* Apply the new tick Freq */
|
||||
status = HAL_InitTick(uwTickPrio);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return tick frequency.
|
||||
* @retval tick period in Hz
|
||||
*/
|
||||
uint32_t HAL_GetTickFreq(void)
|
||||
{
|
||||
return uwTickFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides minimum delay (in milliseconds) based
|
||||
* on variable incremented.
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals where uwTick
|
||||
* is incremented.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param Delay specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_Delay(uint32_t Delay)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
uint32_t wait = Delay;
|
||||
|
||||
/* Add a freq to guarantee minimum wait */
|
||||
if (wait < HAL_MAX_DELAY)
|
||||
{
|
||||
wait += (uint32_t)(uwTickFreq);
|
||||
}
|
||||
|
||||
while ((HAL_GetTick() - tickstart) < wait)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Suspend Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
|
||||
* is called, the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SuspendTick(void)
|
||||
{
|
||||
/* Disable SysTick Interrupt */
|
||||
CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
|
||||
* is called, the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable SysTick Interrupt */
|
||||
SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the HAL revision
|
||||
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t HAL_GetHalVersion(void)
|
||||
{
|
||||
return __STM32WBxx_HAL_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t HAL_GetREVID(void)
|
||||
{
|
||||
return(LL_DBGMCU_GetRevisionID());
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetDEVID(void)
|
||||
{
|
||||
return(LL_DBGMCU_GetDeviceID());
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the first word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw0(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)UID_BASE)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the second word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw1(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the third word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetUIDw2(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group3
|
||||
* @brief HAL Debug functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL Debug functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Enable/Disable Debug module during SLEEP mode
|
||||
(+) Enable/Disable Debug module during STOP mode
|
||||
(+) Enable/Disable Debug module during STANDBY mode
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void)
|
||||
{
|
||||
LL_DBGMCU_EnableDBGSleepMode();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void)
|
||||
{
|
||||
LL_DBGMCU_DisableDBGSleepMode();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void)
|
||||
{
|
||||
LL_DBGMCU_EnableDBGStopMode();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void)
|
||||
{
|
||||
LL_DBGMCU_DisableDBGStopMode();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void)
|
||||
{
|
||||
LL_DBGMCU_EnableDBGStandbyMode();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void)
|
||||
{
|
||||
LL_DBGMCU_DisableDBGStandbyMode();
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group4 HAL System Configuration functions
|
||||
* @brief HAL System Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### HAL system configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start a hardware SRAM2 erase operation
|
||||
(+) Disable CPU2 SRAM fetch (execution)
|
||||
(+) Configure the Voltage reference buffer
|
||||
(+) Enable/Disable the Voltage reference buffer
|
||||
(+) Enable/Disable the I/O analog switch voltage booster
|
||||
(+) Enable/Disable the access for security IP (AES1, AES2, PKA, RNG)
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start a hardware SRAM2 erase operation.
|
||||
* @note As long as SRAM2 is not erased the SRAM2ER bit will be set.
|
||||
* This bit is automatically reset at the end of the SRAM2 erase operation.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_SRAM2Erase(void)
|
||||
{
|
||||
/* unlock the write protection of the SRAM2ER bit */
|
||||
__HAL_SYSCFG_SRAM2_WRP_UNLOCK();
|
||||
/* Starts a hardware SRAM2 erase operation*/
|
||||
__HAL_SYSCFG_SRAM2_ERASE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable CPU2 SRAM fetch (execution) (This bit can be set by Firmware
|
||||
* and will only be reset by a Hardware reset, including a reset after Standby.)
|
||||
* @note Firmware writing 0 has no effect.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_DisableSRAMFetch(void)
|
||||
{
|
||||
LL_SYSCFG_DisableSRAMFetch();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if CPU2 SRAM fetch is enabled
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void)
|
||||
{
|
||||
return (LL_SYSCFG_IsEnabledSRAMFetch());
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the internal voltage reference buffer voltage scale.
|
||||
* @param VoltageScaling specifies the output voltage to achieve
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE0 : VREF_OUT1 around 2.048 V.
|
||||
* This requires VDDA equal to or higher than 2.4 V.
|
||||
* @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE1 : VREF_OUT1 around 2.5 V.
|
||||
* This requires VDDA equal to or higher than 2.8 V.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
|
||||
|
||||
LL_VREFBUF_SetVoltageScaling(VoltageScaling);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the internal voltage reference buffer high impedance mode.
|
||||
* @param Mode specifies the high impedance mode
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE : VREF+ pin is internally connect to VREFINT output.
|
||||
* @arg @ref SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE : VREF+ pin is high impedance.
|
||||
* @retval HAL_OK/HAL_TIMEOUT
|
||||
*/
|
||||
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
|
||||
{
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
|
||||
|
||||
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Tune the Internal Voltage Reference buffer (VREFBUF).
|
||||
* @param TrimmingValue specifies trimming code for VREFBUF calibration
|
||||
* This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x3F
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
|
||||
|
||||
LL_VREFBUF_SetTrimming(TrimmingValue);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Internal Voltage Reference buffer (VREFBUF).
|
||||
* @retval HAL_OK/HAL_TIMEOUT
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
LL_VREFBUF_Enable();
|
||||
|
||||
/* Get Start Tick*/
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for VRR bit */
|
||||
while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Internal Voltage Reference buffer (VREFBUF).
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_DisableVREFBUF(void)
|
||||
{
|
||||
LL_VREFBUF_Disable();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the I/O analog switch voltage booster
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_EnableIOBooster(void)
|
||||
{
|
||||
LL_SYSCFG_EnableAnalogBooster();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the I/O analog switch voltage booster
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_DisableIOBooster(void)
|
||||
{
|
||||
LL_SYSCFG_DisableAnalogBooster();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the I/O analog switch supplied by VDD
|
||||
* @note To be used when I/O analog switch voltage booster is not enabled
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_EnableIOVdd(void)
|
||||
{
|
||||
LL_SYSCFG_EnableAnalogGpioSwitch();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the I/O analog switch supplied by VDD
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_DisableIOVdd(void)
|
||||
{
|
||||
LL_SYSCFG_DisableAnalogGpioSwitch();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the access for security IP
|
||||
* @note When the system is secure (ESE = 1), this register provides write access security and can
|
||||
* only be written by the CPU2. A write access from the CPU1 will be ignored and a bus error
|
||||
* is generated.
|
||||
* @param SecurityAccess This parameter can be a combination of the following values:
|
||||
* @arg @ref HAL_SYSCFG_SECURE_ACCESS_AES1
|
||||
* @arg @ref HAL_SYSCFG_SECURE_ACCESS_AES2
|
||||
* @arg @ref HAL_SYSCFG_SECURE_ACCESS_PKA
|
||||
* @arg @ref HAL_SYSCFG_SECURE_ACCESS_RNG
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_SECURITY_ACCESS(SecurityAccess));
|
||||
|
||||
LL_SYSCFG_EnableSecurityAccess(SecurityAccess);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the access for security IP
|
||||
* @note When the system is secure (ESE = 1), this register provides write access security and can
|
||||
* only be written by the CPU2. A write access from the CPU1 will be ignored and a bus error
|
||||
* is generated.
|
||||
* @param SecurityAccess This parameter can be a combination of the following values:
|
||||
* @arg @ref HAL_SYSCFG_SECURE_ACCESS_AES1
|
||||
* @arg @ref HAL_SYSCFG_SECURE_ACCESS_AES2
|
||||
* @arg @ref HAL_SYSCFG_SECURE_ACCESS_PKA
|
||||
* @arg @ref HAL_SYSCFG_SECURE_ACCESS_RNG
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_SECURITY_ACCESS(SecurityAccess));
|
||||
|
||||
LL_SYSCFG_DisableSecurityAccess(SecurityAccess);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate if access for security IP is enabled
|
||||
* @param SecurityAccess This parameter can be one of the following values:
|
||||
* @arg @ref HAL_SYSCFG_SECURE_ACCESS_AES1
|
||||
* @arg @ref HAL_SYSCFG_SECURE_ACCESS_AES2
|
||||
* @arg @ref HAL_SYSCFG_SECURE_ACCESS_PKA
|
||||
* @arg @ref HAL_SYSCFG_SECURE_ACCESS_RNG
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
uint32_t HAL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess)
|
||||
{
|
||||
return (LL_SYSCFG_IsEnabledSecurityAccess(SecurityAccess));
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,668 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_H
|
||||
#define STM32WBxx_HAL_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_conf.h"
|
||||
#include "stm32wbxx_ll_system.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Constants HAL Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_TICK_FREQ Tick Frequency
|
||||
* @{
|
||||
*/
|
||||
#define HAL_TICK_FREQ_10HZ 100U
|
||||
#define HAL_TICK_FREQ_100HZ 10U
|
||||
#define HAL_TICK_FREQ_1KHZ 1U
|
||||
#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_BootMode BOOT Mode
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH /*!< Main Flash memory mapped at 0x00000000 */
|
||||
#define SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH /*!< System Flash memory mapped at 0x00000000 */
|
||||
#define SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM /*!< SRAM1 mapped at 0x00000000 */
|
||||
#define SYSCFG_BOOT_QUADSPI LL_SYSCFG_REMAP_QUADSPI /*!< QUADSPI memory mapped at 0x00000000 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
|
||||
#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
|
||||
#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
|
||||
#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
|
||||
#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
|
||||
#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_SRAM2WRP_PAGE0 LL_SYSCFG_SRAM2WRP_PAGE0 /*!< SRAM2A Write protection page 0 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE1 LL_SYSCFG_SRAM2WRP_PAGE1 /*!< SRAM2A Write protection page 1 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE2 LL_SYSCFG_SRAM2WRP_PAGE2 /*!< SRAM2A Write protection page 2 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE3 LL_SYSCFG_SRAM2WRP_PAGE3 /*!< SRAM2A Write protection page 3 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE4 LL_SYSCFG_SRAM2WRP_PAGE4 /*!< SRAM2A Write protection page 4 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE5 LL_SYSCFG_SRAM2WRP_PAGE5 /*!< SRAM2A Write protection page 5 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE6 LL_SYSCFG_SRAM2WRP_PAGE6 /*!< SRAM2A Write protection page 6 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE7 LL_SYSCFG_SRAM2WRP_PAGE7 /*!< SRAM2A Write protection page 7 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE8 LL_SYSCFG_SRAM2WRP_PAGE8 /*!< SRAM2A Write protection page 8 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE9 LL_SYSCFG_SRAM2WRP_PAGE9 /*!< SRAM2A Write protection page 9 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE10 LL_SYSCFG_SRAM2WRP_PAGE10 /*!< SRAM2A Write protection page 10 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE11 LL_SYSCFG_SRAM2WRP_PAGE11 /*!< SRAM2A Write protection page 11 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE12 LL_SYSCFG_SRAM2WRP_PAGE12 /*!< SRAM2A Write protection page 12 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE13 LL_SYSCFG_SRAM2WRP_PAGE13 /*!< SRAM2A Write protection page 13 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE14 LL_SYSCFG_SRAM2WRP_PAGE14 /*!< SRAM2A Write protection page 14 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE15 LL_SYSCFG_SRAM2WRP_PAGE15 /*!< SRAM2A Write protection page 15 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE16 LL_SYSCFG_SRAM2WRP_PAGE16 /*!< SRAM2A Write protection page 16 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE17 LL_SYSCFG_SRAM2WRP_PAGE17 /*!< SRAM2A Write protection page 17 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE18 LL_SYSCFG_SRAM2WRP_PAGE18 /*!< SRAM2A Write protection page 18 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE19 LL_SYSCFG_SRAM2WRP_PAGE19 /*!< SRAM2A Write protection page 19 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE20 LL_SYSCFG_SRAM2WRP_PAGE20 /*!< SRAM2A Write protection page 20 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE21 LL_SYSCFG_SRAM2WRP_PAGE21 /*!< SRAM2A Write protection page 21 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE22 LL_SYSCFG_SRAM2WRP_PAGE22 /*!< SRAM2A Write protection page 22 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE23 LL_SYSCFG_SRAM2WRP_PAGE23 /*!< SRAM2A Write protection page 23 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE24 LL_SYSCFG_SRAM2WRP_PAGE24 /*!< SRAM2A Write protection page 24 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE25 LL_SYSCFG_SRAM2WRP_PAGE25 /*!< SRAM2A Write protection page 25 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE26 LL_SYSCFG_SRAM2WRP_PAGE26 /*!< SRAM2A Write protection page 26 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE27 LL_SYSCFG_SRAM2WRP_PAGE27 /*!< SRAM2A Write protection page 27 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE28 LL_SYSCFG_SRAM2WRP_PAGE28 /*!< SRAM2A Write protection page 28 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE29 LL_SYSCFG_SRAM2WRP_PAGE29 /*!< SRAM2A Write protection page 29 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE30 LL_SYSCFG_SRAM2WRP_PAGE30 /*!< SRAM2A Write protection page 30 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE31 LL_SYSCFG_SRAM2WRP_PAGE31 /*!< SRAM2A Write protection page 31 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63)
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_SRAM2WRP_PAGE32 LL_SYSCFG_SRAM2WRP_PAGE32 /*!< SRAM2B Write protection page 32 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE33 LL_SYSCFG_SRAM2WRP_PAGE33 /*!< SRAM2B Write protection page 33 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE34 LL_SYSCFG_SRAM2WRP_PAGE34 /*!< SRAM2B Write protection page 34 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE35 LL_SYSCFG_SRAM2WRP_PAGE35 /*!< SRAM2B Write protection page 35 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE36 LL_SYSCFG_SRAM2WRP_PAGE36 /*!< SRAM2B Write protection page 36 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE37 LL_SYSCFG_SRAM2WRP_PAGE37 /*!< SRAM2B Write protection page 37 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE38 LL_SYSCFG_SRAM2WRP_PAGE38 /*!< SRAM2B Write protection page 38 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE39 LL_SYSCFG_SRAM2WRP_PAGE39 /*!< SRAM2B Write protection page 39 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE40 LL_SYSCFG_SRAM2WRP_PAGE40 /*!< SRAM2B Write protection page 40 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE41 LL_SYSCFG_SRAM2WRP_PAGE41 /*!< SRAM2B Write protection page 41 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE42 LL_SYSCFG_SRAM2WRP_PAGE42 /*!< SRAM2B Write protection page 42 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE43 LL_SYSCFG_SRAM2WRP_PAGE43 /*!< SRAM2B Write protection page 43 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE44 LL_SYSCFG_SRAM2WRP_PAGE44 /*!< SRAM2B Write protection page 44 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE45 LL_SYSCFG_SRAM2WRP_PAGE45 /*!< SRAM2B Write protection page 45 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE46 LL_SYSCFG_SRAM2WRP_PAGE46 /*!< SRAM2B Write protection page 46 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE47 LL_SYSCFG_SRAM2WRP_PAGE47 /*!< SRAM2B Write protection page 47 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE48 LL_SYSCFG_SRAM2WRP_PAGE48 /*!< SRAM2B Write protection page 48 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE49 LL_SYSCFG_SRAM2WRP_PAGE49 /*!< SRAM2B Write protection page 49 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE50 LL_SYSCFG_SRAM2WRP_PAGE50 /*!< SRAM2B Write protection page 50 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE51 LL_SYSCFG_SRAM2WRP_PAGE51 /*!< SRAM2B Write protection page 51 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE52 LL_SYSCFG_SRAM2WRP_PAGE52 /*!< SRAM2B Write protection page 52 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE53 LL_SYSCFG_SRAM2WRP_PAGE53 /*!< SRAM2B Write protection page 53 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE54 LL_SYSCFG_SRAM2WRP_PAGE54 /*!< SRAM2B Write protection page 54 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE55 LL_SYSCFG_SRAM2WRP_PAGE55 /*!< SRAM2B Write protection page 55 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE56 LL_SYSCFG_SRAM2WRP_PAGE56 /*!< SRAM2B Write protection page 56 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE57 LL_SYSCFG_SRAM2WRP_PAGE57 /*!< SRAM2B Write protection page 57 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE58 LL_SYSCFG_SRAM2WRP_PAGE58 /*!< SRAM2B Write protection page 58 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE59 LL_SYSCFG_SRAM2WRP_PAGE59 /*!< SRAM2B Write protection page 59 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE60 LL_SYSCFG_SRAM2WRP_PAGE60 /*!< SRAM2B Write protection page 60 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE61 LL_SYSCFG_SRAM2WRP_PAGE61 /*!< SRAM2B Write protection page 61 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE62 LL_SYSCFG_SRAM2WRP_PAGE62 /*!< SRAM2B Write protection page 62 */
|
||||
#define SYSCFG_SRAM2WRP_PAGE63 LL_SYSCFG_SRAM2WRP_PAGE63 /*!< SRAM2B Write protection page 63 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(VREFBUF)
|
||||
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 LL_VREFBUF_VOLTAGE_SCALE0 /*!< Voltage reference scale 0 (VREF_OUT1) */
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 LL_VREFBUF_VOLTAGE_SCALE1 /*!< Voltage reference scale 1 (VREF_OUT2) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* VREFBUF */
|
||||
|
||||
/** @defgroup SYSCFG_SRAM_flags_definition SRAM Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */
|
||||
#define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Fast-mode Plus driving capability on a specific GPIO
|
||||
*/
|
||||
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
|
||||
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
|
||||
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
|
||||
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Secure_IP_Write_Access Secure IP Write Access
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SYSCFG_SECURE_ACCESS_AES1 LL_SYSCFG_SECURE_ACCESS_AES1 /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */
|
||||
#define HAL_SYSCFG_SECURE_ACCESS_AES2 LL_SYSCFG_SECURE_ACCESS_AES2 /*!< Enabling the security access of Advanced Encryption Standard 2 */
|
||||
#define HAL_SYSCFG_SECURE_ACCESS_PKA LL_SYSCFG_SECURE_ACCESS_PKA /*!< Enabling the security access of Public Key Accelerator */
|
||||
#define HAL_SYSCFG_SECURE_ACCESS_RNG LL_SYSCFG_SECURE_ACCESS_RNG /*!< Enabling the security access of Random Number Generator */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup HAL_Exported_Macros HAL Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Freeze and Unfreeze Peripherals in Debug mode
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_APBx_GRPx_STOP_IP DBGMCU CPU1 APBx GRPx STOP IP
|
||||
* @{
|
||||
*/
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM2() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM2() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_RTC() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_RTC() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_WWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_WWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_IWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_IWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM1() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM1() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM16() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM16() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
|
||||
#define __HAL_DBGMCU_FREEZE_TIM17() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
|
||||
#define __HAL_DBGMCU_UNFREEZE_TIM17() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU_C2_APBx_GRPx_STOP_IP DBGMCU CPU2 APBx GRPx STOP IP
|
||||
* @{
|
||||
*/
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
|
||||
#endif
|
||||
|
||||
#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
|
||||
#define __HAL_C2_DBGMCU_FREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
|
||||
#define __HAL_C2_DBGMCU_UNFREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Main Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH)
|
||||
|
||||
/** @brief System Flash memory mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH)
|
||||
|
||||
/** @brief Embedded SRAM mapped at 0x00000000
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM)
|
||||
|
||||
/** @brief QUADSPI mapped at 0x00000000.
|
||||
*/
|
||||
#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI)
|
||||
|
||||
/**
|
||||
* @brief Return the boot mode as configured by user.
|
||||
* @retval The boot mode as configured by user. The returned value can be one
|
||||
* of the following values:
|
||||
* @arg @ref SYSCFG_BOOT_MAINFLASH
|
||||
* @arg @ref SYSCFG_BOOT_SYSTEMFLASH
|
||||
* @arg @ref SYSCFG_BOOT_SRAM
|
||||
* @arg @ref SYSCFG_BOOT_QUADSPI
|
||||
*/
|
||||
#define __HAL_SYSCFG_GET_BOOT_MODE() LL_SYSCFG_GetRemapMemory()
|
||||
|
||||
/** @brief SRAM2 page 0 to 31 write protection enable macro
|
||||
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP
|
||||
* @note Write protection can only be disabled by a system reset
|
||||
*/
|
||||
/* Legacy define */
|
||||
#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
|
||||
#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
|
||||
LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);\
|
||||
}while(0)
|
||||
|
||||
/** @brief SRAM2 page 32 to 63 write protection enable macro
|
||||
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
|
||||
* @note Write protection can only be disabled by a system reset
|
||||
*/
|
||||
#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
|
||||
LL_SYSCFG_EnableSRAM2PageWRP_32_63(__SRAM2WRP__);\
|
||||
}while(0)
|
||||
|
||||
/** @brief SRAM2 page write protection unlock prior to erase
|
||||
* @note Writing a wrong key reactivates the write protection
|
||||
*/
|
||||
#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() LL_SYSCFG_UnlockSRAM2WRP()
|
||||
|
||||
/** @brief SRAM2 erase
|
||||
* @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
|
||||
*/
|
||||
#define __HAL_SYSCFG_SRAM2_ERASE() LL_SYSCFG_EnableSRAM2Erase()
|
||||
|
||||
/** @brief Floating Point Unit interrupt enable/disable macros
|
||||
* @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts
|
||||
*/
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
|
||||
SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
|
||||
CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
|
||||
}while(0)
|
||||
|
||||
/** @brief SYSCFG Break ECC lock.
|
||||
* Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_ECC_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC)
|
||||
|
||||
/** @brief SYSCFG Break Cortex-M4 Lockup lock.
|
||||
* Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/16/17 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP)
|
||||
|
||||
/** @brief SYSCFG Break PVD lock.
|
||||
* Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
|
||||
* @note The selected configuration is locked and can be unlocked only by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD)
|
||||
|
||||
/** @brief SYSCFG Break SRAM2 parity lock.
|
||||
* Enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break input.
|
||||
* @note The selected configuration is locked and can be unlocked by system reset.
|
||||
*/
|
||||
#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY)
|
||||
|
||||
/** @brief Check SYSCFG flag is set or not.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag
|
||||
* @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
|
||||
|
||||
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
|
||||
*/
|
||||
#define __HAL_SYSCFG_CLEAR_FLAG() LL_SYSCFG_ClearFlag_SP()
|
||||
|
||||
/** @brief Fast mode Plus driving capability enable/disable macros
|
||||
* @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
|
||||
*/
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
|
||||
LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__); \
|
||||
}while(0)
|
||||
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
|
||||
LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__); \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
|
||||
(((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
|
||||
|
||||
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
|
||||
|
||||
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
|
||||
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
|
||||
|
||||
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
|
||||
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
|
||||
|
||||
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
|
||||
|
||||
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
|
||||
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
|
||||
|
||||
#define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1) == HAL_SYSCFG_SECURE_ACCESS_AES1) || \
|
||||
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \
|
||||
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \
|
||||
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Private_Macros HAL Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_100HZ) || \
|
||||
((FREQ) == HAL_TICK_FREQ_1KHZ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions HAL Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and Configuration functions ******************************/
|
||||
HAL_StatusTypeDef HAL_Init(void);
|
||||
HAL_StatusTypeDef HAL_DeInit(void);
|
||||
void HAL_MspInit(void);
|
||||
void HAL_MspDeInit(void);
|
||||
|
||||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_IncTick(void);
|
||||
void HAL_Delay(uint32_t Delay);
|
||||
uint32_t HAL_GetTick(void);
|
||||
uint32_t HAL_GetTickPrio(void);
|
||||
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
|
||||
uint32_t HAL_GetTickFreq(void);
|
||||
void HAL_SuspendTick(void);
|
||||
void HAL_ResumeTick(void);
|
||||
uint32_t HAL_GetHalVersion(void);
|
||||
uint32_t HAL_GetREVID(void);
|
||||
uint32_t HAL_GetDEVID(void);
|
||||
uint32_t HAL_GetUIDw0(void);
|
||||
uint32_t HAL_GetUIDw1(void);
|
||||
uint32_t HAL_GetUIDw2(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* DBGMCU Peripheral Control functions *****************************************/
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void);
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void);
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported variables ---------------------------------------------------------*/
|
||||
/** @addtogroup HAL_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
extern __IO uint32_t uwTick;
|
||||
extern uint32_t uwTickPrio;
|
||||
extern uint32_t uwTickFreq;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HAL_Exported_Functions_Group4 HAL System Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* SYSCFG Control functions ****************************************************/
|
||||
void HAL_SYSCFG_SRAM2Erase(void);
|
||||
void HAL_SYSCFG_DisableSRAMFetch(void);
|
||||
uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void);
|
||||
|
||||
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
|
||||
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
|
||||
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
|
||||
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
|
||||
void HAL_SYSCFG_DisableVREFBUF(void);
|
||||
|
||||
void HAL_SYSCFG_EnableIOBooster(void);
|
||||
void HAL_SYSCFG_DisableIOBooster(void);
|
||||
void HAL_SYSCFG_EnableIOVdd(void);
|
||||
void HAL_SYSCFG_DisableIOVdd(void);
|
||||
|
||||
void HAL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess);
|
||||
void HAL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess);
|
||||
uint32_t HAL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,764 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_adc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of ADC HAL extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_ADC_EX_H
|
||||
#define STM32WBxx_HAL_ADC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ADC Injected Conversion Oversampling structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Ratio; /*!< Configures the oversampling ratio.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
|
||||
|
||||
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
|
||||
}ADC_InjOversamplingTypeDef;
|
||||
|
||||
/**
|
||||
* @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
|
||||
* @note Parameters of this structure are shared within 2 scopes:
|
||||
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
|
||||
* - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
|
||||
* AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
|
||||
* @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
|
||||
* ADC state can be either:
|
||||
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
|
||||
* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
|
||||
* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
|
||||
* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
|
||||
* on ADC groups regular and injected.
|
||||
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
|
||||
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
|
||||
Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
|
||||
|
||||
uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
|
||||
This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
|
||||
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
|
||||
the new channel setting (or parameter number of conversions adjusted) */
|
||||
|
||||
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
|
||||
Unit: ADC clock cycles.
|
||||
Conversion time is the addition of sampling time and processing time
|
||||
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
|
||||
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
|
||||
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
|
||||
It overwrites the last setting.
|
||||
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
|
||||
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
|
||||
Refer to device datasheet for timings values. */
|
||||
|
||||
uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
|
||||
In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
|
||||
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
|
||||
This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
|
||||
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
|
||||
It overwrites the last setting.
|
||||
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
|
||||
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
|
||||
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
|
||||
of another parameter update on the fly) */
|
||||
|
||||
uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
|
||||
This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
|
||||
Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
|
||||
|
||||
uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
|
||||
Offset value must be a positive number.
|
||||
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
|
||||
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
|
||||
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
|
||||
without continuous mode or external trigger that could launch a conversion). */
|
||||
|
||||
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
|
||||
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
|
||||
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
|
||||
(main sequence subdivided in successive parts).
|
||||
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
|
||||
Discontinuous mode can be enabled only if continuous mode is disabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
|
||||
Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
|
||||
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
|
||||
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
|
||||
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
|
||||
To maintain JAUTO always enabled, DMA must be configured in circular mode.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
|
||||
FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
|
||||
new injected context is set when queue is full, error is triggered by interruption and through function
|
||||
'HAL_ADCEx_InjectedQueueOverflowCallback'.
|
||||
Caution: This feature request that the sequence is fully configured before injected conversion start.
|
||||
Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set.
|
||||
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
|
||||
|
||||
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
|
||||
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
|
||||
This parameter can be a value of @ref ADC_injected_external_trigger_source.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
|
||||
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
|
||||
This parameter can be a value of @ref ADC_injected_external_trigger_edge.
|
||||
If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
|
||||
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
|
||||
configure a channel on injected group can impact the configuration of other channels previously set. */
|
||||
|
||||
FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
|
||||
This parameter can be set to ENABLE or DISABLE.
|
||||
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
|
||||
|
||||
ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
|
||||
Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
|
||||
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
|
||||
}ADC_InjectionConfTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
|
||||
* @{
|
||||
*/
|
||||
/* ADC group regular trigger sources for all ADC instances */
|
||||
#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
|
||||
#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
|
||||
#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
|
||||
* @{
|
||||
*/
|
||||
#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */
|
||||
#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
|
||||
#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
|
||||
* @{
|
||||
*/
|
||||
#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
|
||||
#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
|
||||
#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
|
||||
#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
|
||||
* @{
|
||||
*/
|
||||
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
|
||||
#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/
|
||||
#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_CFGR_fields ADCx CFGR fields
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
|
||||
ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
|
||||
ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
|
||||
ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
|
||||
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
|
||||
ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
|
||||
ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
|
||||
ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
|
||||
ADC_SMPR1_SMP0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
|
||||
* @{
|
||||
*/
|
||||
/* ADC_CFGR fields of parameters that can be updated when no conversion
|
||||
(neither regular nor injected) is on-going */
|
||||
#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
/* Macro reserved for internal HAL driver usage, not intended to be used in */
|
||||
/* code of final user. */
|
||||
|
||||
/**
|
||||
* @brief Test if conversion trigger of injected group is software start
|
||||
* or external trigger.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval SET (software start) or RESET (external trigger).
|
||||
*/
|
||||
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
|
||||
(((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
|
||||
|
||||
/**
|
||||
* @brief Check whether or not ADC is independent.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @note When multimode feature is not available, the macro always returns SET.
|
||||
* @retval SET (ADC is independent) or RESET (ADC is not).
|
||||
*/
|
||||
#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
|
||||
|
||||
/**
|
||||
* @brief Set the selected injected Channel rank.
|
||||
* @param __CHANNELNB__ Channel number.
|
||||
* @param __RANKNB__ Rank number.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
|
||||
|
||||
/**
|
||||
* @brief Configure ADC injected context queue
|
||||
* @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure ADC discontinuous conversion mode for injected group
|
||||
* @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure ADC discontinuous conversion mode for regular group
|
||||
* @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure the number of discontinuous conversions for regular group.
|
||||
* @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure the ADC auto delay mode.
|
||||
* @param __AUTOWAIT__ Auto delay bit enable or disable.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure ADC continuous conversion mode.
|
||||
* @param __CONTINUOUS_MODE__ Continuous mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
|
||||
|
||||
/**
|
||||
* @brief Configure the ADC DMA continuous request.
|
||||
* @param __DMACONTREQ_MODE__ DMA continuous request mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Shift the offset with respect to the selected ADC resolution.
|
||||
* @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
|
||||
* If resolution 12 bits, no shift.
|
||||
* If resolution 10 bits, shift of 2 ranks on the left.
|
||||
* If resolution 8 bits, shift of 4 ranks on the left.
|
||||
* If resolution 6 bits, shift of 6 ranks on the left.
|
||||
* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __OFFSET__ Value to be shifted
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
|
||||
((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
|
||||
|
||||
/**
|
||||
* @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
|
||||
* @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
|
||||
* If resolution 12 bits, no shift.
|
||||
* If resolution 10 bits, shift of 2 ranks on the left.
|
||||
* If resolution 8 bits, shift of 4 ranks on the left.
|
||||
* If resolution 6 bits, shift of 6 ranks on the left.
|
||||
* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __THRESHOLD__ Value to be shifted
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
|
||||
((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
|
||||
|
||||
/**
|
||||
* @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
|
||||
* @note Thresholds have to be left-aligned on bit 7.
|
||||
* If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
|
||||
* If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
|
||||
* If resolution 8 bits, no shift.
|
||||
* If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
|
||||
* @param __HANDLE__ ADC handle
|
||||
* @param __THRESHOLD__ Value to be shifted
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
|
||||
((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \
|
||||
((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
|
||||
((__THRESHOLD__) << 2UL) \
|
||||
)
|
||||
|
||||
/**
|
||||
* @brief Clear Common Control Register.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \
|
||||
ADC_CCR_PRESC | \
|
||||
ADC_CCR_VBATEN | \
|
||||
ADC_CCR_TSEN | \
|
||||
ADC_CCR_VREFEN )
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC instance connected to the temperature sensor.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
|
||||
*/
|
||||
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC instance connected to the battery voltage VBAT.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
|
||||
*/
|
||||
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
|
||||
*/
|
||||
#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
|
||||
|
||||
/**
|
||||
* @brief Verify the length of scheduled injected conversions group.
|
||||
* @param __LENGTH__ number of programmed conversions.
|
||||
* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
|
||||
*/
|
||||
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
|
||||
|
||||
/**
|
||||
* @brief Calibration factor size verification (7 bits maximum).
|
||||
* @param __CALIBRATION_FACTOR__ Calibration factor value.
|
||||
* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
|
||||
*/
|
||||
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC channel setting.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @param __CHANNEL__ programmed ADC channel.
|
||||
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \
|
||||
(((__CHANNEL__) == ADC_CHANNEL_0) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_7) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_8) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_9) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_10) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_11) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_13) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_14) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_15) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_16) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_17) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_18) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_VBAT)))
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC channel setting in differential mode.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @param __CHANNEL__ programmed ADC channel.
|
||||
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_2) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_3) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_4) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_5) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_6) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_7) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_8) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_9) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_10) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_11) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_12) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_13) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_14) || \
|
||||
((__CHANNEL__) == ADC_CHANNEL_15) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC single-ended input or differential mode setting.
|
||||
* @param __SING_DIFF__ programmed channel setting.
|
||||
* @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
|
||||
((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC offset management setting.
|
||||
* @param __OFFSET_NUMBER__ ADC offset management.
|
||||
* @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
|
||||
((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
|
||||
((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
|
||||
((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
|
||||
((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC injected channel setting.
|
||||
* @param __CHANNEL__ programmed ADC injected channel.
|
||||
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
|
||||
((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
|
||||
((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
|
||||
((__CHANNEL__) == ADC_INJECTED_RANK_4) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC injected conversions external trigger.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @param __INJTRIG__ programmed ADC injected conversions external trigger.
|
||||
* @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
|
||||
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
|
||||
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC edge trigger setting for injected group.
|
||||
* @param __EDGE__ programmed ADC edge trigger setting.
|
||||
* @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
|
||||
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC analog watchdog setting.
|
||||
* @param __WATCHDOG__ programmed ADC analog watchdog setting.
|
||||
* @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
|
||||
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC analog watchdog mode setting.
|
||||
* @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
|
||||
* @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
|
||||
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC conversion (regular or injected or both).
|
||||
* @param __CONVERSION__ ADC conversion group.
|
||||
* @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
|
||||
((__CONVERSION__) == ADC_INJECTED_GROUP) || \
|
||||
((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC event type.
|
||||
* @param __EVENT__ ADC event.
|
||||
* @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
|
||||
((__EVENT__) == ADC_AWD_EVENT) || \
|
||||
((__EVENT__) == ADC_AWD2_EVENT) || \
|
||||
((__EVENT__) == ADC_AWD3_EVENT) || \
|
||||
((__EVENT__) == ADC_OVR_EVENT) || \
|
||||
((__EVENT__) == ADC_JQOVF_EVENT) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC oversampling ratio.
|
||||
* @param __RATIO__ programmed ADC oversampling ratio.
|
||||
* @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
|
||||
((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC oversampling shift.
|
||||
* @param __SHIFT__ programmed ADC oversampling shift.
|
||||
* @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
|
||||
((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC oversampling triggered mode.
|
||||
* @param __MODE__ programmed ADC oversampling triggered mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
|
||||
((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
|
||||
|
||||
/**
|
||||
* @brief Verify the ADC oversampling regular conversion resumed or continued mode.
|
||||
* @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
|
||||
((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
|
||||
|
||||
/**
|
||||
* @brief Verify the DFSDM mode configuration.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
|
||||
* this reason, the input parameter is the ADC handle and not the configuration parameter
|
||||
* directly.
|
||||
* @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
|
||||
*/
|
||||
#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
|
||||
|
||||
/**
|
||||
* @brief Return the DFSDM configuration mode.
|
||||
* @param __HANDLE__ ADC handle.
|
||||
* @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
|
||||
* For this reason, the input parameter is the ADC handle and not the configuration parameter
|
||||
* directly.
|
||||
* @retval DFSDM configuration mode
|
||||
*/
|
||||
#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup ADCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
|
||||
/* ADC calibration */
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
|
||||
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
|
||||
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
|
||||
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
|
||||
|
||||
/* Non-blocking mode: Interruption */
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* ADC retrieve conversion value intended to be used with polling or interruption */
|
||||
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
|
||||
|
||||
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
|
||||
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
|
||||
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/* ADC group regular conversions stop */
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup ADCEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
|
||||
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
|
||||
HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_ADC_EX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,992 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_comp.c
|
||||
* @author MCD Application Team
|
||||
* @brief COMP HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the COMP peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Start/Stop operation functions in polling mode
|
||||
* + Start/Stop operation functions in interrupt mode (through EXTI interrupt)
|
||||
* + Peripheral control functions
|
||||
* + Peripheral state functions
|
||||
*
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### COMP Peripheral features #####
|
||||
================================================================================
|
||||
|
||||
[..]
|
||||
The STM32WBxx device family integrates two analog comparators instances:
|
||||
COMP1, COMP2.
|
||||
(#) Comparators input minus (inverting input) and input plus (non inverting input)
|
||||
can be set to internal references or to GPIO pins
|
||||
(refer to GPIO list in reference manual).
|
||||
|
||||
(#) Comparators output level is available using HAL_COMP_GetOutputLevel()
|
||||
and can be redirected to other peripherals: GPIO pins (in mode
|
||||
alternate functions for comparator), timers.
|
||||
(refer to GPIO list in reference manual).
|
||||
|
||||
(#) The comparators have interrupt capability through the EXTI controller
|
||||
with wake-up from sleep and stop modes.
|
||||
|
||||
(#) Pairs of comparators instances can be combined in window mode
|
||||
(2 consecutive instances odd and even COMP<x> and COMP<x+1>).
|
||||
|
||||
From the corresponding IRQ handler, the right interrupt source can be retrieved
|
||||
using macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
|
||||
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
This driver provides functions to configure and program the comparator instances
|
||||
of STM32WBxx devices.
|
||||
|
||||
To use the comparator, perform the following steps:
|
||||
|
||||
(#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
|
||||
(++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
|
||||
using HAL_GPIO_Init().
|
||||
(++) If needed, configure the GPIO connected to comparator output in alternate function mode
|
||||
using HAL_GPIO_Init().
|
||||
(++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
|
||||
selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
|
||||
interrupt vector using HAL_NVIC_EnableIRQ() function.
|
||||
|
||||
(#) Configure the comparator using HAL_COMP_Init() function:
|
||||
(++) Select the input minus (inverting input)
|
||||
(++) Select the input plus (non-inverting input)
|
||||
(++) Select the hysteresis
|
||||
(++) Select the blanking source
|
||||
(++) Select the output polarity
|
||||
(++) Select the power mode
|
||||
(++) Select the window mode
|
||||
|
||||
-@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
|
||||
to enable internal control clock of the comparators.
|
||||
However, this is a legacy strategy. In future STM32 families,
|
||||
COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
|
||||
Therefore, for compatibility anticipation, it is recommended to
|
||||
implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
|
||||
|
||||
(#) Reconfiguration on-the-fly of comparator can be done by calling again
|
||||
function HAL_COMP_Init() with new input structure parameters values.
|
||||
|
||||
(#) Enable the comparator using HAL_COMP_Start() function.
|
||||
|
||||
(#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
|
||||
to manage comparator outputs (events and output level).
|
||||
|
||||
(#) Disable the comparator using HAL_COMP_Stop() function.
|
||||
|
||||
(#) De-initialize the comparator using HAL_COMP_DeInit() function.
|
||||
|
||||
(#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
|
||||
The only way to unlock the comparator is a device hardware reset.
|
||||
|
||||
*** Callback registration ***
|
||||
=============================================
|
||||
[..]
|
||||
|
||||
The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
Use Functions @ref HAL_COMP_RegisterCallback()
|
||||
to register an interrupt callback.
|
||||
[..]
|
||||
|
||||
Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks:
|
||||
(+) TriggerCallback : callback for COMP trigger.
|
||||
(+) MspInitCallback : callback for Msp Init.
|
||||
(+) MspDeInitCallback : callback for Msp DeInit.
|
||||
This function takes as parameters the HAL peripheral handle, the Callback ID
|
||||
and a pointer to the user callback function.
|
||||
[..]
|
||||
|
||||
Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default
|
||||
weak function.
|
||||
[..]
|
||||
|
||||
@ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) TriggerCallback : callback for COMP trigger.
|
||||
(+) MspInitCallback : callback for Msp Init.
|
||||
(+) MspDeInitCallback : callback for Msp DeInit.
|
||||
[..]
|
||||
|
||||
By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
example @ref HAL_COMP_TriggerCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are
|
||||
reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when
|
||||
these callbacks are null (not registered beforehand).
|
||||
[..]
|
||||
|
||||
If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
|
||||
[..]
|
||||
|
||||
Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only.
|
||||
Exception done MspInit/MspDeInit functions that can be registered/unregistered
|
||||
in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state,
|
||||
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
[..]
|
||||
|
||||
Then, the user first registers the MspInit/MspDeInit user callbacks
|
||||
using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit()
|
||||
or @ref HAL_COMP_Init() function.
|
||||
[..]
|
||||
|
||||
When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registration feature is not available and all callbacks
|
||||
are set to the corresponding weak functions.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
|
||||
|
||||
|
||||
/** @defgroup COMP COMP
|
||||
* @brief COMP HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup COMP_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Delay for COMP startup time. */
|
||||
/* Note: Delay required to reach propagation delay specification. */
|
||||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* parameter "tSTART"). */
|
||||
/* Unit: us */
|
||||
#define COMP_DELAY_STARTUP_US (80UL) /*!< Delay for COMP startup time */
|
||||
|
||||
/* Delay for COMP voltage scaler stabilization time. */
|
||||
/* Literal set to maximum value (refer to device datasheet, */
|
||||
/* parameter "tSTART_SCALER"). */
|
||||
/* Unit: us */
|
||||
#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL) /*!< Delay for COMP voltage scaler stabilization time */
|
||||
|
||||
#define COMP_OUTPUT_LEVEL_BITOFFSET_POS (30UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions COMP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and de-initialization functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions to initialize and de-initialize comparators
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the COMP according to the specified
|
||||
* parameters in the COMP_InitTypeDef and initialize the associated handle.
|
||||
* @note If the selected comparator is locked, initialization can't be performed.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
uint32_t tmp_csr;
|
||||
uint32_t exti_line;
|
||||
uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */
|
||||
__IO uint32_t wait_loop_index = 0UL;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if(hcomp == NULL)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else if(__HAL_COMP_IS_LOCKED(hcomp))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.InputPlus));
|
||||
assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InputMinus));
|
||||
assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
|
||||
assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
|
||||
assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
|
||||
assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
|
||||
assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
|
||||
assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hcomp->Lock = HAL_UNLOCKED;
|
||||
|
||||
/* Set COMP error code to none */
|
||||
COMP_CLEAR_ERRORCODE(hcomp);
|
||||
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/* Init the COMP Callback settings */
|
||||
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
|
||||
|
||||
if (hcomp->MspInitCallback == NULL)
|
||||
{
|
||||
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
|
||||
}
|
||||
|
||||
/* Init the low level hardware */
|
||||
/* Note: Internal control clock of the comparators must */
|
||||
/* be enabled in "HAL_COMP_MspInit()" */
|
||||
/* using "__HAL_RCC_SYSCFG_CLK_ENABLE()". */
|
||||
hcomp->MspInitCallback(hcomp);
|
||||
#else
|
||||
/* Init the low level hardware */
|
||||
/* Note: Internal control clock of the comparators must */
|
||||
/* be enabled in "HAL_COMP_MspInit()" */
|
||||
/* using "__HAL_RCC_SYSCFG_CLK_ENABLE()". */
|
||||
HAL_COMP_MspInit(hcomp);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
/* Memorize voltage scaler state before initialization */
|
||||
comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN);
|
||||
|
||||
/* Set COMP parameters */
|
||||
tmp_csr = ( hcomp->Init.InputMinus
|
||||
| hcomp->Init.InputPlus
|
||||
| hcomp->Init.BlankingSrce
|
||||
| hcomp->Init.Hysteresis
|
||||
| hcomp->Init.OutputPol
|
||||
| hcomp->Init.Mode
|
||||
);
|
||||
|
||||
/* Set parameters in COMP register */
|
||||
/* Note: Update all bits except read-only, lock and enable bits */
|
||||
MODIFY_REG(hcomp->Instance->CSR,
|
||||
COMP_CSR_PWRMODE | COMP_CSR_INMSEL | COMP_CSR_INPSEL |
|
||||
COMP_CSR_WINMODE | COMP_CSR_POLARITY | COMP_CSR_HYST |
|
||||
COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL,
|
||||
tmp_csr
|
||||
);
|
||||
|
||||
/* Set window mode */
|
||||
/* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */
|
||||
/* instances. Therefore, this function can update another COMP */
|
||||
/* instance that the one currently selected. */
|
||||
if(hcomp->Init.WindowMode == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)
|
||||
{
|
||||
SET_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
|
||||
}
|
||||
|
||||
/* Delay for COMP scaler bridge voltage stabilization */
|
||||
/* Apply the delay if voltage scaler bridge is required and not already enabled */
|
||||
if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) &&
|
||||
(comp_voltage_scaler_initialized == 0UL) )
|
||||
{
|
||||
/* Wait loop initialization and execution */
|
||||
/* Note: Variable divided by 2 to compensate partially */
|
||||
/* CPU processing cycles, scaling in us split to not */
|
||||
/* exceed 32 bits register capacity and handle low frequency. */
|
||||
wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
|
||||
while(wait_loop_index != 0UL)
|
||||
{
|
||||
wait_loop_index--;
|
||||
}
|
||||
}
|
||||
|
||||
/* Get the EXTI line corresponding to the selected COMP instance */
|
||||
exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
|
||||
|
||||
/* Manage EXTI settings */
|
||||
if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
|
||||
{
|
||||
/* Configure EXTI rising edge */
|
||||
if((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
|
||||
{
|
||||
LL_EXTI_EnableRisingTrig_0_31(exti_line);
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_EXTI_DisableRisingTrig_0_31(exti_line);
|
||||
}
|
||||
|
||||
/* Configure EXTI falling edge */
|
||||
if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
|
||||
{
|
||||
LL_EXTI_EnableFallingTrig_0_31(exti_line);
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_EXTI_DisableFallingTrig_0_31(exti_line);
|
||||
}
|
||||
|
||||
/* Clear COMP EXTI pending bit (if any) */
|
||||
LL_EXTI_ClearFlag_0_31(exti_line);
|
||||
|
||||
/* Configure EXTI event mode */
|
||||
if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
|
||||
{
|
||||
LL_EXTI_EnableEvent_0_31(exti_line);
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_EXTI_DisableEvent_0_31(exti_line);
|
||||
}
|
||||
|
||||
/* Configure EXTI interrupt mode */
|
||||
if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
|
||||
{
|
||||
LL_EXTI_EnableIT_0_31(exti_line);
|
||||
}
|
||||
else
|
||||
{
|
||||
LL_EXTI_DisableIT_0_31(exti_line);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable EXTI event mode */
|
||||
LL_EXTI_DisableEvent_0_31(exti_line);
|
||||
|
||||
/* Disable EXTI interrupt mode */
|
||||
LL_EXTI_DisableIT_0_31(exti_line);
|
||||
}
|
||||
|
||||
/* Set HAL COMP handle state */
|
||||
/* Note: Transition from state reset to state ready, */
|
||||
/* otherwise (coming from state ready or busy) no state update. */
|
||||
if (hcomp->State == HAL_COMP_STATE_RESET)
|
||||
{
|
||||
hcomp->State = HAL_COMP_STATE_READY;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the COMP peripheral.
|
||||
* @note Deinitialization cannot be performed if the COMP configuration is locked.
|
||||
* To unlock the configuration, perform a system reset.
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if(hcomp == NULL)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else if(__HAL_COMP_IS_LOCKED(hcomp))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
/* Set COMP_CSR register to reset value */
|
||||
WRITE_REG(hcomp->Instance->CSR, 0x00000000UL);
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
if (hcomp->MspDeInitCallback == NULL)
|
||||
{
|
||||
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
|
||||
}
|
||||
|
||||
/* DeInit the low level hardware: GPIO, RCC clock, NVIC */
|
||||
hcomp->MspDeInitCallback(hcomp);
|
||||
#else
|
||||
/* DeInit the low level hardware: GPIO, RCC clock, NVIC */
|
||||
HAL_COMP_MspDeInit(hcomp);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/* Set HAL COMP handle state */
|
||||
hcomp->State = HAL_COMP_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hcomp);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the COMP MSP.
|
||||
* @param hcomp COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcomp);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_COMP_MspInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the COMP MSP.
|
||||
* @param hcomp COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcomp);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_COMP_MspDeInit could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User COMP Callback
|
||||
* To be used instead of the weak predefined callback
|
||||
* @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified COMP.
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
|
||||
* @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (HAL_COMP_STATE_READY == hcomp->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_COMP_TRIGGER_CB_ID :
|
||||
hcomp->TriggerCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPINIT_CB_ID :
|
||||
hcomp->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPDEINIT_CB_ID :
|
||||
hcomp->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (HAL_COMP_STATE_RESET == hcomp->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_COMP_MSPINIT_CB_ID :
|
||||
hcomp->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPDEINIT_CB_ID :
|
||||
hcomp->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregister a COMP Callback
|
||||
* COMP callback is redirected to the weak predefined callback
|
||||
* @param hcomp Pointer to a COMP_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified COMP.
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
|
||||
* @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (HAL_COMP_STATE_READY == hcomp->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_COMP_TRIGGER_CB_ID :
|
||||
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPINIT_CB_ID :
|
||||
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPDEINIT_CB_ID :
|
||||
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (HAL_COMP_STATE_RESET == hcomp->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_COMP_MSPINIT_CB_ID :
|
||||
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
|
||||
case HAL_COMP_MSPDEINIT_CB_ID :
|
||||
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
|
||||
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
|
||||
* @brief Start-Stop operation functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Start a comparator instance.
|
||||
(+) Stop a comparator instance.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the comparator.
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
__IO uint32_t wait_loop_index = 0UL;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if(hcomp == NULL)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else if(__HAL_COMP_IS_LOCKED(hcomp))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
if(hcomp->State == HAL_COMP_STATE_READY)
|
||||
{
|
||||
/* Enable the selected comparator */
|
||||
SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
|
||||
|
||||
/* Set HAL COMP handle state */
|
||||
hcomp->State = HAL_COMP_STATE_BUSY;
|
||||
|
||||
/* Delay for COMP startup time */
|
||||
/* Wait loop initialization and execution */
|
||||
/* Note: Variable divided by 2 to compensate partially */
|
||||
/* CPU processing cycles, scaling in us split to not */
|
||||
/* exceed 32 bits register capacity and handle low frequency. */
|
||||
wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
|
||||
while(wait_loop_index != 0UL)
|
||||
{
|
||||
wait_loop_index--;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stop the comparator.
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if(hcomp == NULL)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else if(__HAL_COMP_IS_LOCKED(hcomp))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
/* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */
|
||||
/* (all states except HAL_COMP_STATE_RESET and except locked status. */
|
||||
if(hcomp->State != HAL_COMP_STATE_RESET)
|
||||
{
|
||||
/* Disable the selected comparator */
|
||||
CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
|
||||
|
||||
/* Set HAL COMP handle state */
|
||||
hcomp->State = HAL_COMP_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Comparator IRQ handler.
|
||||
* @param hcomp COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Get the EXTI line corresponding to the selected COMP instance */
|
||||
uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
|
||||
|
||||
/* Check COMP EXTI flag */
|
||||
if(LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL)
|
||||
{
|
||||
/* Check whether comparator is in independent or window mode */
|
||||
if(READ_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE) != 0UL)
|
||||
{
|
||||
/* Clear COMP EXTI line pending bit of the pair of comparators */
|
||||
/* in window mode. */
|
||||
/* Note: Pair of comparators in window mode can both trig IRQ when */
|
||||
/* input voltage is changing from "out of window" area */
|
||||
/* (low or high ) to the other "out of window" area (high or low).*/
|
||||
/* Both flags must be cleared to call comparator trigger */
|
||||
/* callback is called once. */
|
||||
LL_EXTI_ClearFlag_0_31((COMP_EXTI_LINE_COMP1 | COMP_EXTI_LINE_COMP2));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear COMP EXTI line pending bit */
|
||||
LL_EXTI_ClearFlag_0_31(exti_line);
|
||||
}
|
||||
|
||||
/* COMP trigger user callback */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
hcomp->TriggerCallback(hcomp);
|
||||
#else
|
||||
HAL_COMP_TriggerCallback(hcomp);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @brief Management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the comparators.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Lock the selected comparator configuration.
|
||||
* @note A system reset is required to unlock the comparator configuration.
|
||||
* @note Locking the comparator from reset state is possible
|
||||
* if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the COMP handle allocation and lock status */
|
||||
if(hcomp == NULL)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else if(__HAL_COMP_IS_LOCKED(hcomp))
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
/* Set HAL COMP handle state */
|
||||
switch(hcomp->State)
|
||||
{
|
||||
case HAL_COMP_STATE_RESET:
|
||||
hcomp->State = HAL_COMP_STATE_RESET_LOCKED;
|
||||
break;
|
||||
case HAL_COMP_STATE_READY:
|
||||
hcomp->State = HAL_COMP_STATE_READY_LOCKED;
|
||||
break;
|
||||
default: /* HAL_COMP_STATE_BUSY */
|
||||
hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Set the lock bit corresponding to selected comparator */
|
||||
__HAL_COMP_LOCK(hcomp);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the output level (high or low) of the selected comparator.
|
||||
* The output level depends on the selected polarity.
|
||||
* If the polarity is not inverted:
|
||||
* - Comparator output is low when the input plus is at a lower
|
||||
* voltage than the input minus
|
||||
* - Comparator output is high when the input plus is at a higher
|
||||
* voltage than the input minus
|
||||
* If the polarity is inverted:
|
||||
* - Comparator output is high when the input plus is at a lower
|
||||
* voltage than the input minus
|
||||
* - Comparator output is low when the input plus is at a higher
|
||||
* voltage than the input minus
|
||||
* @param hcomp COMP handle
|
||||
* @retval Returns the selected comparator output level:
|
||||
* @arg COMP_OUTPUT_LEVEL_LOW
|
||||
* @arg COMP_OUTPUT_LEVEL_HIGH
|
||||
*
|
||||
*/
|
||||
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE)
|
||||
>> COMP_OUTPUT_LEVEL_BITOFFSET_POS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Comparator trigger callback.
|
||||
* @param hcomp COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcomp);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_COMP_TriggerCallback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time the status of the peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the COMP handle state.
|
||||
* @param hcomp COMP handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Check the COMP handle allocation */
|
||||
if(hcomp == NULL)
|
||||
{
|
||||
return HAL_COMP_STATE_RESET;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
/* Return HAL COMP handle state */
|
||||
return hcomp->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the COMP error code.
|
||||
* @param hcomp COMP handle
|
||||
* @retval COMP error code
|
||||
*/
|
||||
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
|
||||
|
||||
return hcomp->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,710 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_comp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of COMP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_COMP_H
|
||||
#define STM32WBxx_HAL_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
#include "stm32wbxx_ll_exti.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Types COMP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances
|
||||
(2 consecutive instances odd and even COMP<x> and COMP<x+1>).
|
||||
Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
|
||||
This parameter can be a value of @ref COMP_WindowMode */
|
||||
|
||||
uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed.
|
||||
Note: For the characteristics of comparator power modes
|
||||
(propagation delay and power consumption), refer to device datasheet.
|
||||
This parameter can be a value of @ref COMP_PowerMode */
|
||||
|
||||
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
|
||||
This parameter can be a value of @ref COMP_InputPlus */
|
||||
|
||||
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
|
||||
This parameter can be a value of @ref COMP_InputMinus */
|
||||
|
||||
uint32_t Hysteresis; /*!< Set comparator hysteresis mode of the input minus.
|
||||
This parameter can be a value of @ref COMP_Hysteresis */
|
||||
|
||||
uint32_t OutputPol; /*!< Set comparator output polarity.
|
||||
This parameter can be a value of @ref COMP_OutputPolarity */
|
||||
|
||||
uint32_t BlankingSrce; /*!< Set comparator blanking source.
|
||||
This parameter can be a value of @ref COMP_BlankingSrce */
|
||||
|
||||
uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
|
||||
This parameter can be a value of @ref COMP_EXTI_TriggerMode */
|
||||
|
||||
}COMP_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL COMP state machine: HAL COMP states definition
|
||||
*/
|
||||
#define COMP_STATE_BITFIELD_LOCK (0x10U)
|
||||
typedef enum
|
||||
{
|
||||
HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized */
|
||||
HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
|
||||
HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */
|
||||
HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
|
||||
HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
|
||||
HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
|
||||
}HAL_COMP_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief COMP Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __COMP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
{
|
||||
COMP_TypeDef *Instance; /*!< Register base address */
|
||||
COMP_InitTypeDef Init; /*!< COMP required parameters */
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
|
||||
__IO uint32_t ErrorCode; /*!< COMP error code */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */
|
||||
void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
} COMP_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL COMP Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */
|
||||
HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */
|
||||
HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */
|
||||
} HAL_COMP_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL COMP Callback pointer definition
|
||||
*/
|
||||
typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
|
||||
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Constants COMP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Error_Code COMP Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_COMP_ERROR_NONE (0x00UL) /*!< No error */
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_WindowMode COMP Window Mode
|
||||
* @{
|
||||
*/
|
||||
#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
|
||||
#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_PowerMode COMP power mode
|
||||
* @{
|
||||
*/
|
||||
/* Note: For the characteristics of comparator power modes */
|
||||
/* (propagation delay and power consumption), */
|
||||
/* refer to device datasheet. */
|
||||
#define COMP_POWERMODE_HIGHSPEED (0x00000000UL) /*!< High Speed */
|
||||
#define COMP_POWERMODE_MEDIUMSPEED (COMP_CSR_PWRMODE_0) /*!< Medium Speed */
|
||||
#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CSR_PWRMODE) /*!< Ultra-low power mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
|
||||
* @{
|
||||
*/
|
||||
#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PC5 for COMP1, pin PB4 for COMP2) */
|
||||
#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL_0) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB6 for COMP2) */
|
||||
#if defined(COMP_CSR_INPSEL_1)
|
||||
#define COMP_INPUT_PLUS_IO3 (COMP_CSR_INPSEL_1) /*!< Comparator input plus connected to IO3 (pin PA1 for COMP1, pin PA3 for COMP2) */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InputMinus COMP input minus (inverting input)
|
||||
* @{
|
||||
*/
|
||||
#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/4 VrefInt */
|
||||
#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */
|
||||
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
|
||||
#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */
|
||||
#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PB3 for COMP2) */
|
||||
#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PB7 for COMP2) */
|
||||
#define COMP_INPUT_MINUS_IO3 ( COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA0 for COMP1, pin PA2 for COMP2) */
|
||||
#define COMP_INPUT_MINUS_IO4 (COMP_CSR_INMESEL_1 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA4 for COMP1, pin PA4 for COMP2) */
|
||||
#define COMP_INPUT_MINUS_IO5 (COMP_CSR_INMESEL_1 | COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO5 (pin PA5 for COMP1, pin PA5 for COMP2) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Hysteresis COMP hysteresis
|
||||
* @{
|
||||
*/
|
||||
#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */
|
||||
#define COMP_HYSTERESIS_LOW ( COMP_CSR_HYST_0) /*!< Hysteresis level low */
|
||||
#define COMP_HYSTERESIS_MEDIUM (COMP_CSR_HYST_1 ) /*!< Hysteresis level medium */
|
||||
#define COMP_HYSTERESIS_HIGH (COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level high */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputPolarity COMP output Polarity
|
||||
* @{
|
||||
*/
|
||||
#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
|
||||
#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_BlankingSrce COMP blanking source
|
||||
* @{
|
||||
*/
|
||||
#define COMP_BLANKINGSRC_NONE (0x00000000UL) /*!<Comparator output without blanking */
|
||||
/* Note: Output blanking source common to all COMP instances */
|
||||
#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2) */
|
||||
#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CSR_BLANKING_1) /*!< Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputLevel COMP Output Level
|
||||
* @{
|
||||
*/
|
||||
/* Note: Comparator output level values are fixed to "0" and "1", */
|
||||
/* corresponding COMP register bit is managed by HAL function to match */
|
||||
/* with these values (independently of bit position in register). */
|
||||
|
||||
/* When output polarity is not inverted, comparator output is low when
|
||||
the input plus is at a lower voltage than the input minus */
|
||||
#define COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
|
||||
/* When output polarity is not inverted, comparator output is high when
|
||||
the input plus is at a higher voltage than the input minus */
|
||||
#define COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
|
||||
* @{
|
||||
*/
|
||||
#define COMP_TRIGGERMODE_NONE (0x00000000UL) /*!< Comparator output triggering no External Interrupt Line */
|
||||
#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
|
||||
#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
|
||||
#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
|
||||
#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
|
||||
#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
|
||||
#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Exported_Macros COMP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Handle_Management COMP Handle Management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset COMP handle state.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified comparator.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified comparator.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
|
||||
|
||||
/**
|
||||
* @brief Lock the specified comparator configuration.
|
||||
* @note Using this macro induce HAL COMP handle state machine being no
|
||||
* more in line with COMP instance state.
|
||||
* To keep HAL COMP handle state machine updated, it is recommended
|
||||
* to use function "HAL_COMP_Lock')".
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified comparator is locked.
|
||||
* @param __HANDLE__ COMP handle
|
||||
* @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
|
||||
*/
|
||||
#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Exti_Management COMP external interrupt line management
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
||||
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
||||
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP1 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP1 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP1 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP1 EXTI line flag is set.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP1 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line rising edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
||||
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
||||
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line in interrupt mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt on the COMP2 EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Enable the COMP2 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Disable the COMP2 EXTI line in event mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Check whether the COMP2 EXTI line flag is set.
|
||||
* @retval RESET or SET
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @brief Clear the COMP2 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup COMP_Private_Constants COMP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_ExtiLine COMP EXTI Lines
|
||||
* @{
|
||||
*/
|
||||
#define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_20) /*!< EXTI line 20 connected to COMP1 output */
|
||||
#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP2 output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_ExtiLine COMP EXTI Lines
|
||||
* @{
|
||||
*/
|
||||
#define COMP_EXTI_IT (0x00000001UL) /*!< EXTI line event with interruption */
|
||||
#define COMP_EXTI_EVENT (0x00000002UL) /*!< EXTI line event only (without interruption) */
|
||||
#define COMP_EXTI_RISING (0x00000010UL) /*!< EXTI line event on rising edge */
|
||||
#define COMP_EXTI_FALLING (0x00000020UL) /*!< EXTI line event on falling edge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup COMP_Private_Macros COMP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Get the specified EXTI line for a comparator instance.
|
||||
* @param __INSTANCE__ specifies the COMP instance.
|
||||
* @retval value of @ref COMP_ExtiLine
|
||||
*/
|
||||
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
|
||||
: COMP_EXTI_LINE_COMP2)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
#define IS_COMP_WINDOWMODE(__WINDOWMODE__) (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \
|
||||
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) )
|
||||
|
||||
#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \
|
||||
((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \
|
||||
((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) )
|
||||
|
||||
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
|
||||
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
|
||||
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3))
|
||||
|
||||
/* Note: On this STM32 serie, comparator input minus parameters are */
|
||||
/* the same on all COMP instances. */
|
||||
/* However, comparator instance kept as macro parameter for */
|
||||
/* compatibility with other STM32 families. */
|
||||
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4) || \
|
||||
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO5))
|
||||
|
||||
#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
|
||||
((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
|
||||
|
||||
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
|
||||
((__POL__) == COMP_OUTPUTPOL_INVERTED))
|
||||
|
||||
#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \
|
||||
( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) \
|
||||
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) \
|
||||
)
|
||||
|
||||
/* Note: Output blanking source common to all COMP instances */
|
||||
/* Macro kept for compatibility with other STM32 series */
|
||||
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
|
||||
(IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))
|
||||
|
||||
|
||||
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
|
||||
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
|
||||
|
||||
#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \
|
||||
((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup COMP_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions **********************************/
|
||||
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
|
||||
|
||||
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup COMP_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
|
||||
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
|
||||
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
/** @addtogroup COMP_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
|
||||
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
|
||||
/* Callback in interrupt mode */
|
||||
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions **************************************************/
|
||||
/** @addtogroup COMP_Exported_Functions_Group4
|
||||
* @{
|
||||
*/
|
||||
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
|
||||
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_COMP_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,354 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_CONF_H
|
||||
#define STM32WBxx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_COMP_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_CRC_MODULE_ENABLED
|
||||
#define HAL_CRYP_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_HSEM_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_IPCC_MODULE_ENABLED
|
||||
#define HAL_IRDA_MODULE_ENABLED
|
||||
#define HAL_IWDG_MODULE_ENABLED
|
||||
#define HAL_LCD_MODULE_ENABLED
|
||||
#define HAL_LPTIM_MODULE_ENABLED
|
||||
#define HAL_PCD_MODULE_ENABLED
|
||||
#define HAL_PKA_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_QSPI_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_RNG_MODULE_ENABLED
|
||||
#define HAL_RTC_MODULE_ENABLED
|
||||
#define HAL_SAI_MODULE_ENABLED
|
||||
#define HAL_SMARTCARD_MODULE_ENABLED
|
||||
#define HAL_SMBUS_MODULE_ENABLED
|
||||
#define HAL_SPI_MODULE_ENABLED
|
||||
#define HAL_TIM_MODULE_ENABLED
|
||||
#define HAL_TSC_MODULE_ENABLED
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
#define HAL_USART_MODULE_ENABLED
|
||||
#define HAL_WWDG_MODULE_ENABLED
|
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_COMP_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_PKA_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_TSC_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0u
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0u
|
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE (32000000UL) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal Multiple Speed oscillator (MSI) default value.
|
||||
* This value is the default MSI range value after Reset.
|
||||
*/
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI1) value.
|
||||
*/
|
||||
#if !defined (LSI1_VALUE)
|
||||
#define LSI1_VALUE (32000UL) /*!< LSI1 Typical Value in Hz*/
|
||||
#endif /* LSI1_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature.*/
|
||||
/**
|
||||
* @brief Internal Low Speed oscillator (LSI2) value.
|
||||
*/
|
||||
#if !defined (LSI2_VALUE)
|
||||
#define LSI2_VALUE (32000UL) /*!< LSI2 Typical Value in Hz*/
|
||||
#endif /* LSI2_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature.*/
|
||||
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal Multiple Speed oscillator (HSI48) default value.
|
||||
* This value is the default HSI48 range value after Reset.
|
||||
*/
|
||||
#if !defined (HSI48_VALUE)
|
||||
#define HSI48_VALUE (48000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI48_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief External clock source for SAI1 peripheral
|
||||
* This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
|
||||
* frequency.
|
||||
*/
|
||||
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
|
||||
#define EXTERNAL_SAI1_CLOCK_VALUE (48000UL) /*!< Value of the SAI1 External clock source in Hz*/
|
||||
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */
|
||||
#define USE_RTOS 0
|
||||
#define PREFETCH_ENABLE 0
|
||||
#define INSTRUCTION_CACHE_ENABLE 1
|
||||
#define DATA_CACHE_ENABLE 1
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
|
||||
* Activated: CRC code is present inside driver
|
||||
* Deactivated: CRC code cleaned from driver
|
||||
*/
|
||||
|
||||
#define USE_SPI_CRC 1U
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_comp.h"
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HSEM_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_hsem.h"
|
||||
#endif /* HAL_HSEM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IPCC_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_ipcc.h"
|
||||
#endif /* HAL_IPCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LCD_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_lcd.h"
|
||||
#endif /* HAL_LCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PKA_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_pka.h"
|
||||
#endif /* HAL_PKA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TSC_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_tsc.h"
|
||||
#endif /* HAL_TSC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32wbxx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,482 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @brief CORTEX HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX:
|
||||
* + Initialization and Configuration functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
*** How to configure Interrupts using CORTEX HAL driver ***
|
||||
===========================================================
|
||||
[..]
|
||||
This section provides functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex M0+ exceptions are managed by CMSIS functions.
|
||||
(#) Enable and Configure the priority of the selected IRQ Channels.
|
||||
The priority can be 0..3.
|
||||
|
||||
-@- Lower priority values gives higher priority.
|
||||
-@- Priority Order:
|
||||
(#@) Lowest priority.
|
||||
(#@) Lowest hardware priority (IRQn position).
|
||||
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
|
||||
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
|
||||
|
||||
-@- Negative value of IRQn_Type are not allowed.
|
||||
|
||||
*** How to configure Systick using CORTEX HAL driver ***
|
||||
========================================================
|
||||
[..]
|
||||
Setup SysTick Timer for time base.
|
||||
|
||||
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
|
||||
is a CMSIS function that:
|
||||
(++) Configures the SysTick Reload register with value passed as function parameter.
|
||||
(++) Configures the SysTick IRQ priority to the lowest value (0x03).
|
||||
(++) Resets the SysTick Counter register.
|
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
|
||||
(++) Enables the SysTick Interrupt.
|
||||
(++) Starts the SysTick Counter.
|
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
|
||||
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
|
||||
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
|
||||
inside the stm32wbxx_hal_cortex.h file.
|
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
|
||||
|
||||
(+) To adjust the SysTick time base, use the following formula:
|
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
|
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
|
||||
(++) Reload Value should not exceed 0xFFFFFF
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group1
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
|
||||
Systick functionalities
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the priority grouping field (pre-emption priority and subpriority)
|
||||
* using the required unlock sequence.
|
||||
* @param PriorityGroup The priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
|
||||
* 1 bit for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
|
||||
* 0 bit for subpriority
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
||||
NVIC_SetPriorityGrouping(PriorityGroup);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the priority of an interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
|
||||
* @param PreemptPriority The pre-emption priority for the IRQn channel.
|
||||
* This parameter can be a value between 0 and 15
|
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority the subpriority level for the IRQ channel.
|
||||
* This parameter can be a value between 0 and 15
|
||||
* A lower priority value indicates a higher priority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t prioritygroup;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||||
|
||||
prioritygroup = NVIC_GetPriorityGrouping();
|
||||
|
||||
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable a device specific interrupt in the NVIC interrupt controller.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Enable interrupt */
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a device specific interrupt in the NVIC interrupt controller.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Disable interrupt */
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiate a system reset request to reset the MCU.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SystemReset(void)
|
||||
{
|
||||
/* System Reset */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick):
|
||||
* Counter is in free running mode to generate periodic interrupts.
|
||||
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
||||
* @retval status: - 0 Function succeeded.
|
||||
* - 1 Function failed.
|
||||
*/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||||
{
|
||||
return SysTick_Config(TicksNumb);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CORTEX_Exported_Functions_Group2
|
||||
* @brief Cortex control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CORTEX
|
||||
(NVIC, SYSTICK, MPU) functionalities.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the priority grouping field from the NVIC Interrupt Controller.
|
||||
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void)
|
||||
{
|
||||
/* Get the PRIGROUP[10:8] field value */
|
||||
return NVIC_GetPriorityGrouping();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the priority of an interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
|
||||
* @param PriorityGroup the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
|
||||
* 1 bit for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
|
||||
* 0 bit for subpriority
|
||||
* @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
|
||||
* @param pSubPriority Pointer on the Subpriority value (starting from 0).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
/* Get priority for Cortex-M system or device specific interrupts */
|
||||
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set Pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Set interrupt pending */
|
||||
NVIC_SetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get Pending Interrupt (read the pending register in the NVIC
|
||||
* and return the pending bit for the specified interrupt).
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Return 1 if pending else 0 */
|
||||
return NVIC_GetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number.
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32wbxxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Clear pending interrupt */
|
||||
NVIC_ClearPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the SysTick clock source.
|
||||
* @param CLKSource specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
|
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle SYSTICK interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_IRQHandler(void)
|
||||
{
|
||||
HAL_SYSTICK_Callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SYSTICK callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SYSTICK_Callback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/**
|
||||
* @brief Disables the MPU
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_Disable(void)
|
||||
{
|
||||
/* Make sure outstanding transfers are done */
|
||||
__DMB();
|
||||
|
||||
/* Disable fault exceptions */
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
|
||||
/* Disable the MPU and clear the control register*/
|
||||
MPU->CTRL = 0U;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the MPU.
|
||||
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
|
||||
* NMI, FAULTMASK and privileged access to the default memory
|
||||
* This parameter can be one of the following values:
|
||||
* @arg MPU_HFNMI_PRIVDEF_NONE
|
||||
* @arg MPU_HARDFAULT_NMI
|
||||
* @arg MPU_PRIVILEGED_DEFAULT
|
||||
* @arg MPU_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
/* Enable the MPU */
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
|
||||
/* Enable fault exceptions */
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
|
||||
/* Ensure MPU setting take effects */
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize and configure the Region and the memory to be protected.
|
||||
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
|
||||
* the initialization and configuration information.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
|
||||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = MPU_Init->Number;
|
||||
|
||||
if ((MPU_Init->Enable) != 0U)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||||
|
||||
MPU->RBAR = MPU_Init->BaseAddress;
|
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
MPU->RBAR = 0x00U;
|
||||
MPU->RASR = 0x00U;
|
||||
}
|
||||
}
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,420 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_CORTEX_H
|
||||
#define STM32WBxx_HAL_CORTEX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
#include "stm32wb55xx.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @brief CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
|
||||
* @brief MPU Region initialization structure
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Enable; /*!< Specifies the status of the region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
|
||||
uint8_t Number; /*!< Specifies the number of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
|
||||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect.
|
||||
*/
|
||||
uint8_t Size; /*!< Specifies the size of the region to protect.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
|
||||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
uint8_t TypeExtField; /*!< Specifies the TEX field level.
|
||||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
|
||||
uint8_t AccessPermission; /*!< Specifies the region access permission type.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
|
||||
uint8_t DisableExec; /*!< Specifies the instruction access status.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
|
||||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
|
||||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
|
||||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
|
||||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
|
||||
}MPU_Region_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
|
||||
* @{
|
||||
*/
|
||||
#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bit for pre-emption priority,
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bit for pre-emption priority,
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority,
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority,
|
||||
1 bit for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority,
|
||||
0 bit for subpriority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
|
||||
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
|
||||
* @{
|
||||
*/
|
||||
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
|
||||
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
|
||||
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
|
||||
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_ENABLE ((uint8_t)0x01)
|
||||
#define MPU_REGION_DISABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
|
||||
* @{
|
||||
*/
|
||||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
|
||||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
|
||||
* @{
|
||||
*/
|
||||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
|
||||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
|
||||
* @{
|
||||
*/
|
||||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
|
||||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
|
||||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
|
||||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
|
||||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
|
||||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
|
||||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
|
||||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
|
||||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
|
||||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
|
||||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
|
||||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
|
||||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
|
||||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
|
||||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
|
||||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
|
||||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
|
||||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
|
||||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
|
||||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
|
||||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
|
||||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
|
||||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
|
||||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
|
||||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
|
||||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
|
||||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
|
||||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
|
||||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
|
||||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
|
||||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
|
||||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
|
||||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
|
||||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
|
||||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
|
||||
* @{
|
||||
*/
|
||||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
|
||||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
|
||||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
|
||||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
|
||||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
|
||||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
|
||||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
|
||||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and Configuration functions *****************************/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SystemReset(void);
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions *************************************************/
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
|
||||
void HAL_SYSTICK_IRQHandler(void);
|
||||
void HAL_SYSTICK_Callback(void);
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_1) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_2) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_3) || \
|
||||
((GROUP) == NVIC_PRIORITYGROUP_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
|
||||
|
||||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
|
||||
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
|
||||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
|
||||
((STATE) == MPU_REGION_DISABLE))
|
||||
|
||||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
|
||||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
|
||||
|
||||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
|
||||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
|
||||
|
||||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
|
||||
((TYPE) == MPU_TEX_LEVEL1) || \
|
||||
((TYPE) == MPU_TEX_LEVEL2))
|
||||
|
||||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
|
||||
((TYPE) == MPU_REGION_FULL_ACCESS) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO) || \
|
||||
((TYPE) == MPU_REGION_PRIV_RO_URO))
|
||||
|
||||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER1) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER2) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER3) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER4) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER5) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER6) || \
|
||||
((NUMBER) == MPU_REGION_NUMBER7))
|
||||
|
||||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512B) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512KB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_8MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_16MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_32MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_64MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_128MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_256MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_512MB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_1GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_2GB) || \
|
||||
((SIZE) == MPU_REGION_SIZE_4GB))
|
||||
|
||||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_CORTEX_H */
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,518 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_crc.c
|
||||
* @author MCD Application Team
|
||||
* @brief CRC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
|
||||
(+) Initialize CRC calculator
|
||||
(++) specify generating polynomial (peripheral default or non-default one)
|
||||
(++) specify initialization value (peripheral default or non-default one)
|
||||
(++) specify input data format
|
||||
(++) specify input or output data inversion mode if any
|
||||
(+) Use HAL_CRC_Accumulate() function to compute the CRC value of the
|
||||
input data buffer starting with the previously computed CRC as
|
||||
initialization value
|
||||
(+) Use HAL_CRC_Calculate() function to compute the CRC value of the
|
||||
input data buffer starting with the defined initialization value
|
||||
(default or non-default) to initiate CRC calculation
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC CRC
|
||||
* @brief CRC HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Functions CRC Private Functions
|
||||
* @{
|
||||
*/
|
||||
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
|
||||
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the CRC according to the specified parameters
|
||||
in the CRC_InitTypeDef and create the associated handle
|
||||
(+) DeInitialize the CRC peripheral
|
||||
(+) Initialize the CRC MSP (MCU Specific Package)
|
||||
(+) DeInitialize the CRC MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the CRC according to the specified
|
||||
* parameters in the CRC_InitTypeDef and create the associated handle.
|
||||
* @param hcrc CRC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if (hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
if (hcrc->State == HAL_CRC_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hcrc->Lock = HAL_UNLOCKED;
|
||||
/* Init the low level hardware */
|
||||
HAL_CRC_MspInit(hcrc);
|
||||
}
|
||||
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* check whether or not non-default generating polynomial has been
|
||||
* picked up by user */
|
||||
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
|
||||
if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
|
||||
{
|
||||
/* initialize peripheral with default generating polynomial */
|
||||
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* initialize CRC peripheral with generating polynomial defined by user */
|
||||
if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* check whether or not non-default CRC initial value has been
|
||||
* picked up by user */
|
||||
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
|
||||
if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
|
||||
{
|
||||
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
|
||||
}
|
||||
else
|
||||
{
|
||||
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
|
||||
}
|
||||
|
||||
|
||||
/* set input data inversion mode */
|
||||
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
|
||||
|
||||
/* set output data inversion mode */
|
||||
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
|
||||
|
||||
/* makes sure the input data format (bytes, halfwords or words stream)
|
||||
* is properly specified by user */
|
||||
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the CRC peripheral.
|
||||
* @param hcrc CRC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Check the CRC handle allocation */
|
||||
if (hcrc == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
|
||||
|
||||
/* Check the CRC peripheral state */
|
||||
if (hcrc->State == HAL_CRC_STATE_BUSY)
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Reset CRC calculation unit */
|
||||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
/* Reset IDR register content */
|
||||
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_CRC_MspDeInit(hcrc);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_RESET;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcrc);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the CRC MSP.
|
||||
* @param hcrc CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcrc);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the CRC MSP.
|
||||
* @param hcrc CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hcrc);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_CRC_MspDeInit can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
using combination of the previous CRC value and the new one.
|
||||
|
||||
[..] or
|
||||
|
||||
(+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
independently of the previous CRC value.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
* starting with the previously computed CRC as initialization value.
|
||||
* @param hcrc CRC handle
|
||||
* @param pBuffer pointer to the input data buffer, exact input data format is
|
||||
* provided by hcrc->InputDataFormat.
|
||||
* @param BufferLength input data buffer length (number of bytes if pBuffer
|
||||
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
|
||||
* number of words if pBuffer type is * uint32_t).
|
||||
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
|
||||
* Input buffer pointers with other types simply need to be cast in uint32_t
|
||||
* and the API will internally adjust its input data processing based on the
|
||||
* handle field hcrc->InputDataFormat.
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index; /* CRC input data buffer index */
|
||||
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
switch (hcrc->InputDataFormat)
|
||||
{
|
||||
case CRC_INPUTDATA_FORMAT_WORDS:
|
||||
/* Enter Data to the CRC calculator */
|
||||
for (index = 0U; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
temp = hcrc->Instance->DR;
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_BYTES:
|
||||
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_HALFWORDS:
|
||||
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
|
||||
* starting with hcrc->Instance->INIT as initialization value.
|
||||
* @param hcrc CRC handle
|
||||
* @param pBuffer pointer to the input data buffer, exact input data format is
|
||||
* provided by hcrc->InputDataFormat.
|
||||
* @param BufferLength input data buffer length (number of bytes if pBuffer
|
||||
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
|
||||
* number of words if pBuffer type is * uint32_t).
|
||||
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
|
||||
* Input buffer pointers with other types simply need to be cast in uint32_t
|
||||
* and the API will internally adjust its input data processing based on the
|
||||
* handle field hcrc->InputDataFormat.
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index; /* CRC input data buffer index */
|
||||
uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
|
||||
* written in hcrc->Instance->DR) */
|
||||
__HAL_CRC_DR_RESET(hcrc);
|
||||
|
||||
switch (hcrc->InputDataFormat)
|
||||
{
|
||||
case CRC_INPUTDATA_FORMAT_WORDS:
|
||||
/* Enter 32-bit input data to the CRC calculator */
|
||||
for (index = 0U; index < BufferLength; index++)
|
||||
{
|
||||
hcrc->Instance->DR = pBuffer[index];
|
||||
}
|
||||
temp = hcrc->Instance->DR;
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_BYTES:
|
||||
/* Specific 8-bit input data handling */
|
||||
temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength);
|
||||
break;
|
||||
|
||||
case CRC_INPUTDATA_FORMAT_HALFWORDS:
|
||||
/* Specific 16-bit input data handling */
|
||||
temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return temp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @brief Peripheral State functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the CRC handle state.
|
||||
* @param hcrc CRC handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
|
||||
{
|
||||
/* Return CRC handle state */
|
||||
return hcrc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enter 8-bit input data to the CRC calculator.
|
||||
* Specific data handling to optimize processing time.
|
||||
* @param hcrc CRC handle
|
||||
* @param pBuffer pointer to the input data buffer
|
||||
* @param BufferLength input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t i; /* input data buffer index */
|
||||
uint16_t data;
|
||||
__IO uint16_t *pReg;
|
||||
|
||||
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
|
||||
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
|
||||
* handling by the peripheral */
|
||||
for (i = 0U; i < (BufferLength / 4U); i++)
|
||||
{
|
||||
hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \
|
||||
((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \
|
||||
((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \
|
||||
(uint32_t)pBuffer[(4U * i) + 3U];
|
||||
}
|
||||
/* last bytes specific handling */
|
||||
if ((BufferLength % 4U) != 0U)
|
||||
{
|
||||
if ((BufferLength % 4U) == 1U)
|
||||
{
|
||||
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */
|
||||
}
|
||||
if ((BufferLength % 4U) == 2U)
|
||||
{
|
||||
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
|
||||
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
|
||||
*pReg = data;
|
||||
}
|
||||
if ((BufferLength % 4U) == 3U)
|
||||
{
|
||||
data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U];
|
||||
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
|
||||
*pReg = data;
|
||||
|
||||
*(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enter 16-bit input data to the CRC calculator.
|
||||
* Specific data handling to optimize processing time.
|
||||
* @param hcrc CRC handle
|
||||
* @param pBuffer pointer to the input data buffer
|
||||
* @param BufferLength input data buffer length
|
||||
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
|
||||
*/
|
||||
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t i; /* input data buffer index */
|
||||
__IO uint16_t *pReg;
|
||||
|
||||
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
|
||||
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
|
||||
* a correct type handling by the peripheral */
|
||||
for (i = 0U; i < (BufferLength / 2U); i++)
|
||||
{
|
||||
hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U];
|
||||
}
|
||||
if ((BufferLength % 2U) != 0U)
|
||||
{
|
||||
pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */
|
||||
*pReg = pBuffer[2U * i];
|
||||
}
|
||||
|
||||
/* Return the CRC computed value */
|
||||
return hcrc->Instance->DR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,344 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_CRC_H
|
||||
#define STM32WBxx_HAL_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Types CRC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRC HAL State Structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
|
||||
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
|
||||
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
|
||||
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
|
||||
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
|
||||
} HAL_CRC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
|
||||
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
|
||||
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
|
||||
In that case, there is no need to set GeneratingPolynomial field.
|
||||
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
|
||||
|
||||
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
|
||||
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
|
||||
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
|
||||
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
|
||||
|
||||
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
|
||||
respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
|
||||
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
|
||||
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE. */
|
||||
|
||||
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
|
||||
Value can be either one of
|
||||
@arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
|
||||
@arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
|
||||
|
||||
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
|
||||
is set to DEFAULT_INIT_VALUE_ENABLE. */
|
||||
|
||||
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
|
||||
Can be either one of the following values
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
|
||||
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
|
||||
|
||||
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
|
||||
Can be either
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
|
||||
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
|
||||
} CRC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief CRC Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CRC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRC Locking object */
|
||||
|
||||
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
|
||||
|
||||
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
|
||||
Can be either
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
|
||||
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bit data)
|
||||
|
||||
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
|
||||
must occur if InputBufferFormat is not one of the three values listed above */
|
||||
} CRC_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Constants CRC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
|
||||
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
|
||||
* @{
|
||||
*/
|
||||
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
|
||||
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
|
||||
* @{
|
||||
*/
|
||||
#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
|
||||
#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
|
||||
#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
|
||||
* @{
|
||||
*/
|
||||
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
|
||||
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
|
||||
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
|
||||
* the CRC APIs to provide a correct result */
|
||||
#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
|
||||
#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
|
||||
#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
|
||||
#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_Aliases CRC API aliases
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Macros CRC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRC handle state.
|
||||
* @param __HANDLE__ CRC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Reset CRC Data Register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
|
||||
|
||||
/**
|
||||
* @brief Set CRC INIT non-default value
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __INIT__ 32-bit initial value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
|
||||
|
||||
/**
|
||||
* @brief Store data in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __VALUE__ Value to be stored in the ID register
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
|
||||
|
||||
/**
|
||||
* @brief Return the data stored in the Independent Data (ID) register.
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
|
||||
* @retval Value of the ID register
|
||||
*/
|
||||
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Private_Macros CRC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
|
||||
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
|
||||
|
||||
|
||||
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
|
||||
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
|
||||
|
||||
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_16B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_8B) || \
|
||||
((LENGTH) == CRC_POLYLENGTH_7B))
|
||||
|
||||
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
|
||||
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRC HAL Extended module */
|
||||
#include "stm32wbxx_hal_crc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRC_Exported_Functions CRC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
|
||||
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
|
||||
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_CRC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_crc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended CRC HAL module driver.
|
||||
* This file provides firmware functions to manage the extended
|
||||
* functionalities of the CRC peripheral.
|
||||
*
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
(+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
|
||||
(+) Configure Input or Output data inversion
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx CRCEx
|
||||
* @brief CRC Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions
|
||||
* @brief Extended Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the generating polynomial
|
||||
(+) Configure the input data inversion
|
||||
(+) Configure the output data inversion
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialize the CRC polynomial if different from default one.
|
||||
* @param hcrc CRC handle
|
||||
* @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
|
||||
* This parameter is written in normal representation, e.g.
|
||||
* @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
|
||||
* @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
|
||||
* @param PolyLength CRC polynomial length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7)
|
||||
* @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8)
|
||||
* @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16)
|
||||
* @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32)
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_POL_LENGTH(PolyLength));
|
||||
|
||||
/* check polynomial definition vs polynomial size:
|
||||
* polynomial length must be aligned with polynomial
|
||||
* definition. HAL_ERROR is reported if Pol degree is
|
||||
* larger than that indicated by PolyLength.
|
||||
* Look for MSB position: msb will contain the degree of
|
||||
* the second to the largest polynomial member. E.g., for
|
||||
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
|
||||
while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
|
||||
{
|
||||
}
|
||||
|
||||
switch (PolyLength)
|
||||
{
|
||||
case CRC_POLYLENGTH_7B:
|
||||
if (msb >= HAL_CRC_LENGTH_7B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_8B:
|
||||
if (msb >= HAL_CRC_LENGTH_8B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
case CRC_POLYLENGTH_16B:
|
||||
if (msb >= HAL_CRC_LENGTH_16B)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
break;
|
||||
|
||||
case CRC_POLYLENGTH_32B:
|
||||
/* no polynomial definition vs. polynomial length issue possible */
|
||||
break;
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* set generating polynomial */
|
||||
WRITE_REG(hcrc->Instance->POL, Pol);
|
||||
|
||||
/* set generating polynomial size */
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
|
||||
}
|
||||
/* Return function status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Reverse Input data mode.
|
||||
* @param hcrc CRC handle
|
||||
* @param InputReverseMode Input Data inversion mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value)
|
||||
* @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal
|
||||
* @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal
|
||||
* @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* set input data inversion mode */
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the Reverse Output data mode.
|
||||
* @param hcrc CRC handle
|
||||
* @param OutputReverseMode Output Data inversion mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value)
|
||||
* @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_BUSY;
|
||||
|
||||
/* set output data inversion mode */
|
||||
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
|
||||
|
||||
/* Change CRC peripheral state */
|
||||
hcrc->State = HAL_CRC_STATE_READY;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_crc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRC HAL extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_CRC_EX_H
|
||||
#define STM32WBxx_HAL_CRC_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
|
||||
#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
|
||||
* @{
|
||||
*/
|
||||
#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
|
||||
#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set CRC output reversal
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
|
||||
|
||||
/**
|
||||
* @brief Unset CRC output reversal
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
|
||||
|
||||
/**
|
||||
* @brief Set CRC non-default polynomial
|
||||
* @param __HANDLE__ CRC handle
|
||||
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
|
||||
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
|
||||
|
||||
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
|
||||
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup CRCEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRCEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
|
||||
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_CRC_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,627 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_cryp.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRYP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_CRYP_H
|
||||
#define STM32WBxx_HAL_CRYP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup CRYP CRYP
|
||||
* @brief CRYP HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRYP_Exported_Types CRYP Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief CRYP Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
|
||||
This parameter can be a value of @ref CRYP_Data_Type */
|
||||
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
|
||||
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
|
||||
uint32_t *pKey; /*!< The key used for encryption/decryption */
|
||||
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
|
||||
counter in CTR mode */
|
||||
uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
|
||||
AES Algorithm ECB/CBC/CTR/GCM or CCM
|
||||
This parameter can be a value of @ref CRYP_Algorithm_Mode */
|
||||
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
|
||||
GCM : also known as Additional Authentication Data
|
||||
CCM : named B1 composed of the associated data length and Associated Data. */
|
||||
uint32_t HeaderSize; /*!< The size of header buffer in word */
|
||||
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
|
||||
uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
|
||||
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
|
||||
Vector only once and to skip configuration for consecutive processings.
|
||||
This parameter can be a value of @ref CRYP_Configuration_Skip */
|
||||
|
||||
} CRYP_ConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief CRYP State Structure definition
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
|
||||
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
|
||||
HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP BUSY, internal processing is ongoing */
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
HAL_CRYP_STATE_SUSPENDED = 0x03U, /*!< CRYP suspended */
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
} HAL_CRYP_STATETypeDef;
|
||||
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
/**
|
||||
* @brief HAL CRYP mode suspend definitions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */
|
||||
HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */
|
||||
}HAL_SuspendTypeDef;
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
|
||||
/**
|
||||
* @brief CRYP handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __CRYP_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
{
|
||||
AES_TypeDef *Instance; /*!< AES Register base address */
|
||||
|
||||
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
|
||||
|
||||
FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allow to bypass or not key write-up before decryption.
|
||||
This parameter can be a value of ENABLE/DISABLE */
|
||||
|
||||
uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
||||
|
||||
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
|
||||
|
||||
__IO uint16_t CrypHeaderCount; /*!< Counter of header data */
|
||||
|
||||
__IO uint16_t CrypInCount; /*!< Counter of input data */
|
||||
|
||||
__IO uint16_t CrypOutCount; /*!< Counter of output data */
|
||||
|
||||
uint16_t Size; /*!< length of input data in words */
|
||||
|
||||
uint32_t Phase; /*!< CRYP peripheral phase */
|
||||
|
||||
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< CRYP locking object */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
|
||||
|
||||
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
|
||||
configuration can be skipped */
|
||||
|
||||
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
|
||||
for a single signature computation after several
|
||||
messages processing */
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
|
||||
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
|
||||
void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
|
||||
|
||||
void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
|
||||
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
|
||||
__IO HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
|
||||
|
||||
CRYP_ConfigTypeDef Init_saved; /*!< copy of CRYP required parameters when processing is suspended */
|
||||
|
||||
uint32_t *pCrypInBuffPtr_saved; /*!< copy of CRYP input pointer when processing is suspended */
|
||||
|
||||
uint32_t *pCrypOutBuffPtr_saved; /*!< copy of CRYP output pointer when processing is suspended */
|
||||
|
||||
uint32_t CrypInCount_saved; /*!< copy of CRYP input data counter when processing is suspended */
|
||||
|
||||
uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing is suspended */
|
||||
|
||||
uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing is suspended */
|
||||
|
||||
__IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing is suspended */
|
||||
|
||||
uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */
|
||||
|
||||
uint32_t SUSPxR_saved[8]; /*!< copy of suspension registers */
|
||||
|
||||
uint32_t CR_saved; /*!< copy of CRYP control register when processing is suspended*/
|
||||
|
||||
uint32_t Key_saved[8]; /*!< copy of key registers */
|
||||
|
||||
uint32_t Size_saved; /*!< copy of input buffer size */
|
||||
|
||||
uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */
|
||||
|
||||
uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */
|
||||
|
||||
FunctionalState AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
|
||||
|
||||
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
|
||||
|
||||
} CRYP_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
|
||||
* @brief HAL CRYP Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_CRYP_MSPINIT_CB_ID = 0x00U, /*!< CRYP MspInit callback ID */
|
||||
HAL_CRYP_MSPDEINIT_CB_ID = 0x01U, /*!< CRYP MspDeInit callback ID */
|
||||
HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Input FIFO transfer completed callback ID */
|
||||
HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x03U, /*!< CRYP Output FIFO transfer completed callback ID */
|
||||
HAL_CRYP_ERROR_CB_ID = 0x04U, /*!< CRYP Error callback ID */
|
||||
} HAL_CRYP_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
|
||||
* @brief HAL CRYP Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Error_Definition CRYP Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
|
||||
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
|
||||
#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
|
||||
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
|
||||
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
|
||||
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
|
||||
#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
|
||||
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
|
||||
#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
|
||||
#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
|
||||
#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
|
||||
#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Key_Size CRYP Key Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
|
||||
#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Data_Type CRYP Data Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_DATATYPE_32B 0x00000000U /*!< 32-bit data type (no swapping) */
|
||||
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
|
||||
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
|
||||
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Interrupt CRYP Interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
|
||||
#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
|
||||
#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
|
||||
#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
|
||||
#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Flags CRYP Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* status flags */
|
||||
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
|
||||
#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */
|
||||
#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */
|
||||
#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */
|
||||
/* clearing flags */
|
||||
#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */
|
||||
#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
|
||||
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset CRYP handle state
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
|
||||
(__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL;\
|
||||
(__HANDLE__)->MspDeInitCallback = NULL;\
|
||||
}while(0U)
|
||||
#else
|
||||
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the CRYP peripheral.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
|
||||
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
|
||||
|
||||
|
||||
/** @brief Check whether the specified CRYP status flag is set or not.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
|
||||
* @arg @ref CRYP_IT_WRERR Write Error
|
||||
* @arg @ref CRYP_IT_RDERR Read Error
|
||||
* @arg @ref CRYP_IT_CCF Computation Complete
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
|
||||
* or a key preparation (for AES decryption).
|
||||
* @arg CRYP_FLAG_IFEM: Input FIFO is empty
|
||||
* @arg CRYP_FLAG_IFNF: Input FIFO is not full
|
||||
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
|
||||
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
|
||||
* @arg CRYP_FLAG_OFFU: Output FIFO is full
|
||||
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
|
||||
* @retval The state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define CRYP_FLAG_MASK 0x0000001FU
|
||||
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the CRYP pending status flag.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
|
||||
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ CRYP interrupt source to check
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* @retval State of interruption (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified CRYP interrupt is set or not.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt to check.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_WRERR Write Error
|
||||
* @arg @ref CRYP_IT_RDERR Read Error
|
||||
* @arg @ref CRYP_IT_CCF Computation Complete
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status
|
||||
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
|
||||
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Enable the CRYP interrupt.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ CRYP Interrupt.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
|
||||
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the CRYP interrupt.
|
||||
* @param __HANDLE__ specifies the CRYP handle.
|
||||
* @param __INTERRUPT__ CRYP Interrupt.
|
||||
* This parameter can be one of the following values for TinyAES:
|
||||
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
|
||||
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
|
||||
* This parameter can be one of the following values for CRYP:
|
||||
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
|
||||
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include CRYP HAL Extended module */
|
||||
#include "stm32wbxx_hal_cryp_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
||||
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
|
||||
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
|
||||
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
|
||||
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
|
||||
void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
|
||||
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* encryption/decryption ***********************************/
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup CRYP_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Interrupt Handler functions **********************************************/
|
||||
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
|
||||
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
|
||||
uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Macros CRYP Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
|
||||
((ALGORITHM) == CRYP_AES_CBC) || \
|
||||
((ALGORITHM) == CRYP_AES_CTR) || \
|
||||
((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
|
||||
((ALGORITHM) == CRYP_AES_CCM))
|
||||
|
||||
|
||||
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
|
||||
((KEYSIZE) == CRYP_KEYSIZE_256B))
|
||||
|
||||
#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_16B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_8B) || \
|
||||
((DATATYPE) == CRYP_DATATYPE_1B))
|
||||
|
||||
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
|
||||
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Constants CRYP Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Defines CRYP Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Variables CRYP Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYP_Private_Functions CRYP Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_CRYP_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,382 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_cryp_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief CRYPEx HAL module driver.
|
||||
* This file provides firmware functions to manage the extended
|
||||
* functionalities of the Cryptography (CRYP) peripheral.
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup CRYPEx_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
|
||||
#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
|
||||
#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
|
||||
#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
|
||||
|
||||
#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
|
||||
#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions */
|
||||
#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */
|
||||
#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions */
|
||||
|
||||
#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */
|
||||
#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */
|
||||
|
||||
/* CTR0 information to use in CCM algorithm */
|
||||
#define CRYP_CCM_CTR0_0 0x07FFFFFFU
|
||||
#define CRYP_CCM_CTR0_3 0xFFFFFF00U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions---------------------------------------------------------*/
|
||||
/** @addtogroup CRYPEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions
|
||||
* @brief Extended processing functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Extended AES processing functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to generate the authentication
|
||||
TAG in Polling mode
|
||||
(#)HAL_CRYPEx_AESGCM_GenerateAuthTAG
|
||||
(#)HAL_CRYPEx_AESCCM_GenerateAuthTAG
|
||||
they should be used after Encrypt/Decrypt operation.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief generate the GCM authentication TAG.
|
||||
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
|
||||
* the configuration information for CRYP module
|
||||
* @param AuthTag Pointer to the authentication buffer
|
||||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */
|
||||
uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
|
||||
uint32_t tagaddr = (uint32_t)AuthTag;
|
||||
|
||||
if (hcryp->State == HAL_CRYP_STATE_READY)
|
||||
{
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcryp);
|
||||
|
||||
/* Change the CRYP peripheral state */
|
||||
hcryp->State = HAL_CRYP_STATE_BUSY;
|
||||
|
||||
/* Check if initialization phase has already been performed */
|
||||
if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
|
||||
{
|
||||
/* Change the CRYP phase */
|
||||
hcryp->Phase = CRYPEx_PHASE_FINAL;
|
||||
}
|
||||
else /* Initialization phase has not been performed*/
|
||||
{
|
||||
/* Disable the Peripheral */
|
||||
__HAL_CRYP_DISABLE(hcryp);
|
||||
|
||||
/* Sequence error code field */
|
||||
hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
|
||||
|
||||
/* Change the CRYP peripheral state */
|
||||
hcryp->State = HAL_CRYP_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcryp);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Select final phase */
|
||||
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
|
||||
|
||||
/* Set the encrypt operating mode*/
|
||||
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
|
||||
|
||||
/*TinyAES peripheral from V3.1.1 : data has to be inserted normally (no swapping)*/
|
||||
/* Write into the AES_DINR register the number of bits in header (64 bits)
|
||||
followed by the number of bits in the payload */
|
||||
|
||||
hcryp->Instance->DINR = 0U;
|
||||
hcryp->Instance->DINR = (uint32_t)(headerlength);
|
||||
hcryp->Instance->DINR = 0U;
|
||||
hcryp->Instance->DINR = (uint32_t)(inputlength);
|
||||
|
||||
/* Wait for CCF flag to be raised */
|
||||
tickstart = HAL_GetTick();
|
||||
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if (((HAL_GetTick() - tickstart) > Timeout)||(Timeout == 0U))
|
||||
{
|
||||
/* Disable the CRYP peripheral clock */
|
||||
__HAL_CRYP_DISABLE(hcryp);
|
||||
|
||||
/* Change state */
|
||||
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
|
||||
hcryp->State = HAL_CRYP_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcryp);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Read the authentication TAG in the output FIFO */
|
||||
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
|
||||
tagaddr += 4U;
|
||||
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
|
||||
tagaddr += 4U;
|
||||
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
|
||||
tagaddr += 4U;
|
||||
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
|
||||
|
||||
/* Clear CCF flag */
|
||||
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_CRYP_DISABLE(hcryp);
|
||||
|
||||
/* Change the CRYP peripheral state */
|
||||
hcryp->State = HAL_CRYP_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcryp);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Busy error code field */
|
||||
hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief AES CCM Authentication TAG generation.
|
||||
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
|
||||
* the configuration information for CRYP module
|
||||
* @param AuthTag Pointer to the authentication buffer
|
||||
* @param Timeout Timeout duration
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tagaddr = (uint32_t)AuthTag;
|
||||
uint32_t tickstart;
|
||||
|
||||
if (hcryp->State == HAL_CRYP_STATE_READY)
|
||||
{
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hcryp);
|
||||
|
||||
/* Disable interrupts in case they were kept enabled to proceed
|
||||
a single message in several iterations */
|
||||
__HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
|
||||
|
||||
/* Change the CRYP peripheral state */
|
||||
hcryp->State = HAL_CRYP_STATE_BUSY;
|
||||
|
||||
/* Check if initialization phase has already been performed */
|
||||
if (hcryp->Phase == CRYPEx_PHASE_PROCESS)
|
||||
{
|
||||
/* Change the CRYP phase */
|
||||
hcryp->Phase = CRYPEx_PHASE_FINAL;
|
||||
}
|
||||
else /* Initialization phase has not been performed*/
|
||||
{
|
||||
/* Disable the peripheral */
|
||||
__HAL_CRYP_DISABLE(hcryp);
|
||||
|
||||
/* Sequence error code field */
|
||||
hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE;
|
||||
|
||||
/* Change the CRYP peripheral state */
|
||||
hcryp->State = HAL_CRYP_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcryp);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Select final phase */
|
||||
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
|
||||
|
||||
/* Set encrypt operating mode*/
|
||||
MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
|
||||
|
||||
/* Wait for CCF flag to be raised */
|
||||
tickstart = HAL_GetTick();
|
||||
while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if (((HAL_GetTick() - tickstart) > Timeout) ||(Timeout == 0U))
|
||||
{
|
||||
/* Disable the CRYP peripheral Clock */
|
||||
__HAL_CRYP_DISABLE(hcryp);
|
||||
|
||||
/* Change state */
|
||||
hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
|
||||
hcryp->State = HAL_CRYP_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcryp);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Read the authentication TAG in the output FIFO */
|
||||
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
|
||||
tagaddr += 4U;
|
||||
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
|
||||
tagaddr += 4U;
|
||||
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
|
||||
tagaddr += 4U;
|
||||
*(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR;
|
||||
|
||||
/* Clear CCF Flag */
|
||||
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
|
||||
|
||||
|
||||
/* Change the CRYP peripheral state */
|
||||
hcryp->State = HAL_CRYP_STATE_READY;
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hcryp);
|
||||
|
||||
/* Disable CRYP */
|
||||
__HAL_CRYP_DISABLE(hcryp);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Busy error code field */
|
||||
hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CRYPEx_Exported_Functions_Group2 Extended AES Key Derivations functions
|
||||
* @brief Extended Key Derivations functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Key Derivation functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to Enable or Disable the
|
||||
the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure
|
||||
These function are allowed only in TinyAES peripheral.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AES enable key derivation functions
|
||||
* @param hcryp pointer to a CRYP_HandleTypeDef structure.
|
||||
*/
|
||||
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
|
||||
{
|
||||
if (hcryp->State == HAL_CRYP_STATE_READY)
|
||||
{
|
||||
hcryp->AutoKeyDerivation = ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Busy error code field */
|
||||
hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief AES disable key derivation functions
|
||||
* @param hcryp pointer to a CRYP_HandleTypeDef structure.
|
||||
*/
|
||||
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp)
|
||||
{
|
||||
if (hcryp->State == HAL_CRYP_STATE_READY)
|
||||
{
|
||||
hcryp->AutoKeyDerivation = DISABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Busy error code field */
|
||||
hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_cryp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of CRYPEx HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_CRYP_EX_H
|
||||
#define STM32WBxx_HAL_CRYP_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup CRYPEx CRYPEx
|
||||
* @brief CRYP Extension HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup CRYPEx_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
|
||||
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_CRYP_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32WBxx_HAL_DEF
|
||||
#define __STM32WBxx_HAL_DEF
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx.h"
|
||||
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
|
||||
#include <stddef.h>
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief HAL Status structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_OK = 0x00,
|
||||
HAL_ERROR = 0x01,
|
||||
HAL_BUSY = 0x02,
|
||||
HAL_TIMEOUT = 0x03
|
||||
} HAL_StatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL Lock structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_UNLOCKED = 0x00,
|
||||
HAL_LOCKED = 0x01
|
||||
} HAL_LockTypeDef;
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
|
||||
|
||||
#define HAL_MAX_DELAY 0xFFFFFFFFU
|
||||
|
||||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
|
||||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
|
||||
|
||||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__ specifies the Peripheral Handle.
|
||||
* @note This macro can be used for the following purpose:
|
||||
* - When the Handle is declared as local variable; before passing it as parameter
|
||||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
|
||||
* to set to 0 the Handle's "State" field.
|
||||
* Otherwise, "State" field may have any random value and the first time the function
|
||||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
|
||||
* (i.e. HAL_PPP_MspInit() will not be executed).
|
||||
* - When there is a need to reconfigure the low level hardware: instead of calling
|
||||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
|
||||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
|
||||
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
|
||||
|
||||
#if (USE_RTOS == 1)
|
||||
/* Reserved for future use */
|
||||
#error " USE_RTOS should be 0 in the current HAL release "
|
||||
#else
|
||||
#define __HAL_LOCK(__HANDLE__) \
|
||||
do{ \
|
||||
if((__HANDLE__)->Lock == HAL_LOCKED) \
|
||||
{ \
|
||||
return HAL_BUSY; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Lock = HAL_LOCKED; \
|
||||
} \
|
||||
}while (0)
|
||||
|
||||
#define __HAL_UNLOCK(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Lock = HAL_UNLOCKED; \
|
||||
}while (0)
|
||||
#endif /* USE_RTOS */
|
||||
|
||||
#if defined ( __GNUC__ )
|
||||
#ifndef __weak
|
||||
#define __weak __attribute__((weak))
|
||||
#endif /* __weak */
|
||||
#ifndef __packed
|
||||
#define __packed __attribute__((__packed__))
|
||||
#endif /* __packed */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
|
||||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
|
||||
/* GNU Compiler */
|
||||
#if defined (__GNUC__)
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#else
|
||||
#ifndef __ALIGN_END
|
||||
#define __ALIGN_END
|
||||
#endif /* __ALIGN_END */
|
||||
#ifndef __ALIGN_BEGIN
|
||||
/* ARM Compiler */
|
||||
#if defined (__CC_ARM)
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
/* IAR Compiler */
|
||||
#elif defined (__ICCARM__)
|
||||
#define __ALIGN_BEGIN
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __ALIGN_BEGIN */
|
||||
#endif /* __GNUC__ */
|
||||
|
||||
/**
|
||||
* @brief __RAM_FUNC definition
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
/* ARM Compiler
|
||||
------------
|
||||
RAM functions are defined using the toolchain options.
|
||||
Functions that are executed in RAM should reside in a separate source module.
|
||||
Using the 'Options for File' dialog you can simply change the 'Code / Const'
|
||||
area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
|
||||
dialog.
|
||||
*/
|
||||
#define __RAM_FUNC
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
*/
|
||||
#define __RAM_FUNC __ramfunc
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
/* GNU Compiler
|
||||
------------
|
||||
RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
*/
|
||||
#define __RAM_FUNC __attribute__((section(".RamFunc")))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief __NOINLINE definition
|
||||
*/
|
||||
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
|
||||
/* ARM & GNUCompiler
|
||||
----------------
|
||||
*/
|
||||
#define __NOINLINE __attribute__ ( (noinline) )
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* ICCARM Compiler
|
||||
---------------
|
||||
*/
|
||||
#define __NOINLINE _Pragma("optimize = no_inline")
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ___STM32WBxx_HAL_DEF */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,651 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_DMA_H
|
||||
#define STM32WBxx_HAL_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
#include "stm32wbxx_ll_dma.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Exported_Types DMA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief DMA Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Request; /*!< Specifies the request selected for the specified channel.
|
||||
This parameter can be a value of @ref DMA_request */
|
||||
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_Data_transfer_direction */
|
||||
|
||||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
|
||||
|
||||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_Memory_incremented_mode */
|
||||
|
||||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_Peripheral_data_size */
|
||||
|
||||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_Memory_data_size */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_Priority_level */
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
|
||||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
|
||||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
|
||||
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
|
||||
} HAL_DMA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Error Code structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
|
||||
} HAL_DMA_LevelCompleteTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Callback ID structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
|
||||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
|
||||
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
|
||||
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
|
||||
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
|
||||
|
||||
} HAL_DMA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief DMA handle Structure definition
|
||||
*/
|
||||
typedef struct __DMA_HandleTypeDef
|
||||
{
|
||||
DMA_Channel_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
DMA_InitTypeDef Init; /*!< DMA communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< DMA locking object */
|
||||
|
||||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
|
||||
|
||||
void *Parent; /*!< Parent object state */
|
||||
|
||||
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
|
||||
|
||||
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
|
||||
|
||||
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
|
||||
|
||||
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< DMA Error code */
|
||||
|
||||
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
|
||||
|
||||
uint32_t ChannelIndex; /*!< DMA Channel Index */
|
||||
|
||||
DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
|
||||
|
||||
DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
|
||||
|
||||
uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
|
||||
|
||||
DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
|
||||
|
||||
DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
|
||||
|
||||
uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
|
||||
} DMA_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants DMA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Error_Code DMA Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
|
||||
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
|
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
|
||||
#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
|
||||
#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_request DMA request
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_REQUEST_MEM2MEM LL_DMAMUX_REQ_MEM2MEM /*!< memory to memory transfer */
|
||||
|
||||
#define DMA_REQUEST_GENERATOR0 LL_DMAMUX_REQ_GENERATOR0 /*!< DMAMUX request generator 0 */
|
||||
#define DMA_REQUEST_GENERATOR1 LL_DMAMUX_REQ_GENERATOR1 /*!< DMAMUX request generator 1 */
|
||||
#define DMA_REQUEST_GENERATOR2 LL_DMAMUX_REQ_GENERATOR2 /*!< DMAMUX request generator 2 */
|
||||
#define DMA_REQUEST_GENERATOR3 LL_DMAMUX_REQ_GENERATOR3 /*!< DMAMUX request generator 3 */
|
||||
|
||||
#define DMA_REQUEST_ADC1 LL_DMAMUX_REQ_ADC1 /*!< DMAMUX ADC1 request */
|
||||
|
||||
#define DMA_REQUEST_SPI1_RX LL_DMAMUX_REQ_SPI1_RX /*!< DMAMUX SPI1 RX request */
|
||||
#define DMA_REQUEST_SPI1_TX LL_DMAMUX_REQ_SPI1_TX /*!< DMAMUX SPI1 TX request */
|
||||
#define DMA_REQUEST_SPI2_RX LL_DMAMUX_REQ_SPI2_RX /*!< DMAMUX SPI2 RX request */
|
||||
#define DMA_REQUEST_SPI2_TX LL_DMAMUX_REQ_SPI2_TX /*!< DMAMUX SPI2 TX request */
|
||||
|
||||
#define DMA_REQUEST_I2C1_RX LL_DMAMUX_REQ_I2C1_RX /*!< DMAMUX I2C1 RX request */
|
||||
#define DMA_REQUEST_I2C1_TX LL_DMAMUX_REQ_I2C1_TX /*!< DMAMUX I2C1 TX request */
|
||||
#define DMA_REQUEST_I2C3_RX LL_DMAMUX_REQ_I2C3_RX /*!< DMAMUX I2C3 RX request */
|
||||
#define DMA_REQUEST_I2C3_TX LL_DMAMUX_REQ_I2C3_TX /*!< DMAMUX I2C3 TX request */
|
||||
|
||||
#define DMA_REQUEST_USART1_RX LL_DMAMUX_REQ_USART1_RX /*!< DMAMUX USART1 RX request */
|
||||
#define DMA_REQUEST_USART1_TX LL_DMAMUX_REQ_USART1_TX /*!< DMAMUX USART1 TX request */
|
||||
|
||||
#define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LP_UART1_RX request */
|
||||
#define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LP_UART1_RX request */
|
||||
|
||||
#define DMA_REQUEST_SAI1_A LL_DMAMUX_REQ_SAI1_A /*!< DMAMUX SAI1 A request */
|
||||
#define DMA_REQUEST_SAI1_B LL_DMAMUX_REQ_SAI1_B /*!< DMAMUX SAI1 B request */
|
||||
|
||||
#define DMA_REQUEST_QUADSPI LL_DMAMUX_REQ_QUADSPI /*!< DMAMUX QUADSPI request */
|
||||
|
||||
#define DMA_REQUEST_TIM1_CH1 LL_DMAMUX_REQ_TIM1_CH1 /*!< DMAMUX TIM1 CH1 request */
|
||||
#define DMA_REQUEST_TIM1_CH2 LL_DMAMUX_REQ_TIM1_CH2 /*!< DMAMUX TIM1 CH2 request */
|
||||
#define DMA_REQUEST_TIM1_CH3 LL_DMAMUX_REQ_TIM1_CH3 /*!< DMAMUX TIM1 CH3 request */
|
||||
#define DMA_REQUEST_TIM1_CH4 LL_DMAMUX_REQ_TIM1_CH4 /*!< DMAMUX TIM1 CH4 request */
|
||||
#define DMA_REQUEST_TIM1_UP LL_DMAMUX_REQ_TIM1_UP /*!< DMAMUX TIM1 UP request */
|
||||
#define DMA_REQUEST_TIM1_TRIG LL_DMAMUX_REQ_TIM1_TRIG /*!< DMAMUX TIM1 TRIG request */
|
||||
#define DMA_REQUEST_TIM1_COM LL_DMAMUX_REQ_TIM1_COM /*!< DMAMUX TIM1 COM request */
|
||||
|
||||
#define DMA_REQUEST_TIM2_CH1 LL_DMAMUX_REQ_TIM2_CH1 /*!< DMAMUX TIM2 CH1 request */
|
||||
#define DMA_REQUEST_TIM2_CH2 LL_DMAMUX_REQ_TIM2_CH2 /*!< DMAMUX TIM2 CH2 request */
|
||||
#define DMA_REQUEST_TIM2_CH3 LL_DMAMUX_REQ_TIM2_CH3 /*!< DMAMUX TIM2 CH3 request */
|
||||
#define DMA_REQUEST_TIM2_CH4 LL_DMAMUX_REQ_TIM2_CH4 /*!< DMAMUX TIM2 CH4 request */
|
||||
#define DMA_REQUEST_TIM2_UP LL_DMAMUX_REQ_TIM2_UP /*!< DMAMUX TIM2 UP request */
|
||||
|
||||
#define DMA_REQUEST_TIM16_CH1 LL_DMAMUX_REQ_TIM16_CH1 /*!< DMAMUX TIM16 CH1 request */
|
||||
#define DMA_REQUEST_TIM16_UP LL_DMAMUX_REQ_TIM16_UP /*!< DMAMUX TIM16 UP request */
|
||||
|
||||
#define DMA_REQUEST_TIM17_CH1 LL_DMAMUX_REQ_TIM17_CH1 /*!< DMAMUX TIM17 CH1 request */
|
||||
#define DMA_REQUEST_TIM17_UP LL_DMAMUX_REQ_TIM17_UP /*!< DMAMUX TIM17 UP request */
|
||||
|
||||
#define DMA_REQUEST_AES1_IN LL_DMAMUX_REQ_AES1_IN /*!< DMAMUX AES1 IN request */
|
||||
#define DMA_REQUEST_AES1_OUT LL_DMAMUX_REQ_AES1_OUT /*!< DMAMUX AES1 OUT request */
|
||||
|
||||
#define DMA_REQUEST_AES2_IN LL_DMAMUX_REQ_AES2_IN /*!< DMAMUX AES2 IN request */
|
||||
#define DMA_REQUEST_AES2_OUT LL_DMAMUX_REQ_AES2_OUT /*!< DMAMUX AES2 OUT request */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY LL_DMA_DIRECTION_PERIPH_TO_MEMORY /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH LL_DMA_DIRECTION_MEMORY_TO_PERIPH /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY LL_DMA_DIRECTION_MEMORY_TO_MEMORY /*!< Memory to memory direction */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINC_ENABLE LL_DMA_PERIPH_INCREMENT /*!< Peripheral increment mode Enable */
|
||||
#define DMA_PINC_DISABLE LL_DMA_PERIPH_NOINCREMENT /*!< Peripheral increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MINC_ENABLE LL_DMA_MEMORY_INCREMENT /*!< Memory increment mode Enable */
|
||||
#define DMA_MINC_DISABLE LL_DMA_MEMORY_NOINCREMENT /*!< Memory increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE LL_DMA_PDATAALIGN_BYTE /*!< Peripheral data alignment : Byte */
|
||||
#define DMA_PDATAALIGN_HALFWORD LL_DMA_PDATAALIGN_HALFWORD /*!< Peripheral data alignment : HalfWord */
|
||||
#define DMA_PDATAALIGN_WORD LL_DMA_PDATAALIGN_WORD /*!< Peripheral data alignment : Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MDATAALIGN_BYTE LL_DMA_MDATAALIGN_BYTE /*!< Memory data alignment : Byte */
|
||||
#define DMA_MDATAALIGN_HALFWORD LL_DMA_MDATAALIGN_HALFWORD /*!< Memory data alignment : HalfWord */
|
||||
#define DMA_MDATAALIGN_WORD LL_DMA_MDATAALIGN_WORD /*!< Memory data alignment : Word */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_mode DMA mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL LL_DMA_MODE_NORMAL /*!< Normal mode */
|
||||
#define DMA_CIRCULAR LL_DMA_MODE_CIRCULAR /*!< Circular mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Priority_level DMA Priority level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PRIORITY_LOW LL_DMA_PRIORITY_LOW /*!< Priority level : Low */
|
||||
#define DMA_PRIORITY_MEDIUM LL_DMA_PRIORITY_MEDIUM /*!< Priority level : Medium */
|
||||
#define DMA_PRIORITY_HIGH LL_DMA_PRIORITY_HIGH /*!< Priority level : High */
|
||||
#define DMA_PRIORITY_VERY_HIGH LL_DMA_PRIORITY_VERYHIGH /*!< Priority level : Very_High */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_TC LL_DMA_CCR_TCIE /*!< Transfer complete interrupt */
|
||||
#define DMA_IT_HT LL_DMA_CCR_HTIE /*!< Half Transfer interrupt */
|
||||
#define DMA_IT_TE LL_DMA_CCR_TEIE /*!< Transfer error interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_GL1 LL_DMA_ISR_GIF1 /*!< Channel 1 global flag */
|
||||
#define DMA_FLAG_TC1 LL_DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
|
||||
#define DMA_FLAG_HT1 LL_DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
|
||||
#define DMA_FLAG_TE1 LL_DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
|
||||
#define DMA_FLAG_GL2 LL_DMA_ISR_GIF2 /*!< Channel 2 global flag */
|
||||
#define DMA_FLAG_TC2 LL_DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
|
||||
#define DMA_FLAG_HT2 LL_DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
|
||||
#define DMA_FLAG_TE2 LL_DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
|
||||
#define DMA_FLAG_GL3 LL_DMA_ISR_GIF3 /*!< Channel 3 global flag */
|
||||
#define DMA_FLAG_TC3 LL_DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
|
||||
#define DMA_FLAG_HT3 LL_DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
|
||||
#define DMA_FLAG_TE3 LL_DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
|
||||
#define DMA_FLAG_GL4 LL_DMA_ISR_GIF4 /*!< Channel 4 global flag */
|
||||
#define DMA_FLAG_TC4 LL_DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
|
||||
#define DMA_FLAG_HT4 LL_DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
|
||||
#define DMA_FLAG_TE4 LL_DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
|
||||
#define DMA_FLAG_GL5 LL_DMA_ISR_GIF5 /*!< Channel 5 global flag */
|
||||
#define DMA_FLAG_TC5 LL_DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
|
||||
#define DMA_FLAG_HT5 LL_DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
|
||||
#define DMA_FLAG_TE5 LL_DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
|
||||
#define DMA_FLAG_GL6 LL_DMA_ISR_GIF6 /*!< Channel 6 global flag */
|
||||
#define DMA_FLAG_TC6 LL_DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
|
||||
#define DMA_FLAG_HT6 LL_DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
|
||||
#define DMA_FLAG_TE6 LL_DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
|
||||
#define DMA_FLAG_GL7 LL_DMA_ISR_GIF7 /*!< Channel 7 global flag */
|
||||
#define DMA_FLAG_TC7 LL_DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
|
||||
#define DMA_FLAG_HT7 LL_DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
|
||||
#define DMA_FLAG_TE7 LL_DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup DMA_Exported_Macros DMA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset DMA handle state
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
|
||||
|
||||
|
||||
/* Interrupt & Flag management */
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer complete flag index.
|
||||
*/
|
||||
|
||||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
|
||||
DMA_FLAG_TC7)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel half transfer complete flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified half transfer complete flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
|
||||
DMA_FLAG_HT7)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel transfer error flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
|
||||
DMA_FLAG_TE7)
|
||||
|
||||
/**
|
||||
* @brief Returns the current DMA Channel Global interrupt flag.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The specified transfer error flag index.
|
||||
*/
|
||||
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
|
||||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
|
||||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
|
||||
DMA_ISR_GIF7)
|
||||
|
||||
/**
|
||||
* @brief Get the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ Get the specified flag.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* @arg DMA_FLAG_GLx: Global interrupt flag
|
||||
* Where x can be from 1 to 7 to select the DMA Channel x flag.
|
||||
* @retval The state of FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
|
||||
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Clear the DMA Channel pending flags.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_FLAG_TCx: Transfer complete flag
|
||||
* @arg DMA_FLAG_HTx: Half transfer complete flag
|
||||
* @arg DMA_FLAG_TEx: Transfer error flag
|
||||
* @arg DMA_FLAG_GLx: Global interrupt flag
|
||||
* Where x can be from 1 to 7 to select the DMA Channel x flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
|
||||
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified DMA Channel interrupts.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified DMA Channel interrupt is enabled or not.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer complete interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @retval The state of DMA_IT (SET or RESET).
|
||||
*/
|
||||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current DMA Channel transfer.
|
||||
* @param __HANDLE__ DMA handle
|
||||
* @retval The number of remaining data units in the current DMA Channel transfer.
|
||||
*/
|
||||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include DMA HAL Extension module */
|
||||
#include "stm32wbxx_hal_dma_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Macros DMA Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
|
||||
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
|
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
|
||||
((STATE) == DMA_PINC_DISABLE))
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
|
||||
((STATE) == DMA_MINC_DISABLE))
|
||||
|
||||
|
||||
#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_AES2_OUT)
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_PDATAALIGN_WORD))
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
|
||||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
|
||||
((SIZE) == DMA_MDATAALIGN_WORD ))
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
||||
((MODE) == DMA_CIRCULAR))
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
||||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
||||
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
||||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_DMA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,296 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_dma_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief DMA Extension HAL module driver
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the DMA Extension peripheral:
|
||||
* + Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The DMA Extension HAL driver can be used as follows:
|
||||
|
||||
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
|
||||
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
|
||||
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
|
||||
to respectively enable/disable the request generator.
|
||||
|
||||
(+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
|
||||
the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler.
|
||||
As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be
|
||||
called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
|
||||
(exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx DMAEx
|
||||
* @brief DMA Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private Constants ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
|
||||
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
|
||||
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
|
||||
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
|
||||
to respectively enable/disable the request generator.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance).
|
||||
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA channel.
|
||||
* @param pSyncConfig Pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
|
||||
assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity));
|
||||
assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
|
||||
assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
|
||||
assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
|
||||
|
||||
/*Check if the DMA state is ready */
|
||||
if (hdma->State == HAL_DMA_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
|
||||
MODIFY_REG(hdma->DMAmuxChannel->CCR, \
|
||||
(DMAMUX_CxCR_SYNC_ID | DMAMUX_CxCR_NBREQ | DMAMUX_CxCR_SPOL | DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE), \
|
||||
(pSyncConfig->SyncSignalID | \
|
||||
((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
|
||||
pSyncConfig->SyncPolarity | \
|
||||
((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
|
||||
((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)));
|
||||
|
||||
/* Process UnLocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
/*DMA State not Ready*/
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the DMAMUX request generator block used by the given DMA channel (instance).
|
||||
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA channel.
|
||||
* @param pRequestGeneratorConfig Pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
|
||||
* contains the request generator parameters.
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
|
||||
assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
|
||||
assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
|
||||
|
||||
/* check if the DMA state is ready
|
||||
and DMA is using a DMAMUX request generator block
|
||||
*/
|
||||
if ((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U))
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
/* Set the request generator new parameters*/
|
||||
WRITE_REG(hdma->DMAmuxRequestGen->RGCR, (pRequestGeneratorConfig->SignalID | \
|
||||
pRequestGeneratorConfig->Polarity | \
|
||||
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)));
|
||||
|
||||
/* Process UnLocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the DMAMUX request generator block used by the given DMA channel (instance).
|
||||
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* check if the DMA state is ready
|
||||
and DMA is using a DMAMUX request generator block
|
||||
*/
|
||||
if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
|
||||
{
|
||||
/* Enable the request generator*/
|
||||
SET_BIT(hdma->DMAmuxRequestGen->RGCR, DMAMUX_RGxCR_GE);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the DMAMUX request generator block used by the given DMA channel (instance).
|
||||
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* check if the DMA state is ready
|
||||
and DMA is using a DMAMUX request generator block
|
||||
*/
|
||||
if ((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0))
|
||||
{
|
||||
/* Disable the request generator*/
|
||||
CLEAR_BIT(hdma->DMAmuxRequestGen->RGCR, DMAMUX_RGxCR_GE);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles DMAMUX interrupt request.
|
||||
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA channel.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Check for DMAMUX Synchronization overrun */
|
||||
if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
|
||||
{
|
||||
/* Disable the synchro overrun interrupt */
|
||||
CLEAR_BIT(hdma->DMAmuxChannel->CCR, DMAMUX_CxCR_SOIE);
|
||||
|
||||
/* Clear the DMAMUX synchro overrun flag */
|
||||
WRITE_REG(hdma->DMAmuxChannelStatus->CFR, hdma->DMAmuxChannelStatusMask);
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
|
||||
|
||||
if (hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
if (hdma->DMAmuxRequestGen != 0U)
|
||||
{
|
||||
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
|
||||
if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
|
||||
{
|
||||
/* Disable the request gen overrun interrupt */
|
||||
CLEAR_BIT(hdma->DMAmuxRequestGen->RGCR, DMAMUX_RGxCR_OIE);
|
||||
|
||||
/* Clear the DMAMUX request generator overrun flag */
|
||||
WRITE_REG(hdma->DMAmuxRequestGenStatus->RGCFR, hdma->DMAmuxRequestGenStatusMask);
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
|
||||
|
||||
if (hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,265 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_dma_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of DMA HAL extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_DMA_EX_H
|
||||
#define STM32WBxx_HAL_DMA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
#include "stm32wbxx_ll_dmamux.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL DMA Synchro definition
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DMAMUX Synchronization configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
|
||||
|
||||
uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
|
||||
|
||||
FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
|
||||
This parameter can take the value ENABLE or DISABLE*/
|
||||
|
||||
FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
|
||||
This parameter can take the value ENABLE or DISABLE */
|
||||
|
||||
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
||||
|
||||
|
||||
} HAL_DMA_MuxSyncConfigTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief HAL DMAMUX request generator parameters structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
|
||||
|
||||
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
|
||||
This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
|
||||
|
||||
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
|
||||
|
||||
} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX1_SYNC_EXTI0 LL_DMAMUX_SYNC_EXTI_LINE0 /*!< Synchronization Signal is EXTI0 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI1 LL_DMAMUX_SYNC_EXTI_LINE1 /*!< Synchronization Signal is EXTI1 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI2 LL_DMAMUX_SYNC_EXTI_LINE2 /*!< Synchronization Signal is EXTI2 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI3 LL_DMAMUX_SYNC_EXTI_LINE3 /*!< Synchronization Signal is EXTI3 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI4 LL_DMAMUX_SYNC_EXTI_LINE4 /*!< Synchronization Signal is EXTI4 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI5 LL_DMAMUX_SYNC_EXTI_LINE5 /*!< Synchronization Signal is EXTI5 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI6 LL_DMAMUX_SYNC_EXTI_LINE6 /*!< Synchronization Signal is EXTI6 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI7 LL_DMAMUX_SYNC_EXTI_LINE7 /*!< Synchronization Signal is EXTI7 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI8 LL_DMAMUX_SYNC_EXTI_LINE8 /*!< Synchronization Signal is EXTI8 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI9 LL_DMAMUX_SYNC_EXTI_LINE9 /*!< Synchronization Signal is EXTI9 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI10 LL_DMAMUX_SYNC_EXTI_LINE10 /*!< Synchronization Signal is EXTI10 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI11 LL_DMAMUX_SYNC_EXTI_LINE11 /*!< Synchronization Signal is EXTI11 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI12 LL_DMAMUX_SYNC_EXTI_LINE12 /*!< Synchronization Signal is EXTI12 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI13 LL_DMAMUX_SYNC_EXTI_LINE13 /*!< Synchronization Signal is EXTI13 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI14 LL_DMAMUX_SYNC_EXTI_LINE14 /*!< Synchronization Signal is EXTI14 IT */
|
||||
#define HAL_DMAMUX1_SYNC_EXTI15 LL_DMAMUX_SYNC_EXTI_LINE15 /*!< Synchronization Signal is EXTI15 IT */
|
||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT LL_DMAMUX_SYNC_DMAMUX_CH0 /*!< Synchronization Signal is DMAMUX1 Channel0 Event */
|
||||
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT LL_DMAMUX_SYNC_DMAMUX_CH1 /*!< Synchronization Signal is DMAMUX1 Channel1 Event */
|
||||
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT LL_DMAMUX_SYNC_LPTIM1_OUT /*!< Synchronization Signal is LPTIM1 OUT */
|
||||
#define HAL_DMAMUX1_SYNC_LPTIM2_OUT LL_DMAMUX_SYNC_LPTIM2_OUT /*!< Synchronization Signal is LPTIM2 OUT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX_SYNC_NO_EVENT LL_DMAMUX_SYNC_NO_EVENT /*!< block synchronization events */
|
||||
#define HAL_DMAMUX_SYNC_RISING LL_DMAMUX_SYNC_POL_RISING /*!< synchronize with rising edge events */
|
||||
#define HAL_DMAMUX_SYNC_FALLING LL_DMAMUX_SYNC_POL_FALLING /*!< synchronize with falling edge events */
|
||||
#define HAL_DMAMUX_SYNC_RISING_FALLING LL_DMAMUX_SYNC_POL_RISING_FALLING /*!< synchronize with rising and falling edge events */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI0 LL_DMAMUX_REQ_GEN_EXTI_LINE0 /*!< Request generator Signal is EXTI0 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI1 LL_DMAMUX_REQ_GEN_EXTI_LINE1 /*!< Request generator Signal is EXTI1 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI2 LL_DMAMUX_REQ_GEN_EXTI_LINE2 /*!< Request generator Signal is EXTI2 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI3 LL_DMAMUX_REQ_GEN_EXTI_LINE3 /*!< Request generator Signal is EXTI3 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI4 LL_DMAMUX_REQ_GEN_EXTI_LINE4 /*!< Request generator Signal is EXTI4 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI5 LL_DMAMUX_REQ_GEN_EXTI_LINE5 /*!< Request generator Signal is EXTI5 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI6 LL_DMAMUX_REQ_GEN_EXTI_LINE6 /*!< Request generator Signal is EXTI6 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI7 LL_DMAMUX_REQ_GEN_EXTI_LINE7 /*!< Request generator Signal is EXTI7 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI8 LL_DMAMUX_REQ_GEN_EXTI_LINE8 /*!< Request generator Signal is EXTI8 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI9 LL_DMAMUX_REQ_GEN_EXTI_LINE9 /*!< Request generator Signal is EXTI9 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI10 LL_DMAMUX_REQ_GEN_EXTI_LINE10 /*!< Request generator Signal is EXTI10 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI11 LL_DMAMUX_REQ_GEN_EXTI_LINE11 /*!< Request generator Signal is EXTI11 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI12 LL_DMAMUX_REQ_GEN_EXTI_LINE12 /*!< Request generator Signal is EXTI12 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI13 LL_DMAMUX_REQ_GEN_EXTI_LINE13 /*!< Request generator Signal is EXTI13 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI14 LL_DMAMUX_REQ_GEN_EXTI_LINE14 /*!< Request generator Signal is EXTI14 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_EXTI15 LL_DMAMUX_REQ_GEN_EXTI_LINE15 /*!< Request generator Signal is EXTI15 IT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH0 /*!< Request generator Signal is DMAMUX1 Channel0 Event */
|
||||
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT LL_DMAMUX_REQ_GEN_DMAMUX_CH1 /*!< Request generator Signal is DMAMUX1 Channel1 Event */
|
||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT LL_DMAMUX_REQ_GEN_LPTIM1_OUT /*!< Request generator Signal is LPTIM1 OUT */
|
||||
#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT LL_DMAMUX_REQ_GEN_LPTIM2_OUT /*!< Request generator Signal is LPTIM2 OUT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMAMUX_REQ_GEN_NO_EVENT LL_DMAMUX_REQ_GEN_NO_EVENT /*!< block request generator events */
|
||||
#define HAL_DMAMUX_REQ_GEN_RISING LL_DMAMUX_REQ_GEN_POL_RISING /*!< generate request on rising edge events */
|
||||
#define HAL_DMAMUX_REQ_GEN_FALLING LL_DMAMUX_REQ_GEN_POL_FALLING /*!< generate request on falling edge events */
|
||||
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING /*!< generate request on rising and falling edge events */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup DMAEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
/** @addtogroup DMAEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ------------------------- REQUEST -----------------------------------------*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
|
||||
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
|
||||
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
|
||||
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
|
||||
/* -------------------------------------------------------------------------- */
|
||||
|
||||
/* ------------------------- SYNCHRO -----------------------------------------*/
|
||||
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
|
||||
/* -------------------------------------------------------------------------- */
|
||||
|
||||
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
|
||||
* @brief DMAEx private macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM2_OUT)
|
||||
|
||||
#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
|
||||
|
||||
#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
|
||||
((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
|
||||
((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
|
||||
((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
|
||||
|
||||
#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
|
||||
|
||||
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
|
||||
((EVENT) == ENABLE))
|
||||
|
||||
#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT)
|
||||
|
||||
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
|
||||
|
||||
#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
|
||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
|
||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
|
||||
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_DMA_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,643 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_exti.c
|
||||
* @author MCD Application Team
|
||||
* @brief EXTI HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (EXTI) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### EXTI Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each Exti line can be configured within this driver.
|
||||
|
||||
(+) Exti line can be configured in 3 different modes
|
||||
(++) Interrupt
|
||||
(++) Event
|
||||
(++) Both of them
|
||||
|
||||
(+) Configurable Exti lines can be configured with 3 different triggers
|
||||
(++) Rising
|
||||
(++) Falling
|
||||
(++) Both of them
|
||||
|
||||
(+) When set in interrupt mode, configurable Exti lines have two diffenrents
|
||||
interrupt pending registers which allow to distinguish which transition
|
||||
occurs:
|
||||
(++) Rising edge pending interrupt
|
||||
(++) Falling
|
||||
|
||||
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
|
||||
be selected throught multiplexer.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
|
||||
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
|
||||
(++) Choose the interrupt line number by setting "Line" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) Configure the interrupt and/or event mode using "Mode" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) For configurable lines, configure rising and/or falling trigger
|
||||
"Trigger" member from EXTI_ConfigTypeDef structure.
|
||||
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
|
||||
member from GPIO_InitTypeDef structure.
|
||||
|
||||
(#) Get current Exti configuration of a dedicated line using
|
||||
HAL_EXTI_GetConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||
(++) Provide exiting handle as first parameter.
|
||||
(++) Provide which callback will be registered using one value from
|
||||
EXTI_CallbackIDTypeDef.
|
||||
(++) Provide callback function pointer.
|
||||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
/** MISRA C:2012 deviation rule has been granted for following rule:
|
||||
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
|
||||
* of bounds [0,3] in following API :
|
||||
* HAL_EXTI_SetConfigLine
|
||||
* HAL_EXTI_GetConfigLine
|
||||
* HAL_EXTI_ClearConfigLine
|
||||
*/
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */
|
||||
#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group1
|
||||
* @brief Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on EXTI configuration to be set.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
__IO uint32_t *regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
|
||||
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
|
||||
|
||||
/* Assign line number to handle */
|
||||
hexti->Line = pExtiConfig->Line;
|
||||
|
||||
/* compute line register offset and line mask */
|
||||
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* Configure triggers for configurable lines */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
|
||||
|
||||
/* Configure rising trigger */
|
||||
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
regval = *regaddr;
|
||||
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
|
||||
{
|
||||
regval |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~maskline;
|
||||
}
|
||||
|
||||
/* Store rising trigger mode */
|
||||
*regaddr = regval;
|
||||
|
||||
/* Configure falling trigger */
|
||||
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
regval = *regaddr;
|
||||
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
|
||||
{
|
||||
regval |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~maskline;
|
||||
}
|
||||
|
||||
/* Store falling trigger mode */
|
||||
*regaddr = regval;
|
||||
|
||||
/* Configure gpio port selection in case of gpio exti line */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure interrupt mode : read current mode */
|
||||
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
|
||||
regval = *regaddr;
|
||||
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
|
||||
{
|
||||
regval |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~maskline;
|
||||
}
|
||||
|
||||
/* Store interrupt mode */
|
||||
*regaddr = regval;
|
||||
|
||||
/* The event mode cannot be configured if the line does not support it */
|
||||
assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
|
||||
|
||||
/* Configure event mode : read current mode */
|
||||
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
|
||||
regval = *regaddr;
|
||||
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
|
||||
{
|
||||
regval |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~maskline;
|
||||
}
|
||||
|
||||
/* Store event mode */
|
||||
*regaddr = regval;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on structure to store Exti configuration.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
__IO uint32_t *regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* Store handle line number to configiguration structure */
|
||||
pExtiConfig->Line = hexti->Line;
|
||||
|
||||
/* compute line register offset and line mask */
|
||||
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Get core mode : interrupt */
|
||||
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
|
||||
regval = *regaddr;
|
||||
|
||||
/* Check if selected line is enable */
|
||||
if ((regval & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_NONE;
|
||||
}
|
||||
|
||||
/* Get event mode */
|
||||
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
|
||||
regval = *regaddr;
|
||||
|
||||
/* Check if selected line is enable */
|
||||
if ((regval & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode |= EXTI_MODE_EVENT;
|
||||
}
|
||||
|
||||
/* 2] Get trigger for configurable lines : rising */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
regval = *regaddr;
|
||||
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((regval & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
}
|
||||
|
||||
/* Get falling configuration */
|
||||
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
regval = *regaddr;
|
||||
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((regval & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
|
||||
}
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->GPIOSel = 0x00u;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
pExtiConfig->GPIOSel = 0x00u;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear whole configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
__IO uint32_t *regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* compute line register offset and line mask */
|
||||
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Clear interrupt mode */
|
||||
regaddr = (&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset));
|
||||
regval = (*regaddr & ~maskline);
|
||||
*regaddr = regval;
|
||||
|
||||
/* 2] Clear event mode */
|
||||
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
|
||||
regval = (*regaddr & ~maskline);
|
||||
*regaddr = regval;
|
||||
|
||||
/* 3] Clear triggers in case of configurable lines */
|
||||
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
regval = (*regaddr & ~maskline);
|
||||
*regaddr = regval;
|
||||
|
||||
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
regval = (*regaddr & ~maskline);
|
||||
*regaddr = regval;
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Register callback for a dedicaated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param CallbackID User callback identifier.
|
||||
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
|
||||
* @param pPendingCbfn function pointer to be stored as callback.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_EXTI_COMMON_CB_ID:
|
||||
hexti->PendingCallback = pPendingCbfn;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Store line number as handle private field.
|
||||
* @param hexti Exti handle.
|
||||
* @param ExtiLine Exti line number.
|
||||
* This parameter can be from 0 to @ref EXTI_LINE_NB.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(ExtiLine));
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Store line number as handle private field */
|
||||
hexti->Line = ExtiLine;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group2
|
||||
* @brief EXTI IO functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request.
|
||||
* @param hexti Exti handle.
|
||||
* @retval none.
|
||||
*/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
__IO uint32_t *regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Compute line register offset and line mask */
|
||||
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Get pending bit */
|
||||
regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
regval = (*regaddr & maskline);
|
||||
|
||||
if (regval != 0x00u)
|
||||
{
|
||||
/* Clear pending bit */
|
||||
*regaddr = maskline;
|
||||
|
||||
/* Call callback */
|
||||
if (hexti->PendingCallback != NULL)
|
||||
{
|
||||
hexti->PendingCallback();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be checked.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval 1 if interrupt is pending else 0.
|
||||
*/
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
__IO uint32_t *regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* compute line register offset and line mask */
|
||||
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* Get pending bit */
|
||||
regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
|
||||
/* return 1 if bit is set else 0 */
|
||||
regval = ((*regaddr & maskline) >> linepos);
|
||||
return regval;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
__IO uint32_t *regaddr;
|
||||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* compute line register offset and line mask */
|
||||
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Get pending register address */
|
||||
regaddr = (&EXTI->PR1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
|
||||
/* Clear Pending bit */
|
||||
*regaddr = maskline;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt for a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
__IO uint32_t *regaddr;
|
||||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
|
||||
/* compute line register offset and line mask */
|
||||
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
|
||||
*regaddr = maskline;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,324 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_exti.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of EXTI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_EXTI_H
|
||||
#define STM32WBxx_HAL_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI EXTI
|
||||
* @brief EXTI HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Types EXTI Exported Types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_EXTI_COMMON_CB_ID = 0x00U,
|
||||
} EXTI_CallbackIDTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief EXTI Handle structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< Exti line number */
|
||||
void (* PendingCallback)(void); /*!< Exti pending callback */
|
||||
} EXTI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief EXTI Configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Line; /*!< The Exti line to be configured. This parameter
|
||||
can be a value of @ref EXTI_Line */
|
||||
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
|
||||
This parameter can be a combination of @ref EXTI_Mode */
|
||||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
|
||||
can be a value of @ref EXTI_Trigger */
|
||||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
|
||||
This parameter is only possible for line 0 to 15. It
|
||||
can be a value of @ref EXTI_GPIOSel */
|
||||
} EXTI_ConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Line EXTI Line
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x00u)
|
||||
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x01u)
|
||||
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x02u)
|
||||
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x03u)
|
||||
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x04u)
|
||||
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x05u)
|
||||
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x06u)
|
||||
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x07u)
|
||||
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x08u)
|
||||
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x09u)
|
||||
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Au)
|
||||
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Bu)
|
||||
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Cu)
|
||||
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Du)
|
||||
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Eu)
|
||||
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Fu)
|
||||
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
|
||||
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u)
|
||||
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u)
|
||||
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u)
|
||||
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x14u)
|
||||
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u)
|
||||
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u)
|
||||
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
|
||||
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
|
||||
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
|
||||
#define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au)
|
||||
#define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)
|
||||
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
|
||||
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)
|
||||
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)
|
||||
#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
|
||||
#define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u)
|
||||
#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
|
||||
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
|
||||
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
|
||||
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
|
||||
#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)
|
||||
#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06u)
|
||||
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07u)
|
||||
#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u)
|
||||
#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u)
|
||||
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
|
||||
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
|
||||
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu)
|
||||
#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0Du)
|
||||
#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu)
|
||||
#define EXTI_LINE_47 (EXTI_RESERVED | EXTI_REG2 | 0x0Fu)
|
||||
#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10u)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Mode EXTI Mode
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_MODE_NONE 0x00000000u
|
||||
#define EXTI_MODE_INTERRUPT 0x00000001u
|
||||
#define EXTI_MODE_EVENT 0x00000002u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Trigger EXTI Trigger
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_TRIGGER_NONE 0x00000000u
|
||||
#define EXTI_TRIGGER_RISING 0x00000001u
|
||||
#define EXTI_TRIGGER_FALLING 0x00000002u
|
||||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
|
||||
* @brief
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_GPIOA 0x00000000u
|
||||
#define EXTI_GPIOB 0x00000001u
|
||||
#define EXTI_GPIOC 0x00000002u
|
||||
#define EXTI_GPIOD 0x00000003u
|
||||
#define EXTI_GPIOE 0x00000004u
|
||||
#define EXTI_GPIOH 0x00000007u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief EXTI Line property definition
|
||||
*/
|
||||
#define EXTI_PROPERTY_SHIFT 24u
|
||||
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
|
||||
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
|
||||
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
|
||||
|
||||
/**
|
||||
* @brief EXTI Event presence definition
|
||||
*/
|
||||
#define EXTI_EVENT_PRESENCE_SHIFT 28u
|
||||
#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
|
||||
#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
|
||||
|
||||
/**
|
||||
* @brief EXTI Register and bit usage
|
||||
*/
|
||||
#define EXTI_REG_SHIFT 16u
|
||||
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
|
||||
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
|
||||
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
|
||||
#define EXTI_PIN_MASK 0x0000001Fu
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for interrupt & event mode
|
||||
*/
|
||||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
|
||||
|
||||
/**
|
||||
* @brief EXTI Mask for trigger possibilities
|
||||
*/
|
||||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
|
||||
|
||||
/**
|
||||
* @brief EXTI Line number
|
||||
*/
|
||||
#define EXTI_LINE_NB 49uL
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Macros EXTI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
|
||||
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
|
||||
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
|
||||
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
|
||||
(((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
|
||||
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
|
||||
|
||||
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
|
||||
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
|
||||
|
||||
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
|
||||
|
||||
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)
|
||||
|
||||
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
|
||||
|
||||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
|
||||
((__PORT__) == EXTI_GPIOB) || \
|
||||
((__PORT__) == EXTI_GPIOC) || \
|
||||
((__PORT__) == EXTI_GPIOD) || \
|
||||
((__PORT__) == EXTI_GPIOE) || \
|
||||
((__PORT__) == EXTI_GPIOH))
|
||||
|
||||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
|
||||
* @brief EXTI Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
|
||||
* @brief Configuration functions
|
||||
* @{
|
||||
*/
|
||||
/* Configuration functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_EXTI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,768 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @brief FLASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
* + Program operations functions
|
||||
* + Memory Control functions
|
||||
* + Peripheral Errors functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH peripheral features #####
|
||||
==============================================================================
|
||||
|
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms.
|
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction
|
||||
prefetch and cache lines.
|
||||
|
||||
[..] The FLASH main features are:
|
||||
(+) Flash memory read operations
|
||||
(+) Flash memory program/erase operations
|
||||
(+) Program and Erase suspension
|
||||
(+) Read / write protections (2 areas per features)
|
||||
(+) CPU2 Security area
|
||||
(+) Option bytes programming
|
||||
(+) Prefetch on CPU1 I-Code and CPU2 S-bus
|
||||
(+) 32 instruction cache lines of 4*64 bits on I-Code for CPU1
|
||||
(+) 8 data cache lines of 4*64 bits on D-Code for CPU1
|
||||
(+) 4 instruction cache lines of 1*64 bits on S-bus for CPU2
|
||||
(+) 4 data cache lines of 1*64 bits on S-Bus for CPU2
|
||||
(+) Error code correction (ECC) : Data in flash are 72-bits word
|
||||
(8 bits added per double word)
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32WBxx devices.
|
||||
|
||||
(#) Flash Memory IO Programming functions:
|
||||
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
|
||||
HAL_FLASH_Lock() functions
|
||||
(++) Program functions: double word and fast program (full row programming)
|
||||
(++) There are two modes of programming:
|
||||
(+++) Polling mode using HAL_FLASH_Program() function
|
||||
(+++) Interrupt mode using HAL_FLASH_Program_IT() function
|
||||
|
||||
(#) Interrupts and flags management functions:
|
||||
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
|
||||
(++) Callback functions are called when the flash operations are finished :
|
||||
HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
|
||||
HAL_FLASH_OperationErrorCallback()
|
||||
(++) Get error flag status by calling HAL_GetError()
|
||||
|
||||
(#) Option bytes management functions :
|
||||
(++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
|
||||
HAL_FLASH_OB_Lock() functions
|
||||
(++) Launch the reload of the option bytes using HAL_FLASH_OB_Launch() function.
|
||||
In this case, a reset is generated
|
||||
|
||||
[..]
|
||||
In addition to these functions, this driver includes a set of macros allowing
|
||||
to handle the following operations:
|
||||
(+) Set the latency
|
||||
(+) Enable/Disable the prefetch buffer
|
||||
(+) Enable/Disable the suspend program or erase request
|
||||
(+) Enable/Disable the Instruction cache and the Data cache
|
||||
(+) Reset the Instruction cache and the Data cache
|
||||
(+) Enable/Disable the Flash interrupts
|
||||
(+) Monitor the Flash flags status
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_NB_DOUBLE_WORDS_IN_ROW 64
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Variable used for Program/Erase sectors under interruption
|
||||
*/
|
||||
FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \
|
||||
.ErrorCode = HAL_FLASH_ERROR_NONE, \
|
||||
.ProcedureOnGoing = 0U, \
|
||||
.Address = 0U, \
|
||||
.Page = 0U, \
|
||||
.NbPagesToErase = 0U
|
||||
};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
|
||||
static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Programming operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the FLASH
|
||||
program operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program double word or fast program of a row at a specified address.
|
||||
* @note Before any operation, it is possible to check there is no operation suspended
|
||||
* by call HAL_FLASHEx_IsOperationSuspended()
|
||||
* @param TypeProgram Indicate the way to program at a specified address
|
||||
* This parameter can be a value of @ref FLASH_TYPE_PROGRAM
|
||||
* @param Address Specifies the address to be programmed.
|
||||
* @param Data Specifies the data to be programmed
|
||||
* This parameter is the data for the double word program and the address where
|
||||
* are stored the data for the row fast program.
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_ADDR_ALIGNED_64BITS(Address));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Reset error code */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Verify that next operation can be proceed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Program double-word (64-bit) at a specified address */
|
||||
FLASH_Program_DoubleWord(Address, Data);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Fast program a 64 row double-word (64-bit) at a specified address */
|
||||
FLASH_Program_Fast(Address, (uint32_t)Data);
|
||||
}
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the program operation is completed, disable the PG or FSTPG Bit */
|
||||
CLEAR_BIT(FLASH->CR, TypeProgram);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
/* return status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program double word or fast program of a row at a specified address with interrupt enabled.
|
||||
* @note Before any operation, it is possible to check there is no operation suspended
|
||||
* by call HAL_FLASHEx_IsOperationSuspended()
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_TYPE_PROGRAM
|
||||
* @param Address Specifies the address to be programmed.
|
||||
* @param Data Specifies the data to be programmed
|
||||
* This parameter is the data for the double word program and the address where
|
||||
* are stored the data for the row fast program.
|
||||
*
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_ADDR_ALIGNED_64BITS(Address));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Reset error code */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* Verify that next operation can be proceed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set internal variables used by the IRQ handler */
|
||||
pFlash.ProcedureOnGoing = TypeProgram;
|
||||
pFlash.Address = Address;
|
||||
|
||||
/* Enable End of Operation and Error interrupts */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR | FLASH_IT_ECCC);
|
||||
|
||||
if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Program double-word (64-bit) at a specified address */
|
||||
FLASH_Program_DoubleWord(Address, Data);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_FAST_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Fast program a 64 row double-word (64-bit) at a specified address */
|
||||
FLASH_Program_Fast(Address, (uint32_t)Data);
|
||||
}
|
||||
}
|
||||
|
||||
/* return status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle FLASH interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASH_IRQHandler(void)
|
||||
{
|
||||
uint32_t clearbit;
|
||||
uint32_t param;
|
||||
uint32_t error;
|
||||
|
||||
/* save flash errors. Only ECC detection can be checked here as ECCC
|
||||
generates NMI */
|
||||
error = (FLASH->SR & FLASH_FLAG_SR_ERROR);
|
||||
error |= (FLASH->ECCR & FLASH_FLAG_ECCC);
|
||||
|
||||
/* A] Set parameter for user or error callbacks */
|
||||
|
||||
/* check operation was a program or erase */
|
||||
if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0U)
|
||||
{
|
||||
/* return adress being programmed */
|
||||
param = pFlash.Address;
|
||||
|
||||
/* set operation bit to clear */
|
||||
clearbit = pFlash.ProcedureOnGoing;
|
||||
}
|
||||
else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_MASSERASE | FLASH_TYPEERASE_PAGES)) != 0U)
|
||||
{
|
||||
/* return page number being erased (0 for mass erase) */
|
||||
param = pFlash.Page;
|
||||
|
||||
if (pFlash.ProcedureOnGoing != FLASH_TYPEERASE_PAGES)
|
||||
{
|
||||
/* set operation bit to clear */
|
||||
clearbit = pFlash.ProcedureOnGoing;
|
||||
}
|
||||
else
|
||||
{
|
||||
clearbit = 0U;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
param = 0U;
|
||||
clearbit = 0U;
|
||||
}
|
||||
|
||||
/* clear operation bit if needed */
|
||||
if (clearbit != 0U)
|
||||
{
|
||||
CLEAR_BIT(FLASH->CR, clearbit);
|
||||
}
|
||||
|
||||
/* B] Check errors */
|
||||
if (error != 0U)
|
||||
{
|
||||
/*Save the error code*/
|
||||
pFlash.ErrorCode |= error;
|
||||
|
||||
/* clear error flags */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_SR_ERROR);
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ECCC);
|
||||
|
||||
/*Stop the procedure ongoing*/
|
||||
pFlash.ProcedureOnGoing = FLASH_TYPENONE;
|
||||
|
||||
/* Error callback */
|
||||
HAL_FLASH_OperationErrorCallback(param);
|
||||
}
|
||||
|
||||
/* C] Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
|
||||
if (pFlash.ProcedureOnGoing == FLASH_TYPEERASE_PAGES)
|
||||
{
|
||||
/* Nb of pages to erased can be decreased */
|
||||
pFlash.NbPagesToErase--;
|
||||
|
||||
/* Check if there are still pages to erase*/
|
||||
if (pFlash.NbPagesToErase != 0U)
|
||||
{
|
||||
/* Increment page number */
|
||||
pFlash.Page++;
|
||||
FLASH_PageErase(pFlash.Page);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No more pages to erase: stop erase pages procedure */
|
||||
/* Reset Address and stop Erase pages procedure */
|
||||
CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing);
|
||||
pFlash.Page = 0xFFFFFFFFU;
|
||||
param = pFlash.Page;
|
||||
pFlash.ProcedureOnGoing = FLASH_TYPENONE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Stop the ongoing procedure */
|
||||
param = 0xFFFFFFFFU;
|
||||
pFlash.ProcedureOnGoing = FLASH_TYPENONE;
|
||||
}
|
||||
|
||||
/* User callback */
|
||||
HAL_FLASH_EndOfOperationCallback(param);
|
||||
}
|
||||
|
||||
if (pFlash.ProcedureOnGoing == FLASH_TYPENONE)
|
||||
{
|
||||
/* Disable End of Operation and Error interrupts */
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback.
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* Mass Erase: 0
|
||||
* Page Erase: Page which has been erased
|
||||
* Program: Address which was selected for data program
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback.
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* Mass Erase: 0
|
||||
* Page Erase: Page number which returned an error
|
||||
* Program: Address which was selected for data program
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
|
||||
{
|
||||
/* Authorize the FLASH Registers access */
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY1);
|
||||
WRITE_REG(FLASH->KEYR, FLASH_KEY2);
|
||||
|
||||
/* verify Flash is unlock */
|
||||
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) != 0U)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the FLASH control register access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Verify that next operation can be proceed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Set the LOCK Bit to lock the FLASH Registers access */
|
||||
/* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
|
||||
|
||||
/* verify Flash is locked */
|
||||
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) == 0U)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Bytes Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */
|
||||
if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != 0U)
|
||||
{
|
||||
/* Authorizes the Option Byte register programming */
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
|
||||
|
||||
/* verify option bytes are unlocked */
|
||||
if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0U)
|
||||
{
|
||||
status = HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Bytes Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Verify that next operation can be proceed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
|
||||
/* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
|
||||
|
||||
/* verify option bytes are lock */
|
||||
if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0U)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Verify that next operation can be proceed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Set the bit to force the option byte reloading */
|
||||
/* The OB launch is done from the same register either from CPU1 or CPU2 */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
|
||||
}
|
||||
|
||||
/* We should not reach here : Option byte launch generates Option byte reset
|
||||
so return error */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @brief Peripheral Errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time Errors of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag.
|
||||
* @retval FLASH_ErrorCode The returned value can be
|
||||
* @arg @ref HAL_FLASH_ERROR_NONE No error set
|
||||
* @arg @ref HAL_FLASH_ERROR_OP FLASH Operation error
|
||||
* @arg @ref HAL_FLASH_ERROR_PROG FLASH Programming error
|
||||
* @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protection error
|
||||
* @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming alignment error
|
||||
* @arg @ref HAL_FLASH_ERROR_SIZ FLASH Size error
|
||||
* @arg @ref HAL_FLASH_ERROR_PGS FLASH Programming sequence error
|
||||
* @arg @ref HAL_FLASH_ERROR_MIS FLASH Fast programming data miss error
|
||||
* @arg @ref HAL_FLASH_ERROR_FAST FLASH Fast programming error
|
||||
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error (PCROP)
|
||||
* @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option validity error
|
||||
* @arg @ref HAL_FLASH_ERROR_ECCD FLASH two ECC errors have been detected
|
||||
*/
|
||||
uint32_t HAL_FLASH_GetError(void)
|
||||
{
|
||||
return pFlash.ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout Maximum flash operation timeout
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
uint32_t error;
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) >= Timeout)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* check flash errors. Only ECC correction can be checked here as ECCD
|
||||
generates NMI */
|
||||
error = (FLASH->SR & FLASH_FLAG_SR_ERROR);
|
||||
if (error != 0U)
|
||||
{
|
||||
/*Save the error code*/
|
||||
pFlash.ErrorCode |= error;
|
||||
|
||||
/* clear error flags */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_SR_ERROR);
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ECCC);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program double-word (64-bit) at a specified address.
|
||||
* @param Address Specifies the address to be programmed.
|
||||
* @param Data Specifies the data to be programmed.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
|
||||
{
|
||||
/* Set PG bit */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_PG);
|
||||
|
||||
/* Program first word */
|
||||
*(__IO uint32_t *)Address = (uint32_t)Data;
|
||||
|
||||
/* Barrier to ensure programming is performed in 2 steps, in right order
|
||||
(independently of compiler optimization behavior) */
|
||||
__ISB();
|
||||
|
||||
/* Program second word */
|
||||
*(__IO uint32_t *)((uint32_t)(Address + 4U)) = (uint32_t)(Data >> 32U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fast program a 32 row double-word (64-bit) at a specified address.
|
||||
* @param Address Specifies the address to be programmed.
|
||||
* @param DataAddress Specifies the address where the data are stored.
|
||||
* @retval None
|
||||
*/
|
||||
static __RAM_FUNC void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
|
||||
{
|
||||
uint8_t row_index = (2 * FLASH_NB_DOUBLE_WORDS_IN_ROW);
|
||||
__IO uint32_t *dest_addr = (__IO uint32_t *)Address;
|
||||
__IO uint32_t *src_addr = (__IO uint32_t *)DataAddress;
|
||||
uint32_t primask_bit;
|
||||
|
||||
/* Set FSTPG bit */
|
||||
SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
|
||||
|
||||
/* Enter critical section: row programming should not be longer than 7 ms */
|
||||
primask_bit = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
|
||||
/* Program the double word of the row */
|
||||
do
|
||||
{
|
||||
*dest_addr = *src_addr;
|
||||
dest_addr++;
|
||||
src_addr++;
|
||||
row_index--;
|
||||
}
|
||||
while (row_index != 0U);
|
||||
|
||||
/* wait for BSY in order to be sure that flash operation is ended before
|
||||
allowing prefetch in flash. Timeout does not return status, as it will
|
||||
be anyway done later */
|
||||
while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != 0U)
|
||||
{
|
||||
}
|
||||
|
||||
/* Exit critical section: restore previous priority mask */
|
||||
__set_PRIMASK(primask_bit);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,937 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_FLASH_H
|
||||
#define STM32WBxx_HAL_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Types FLASH Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Erase structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TypeErase; /*!< Mass erase or page erase.
|
||||
This parameter can be a value of @ref FLASH_TYPE_ERASE */
|
||||
uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled
|
||||
This parameter must be a value between 0 and (max number of pages - 1) */
|
||||
uint32_t NbPages; /*!< Number of pages to be erased.
|
||||
This parameter must be a value between 1 and (max number of pages - value of initial page)*/
|
||||
} FLASH_EraseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH Option Bytes Program structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OptionType; /*!< Option byte to be configured.
|
||||
This parameter can be a combination of the values of @ref FLASH_OB_TYPE */
|
||||
uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
|
||||
Only one WRP area could be programmed at the same time.
|
||||
This parameter can be value of @ref FLASH_OB_WRP_AREA */
|
||||
uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
|
||||
This parameter must be a value between 0 and (max number of pages - 1) */
|
||||
uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
|
||||
This parameter must be a value between WRPStartOffset and (max number of pages - 1) */
|
||||
uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP).
|
||||
This parameter can be a value of @ref FLASH_OB_READ_PROTECTION */
|
||||
uint32_t UserType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of @ref FLASH_OB_USER_TYPE */
|
||||
uint32_t UserConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
|
||||
This parameter can be a combination of the values of
|
||||
@ref FLASH_OB_USER_AGC_TRIM, @ref FLASH_OB_USER_BOR_LEVEL
|
||||
@ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
|
||||
@ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
|
||||
@ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
|
||||
@ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nBOOT1,
|
||||
@ref FLASH_OB_USER_SRAM2PE, @ref FLASH_OB_USER_SRAM2RST,
|
||||
@ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0 */
|
||||
uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
|
||||
This parameter must be a combination of values of @ref FLASH_OB_PCROP_ZONE
|
||||
and @ref FLASH_OB_PCROP_RDP */
|
||||
uint32_t PCROP1AStartAddr; /*!< PCROP Zone A Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
|
||||
to protect. Make sure this parameter is multiple of PCROP granularity */
|
||||
uint32_t PCROP1AEndAddr; /*!< PCROP Zone A End address (used for OPTIONBYTE_PCROP). It represents first address of end block
|
||||
to protect. Make sure this parameter is multiple of PCROP granularity */
|
||||
uint32_t PCROP1BStartAddr; /*!< PCROP Zone B Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
|
||||
to protect. Make sure this parameter is multiple of PCROP granularity */
|
||||
uint32_t PCROP1BEndAddr; /*!< PCROP Zone B End address (used for OPTIONBYTE_PCROP). It represents first address of end block
|
||||
to protect. Make sure this parameter is multiple of PCROP granularity */
|
||||
uint32_t SecureFlashStartAddr; /*!< Secure Flash start address (used for OPTIONBYTE_SFSA).
|
||||
This parameter must be a value between begin and end of bank
|
||||
=> Contains the start address of the first 4K page of the secure Flash area */
|
||||
uint32_t SecureRAM2aStartAddr; /*!< Secure Backup RAM2a start address (used for OPTIONBYTE_SBRSA).
|
||||
This parameter can be a value of @ref FLASH_SRAM2A_ADDRESS_RANGE */
|
||||
uint32_t SecureRAM2bStartAddr; /*!< Secure non-Backup RAM2b start address (used for OPTIONBYTE_SNBRSB)
|
||||
This parameter can be a value of @ref FLASH_SRAM2B_ADDRESS_RANGE */
|
||||
uint32_t SecureMode; /*!< Secure mode activated or desactivated.
|
||||
This parameter can be a value of @ref FLASH_OB_SECURITY_MODE */
|
||||
uint32_t C2BootRegion; /*!< CPU2 Secure Boot memory region(used for OPTIONBYTE_C2_BOOT_VECT).
|
||||
This parameter can be a value of @ref FLASH_OB_C2_BOOT_REGION */
|
||||
uint32_t C2SecureBootVectAddr; /*!< CPU2 Secure Boot reset vector (used for OPTIONBYTE_C2_BOOT_VECT).
|
||||
This parameter contains the CPU2 boot reset start address within
|
||||
the selected memory region. Make sure this parameter is word aligned. */
|
||||
uint32_t IPCCdataBufAddr; /*!< IPCC mailbox data buffer base address (used for OPTIONBYTE_IPCC_BUF_ADDR).
|
||||
This parameter contains the IPCC mailbox data buffer start address area in SRAM2 */
|
||||
} FLASH_OBProgramInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FLASH handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
HAL_LockTypeDef Lock; /* FLASH locking object */
|
||||
uint32_t ErrorCode; /* FLASH error code */
|
||||
uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
|
||||
uint32_t Address; /* Internal variable to save address selected for program in IT context */
|
||||
uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
|
||||
uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
|
||||
} FLASH_ProcessTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_KEYS FLASH Keys
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_KEY1 0x45670123U /*!< Flash key1 */
|
||||
#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1
|
||||
to unlock the FLASH registers access */
|
||||
|
||||
#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */
|
||||
#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1
|
||||
to allow option bytes operations */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_LATENCY FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 (FLASH_ACR_LATENCY_0WS) /*!< FLASH Zero wait state */
|
||||
#define FLASH_LATENCY_1 (FLASH_ACR_LATENCY_1WS) /*!< FLASH One wait state */
|
||||
#define FLASH_LATENCY_2 (FLASH_ACR_LATENCY_2WS) /*!< FLASH Two wait states */
|
||||
#define FLASH_LATENCY_3 (FLASH_ACR_LATENCY_3WS) /*!< FLASH Three wait states */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_FLAGS FLASH Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */
|
||||
#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */
|
||||
#define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */
|
||||
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */
|
||||
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
|
||||
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */
|
||||
#define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */
|
||||
#define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */
|
||||
#define FLASH_FLAG_OPTNV FLASH_SR_OPTNV /*!< FLASH User Option OPTVAL indication */
|
||||
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */
|
||||
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_CFGBSY FLASH_SR_CFGBSY /*!< FLASH Programming/erase configuration busy */
|
||||
#define FLASH_FLAG_PESD FLASH_SR_PESD /*!< FLASH Programming/erase operation suspended */
|
||||
#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */
|
||||
#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */
|
||||
|
||||
#define FLASH_FLAG_SR_ERROR (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
|
||||
FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
|
||||
FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
|
||||
FLASH_FLAG_OPTVERR) /*!< All SR error flags */
|
||||
|
||||
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERROR | FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
|
||||
|
||||
/** @defgroup FLASH_INTERRUPT_DEFINITION FLASH Interrupts Definition
|
||||
* @brief FLASH Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */
|
||||
#define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source */
|
||||
#define FLASH_IT_ECCC (FLASH_ECCR_ECCCIE >> FLASH_ECCR_ECCCIE_Pos) /*!< ECC Correction Interrupt source */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_ERROR FLASH Error
|
||||
* @{
|
||||
*/
|
||||
#define HAL_FLASH_ERROR_NONE 0x00000000U
|
||||
#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
|
||||
#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
|
||||
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
|
||||
#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
|
||||
#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
|
||||
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
|
||||
#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
|
||||
#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
|
||||
#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
|
||||
#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
|
||||
#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_TYPE_ERASE FLASH Erase Type
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASE_PAGES FLASH_CR_PER /*!< Pages erase only*/
|
||||
#define FLASH_TYPEERASE_MASSERASE FLASH_CR_MER /*!< Flash mass erase activation*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_TYPE_PROGRAM FLASH Program Type
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_DOUBLEWORD FLASH_CR_PG /*!< Program a double-word (64-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAM_FAST FLASH_CR_FSTPG /*!< Fast program a 64 row double-word (64-bit) at a specified address.
|
||||
And another 64 row double-word (64-bit) will be programmed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_TYPE FLASH Option Bytes Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP 0x00000001U /*!< WRP option byte configuration */
|
||||
#define OPTIONBYTE_RDP 0x00000002U /*!< RDP option byte configuration */
|
||||
#define OPTIONBYTE_USER 0x00000004U /*!< User option byte configuration */
|
||||
#define OPTIONBYTE_PCROP 0x00000008U /*!< PCROP option byte configuration */
|
||||
#define OPTIONBYTE_IPCC_BUF_ADDR 0x00000010U /*!< IPCC mailbox buffer address configuration */
|
||||
#define OPTIONBYTE_C2_BOOT_VECT 0x00000100U /*!< CPU2 Secure Boot reset vector */
|
||||
#define OPTIONBYTE_SECURE_MODE 0x00000200U /*!< Secure mode on activated or not */
|
||||
#define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \
|
||||
OPTIONBYTE_PCROP | OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | \
|
||||
OPTIONBYTE_SECURE_MODE) /*!< All option byte configuration */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_WRP_AREA FLASH WRP Area
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPAREA_BANK1_AREAA 0x00000000U /*!< Flash Area A */
|
||||
#define OB_WRPAREA_BANK1_AREAB 0x00000001U /*!< Flash Area B */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_READ_PROTECTION FLASH Option Bytes Read Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_LEVEL_0 0x000000AAU
|
||||
#define OB_RDP_LEVEL_1 0x000000BBU
|
||||
#define OB_RDP_LEVEL_2 0x000000CCU /*!< Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_USER_BOR_LEV (FLASH_OPTR_BOR_LEV) /*!< BOR reset Level */
|
||||
#define OB_USER_nRST_STOP (FLASH_OPTR_nRST_STOP) /*!< Reset generated when entering the stop mode */
|
||||
#define OB_USER_nRST_STDBY (FLASH_OPTR_nRST_STDBY) /*!< Reset generated when entering the standby mode */
|
||||
#define OB_USER_nRST_SHDW (FLASH_OPTR_nRST_SHDW) /*!< Reset generated when entering the shutdown mode */
|
||||
#define OB_USER_IWDG_SW (FLASH_OPTR_IWDG_SW) /*!< Independent watchdog selection */
|
||||
#define OB_USER_IWDG_STOP (FLASH_OPTR_IWDG_STOP) /*!< Independent watchdog counter freeze in stop mode */
|
||||
#define OB_USER_IWDG_STDBY (FLASH_OPTR_IWDG_STDBY) /*!< Independent watchdog counter freeze in standby mode */
|
||||
#define OB_USER_WWDG_SW (FLASH_OPTR_WWDG_SW) /*!< Window watchdog selection */
|
||||
#define OB_USER_nBOOT1 (FLASH_OPTR_nBOOT1) /*!< Boot configuration */
|
||||
#define OB_USER_SRAM2PE (FLASH_OPTR_SRAM2PE) /*!< SRAM2 parity check enable */
|
||||
#define OB_USER_SRAM2RST (FLASH_OPTR_SRAM2RST) /*!< SRAM2 erase when system reset */
|
||||
#define OB_USER_nSWBOOT0 (FLASH_OPTR_nSWBOOT0) /*!< Software BOOT0 */
|
||||
#define OB_USER_nBOOT0 (FLASH_OPTR_nBOOT0) /*!< nBOOT0 option bit */
|
||||
#define OB_USER_AGC_TRIM (FLASH_OPTR_AGC_TRIM) /*!< Automatic Gain Control Trimming */
|
||||
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \
|
||||
OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \
|
||||
OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \
|
||||
OB_USER_SRAM2PE | OB_USER_SRAM2RST | OB_USER_nSWBOOT0 | \
|
||||
OB_USER_nBOOT0 | OB_USER_AGC_TRIM) /*!< all option bits */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_AGC_TRIM FLASH Option Bytes Automatic Gain Control Trimming
|
||||
* @{
|
||||
*/
|
||||
#define OB_AGC_TRIM_0 0x00000000U /*!< Automatic Gain Control Trimming Value 0 */
|
||||
#define OB_AGC_TRIM_1 (FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 1 */
|
||||
#define OB_AGC_TRIM_2 (FLASH_OPTR_AGC_TRIM_1) /*!< Automatic Gain Control Trimming Value 2 */
|
||||
#define OB_AGC_TRIM_3 (FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 3 */
|
||||
#define OB_AGC_TRIM_4 (FLASH_OPTR_AGC_TRIM_2) /*!< Automatic Gain Control Trimming Value 4 */
|
||||
#define OB_AGC_TRIM_5 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 5 */
|
||||
#define OB_AGC_TRIM_6 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1) /*!< Automatic Gain Control Trimming Value 6 */
|
||||
#define OB_AGC_TRIM_7 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 7 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOR_LEVEL_0 0x00000000U /*!< Reset level threshold is around 1.7V */
|
||||
#define OB_BOR_LEVEL_1 (FLASH_OPTR_BOR_LEV_0) /*!< Reset level threshold is around 2.0V */
|
||||
#define OB_BOR_LEVEL_2 (FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.2V */
|
||||
#define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.5V */
|
||||
#define OB_BOR_LEVEL_4 (FLASH_OPTR_BOR_LEV_2) /*!< Reset level threshold is around 2.8V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */
|
||||
#define OB_STOP_NORST (FLASH_OPTR_nRST_STOP) /*!< No reset generated when entering the stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
|
||||
* @{
|
||||
*/
|
||||
#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */
|
||||
#define OB_STANDBY_NORST (FLASH_OPTR_nRST_STDBY) /*!< No reset generated when entering the standby mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
|
||||
* @{
|
||||
*/
|
||||
#define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */
|
||||
#define OB_SHUTDOWN_NORST (FLASH_OPTR_nRST_SHDW) /*!< No reset generated when entering the shutdown mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */
|
||||
#define OB_IWDG_SW (FLASH_OPTR_IWDG_SW) /*!< Software independent watchdog */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */
|
||||
#define OB_IWDG_STOP_RUN (FLASH_OPTR_IWDG_STOP) /*!< Independent watchdog counter is running in Stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */
|
||||
#define OB_IWDG_STDBY_RUN (FLASH_OPTR_IWDG_STDBY) /*!< Independent watchdog counter is running in Standby mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */
|
||||
#define OB_WWDG_SW (FLASH_OPTR_WWDG_SW) /*!< Software window watchdog */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SRAM2PE FLASH Option Bytes SRAM2 parity check
|
||||
* @{
|
||||
*/
|
||||
#define OB_SRAM2_PARITY_ENABLE 0x00000000U /*!< SRAM2 parity check enable */
|
||||
#define OB_SRAM2_PARITY_DISABLE (FLASH_OPTR_SRAM2PE) /*!< SRAM2 parity check disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_SRAM2RST FLASH Option Bytes SRAM2 erase when system reset
|
||||
* @{
|
||||
*/
|
||||
#define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset */
|
||||
#define OB_SRAM2_RST_NOT_ERASE (FLASH_OPTR_SRAM2RST) /*!< SRAM2 is not erased when a system reset */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM is selected as boot space (if BOOT0=1) */
|
||||
#define OB_BOOT1_SYSTEM (FLASH_OPTR_nBOOT1) /*!< System memory is selected as boot space (if BOOT0=1) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */
|
||||
#define OB_BOOT0_FROM_PIN (FLASH_OPTR_nSWBOOT0) /*!< BOOT0 taken from PH3/BOOT0 pin */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOOT0_RESET 0x0000000U /*!< nBOOT0 = 0 */
|
||||
#define OB_BOOT0_SET (FLASH_OPTR_nBOOT0) /*!< nBOOT0 = 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_PCROP_ZONE FLASH PCROP ZONE
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_ZONE_A 0x00000001U /*!< PCROP Zone A */
|
||||
#define OB_PCROP_ZONE_B 0x00000002U /*!< PCROP Zone B */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
|
||||
is decreased from Level 1 to Level 0 */
|
||||
#define OB_PCROP_RDP_ERASE (FLASH_PCROP1AER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is
|
||||
decreased from Level 1 to Level 0 (full mass erase) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_SECURITY_MODE Option Bytes FLASH Secure mode
|
||||
* @{
|
||||
*/
|
||||
#define SYSTEM_NOT_IN_SECURE_MODE 0x00000000U /*!< Unsecure mode: Security disabled */
|
||||
#define SYSTEM_IN_SECURE_MODE (FLASH_OPTR_ESE) /*!< Secure mode : Security enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_OB_C2_BOOT_REGION CPU2 Option Bytes Reset Boot Vector
|
||||
* @{
|
||||
*/
|
||||
#define OB_C2_BOOT_FROM_SRAM 0x00000000U /*!< CPU2 boot from Sram */
|
||||
#define OB_C2_BOOT_FROM_FLASH (FLASH_SRRVR_C2OPT) /*!< CPU2 boot from Flash */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_SRAM2A_ADDRESS_RANGE RAM2A address range in secure mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SRAM2A_START_SECURE_ADDR_0 0x20030000U /* When in secure mode 0x20030000 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_1 0x20030400U /* When in secure mode 0x20030400 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_2 0x20030800U /* When in secure mode 0x20030800 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_3 0x20030C00U /* When in secure mode 0x20030C00 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_4 0x20031000U /* When in secure mode 0x20031000 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_5 0x20031400U /* When in secure mode 0x20031400 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_6 0x20031800U /* When in secure mode 0x20031800 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_7 0x20031C00U /* When in secure mode 0x20031C00 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_8 0x20032000U /* When in secure mode 0x20032000 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_9 0x20032400U /* When in secure mode 0x20032400 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_10 0x20032800U /* When in secure mode 0x20032800 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_11 0x20032C00U /* When in secure mode 0x20032C00 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_12 0x20033000U /* When in secure mode 0x20033000 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_13 0x20033400U /* When in secure mode 0x20033400 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_14 0x20033800U /* When in secure mode 0x20033800 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_15 0x20033C00U /* When in secure mode 0x20033C00 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_16 0x20034000U /* When in secure mode 0x20034000 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_17 0x20034400U /* When in secure mode 0x20034400 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_18 0x20034800U /* When in secure mode 0x20034800 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_19 0x20034C00U /* When in secure mode 0x20034C00 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_20 0x20035000U /* When in secure mode 0x20035000 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_21 0x20035400U /* When in secure mode 0x20035400 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_22 0x20035800U /* When in secure mode 0x20035800 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_23 0x20035C00U /* When in secure mode 0x20035C00 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_24 0x20036000U /* When in secure mode 0x20036000 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_25 0x20036400U /* When in secure mode 0x20036400 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_26 0x20036800U /* When in secure mode 0x20036800 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_27 0x20036C00U /* When in secure mode 0x20036C00 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_28 0x20037000U /* When in secure mode 0x20037000 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_29 0x20037400U /* When in secure mode 0x20037400 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_30 0x20037800U /* When in secure mode 0x20037800 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_START_SECURE_ADDR_31 0x20037C00U /* When in secure mode 0x20037C00 - 0x20037FFF is accessible only by M0 Plus */
|
||||
#define SRAM2A_FULL_UNSECURE 0x20040000U /* The RAM2A is accessible to M0 Plus and M4 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_SRAM2B_ADDRESS_RANGE RAM2B address range in secure mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SRAM2B_START_SECURE_ADDR_0 0x20038000U /* When in secure mode 0x20038000 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_1 0x20038400U /* When in secure mode 0x20038400 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_2 0x20038800U /* When in secure mode 0x20038800 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_3 0x20038C00U /* When in secure mode 0x20038C00 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_4 0x20039000U /* When in secure mode 0x20039000 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_5 0x20039400U /* When in secure mode 0x20039400 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_6 0x20039800U /* When in secure mode 0x20039800 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_7 0x20039C00U /* When in secure mode 0x20039C00 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_8 0x2003A000U /* When in secure mode 0x2003A000 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_9 0x2003A400U /* When in secure mode 0x2003A400 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_10 0x2003A800U /* When in secure mode 0x2003A800 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_11 0x2003AC00U /* When in secure mode 0x2003AC00 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_12 0x2003B000U /* When in secure mode 0x2003B000 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_13 0x2003B400U /* When in secure mode 0x2003B400 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_14 0x2003B800U /* When in secure mode 0x2003B800 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_15 0x2003BC00U /* When in secure mode 0x2003BC00 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_16 0x2003C000U /* When in secure mode 0x2003C000 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_17 0x2003C400U /* When in secure mode 0x2003C400 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_18 0x2003C800U /* When in secure mode 0x2003C800 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_19 0x2003CC00U /* When in secure mode 0x2003CC00 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_20 0x2003D000U /* When in secure mode 0x2003D000 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_21 0x2003D400U /* When in secure mode 0x2003D400 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_22 0x2003D800U /* When in secure mode 0x2003D800 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_23 0x2003DC00U /* When in secure mode 0x2003DC00 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_24 0x2003E000U /* When in secure mode 0x2003E000 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_25 0x2003E400U /* When in secure mode 0x2003E400 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_26 0x2003E800U /* When in secure mode 0x2003E800 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_27 0x2003EC00U /* When in secure mode 0x2003EC00 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_28 0x2003F000U /* When in secure mode 0x2003F000 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_29 0x2003F400U /* When in secure mode 0x2003F400 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_30 0x2003F800U /* When in secure mode 0x2003F800 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_START_SECURE_ADDR_31 0x2003FC00U /* When in secure mode 0x2003FC00 - 0x2003FFFF is accessible only by M0 Plus */
|
||||
#define SRAM2B_FULL_UNSECURE 0x2003FF00U /* The RAM2B is accessible to M0 Plus and M4 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
|
||||
* @brief macros to control FLASH features
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the FLASH Latency.
|
||||
* @param __LATENCY__ FLASH Latency
|
||||
* This parameter can be one of the following values :
|
||||
* @arg @ref FLASH_LATENCY_0 FLASH Zero wait state
|
||||
* @arg @ref FLASH_LATENCY_1 FLASH One wait state
|
||||
* @arg @ref FLASH_LATENCY_2 FLASH Two wait states
|
||||
* @arg @ref FLASH_LATENCY_3 FLASH Three wait states
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
* @retval FLASH Latency
|
||||
* Returned value can be one of the following values :
|
||||
* @arg @ref FLASH_LATENCY_0 FLASH Zero wait state
|
||||
* @arg @ref FLASH_LATENCY_1 FLASH One wait state
|
||||
* @arg @ref FLASH_LATENCY_2 FLASH Two wait states
|
||||
* @arg @ref FLASH_LATENCY_3 FLASH Three wait states
|
||||
*/
|
||||
#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH instruction cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH instruction cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
|
||||
|
||||
/**
|
||||
* @brief Enable the FLASH data cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH data cache.
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
|
||||
|
||||
/**
|
||||
* @brief Reset the FLASH instruction Cache.
|
||||
* @note This function must be used only when the Instruction Cache is disabled.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
|
||||
CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @brief Reset the FLASH data Cache.
|
||||
* @note This function must be used only when the data Cache is disabled.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
|
||||
CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
|
||||
} while (0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
|
||||
* @brief macros to handle FLASH interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
|
||||
* @arg @ref FLASH_IT_OPERR Error Interrupt
|
||||
* @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt
|
||||
* @arg @ref FLASH_IT_ECCC ECC Correction Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\
|
||||
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the specified FLASH interrupt.
|
||||
* @param __INTERRUPT__ FLASH interrupt
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
|
||||
* @arg @ref FLASH_IT_OPERR Error Interrupt
|
||||
* @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt
|
||||
* @arg @ref FLASH_IT_ECCC ECC Correction Interrupt
|
||||
* @retval none
|
||||
*/
|
||||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\
|
||||
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified FLASH flag is set or not.
|
||||
* @param __FLAG__ specifies the FLASH flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag
|
||||
* @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag
|
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag
|
||||
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag
|
||||
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
|
||||
* @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag
|
||||
* @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
|
||||
* @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
|
||||
* @arg @ref FLASH_FLAG_OPTNV FLASH User Option OPTVAL indication
|
||||
* @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag
|
||||
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
|
||||
* @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag
|
||||
* @arg @ref FLASH_FLAG_CFGBSY Programming/erase configuration busy
|
||||
* @arg @ref FLASH_FLAG_PESD FLASH Programming/erase operation suspended
|
||||
* @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected
|
||||
* @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected
|
||||
* @retval The new state of FLASH_FLAG (SET or RESET).
|
||||
*/
|
||||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \
|
||||
(READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
|
||||
(READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
|
||||
/**
|
||||
* @brief Clear the FLASH's pending flags.
|
||||
* @param __FLAG__ specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag
|
||||
* @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag
|
||||
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag
|
||||
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag
|
||||
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
|
||||
* @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag
|
||||
* @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
|
||||
* @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
|
||||
* @arg @ref FLASH_FLAG_RDERR FLASH PCROP read error flag
|
||||
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
|
||||
* @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected
|
||||
* @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected
|
||||
* @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
|
||||
if(((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
|
||||
} while(0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include FLASH HAL Extended module */
|
||||
#include "stm32wbxx_hal_flash_ex.h"
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Variables FLASH Exported Variables
|
||||
* @{
|
||||
*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASH_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Program operation functions ***********************************************/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
|
||||
/* FLASH IRQ handler method */
|
||||
void HAL_FLASH_IRQHandler(void);
|
||||
/* Callbacks in non blocking modes */
|
||||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
|
||||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void);
|
||||
/* Option bytes control */
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup FLASH_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
uint32_t HAL_FLASH_GetError(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_types FLASH Private Types
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U)
|
||||
#define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U)
|
||||
|
||||
#define FLASH_BANK_SIZE FLASH_SIZE /*!< FLASH Bank Size */
|
||||
#define FLASH_PAGE_SIZE 0x00001000U /*!< FLASH Page Size, 4KBytes */
|
||||
#define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */
|
||||
|
||||
#define FLASH_WRP_GRANULARITY 0x00001000U /*!< FLASH Write Protection Granularity, 4KBytes */
|
||||
#define FLASH_PCROP_GRANULARITY 0x00000800U /*!< FLASH Code Readout Protection Granularity, 2KBytes */
|
||||
#define FLASH_SECURE_PAGE_GRANULARITY 0x00001000U /*!< FLASH Code Readout Protection Granularity, 4KBytes */
|
||||
|
||||
#define FLASH_TYPENONE 0x00000000u /*!< No Programming Procedure On Going */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SRAM_MEMORY_SIZE SRAM memory size
|
||||
* @{
|
||||
*/
|
||||
#define SRAM_SECURE_PAGE_GRANULARITY 0x00000400U /*!< Secure SRAM2A and SRAM2B Protection Granularity, 1KBytes */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
|
||||
|
||||
#define IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL))
|
||||
|
||||
#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
|
||||
|
||||
#define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
|
||||
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) ((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__)) || (IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__)))
|
||||
|
||||
#define IS_FLASH_PAGE(__VALUE__) ((__VALUE__) <= 0xFFU)
|
||||
|
||||
#define IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & ~0x7U) == (__VALUE__))
|
||||
|
||||
#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \
|
||||
((__VALUE__) == FLASH_TYPEERASE_MASSERASE))
|
||||
|
||||
#define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
|
||||
((__VALUE__) == FLASH_TYPEPROGRAM_FAST))
|
||||
|
||||
#define IS_OB_BOOT_VECTOR_ADDR(__VALUE__) ((((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1U))) || \
|
||||
(((__VALUE__) >= SRAM1_BASE) && ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE - 1U))) || \
|
||||
(((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U))) || \
|
||||
(((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U))))
|
||||
|
||||
#define IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM))
|
||||
|
||||
#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)0xFFFU) == (__VALUE__)))
|
||||
#define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
|
||||
#define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
|
||||
#define IS_OB_SECURE_MODE(__VALUE__) (((__VALUE__) == SYSTEM_IN_SECURE_MODE) || ((__VALUE__) == SYSTEM_NOT_IN_SECURE_MODE))
|
||||
|
||||
#define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \
|
||||
OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE)))
|
||||
|
||||
#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) || ((__VALUE__) == OB_WRPAREA_BANK1_AREAB))
|
||||
|
||||
#define IS_OB_RDP_LEVEL(__VALUE__) (((__VALUE__) == OB_RDP_LEVEL_0) ||\
|
||||
((__VALUE__) == OB_RDP_LEVEL_1) ||\
|
||||
((__VALUE__) == OB_RDP_LEVEL_2))
|
||||
|
||||
#define IS_OB_USER_TYPE(__VALUE__) ((((__VALUE__) & OB_USER_ALL) != 0U) && \
|
||||
(((__VALUE__) & ~OB_USER_ALL) == 0U))
|
||||
|
||||
#define IS_OB_USER_CONFIG(__TYPE__, __VALUE__) ((((__TYPE__) & OB_USER_BOR_LEV) == OB_USER_BOR_LEV) \
|
||||
? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \
|
||||
: ((((__TYPE__) & OB_USER_AGC_TRIM) == OB_USER_AGC_TRIM) \
|
||||
? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_0) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_1) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_2) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_3) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_4) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_5) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_6) || \
|
||||
(((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_AGC_TRIM)) == OB_AGC_TRIM_7)) \
|
||||
: ((~(__TYPE__) & (__VALUE__)) == 0U)))
|
||||
|
||||
#define IS_OB_USER_AGC_TRIMMING(__VALUE__) (((__VALUE__) == OB_AGC_TRIM_0) || ((__VALUE__) == OB_AGC_TRIM_1) || \
|
||||
((__VALUE__) == OB_AGC_TRIM_2) || ((__VALUE__) == OB_AGC_TRIM_3) || \
|
||||
((__VALUE__) == OB_AGC_TRIM_4) || ((__VALUE__) == OB_AGC_TRIM_5) || \
|
||||
((__VALUE__) == OB_AGC_TRIM_6) || ((__VALUE__) == OB_AGC_TRIM_7))
|
||||
|
||||
#define IS_OB_USER_BOR_LEVEL(__VALUE__) (((__VALUE__) == OB_BOR_LEVEL_0) || ((__VALUE__) == OB_BOR_LEVEL_1) || \
|
||||
((__VALUE__) == OB_BOR_LEVEL_2) || ((__VALUE__) == OB_BOR_LEVEL_3) || \
|
||||
((__VALUE__) == OB_BOR_LEVEL_4))
|
||||
|
||||
#define IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U)
|
||||
|
||||
#define IS_OB_SECURE_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_SECURE_CONFIG_MEMORY | OB_SECURE_CONFIG_BOOT_RESET)) == 0U)
|
||||
|
||||
#define IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__))
|
||||
|
||||
#define IS_FLASH_LATENCY(__VALUE__) (((__VALUE__) == FLASH_LATENCY_0) || \
|
||||
((__VALUE__) == FLASH_LATENCY_1) || \
|
||||
((__VALUE__) == FLASH_LATENCY_2) || \
|
||||
((__VALUE__) == FLASH_LATENCY_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_FLASH_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,115 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of FLASH HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_FLASH_EX_H
|
||||
#define STM32WBxx_HAL_FLASH_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASHEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */
|
||||
#define FLASH_PROG_EMPTY FLASH_ACR_EMPTY /*!< 1st location in Flash is empty */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup FLASHEx_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Extended Program operation functions *************************************/
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
|
||||
uint32_t HAL_FLASHEx_FlashEmptyCheck(void);
|
||||
void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty);
|
||||
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
void HAL_FLASHEx_SuspendOperation(void);
|
||||
void HAL_FLASHEx_AllowOperation(void);
|
||||
uint32_t HAL_FLASHEx_IsOperationSuspended(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
|
||||
* @{
|
||||
*/
|
||||
void FLASH_PageErase(uint32_t Page);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_FLASH_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,532 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @brief GPIO HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### GPIO Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
|
||||
configured by software in several modes:
|
||||
(++) Input mode
|
||||
(++) Analog mode
|
||||
(++) Output mode
|
||||
(++) Alternate function mode
|
||||
(++) External interrupt/event lines
|
||||
|
||||
(+) During and just after reset, the alternate functions and external interrupt
|
||||
lines are not active and the I/O ports are configured in input floating mode.
|
||||
|
||||
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
|
||||
activated or not.
|
||||
|
||||
(+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
|
||||
type and the IO speed can be selected depending on the VDD value.
|
||||
|
||||
(+) The microcontroller IO pins are connected to onboard peripherals/modules through a
|
||||
multiplexer that allows only one peripheral alternate function (AF) connected
|
||||
to an IO pin at a time. In this way, there can be no conflict between peripherals
|
||||
sharing the same IO pin.
|
||||
|
||||
(+) All ports have external interrupt/event capability. To use external interrupt
|
||||
lines, the port must be configured in input mode. All available GPIO pins are
|
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
|
||||
|
||||
(+) The external interrupt/event controller consists of up to 28 edge detectors
|
||||
(16 lines are connected to GPIO) for generating event/interrupt requests (each
|
||||
input line can be independently configured to select the type (interrupt or event)
|
||||
and the corresponding trigger event (rising or falling or both). Each line can
|
||||
also be masked independently.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
|
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
|
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
|
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
|
||||
structure.
|
||||
(++) In case of Output or alternate function mode selection: the speed is
|
||||
configured through "Speed" member from GPIO_InitTypeDef structure.
|
||||
(++) In alternate mode is selection, the alternate function connected to the IO
|
||||
is configured through "Alternate" member from GPIO_InitTypeDef structure.
|
||||
(++) Analog mode is required when a pin is to be used as ADC channel
|
||||
or DAC output.
|
||||
(++) In case of external interrupt/event selection the "Mode" member from
|
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and
|
||||
the corresponding trigger event (rising or falling or both).
|
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
|
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
|
||||
HAL_NVIC_EnableIRQ().
|
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
|
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
/** MISRA C:2012 deviation rule has been granted for following rules:
|
||||
* Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of
|
||||
* range of the shift operator in following API :
|
||||
* HAL_GPIO_Init
|
||||
* HAL_GPIO_DeInit
|
||||
*/
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Constants GPIO Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE (0x00000003u)
|
||||
#define EXTI_MODE (0x10000000u)
|
||||
#define GPIO_MODE_IT (0x00010000u)
|
||||
#define GPIO_MODE_EVT (0x00020000u)
|
||||
#define RISING_EDGE (0x00100000u)
|
||||
#define FALLING_EDGE (0x00200000u)
|
||||
#define GPIO_OUTPUT_TYPE (0x00000010u)
|
||||
|
||||
#define GPIO_NUMBER (16u)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
|
||||
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
|
||||
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||
{
|
||||
uint32_t position = 0x00u;
|
||||
uint32_t iocurrent;
|
||||
uint32_t temp;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Configure the port pins */
|
||||
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
||||
|
||||
if (iocurrent != 0x00u)
|
||||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Alternate function mode selection */
|
||||
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{
|
||||
/* Check the Alternate function parameters */
|
||||
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||
|
||||
/* Configure Alternate function mapped with the current IO */
|
||||
temp = GPIOx->AFR[position >> 3u];
|
||||
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
||||
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
||||
GPIOx->AFR[position >> 3u] = temp;
|
||||
}
|
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||
temp = GPIOx->MODER;
|
||||
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
|
||||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
||||
GPIOx->MODER = temp;
|
||||
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
||||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
||||
temp |= (GPIO_Init->Speed << (position * 2u));
|
||||
GPIOx->OSPEEDR = temp;
|
||||
|
||||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
||||
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4u) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
|
||||
temp |= ((GPIO_Init->Pull) << (position * 2u));
|
||||
GPIOx->PUPDR = temp;
|
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
||||
{
|
||||
temp = SYSCFG->EXTICR[position >> 2u];
|
||||
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
||||
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
||||
SYSCFG->EXTICR[position >> 2u] = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI->IMR1;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->IMR1 = temp;
|
||||
|
||||
temp = EXTI->EMR1;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->EMR1 = temp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR1;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->RTSR1 = temp;
|
||||
|
||||
temp = EXTI->FTSR1;
|
||||
temp &= ~(iocurrent);
|
||||
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
||||
{
|
||||
temp |= iocurrent;
|
||||
}
|
||||
EXTI->FTSR1 = temp;
|
||||
}
|
||||
}
|
||||
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-initialize the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint32_t position = 0x00u;
|
||||
uint32_t iocurrent;
|
||||
uint32_t tmp;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Configure the port pins */
|
||||
while ((GPIO_Pin >> position) != 0x00u)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Pin) & (1uL << position);
|
||||
|
||||
if (iocurrent != 0x00u)
|
||||
{
|
||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||
/* Clear the External Interrupt or Event for the current IO */
|
||||
|
||||
tmp = SYSCFG->EXTICR[position >> 2u];
|
||||
tmp &= (0x0FUL << (4u * (position & 0x03u)));
|
||||
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))))
|
||||
{
|
||||
tmp = 0x0FuL << (4u * (position & 0x03u));
|
||||
SYSCFG->EXTICR[position >> 2u] &= ~tmp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR1 &= ~(iocurrent);
|
||||
EXTI->EMR1 &= ~(iocurrent);
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR1 &= ~(iocurrent);
|
||||
EXTI->FTSR1 &= ~(iocurrent);
|
||||
}
|
||||
|
||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||
/* Configure IO in Analog Mode */
|
||||
GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2u));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
GPIOx->AFR[position >> 3u] &= ~(0xFu << ((position & 0x07u) * 4u)) ;
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
||||
|
||||
/* Configure the default value IO Output Type */
|
||||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
|
||||
|
||||
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2u));
|
||||
}
|
||||
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2
|
||||
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read the specified input port pin.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WBxx family
|
||||
* @param GPIO_Pin specifies the port bit to read.
|
||||
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIO_PinState bitstatus;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != 0x00u)
|
||||
{
|
||||
bitstatus = GPIO_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = GPIO_PIN_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set or clear the selected data port bit.
|
||||
*
|
||||
* @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
*
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WBxx family
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @param PinState specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the GPIO_PinState enum values:
|
||||
* @arg GPIO_PIN_RESET: to clear the port pin
|
||||
* @arg GPIO_PIN_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||||
|
||||
if(PinState != GPIO_PIN_RESET)
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle the specified GPIO pin.
|
||||
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
|
||||
* @param GPIO_Pin specifies the pin to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin)
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRR = GPIO_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
|
||||
* @param GPIO_Pin specifies the port bits to be locked.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Apply lock key write sequence */
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
|
||||
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
|
||||
{
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request.
|
||||
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* EXTI line interrupt detected */
|
||||
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
|
||||
{
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI line detection callback.
|
||||
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(GPIO_Pin);
|
||||
|
||||
/* NOTE: This function should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,301 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_GPIO_H
|
||||
#define STM32WBxx_HAL_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Types GPIO Exported Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_mode */
|
||||
|
||||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_pull */
|
||||
|
||||
uint32_t Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIO_speed */
|
||||
|
||||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
|
||||
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PIN_RESET = 0U,
|
||||
GPIO_PIN_SET
|
||||
}GPIO_PinState;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup GPIO_pins GPIO pins
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_mode GPIO mode
|
||||
* @brief GPIO Configuration Mode
|
||||
* Elements values convention: 0xX0yz00YZ
|
||||
* - X : GPIO mode or EXTI Mode
|
||||
* - y : External IT or Event trigger detection
|
||||
* - z : IO configuration on External IT or Event
|
||||
* - Y : Output type (Push Pull or Open Drain)
|
||||
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT (0x00000000u) /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (0x00000001u) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (0x00000011u) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (0x00000002u) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (0x00000012u) /*!< Alternate Function Open Drain Mode */
|
||||
#define GPIO_MODE_ANALOG (0x00000003u) /*!< Analog Mode */
|
||||
#define GPIO_MODE_IT_RISING (0x10110000u) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (0x10210000u) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (0x10310000u) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING (0x10120000u) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (0x10220000u) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (0x10320000u) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_speed GPIO speed
|
||||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW (0x00000000u) /*!< Low speed */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001u) /*!< Medium speed */
|
||||
#define GPIO_SPEED_FREQ_HIGH (0x00000002u) /*!< High speed */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003u) /*!< Very high speed */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pull GPIO pull
|
||||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL (0x00000000u) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP (0x00000001u) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN (0x00000002u) /*!< Pull-down activation */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line flag is set or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending flags.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified EXTI line is asserted or not.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval The new state of __EXTI_LINE__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Clear the EXTI's line pending bits.
|
||||
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @param __EXTI_LINE__ specifies the EXTI line to check.
|
||||
* This parameter can be GPIO_PIN_x where x can be(0..15)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Private_Macros GPIO Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
|
||||
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
|
||||
(((__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
|
||||
|
||||
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_PP) ||\
|
||||
((__MODE__) == GPIO_MODE_AF_OD) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
|
||||
((__MODE__) == GPIO_MODE_ANALOG))
|
||||
|
||||
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
|
||||
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
|
||||
|
||||
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
|
||||
((__PULL__) == GPIO_PULLUP) || \
|
||||
((__PULL__) == GPIO_PULLDOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include GPIO HAL Extended module */
|
||||
#include "stm32wbxx_hal_gpio_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
|
||||
* @brief GPIO Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
|
||||
* @brief IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
|
||||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_GPIO_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,408 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of GPIO HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_GPIO_EX_H
|
||||
#define STM32WBxx_HAL_GPIO_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx GPIOEx
|
||||
* @brief GPIO Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* The table below gives an overview of the different alternate functions per port.
|
||||
* For more details refer yourself to the product data sheet.
|
||||
*
|
||||
*/
|
||||
|
||||
/* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
|
||||
*_____________________________________________________________________________________________
|
||||
* |SYS_AF |TIM |TIM |SPI/SAI/TI|I2C | I2C | RF | USART |
|
||||
*_____________________________________________________________________________________________
|
||||
* PA0 | |TIM2_CH1 | | | | |RF_DTB2 | |
|
||||
* PA1 | |TIM2_CH2 | | |I2C1_SMBA |SPI1_SCK |RF_DTB3 | |
|
||||
* PA2 | |TIM2_CH3 | | | | |RF_DTB4 | |
|
||||
* PA3 | |TIM2_CH4 | |SAI1_CK1 | | |RF_DTB5 | |
|
||||
* PA4 | | | | | |SPI1_NSS |RF_DTB6 | |
|
||||
* PA5 | |TIM2_CH1 |TIM2_ETR | | |SPI1_SCK |RF_DTB7 | |
|
||||
* PA6 | |TIM1_BKIN | | | |SPI1_MISO |RF_DTB8 | |
|
||||
* PA7 | |TIM1_CH1N | | |I2C3_SCL |SPI1_MOSI |RF_DTB9 | |
|
||||
* PA8 |MCO |TIM1_CH1 | |SAI1_CK2 | | |RF_DTB12 |USART1_CK |
|
||||
* PA9 | |TIM2_CH2 | |SAI1_DI2 |I2C1_SCL |SPI2_SCK |RF_DTB13 |USART1_TX |
|
||||
* PA10| |TIM2_CH3 | |SAI1_DI1 |I2C1_SDA | |RF_DTB14 |USART1_RX |
|
||||
* PA11| |TIM2_CH4 |TIM1_BKIN2| | |SPI1_MISO |RF_DTB15 |USART1_CTS|
|
||||
* PA12| |TIM2_ETR | | | |SPI1_MOSI |RF_MISO |USART1_RTS|
|
||||
* PA13|JTMS_SWDIO| | | | | | | |
|
||||
* PA14|JTCK_SWCLK|LPTIM1_OUT| | |I2C1_SMBA | | | |
|
||||
* PA15|JTDI |TIM2_CH1 |TIM2_ETR | | |SPI1_NSS | | |
|
||||
*______________________________________________________________________________________________
|
||||
* PB0 | | | | | | | | |
|
||||
* PB1 | | | | | | | | |
|
||||
* PB2 |RTC_OUT |LPTIM1_OUT| | |I2C3_SMBA |SPI1_NSS |RF_DTB10 | |
|
||||
* PB3 |JTDO |TIM2_CH2 | | | |SPI1_SCK | |USART1_RTS|
|
||||
* PB4 |NJTRST | | | |I2C3_SDA |SPI1_MISO | |USART1_CTS|
|
||||
* PB5 | |LPTIM1_IN1| | |I2C1_SMBA |SPI1_MOSI |RF_MOSI |USART1_CK |
|
||||
* PB6 | |LPTIM1_ETR| | |I2C1_SCL | |RF_SCK |USART1_TX |
|
||||
* PB7 | |LPTIM1_IN2| |TIM1_BKIN |I2C1_SDA | |RF_DTB11 |USART1_RX |
|
||||
* PB8 | |TIM1_CH2N | |SAI1_CK1 |I2C1_SCL | |RF_DTB16 | |
|
||||
* PB9 | |TIM1_CH3N | |SAI1_DI2 |I2C1_SDA |SPI2_NSS | | |
|
||||
* PB10| |TIM2_CH3 | | |I2C3_SCL |SPI2_SCK |RF_DTB18 | |
|
||||
* PB11| |TIM2_CH4 | | |I2C3_SDA | |RF_DTB17 | |
|
||||
* PB12| |TIM1_BKIN | |TIM1_BKIN |I2C3_SMBA |SPI2_NSS | | |
|
||||
* PB13| |TIM1_CH1N | | |I2C3_SCL |SPI2_SCK | | |
|
||||
* PB14| |TIM1_CH2N | | |I2C3_SDA |SPI2_MISO | | |
|
||||
* PB15|RTC_REFIN |TIM1_CH3N | | | |SPI2_MOSI | | |
|
||||
*______________________________________________________________________________________________
|
||||
* PC0 | |LPTIM1_IN1| | |I2C3_SCL | | | |
|
||||
* PC1 | |LPTIM1_OUT| |SPI2_MOSI |I2C3_SDA | | | |
|
||||
* PC2 | |LPTIM1_IN2| | | |SPI2_MISO | | |
|
||||
* PC3 | |LPTIM1_ETR| |SAI1_DI1 | |SPI2_MOSI | | |
|
||||
* PC4 | | | | | | | | |
|
||||
* PC5 | | | |SAI1_DI3 | | | | |
|
||||
* PC6 | | | | | | | | |
|
||||
* PC7 | | | | | | | | |
|
||||
* PC8 | | | | | | | | |
|
||||
* PC9 | | | |TIM1_BKIN | | | | |
|
||||
* PC10|TRACED1 | | | | | | | |
|
||||
* PC11| | | | | | | | |
|
||||
* PC12|TRACED3 | | | | | | | |
|
||||
* PC13| | | | | | | | |
|
||||
* PC14| | | | | | |RF_DTB0 | |
|
||||
* PC15| | | | | | |RF_DTB1 | |
|
||||
*______________________________________________________________________________________________
|
||||
* PD0 | | | | | |SPI2_NSS | | |
|
||||
* PD1 | | | | | |SPI2_SCK | | |
|
||||
* PD2 |TRACED2 | | | | | | | |
|
||||
* PD3 | | | |SPI2_SCK | |SPI2_MISO | | |
|
||||
* PD4 | | | | | |SPI2_MOSI | | |
|
||||
* PD5 | | | | | | | | |
|
||||
* PD6 | | | |SAI1_DI1 | | | | |
|
||||
* PD7 | | | | | | | | |
|
||||
* PD8 | | |TIM1_BKIN2| | | | | |
|
||||
* PD9 |TRACED0 | | | | | | | |
|
||||
* PD10|TRIG_IO | | | | | | | |
|
||||
* PD11| | | | | | | | |
|
||||
* PD12| | | | | | | | |
|
||||
* PD13| | | | | | | | |
|
||||
* PD14| |TIM1_CH1 | | | | | | |
|
||||
* PD15| |TIM1_CH2 | | | | | | |
|
||||
*______________________________________________________________________________________________
|
||||
* PE0 | |TIM1_ETR | | | | | | |
|
||||
* PE1 | | | | | | | | |
|
||||
* PE2 |TRACED2 | | |SAI1_CK1 | | | | |
|
||||
* PE3 | | | | | | | | |
|
||||
* PE4 | | | | | | | | |
|
||||
*______________________________________________________________________________________________
|
||||
* PH0 | | | | | | | | |
|
||||
* PH1 | | | | | | | | |
|
||||
* PE2 | | | | | | | | |
|
||||
* PH3 | | | | | | |RF_NSS | |
|
||||
*______________________________________________________________________________________________*/
|
||||
|
||||
|
||||
/* | AF8 | AF9 | AF10 | AF11 | AF12 | AF13 | AF14 | AF15 |
|
||||
*_____________________________________________________________________________________________
|
||||
* |LPUART1 |TSC |USB/QUADSP|LCD |COMP/TIM |SAI |TIM |EVENTOUT |
|
||||
*_____________________________________________________________________________________________
|
||||
* PA0 | | | | |COMP1_OUT |SAI1_E_CLK|TIM2_ETR |EVENTOUT |
|
||||
* PA1 | | | |LCD_SEG0 | | | |EVENTOUT |
|
||||
* PA2 |LPUART1_TX| |QSPI_NCS |LCD_SEG1 |COMP2_OUT | | |EVENTOUT |
|
||||
* PA3 |LPUART1_RX| |QSPI_CLK |LCD_SEG2 | |SAI1_CLK_A| |EVENTOUT |
|
||||
* PA4 | | | | | |SAI1_FS_B |LPTIM2_OUT|EVENTOUT |
|
||||
* PA5 | | | | | | |LPTIM2_ETR|EVENTOUT |
|
||||
* PA6 |LPUART1_CT| |QSPI_IO3 |LCD_SEG3 |TIM1_BKIN | |TIM16_CH1 |EVENTOUT |
|
||||
* PA7 | | |QSPI_IO2 |LCD_SEG4 |COMP2_OUT | |TIM17_CH1 |EVENTOUT |
|
||||
* PA8 | | | |LCD_COM0 | |SAI1_SCK_A|LPTIM2_OUT|EVENTOUT |
|
||||
* PA9 | | | |LCD_COM1 | |SAI1_FS_A | |EVENTOUT |
|
||||
* PA10| | |USB_CRS_SY|LCD_COM2 | |SAI1_SD_A |TIM17_BKIN|EVENTOUT |
|
||||
* PA11| | |USB_DM | |TIM1_BKIN2| | |EVENTOUT |
|
||||
* PA12| | |USB_DP | | | | |EVENTOUT |
|
||||
* PA13|IR_OUT | |USB_NOE | | |SAI1_SD_B | |EVENTOUT |
|
||||
* PA14| | | | | |SAI1_FS_B | |EVENTOUT |
|
||||
* PA15| |TSC_G3_IO1| |LCD_SEG17 | | | |EVENTOUT |
|
||||
*______________________________________________________________________________________________
|
||||
* PB0 | | | |LCD_SEG5 |COMP1_OUT | | |EVENTOUT |
|
||||
* PB1 |LPUART1_RT| | |LCD_SEG6 | | |LPTIM2_IN1|EVENTOUT |
|
||||
* PB2 | | | |LCD_VLCD | |SAI1_E_CLK| |EVENTOUT |
|
||||
* PB3 | | | |LCD_SEG7 | |SAI1_SCK_B| |EVENTOUT |
|
||||
* PB4 | |TSC_G2_IO1| |LCD_SEG8 | |SAI1_CLK_B|TIM17_BKIN|EVENTOUT |
|
||||
* PB5 | |TSC_G2_IO2| |LCD_SEG9 |COMP2_OUT |SAI1_SD_B |TIM16_BKIN|EVENTOUT |
|
||||
* PB6 | |TSC_G2_IO3| | | |SAI1_FS_B |TIM16_CH1N|EVENTOUT |
|
||||
* PB7 | |TSC_G2_IO4| |LCD_SEG21 | | |TIM17_CH1N|EVENTOUT |
|
||||
* PB8 | | |QSPI_IO1 |LCD_SEG16 | |SAI1_CLK_A|TIM16_CH1 |EVENTOUT |
|
||||
* PB9 |IR_OUT |TSC_G7_IO4|QSPI_IO0 |LCD_COM3 | |SAI1_FS_A |TIM17_CH1 |EVENTOUT |
|
||||
* PB10|LPUART1_RX|TSC_SYNC |QSPI_CLK |LCD_SEG10 |COMP1_OUT |SAI1_SCK_A| |EVENTOUT |
|
||||
* PB11|LPUART1_TX| |QSPI_NCS |LCD_SEG11 |COMP2_OUT | | |EVENTOUT |
|
||||
* PB12|LPUART1_RT|TSC_G1_IO1| |LCD_SEG12 | |SAI1_FS_A | |EVENTOUT |
|
||||
* PB13|LPUART1_CT|TSC_G1_IO2| |LCD_SEG13 | |SAI1_SCK_A| |EVENTOUT |
|
||||
* PB14| |TSC_G1_IO3| |LCD_SEG14 | |SAI1_CLK_A| |EVENTOUT |
|
||||
* PB15| |TSC_G1_IO4| |LCD_SEG15 | |SAI1_SD_A | |EVENTOUT |
|
||||
*______________________________________________________________________________________________
|
||||
* PC0 |LPUART1_RX| | |LCD_SEG18 | | |LPTIM2_IN1|EVENTOUT |
|
||||
* PC1 |LPUART1_TX| | |LCD_SEG19 | | | |EVENTOUT |
|
||||
* PC2 | | | |LCD_SEG20 | | | |EVENTOUT |
|
||||
* PC3 | | | |LCD_VLCD | |SAI1_SD_A |LPTIM2_ETR|EVENTOUT |
|
||||
* PC4 | | | |LCD_SEG22 | | | |EVENTOUT |
|
||||
* PC5 | | | |LCD_SEG23 | | | |EVENTOUT |
|
||||
* PC6 | |TSC_G4_IO1| |LCD_SEG24 | | | |EVENTOUT |
|
||||
* PC7 | |TSC_G4_IO2| |LCD_SEG25 | | | |EVENTOUT |
|
||||
* PC8 | |TSC_G4_IO3| |LCD_SEG26 | | | |EVENTOUT |
|
||||
* PC9 | |TSC_G4_IO4|USB_NOE |LCD_SEG27 | |SAI1_SCK_B| |EVENTOUT |
|
||||
* PC10| |TSC_G3_IO2| |LCD_Cx_SEx| | | |EVENTOUT |
|
||||
* PC11| |TSC_G3_IO3| |LCD_Cx_SEx| | | |EVENTOUT |
|
||||
* PC12| |TSC_G3_IO4| |LCD_Cx_SEx| | | |EVENTOUT |
|
||||
* PC13| | | | | | | |EVENTOUT |
|
||||
* PC14| | | | | | | |EVENTOUT |
|
||||
* PC15| | | | | | | |EVENTOUT |
|
||||
*______________________________________________________________________________________________
|
||||
* PD0 | | | | | | | |EVENTOUT |
|
||||
* PD1 | | | | | | | |EVENTOUT |
|
||||
* PD2 | |TSC_SYNC | |LCD_Cx_SEx| | | |EVENTOUT |
|
||||
* PD3 | | |QSPI_NCS | | | | |EVENTOUT |
|
||||
* PD4 | |TSC_G5_IO1|QSPI_IO0 | | | | |EVENTOUT |
|
||||
* PD5 | |TSC_G5_IO2|QSPI_IO1 | | |SAI1_CLK_B| |EVENTOUT |
|
||||
* PD6 | |TSC_G5_IO3|QSPI_IO2 | | |SAI1_SD_A | |EVENTOUT |
|
||||
* PD7 | |TSC_G5_IO4|QSPI_IO3 |LCD_SEG39 | | | |EVENTOUT |
|
||||
* PD8 | | | |LCD_SEG28 | | | |EVENTOUT |
|
||||
* PD9 | | | |LCD_SEG29 | | | |EVENTOUT |
|
||||
* PD10| |TSC_G6_IO1| |LCD_SEG30 | | | |EVENTOUT |
|
||||
* PD11| |TSC_G6_IO2| |LCD_SEG31 | | |LPTIM2_ETR|EVENTOUT |
|
||||
* PD12| |TSC_G6_IO3| |LCD_SEG32 | | |LPTIM2_IN1|EVENTOUT |
|
||||
* PD13| |TSC_G6_IO4| |LCD_SEG33 | | |LPTIM2_OUT|EVENTOUT |
|
||||
* PD14| | | |LCD_SEG34 | | | |EVENTOUT |
|
||||
* PD15| | | |LCD_SEG35 | | | |EVENTOUT |
|
||||
*______________________________________________________________________________________________
|
||||
* PE0 | |TSC_G7_IO3| |LCD_SEG36 | | |TIM16_CH1 |EVENTOUT |
|
||||
* PE1 | |TSC_G7_IO2| |LCD_SEG37 | | |TIM17_CH1 |EVENTOUT |
|
||||
* PE2 | |TSC_G7_IO1| |LCD_SEG38 | |SAI1_CLK_A| |EVENTOUT |
|
||||
* PE3 | | | | | | | |EVENTOUT |
|
||||
* PE4 | | | | | | | |EVENTOUT |
|
||||
*______________________________________________________________________________________________
|
||||
* PH0 | | | | | | | |EVENTOUT |
|
||||
* PH1 | | | | | | | |EVENTOUT |
|
||||
* PE2 | | | | | | | |EVENTOUT |
|
||||
* PH3 | | | | | | | |EVENTOUT |
|
||||
*______________________________________________________________________________________________*/
|
||||
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
|
||||
#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF0_LSCO ((uint8_t)0x00) /*!< LSCO Alternate Function mapping */
|
||||
#define GPIO_AF0_JTMS_SWDIO ((uint8_t)0x00) /*!< JTMS-SWDIO Alternate Function mapping */
|
||||
#define GPIO_AF0_JTCK_SWCLK ((uint8_t)0x00) /*!< JTCK-SWCLK Alternate Function mapping */
|
||||
#define GPIO_AF0_JTDI ((uint8_t)0x00) /*!< JTDI Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC_OUT ((uint8_t)0x00) /*!< RCT_OUT Alternate Function mapping */
|
||||
#define GPIO_AF0_JTD_TRACE ((uint8_t)0x00) /*!< JTDO-TRACESWO Alternate Function mapping */
|
||||
#define GPIO_AF0_NJTRST ((uint8_t)0x00) /*!< NJTRST Alternate Function mapping */
|
||||
#define GPIO_AF0_RTC_REFIN ((uint8_t)0x00) /*!< RTC_REFIN Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED0 ((uint8_t)0x00) /*!< TRACED0 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED1 ((uint8_t)0x00) /*!< TRACED1 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED2 ((uint8_t)0x00) /*!< TRACED2 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACED3 ((uint8_t)0x00) /*!< TRACED3 Alternate Function mapping */
|
||||
#define GPIO_AF0_TRIG_INOUT ((uint8_t)0x00) /*!< TRIG_INOUT Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACECK ((uint8_t)0x00) /*!< TRACECK Alternate Function mapping */
|
||||
#define GPIO_AF0_SYS ((uint8_t)0x00) /*!< System Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /*!< TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /*!< LPTIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
|
||||
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /*!< TIM1 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF3_SAI1 ((uint8_t)0x03) /*!< SAI1_CK1 Alternate Function mapping */
|
||||
#define GPIO_AF3_SPI2 ((uint8_t)0x03) /*!< SPI2 Alternate Function mapping */
|
||||
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /*!< I2C3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF6_MCO ((uint8_t)0x06) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF6_LSCO ((uint8_t)0x06) /*!< LSCO Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB0 ((uint8_t)0x06) /*!< RF_DTB0 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB1 ((uint8_t)0x06) /*!< RF_DTB1 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB2 ((uint8_t)0x06) /*!< RF_DTB2 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB3 ((uint8_t)0x06) /*!< RF_DTB3 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB4 ((uint8_t)0x06) /*!< RF_DTB4 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB5 ((uint8_t)0x06) /*!< RF_DTB5 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB6 ((uint8_t)0x06) /*!< RF_DTB6 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB7 ((uint8_t)0x06) /*!< RF_DTB7 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB8 ((uint8_t)0x06) /*!< RF_DTB8 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB9 ((uint8_t)0x06) /*!< RF_DTB9 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB10 ((uint8_t)0x06) /*!< RF_DTB10 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB11 ((uint8_t)0x06) /*!< RF_DTB11 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB12 ((uint8_t)0x06) /*!< RF_DTB12 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB13 ((uint8_t)0x06) /*!< RF_DTB13 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB14 ((uint8_t)0x06) /*!< RF_DTB14 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB15 ((uint8_t)0x06) /*!< RF_DTB15 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB16 ((uint8_t)0x06) /*!< RF_DTB16 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB17 ((uint8_t)0x06) /*!< RF_DTB17 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_DTB18 ((uint8_t)0x06) /*!< RF_DTB18 Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_MISO ((uint8_t)0x06) /*!< RF_MISO Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_MOSI ((uint8_t)0x06) /*!< RF_MOSI Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_SCK ((uint8_t)0x06) /*!< RF_SCK Alternate Function mapping */
|
||||
#define GPIO_AF6_RF_NSS ((uint8_t)0x06) /*!< RF_NSS Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping */
|
||||
#define GPIO_AF8_IR ((uint8_t)0x08) /*!< IR Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF9_TSC ((uint8_t)0x09) /*!< TSC Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF10_QUADSPI ((uint8_t)0x0a) /*!< QUADSPI Alternate Function mapping */
|
||||
#define GPIO_AF10_USB ((uint8_t)0x0a) /*!< USB Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF11_LCD ((uint8_t)0x0b) /*!< LCD Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF12_COMP1 ((uint8_t)0x0c) /*!< COMP1 Alternate Function mapping */
|
||||
#define GPIO_AF12_COMP2 ((uint8_t)0x0c) /*!< COMP2 Alternate Function mapping */
|
||||
#define GPIO_AF12_TIM1 ((uint8_t)0x0c) /*!< TIM1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF13_SAI1 ((uint8_t)0x0d) /*!< SAI1 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF14_TIM2 ((uint8_t)0x0e) /*!< TIM2 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM16 ((uint8_t)0x0e) /*!< TIM16 Alternate Function mapping */
|
||||
#define GPIO_AF14_TIM17 ((uint8_t)0x0e) /*!< TIM17 Alternate Function mapping */
|
||||
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0e) /*!< LPTIM2 Alternate Function mapping */
|
||||
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
|
||||
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0f) /*!< EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
|
||||
((__GPIOx__) == (GPIOB))? 1uL :\
|
||||
((__GPIOx__) == (GPIOC))? 2uL :\
|
||||
((__GPIOx__) == (GPIOD))? 3uL :\
|
||||
((__GPIOx__) == (GPIOE))? 4uL : 7uL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_GPIO_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,363 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_hsem.c
|
||||
* @author MCD Application Team
|
||||
* @brief HSEM HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the semaphore peripheral:
|
||||
* + Semaphore Take function (2-Step Procedure) , non blocking
|
||||
* + Semaphore FastTake function (1-Step Procedure) , non blocking
|
||||
* + Semaphore Status check
|
||||
* + Semaphore Clear Key Set and Get
|
||||
* + Release and release all functions
|
||||
* + Semaphore notification enabling and disabling and callnack functions
|
||||
* + IRQ handler management
|
||||
*
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#)Take a semaphore In 2-Step mode Using function HAL_HSEM_Take. This function takes as parameters :
|
||||
(++) the semaphore ID from 0 to 31
|
||||
(++) the process ID from 0 to 255
|
||||
(#) Fast Take semaphore In 1-Step mode Using function HAL_HSEM_FastTake. This function takes as parameter :
|
||||
(++) the semaphore ID from 0_ID to 31. Note that the process ID value is implicitly assumed as zero
|
||||
(#) Check if a semaphore is Taken using function HAL_HSEM_IsSemTaken. This function takes as parameter :
|
||||
(++) the semaphore ID from 0_ID to 31
|
||||
(++) It returns 1 if the given semaphore is taken otherwise (Free) zero
|
||||
(#)Release a semaphore using function with HAL_HSEM_Release. This function takes as parameters :
|
||||
(++) the semaphore ID from 0 to 31
|
||||
(++) the process ID from 0 to 255:
|
||||
(++) Note: If ProcessID and MasterID match, semaphore is freed, and an interrupt
|
||||
may be generated when enabled (notification activated). If ProcessID or MasterID does not match,
|
||||
semaphore remains taken (locked)
|
||||
|
||||
(#)Release all semaphores at once taken by a given Master using function HAL_HSEM_Release_All
|
||||
This function takes as parameters :
|
||||
(++) the Release Key (value from 0 to 0xFFFF) can be Set or Get respectively by
|
||||
HAL_HSEM_SetClearKey() or HAL_HSEM_GetClearKey functions
|
||||
(++) the Master ID:
|
||||
(++) Note: If the Key and MasterID match, all semaphores taken by the given CPU that corresponds
|
||||
to MasterID will be freed, and an interrupt may be generated when enabled (notification activated). If the
|
||||
Key or the MasterID doesn't match, semaphores remains taken (locked)
|
||||
|
||||
(#)Semaphores Release all key functions:
|
||||
(++) HAL_HSEM_SetClearKey() to set semaphore release all Key
|
||||
(++) HAL_HSEM_GetClearKey() to get release all Key
|
||||
(#)Semaphores notification functions :
|
||||
(++) HAL_HSEM_ActivateNotification to activate a notification callback on
|
||||
a given semaphores Mask (bitfield). When one or more semaphores defined by the mask are released
|
||||
the callback HAL_HSEM_FreeCallback will be asserted giving as parameters a mask of the released
|
||||
semaphores (bitfield).
|
||||
|
||||
(++) HAL_HSEM_DeactivateNotification to deactivate the notification of a given semaphores Mask (bitfield).
|
||||
(++) See the description of the macro __HAL_HSEM_SEMID_TO_MASK to check how to calculate a semaphore mask
|
||||
Used by the notification functions
|
||||
*** HSEM HAL driver macros list ***
|
||||
=============================================
|
||||
[..] Below the list of most used macros in HSEM HAL driver.
|
||||
|
||||
(+) __HAL_HSEM_SEMID_TO_MASK: Helper macro to convert a Semaphore ID to a Mask.
|
||||
[..] Example of use :
|
||||
[..] mask = __HAL_HSEM_SEMID_TO_MASK(8) | __HAL_HSEM_SEMID_TO_MASK(21) | __HAL_HSEM_SEMID_TO_MASK(25).
|
||||
[..] All next macros take as parameter a semaphore Mask (bitfiled) that can be constructed using __HAL_HSEM_SEMID_TO_MASK as the above example.
|
||||
(+) __HAL_HSEM_ENABLE_IT: Enable the specified semaphores Mask interrupts.
|
||||
(+) __HAL_HSEM_DISABLE_IT: Disable the specified semaphores Mask interrupts.
|
||||
(+) __HAL_HSEM_GET_IT: Checks whether the specified semaphore interrupt has occurred or not.
|
||||
(+) __HAL_HSEM_GET_FLAG: Get the semaphores status release flags.
|
||||
(+) __HAL_HSEM_CLEAR_FLAG: Clear the semaphores status release flags.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HSEM HSEM
|
||||
* @brief HSEM HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_HSEM_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#if defined(DUAL_CORE)
|
||||
#ifndef HSEM_R_MASTERID
|
||||
#define HSEM_R_MASTERID HSEM_R_COREID
|
||||
#endif
|
||||
|
||||
#ifndef HSEM_RLR_MASTERID
|
||||
#define HSEM_RLR_MASTERID HSEM_RLR_COREID
|
||||
#endif
|
||||
|
||||
#ifndef HSEM_CR_MASTERID
|
||||
#define HSEM_CR_MASTERID HSEM_CR_COREID
|
||||
#endif
|
||||
#endif /* DUAL_CORE */
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HSEM_Exported_Functions_Group1 Take and Release functions
|
||||
* @brief HSEM Take and Release functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### HSEM Take and Release functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Take a semaphore with 2 Step method
|
||||
(+) Fast Take a semaphore with 1 Step method
|
||||
(+) Check semaphore state Taken or not
|
||||
(+) Release a semaphore
|
||||
(+) Release all semaphore at once
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Take a semaphore in 2 Step mode.
|
||||
* @param SemID: semaphore ID from 0 to 31
|
||||
* @param ProcessID: Process ID from 0 to 255
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_HSEM_SEMID(SemID));
|
||||
assert_param(IS_HSEM_PROCESSID(ProcessID));
|
||||
|
||||
/* First step write R register with MasterID, processID and take bit=1*/
|
||||
HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK);
|
||||
|
||||
/* second step : read the R register . Take achieved if MasterID and processID match and take bit set to 1 */
|
||||
if (HSEM->R[SemID] == (ProcessID | HSEM_CR_COREID_CURRENT | HSEM_R_LOCK))
|
||||
{
|
||||
/*take success when MasterID and ProcessID match and take bit set*/
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/* Semaphore take fails*/
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fast Take a semaphore with 1 Step mode.
|
||||
* @param SemID: semaphore ID from 0 to 31
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_HSEM_SEMID(SemID));
|
||||
|
||||
/* Read the RLR register to take the semaphore */
|
||||
if (HSEM->RLR[SemID] == (HSEM_CR_COREID_CURRENT | HSEM_RLR_LOCK))
|
||||
{
|
||||
/*take success when MasterID match and take bit set*/
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/* Semaphore take fails */
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/**
|
||||
* @brief Check semaphore state Taken or not.
|
||||
* @param SemID: semaphore ID
|
||||
* @retval HAL HSEM state
|
||||
*/
|
||||
uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID)
|
||||
{
|
||||
return (((HSEM->R[SemID] & HSEM_R_LOCK) != 0U) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Release a semaphore.
|
||||
* @param SemID: semaphore ID from 0 to 31
|
||||
* @param ProcessID: Process ID from 0 to 255
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_HSEM_SEMID(SemID));
|
||||
assert_param(IS_HSEM_PROCESSID(ProcessID));
|
||||
|
||||
/* Clear the semaphore by writing to the R register : the MasterID , the processID and take bit = 0 */
|
||||
HSEM->R[SemID] = (ProcessID | HSEM_CR_COREID_CURRENT);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Release All semaphore used by a given Master .
|
||||
* @param Key: Semaphore Key , value from 0 to 0xFFFF
|
||||
* @param CoreID: CoreID of the CPU that is using semaphores to be released
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID)
|
||||
{
|
||||
assert_param(IS_HSEM_KEY(Key));
|
||||
assert_param(IS_HSEM_COREID(CoreID));
|
||||
|
||||
HSEM->CR = ((Key << HSEM_CR_KEY_Pos) | (CoreID << HSEM_CR_COREID_Pos));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
|
||||
* @brief HSEM Set and Get Key functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### HSEM Set and Get Key functions #####
|
||||
==============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Set semaphore Key
|
||||
(+) Get semaphore Key
|
||||
@endverbatim
|
||||
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set semaphore Key .
|
||||
* @param Key: Semaphore Key , value from 0 to 0xFFFF
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_HSEM_SetClearKey(uint32_t Key)
|
||||
{
|
||||
assert_param(IS_HSEM_KEY(Key));
|
||||
|
||||
MODIFY_REG(HSEM->KEYR, HSEM_KEYR_KEY, (Key << HSEM_KEYR_KEY_Pos));
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get semaphore Key .
|
||||
* @retval Semaphore Key , value from 0 to 0xFFFF
|
||||
*/
|
||||
uint32_t HAL_HSEM_GetClearKey(void)
|
||||
{
|
||||
return (HSEM->KEYR >> HSEM_KEYR_KEY_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HSEM_Exported_Functions_Group3 HSEM IRQ handler management
|
||||
* @brief HSEM Notification functions.
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### HSEM IRQ handler management and Notification functions #####
|
||||
==============================================================================
|
||||
[..] This section provides HSEM IRQ handler and Notification function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Activate Semaphore release Notification for a given Semaphores Mask .
|
||||
* @param SemMask: Mask of Released semaphores
|
||||
* @retval Semaphore Key
|
||||
*/
|
||||
void HAL_HSEM_ActivateNotification(uint32_t SemMask)
|
||||
{
|
||||
HSEM_COMMON->IER |= SemMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivate Semaphore release Notification for a given Semaphores Mask .
|
||||
* @param SemMask: Mask of Released semaphores
|
||||
* @retval Semaphore Key
|
||||
*/
|
||||
void HAL_HSEM_DeactivateNotification(uint32_t SemMask)
|
||||
{
|
||||
HSEM_COMMON->IER &= ~SemMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles HSEM interrupt request
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_HSEM_IRQHandler(void)
|
||||
{
|
||||
uint32_t statusreg;
|
||||
/* Get the list of masked freed semaphores*/
|
||||
statusreg = HSEM_COMMON->MISR;
|
||||
|
||||
/*Disable Interrupts*/
|
||||
HSEM_COMMON->IER &= ~((uint32_t)statusreg);
|
||||
|
||||
/*Clear Flags*/
|
||||
HSEM_COMMON->ICR = ((uint32_t)statusreg);
|
||||
|
||||
/* Call FreeCallback */
|
||||
HAL_HSEM_FreeCallback(statusreg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Semaphore Released Callback.
|
||||
* @param SemMask: Mask of Released semaphores
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_HSEM_FreeCallback(uint32_t SemMask)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(SemMask);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_HSEM_FreeCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_HSEM_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_hsem.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of HSEM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_HSEM_H
|
||||
#define STM32WBxx_HAL_HSEM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HSEM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup HSEM_Exported_Macros HSEM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SemID to mask helper Macro.
|
||||
* @param __SEMID__: semaphore ID from 0 to 31
|
||||
* @retval Semaphore Mask.
|
||||
*/
|
||||
#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
|
||||
|
||||
/**
|
||||
* @brief Enables the specified HSEM interrupts.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval None.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
(HSEM->C1IER |= (__SEM_MASK__)) : \
|
||||
(HSEM->C2IER |= (__SEM_MASK__)))
|
||||
#else
|
||||
#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
|
||||
#endif /* DUAL_CORE */
|
||||
/**
|
||||
* @brief Disables the specified HSEM interrupts.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval None.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
(HSEM->C1IER &= ~(__SEM_MASK__)) : \
|
||||
(HSEM->C2IER &= ~(__SEM_MASK__)))
|
||||
#else
|
||||
#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @brief Checks whether interrupt has occurred or not for semaphores specified by a mask.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval semaphores Mask : Semaphores where an interrupt occurred.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
((__SEM_MASK__) & HSEM->C1MISR) : \
|
||||
((__SEM_MASK__) & HSEM->C2MISR1))
|
||||
#else
|
||||
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @brief Get the semaphores release status flags.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval semaphores Mask : Semaphores where Release flags rise.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
(__SEM_MASK__) & HSEM->C1ISR : \
|
||||
(__SEM_MASK__) & HSEM->C2ISR)
|
||||
#else
|
||||
#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @brief Clears the HSEM Interrupt flags.
|
||||
* @param __SEM_MASK__: semaphores Mask
|
||||
* @retval None.
|
||||
*/
|
||||
#if defined(DUAL_CORE)
|
||||
#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
|
||||
(HSEM->C1ICR |= (__SEM_MASK__)) : \
|
||||
(HSEM->C2ICR |= (__SEM_MASK__)))
|
||||
#else
|
||||
#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
|
||||
#endif /* DUAL_CORE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
|
||||
* @brief HSEM Take and Release functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* HSEM semaphore take (lock) using 2-Step method ****************************/
|
||||
HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
|
||||
/* HSEM semaphore fast take (lock) using 1-Step method ***********************/
|
||||
HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID);
|
||||
/* HSEM Check semaphore state Taken or not **********************************/
|
||||
uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
|
||||
/* HSEM Release **************************************************************/
|
||||
void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
|
||||
/* HSEM Release All************************************************************/
|
||||
void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
|
||||
* @brief HSEM Set and Get Key functions.
|
||||
* @{
|
||||
*/
|
||||
/* HSEM Set Clear Key *********************************************************/
|
||||
void HAL_HSEM_SetClearKey(uint32_t Key);
|
||||
/* HSEM Get Clear Key *********************************************************/
|
||||
uint32_t HAL_HSEM_GetClearKey(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup HSEM_Exported_Functions_Group3
|
||||
* @brief HSEM Notification functions
|
||||
* @{
|
||||
*/
|
||||
/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
|
||||
void HAL_HSEM_ActivateNotification(uint32_t SemMask);
|
||||
/* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/
|
||||
void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
|
||||
/* HSEM Free Callback (When a semaphore is released) *******************************/
|
||||
void HAL_HSEM_FreeCallback(uint32_t SemMask);
|
||||
/* HSEM IRQ Handler **********************************************************/
|
||||
void HAL_HSEM_IRQHandler(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup HSEM_Private_Macros HSEM Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
|
||||
|
||||
#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
|
||||
|
||||
#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
|
||||
|
||||
#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
|
||||
((__COREID__) == HSEM_CPU2_COREID))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_HSEM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,782 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_I2C_H
|
||||
#define STM32WBxx_HAL_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Exported_Types I2C Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
|
||||
* @brief I2C Configuration Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
|
||||
This parameter calculated by referring to I2C initialization
|
||||
section in Reference manual */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
|
||||
|
||||
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
|
||||
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
|
||||
This parameter can be a 7-bit address. */
|
||||
|
||||
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
|
||||
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
|
||||
|
||||
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
|
||||
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
|
||||
|
||||
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
|
||||
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
|
||||
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structure definition
|
||||
* @note HAL I2C State value coding follow below described bitmap :\n
|
||||
* b7-b6 Error information\n
|
||||
* 00 : No Error\n
|
||||
* 01 : Abort (Abort user request on going)\n
|
||||
* 10 : Timeout\n
|
||||
* 11 : Error\n
|
||||
* b5 Peripheral initialization status\n
|
||||
* 0 : Reset (peripheral not initialized)\n
|
||||
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
|
||||
* b4 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b3\n
|
||||
* 0 : Ready or Busy (No Listen mode ongoing)\n
|
||||
* 1 : Listen (peripheral in Address Listen Mode)\n
|
||||
* b2 Intrinsic process state\n
|
||||
* 0 : Ready\n
|
||||
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
|
||||
* b1 Rx state\n
|
||||
* 0 : Ready (no Rx operation ongoing)\n
|
||||
* 1 : Busy (Rx operation ongoing)\n
|
||||
* b0 Tx state\n
|
||||
* 0 : Ready (no Tx operation ongoing)\n
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
|
||||
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
|
||||
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
|
||||
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
|
||||
* @brief HAL Mode structure definition
|
||||
* @note HAL I2C Mode value coding follow below described bitmap :\n
|
||||
* b7 (not used)\n
|
||||
* x : Should be set to 0\n
|
||||
* b6\n
|
||||
* 0 : None\n
|
||||
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
|
||||
* b5\n
|
||||
* 0 : None\n
|
||||
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
|
||||
* b4\n
|
||||
* 0 : None\n
|
||||
* 1 : Master (HAL I2C communication is in Master Mode)\n
|
||||
* b3-b2-b1-b0 (not used)\n
|
||||
* xxxx : Should be set to 0000
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
|
||||
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
|
||||
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
|
||||
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
|
||||
|
||||
} HAL_I2C_ModeTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
|
||||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
|
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
|
||||
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
|
||||
* @brief I2C handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __I2C_HandleTypeDef
|
||||
{
|
||||
I2C_TypeDef *Instance; /*!< I2C registers base address */
|
||||
|
||||
I2C_InitTypeDef Init; /*!< I2C communication parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
|
||||
|
||||
uint16_t XferSize; /*!< I2C transfer size */
|
||||
|
||||
__IO uint16_t XferCount; /*!< I2C transfer counter */
|
||||
|
||||
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
|
||||
be a value of @ref I2C_XFEROPTIONS */
|
||||
|
||||
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
|
||||
|
||||
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
|
||||
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< I2C Error code */
|
||||
|
||||
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Tx Transfer completed callback */
|
||||
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Master Rx Transfer completed callback */
|
||||
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Tx Transfer completed callback */
|
||||
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Slave Rx Transfer completed callback */
|
||||
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Listen Complete callback */
|
||||
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Tx Transfer completed callback */
|
||||
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Memory Rx Transfer completed callback */
|
||||
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Error callback */
|
||||
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Abort callback */
|
||||
|
||||
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< I2C Slave Address Match callback */
|
||||
|
||||
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*!< I2C Msp DeInit callback */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
} I2C_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL I2C Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
|
||||
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
|
||||
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
|
||||
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
|
||||
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
|
||||
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
|
||||
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
|
||||
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
|
||||
|
||||
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
|
||||
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
|
||||
|
||||
} HAL_I2C_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL I2C Callback pointer definition
|
||||
*/
|
||||
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
|
||||
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
|
||||
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Constants I2C Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
|
||||
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
|
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
|
||||
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
|
||||
|
||||
/* List of XferOptions in usage of :
|
||||
* 1- Restart condition in all use cases (direction change or not)
|
||||
*/
|
||||
#define I2C_OTHER_FRAME (0x000000AAU)
|
||||
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
|
||||
* @{
|
||||
*/
|
||||
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
|
||||
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
|
||||
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
|
||||
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
|
||||
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
|
||||
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
|
||||
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
|
||||
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
|
||||
#define I2C_DIRECTION_RECEIVE (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
|
||||
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
|
||||
#define I2C_SOFTEND_MODE (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NO_STARTSTOP (0x00000000U)
|
||||
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
||||
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
|
||||
* @brief I2C Interrupt definition
|
||||
* Elements values convention: 0xXXXXXXXX
|
||||
* - XXXXXXXX : Interrupt control mask
|
||||
* @{
|
||||
*/
|
||||
#define I2C_IT_ERRI I2C_CR1_ERRIE
|
||||
#define I2C_IT_TCI I2C_CR1_TCIE
|
||||
#define I2C_IT_STOPI I2C_CR1_STOPIE
|
||||
#define I2C_IT_NACKI I2C_CR1_NACKIE
|
||||
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
|
||||
#define I2C_IT_RXI I2C_CR1_RXIE
|
||||
#define I2C_IT_TXI I2C_CR1_TXIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Flag_definition I2C Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_TXE I2C_ISR_TXE
|
||||
#define I2C_FLAG_TXIS I2C_ISR_TXIS
|
||||
#define I2C_FLAG_RXNE I2C_ISR_RXNE
|
||||
#define I2C_FLAG_ADDR I2C_ISR_ADDR
|
||||
#define I2C_FLAG_AF I2C_ISR_NACKF
|
||||
#define I2C_FLAG_STOPF I2C_ISR_STOPF
|
||||
#define I2C_FLAG_TC I2C_ISR_TC
|
||||
#define I2C_FLAG_TCR I2C_ISR_TCR
|
||||
#define I2C_FLAG_BERR I2C_ISR_BERR
|
||||
#define I2C_FLAG_ARLO I2C_ISR_ARLO
|
||||
#define I2C_FLAG_OVR I2C_ISR_OVR
|
||||
#define I2C_FLAG_PECERR I2C_ISR_PECERR
|
||||
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
|
||||
#define I2C_FLAG_ALERT I2C_ISR_ALERT
|
||||
#define I2C_FLAG_BUSY I2C_ISR_BUSY
|
||||
#define I2C_FLAG_DIR I2C_ISR_DIR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2C_Exported_Macros I2C Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset I2C handle state.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/** @brief Enable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified I2C interrupt.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified I2C interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_IT_ERRI Errors interrupt enable
|
||||
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
|
||||
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
|
||||
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
|
||||
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
|
||||
* @arg @ref I2C_IT_RXI RX interrupt enable
|
||||
* @arg @ref I2C_IT_TXI TX interrupt enable
|
||||
*
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified I2C flag is set or not.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
|
||||
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
|
||||
* @arg @ref I2C_FLAG_TCR Transfer complete reload
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
* @arg @ref I2C_FLAG_BUSY Bus busy
|
||||
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
|
||||
*
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define I2C_FLAG_MASK (0x0001FFFFU)
|
||||
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref I2C_FLAG_TXE Transmit data register empty
|
||||
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
|
||||
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
|
||||
* @arg @ref I2C_FLAG_STOPF STOP detection flag
|
||||
* @arg @ref I2C_FLAG_BERR Bus error
|
||||
* @arg @ref I2C_FLAG_ARLO Arbitration lost
|
||||
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
|
||||
* @arg @ref I2C_FLAG_PECERR PEC error in reception
|
||||
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
|
||||
* @arg @ref I2C_FLAG_ALERT SMBus alert
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
|
||||
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
|
||||
|
||||
/** @brief Enable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Disable the specified I2C peripheral.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
|
||||
|
||||
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
|
||||
* @param __HANDLE__ specifies the I2C Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include I2C HAL Extended module */
|
||||
#include "stm32wbxx_hal_i2c_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions******************************/
|
||||
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
|
||||
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions ****************************************************/
|
||||
/******* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
|
||||
|
||||
/******* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
|
||||
|
||||
/******* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
|
||||
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Macro I2C Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
|
||||
((MODE) == I2C_ADDRESSINGMODE_10BIT))
|
||||
|
||||
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
|
||||
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
|
||||
((MASK) == I2C_OA2_MASK01) || \
|
||||
((MASK) == I2C_OA2_MASK02) || \
|
||||
((MASK) == I2C_OA2_MASK03) || \
|
||||
((MASK) == I2C_OA2_MASK04) || \
|
||||
((MASK) == I2C_OA2_MASK05) || \
|
||||
((MASK) == I2C_OA2_MASK06) || \
|
||||
((MASK) == I2C_OA2_MASK07))
|
||||
|
||||
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
|
||||
((CALL) == I2C_GENERALCALL_ENABLE))
|
||||
|
||||
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
|
||||
((STRETCH) == I2C_NOSTRETCH_ENABLE))
|
||||
|
||||
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
|
||||
((SIZE) == I2C_MEMADD_SIZE_16BIT))
|
||||
|
||||
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
|
||||
((MODE) == I2C_AUTOEND_MODE) || \
|
||||
((MODE) == I2C_SOFTEND_MODE))
|
||||
|
||||
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
|
||||
((REQUEST) == I2C_GENERATE_START_READ) || \
|
||||
((REQUEST) == I2C_GENERATE_START_WRITE) || \
|
||||
((REQUEST) == I2C_NO_STARTSTOP))
|
||||
|
||||
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_NEXT_FRAME) || \
|
||||
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME) || \
|
||||
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
|
||||
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
|
||||
|
||||
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
|
||||
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
|
||||
|
||||
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
|
||||
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
|
||||
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
|
||||
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
|
||||
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
|
||||
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
|
||||
|
||||
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
|
||||
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
|
||||
|
||||
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2C_Private_Functions I2C Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32wbxx_hal_i2c.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32WBxx_HAL_I2C_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,325 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_i2c_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief I2C Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of I2C Extended peripheral:
|
||||
* + Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### I2C peripheral Extended features #####
|
||||
==============================================================================
|
||||
|
||||
[..] Comparing to other previous devices, the I2C interface for STM32WBxx
|
||||
devices contains the following additional features
|
||||
|
||||
(+) Possibility to disable or enable Analog Noise Filter
|
||||
(+) Use of a configured Digital Noise Filter
|
||||
(+) Disable or enable wakeup from Stop mode(s)
|
||||
(+) Disable or enable Fast Mode Plus
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
|
||||
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
|
||||
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
|
||||
(#) Configure the enable or disable of I2C Wake Up Mode using the functions :
|
||||
(++) HAL_I2CEx_EnableWakeUp()
|
||||
(++) HAL_I2CEx_DisableWakeUp()
|
||||
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
|
||||
(++) HAL_I2CEx_EnableFastModePlus()
|
||||
(++) HAL_I2CEx_DisableFastModePlus()
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx I2CEx
|
||||
* @brief I2C Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure Noise Filters
|
||||
(+) Configure Wake Up Feature
|
||||
(+) Configure Fast Mode Plus
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure I2C Analog noise filter.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param AnalogFilter New state of the Analog filter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Reset I2Cx ANOFF bit */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
||||
|
||||
/* Set analog filter bit*/
|
||||
hi2c->Instance->CR1 |= AnalogFilter;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure I2C Digital noise filter.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
||||
{
|
||||
uint32_t tmpreg;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
||||
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Get the old register value */
|
||||
tmpreg = hi2c->Instance->CR1;
|
||||
|
||||
/* Reset I2Cx DNF bits [11:8] */
|
||||
tmpreg &= ~(I2C_CR1_DNF);
|
||||
|
||||
/* Set I2Cx DNF coefficient */
|
||||
tmpreg |= DigitalFilter << 8U;
|
||||
|
||||
/* Store the new register value */
|
||||
hi2c->Instance->CR1 = tmpreg;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable I2C wakeup from Stop mode(s).
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable I2C wakeup from Stop mode(s).
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2Cx peripheral.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance));
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_BUSY;
|
||||
|
||||
/* Disable the selected I2C peripheral */
|
||||
__HAL_I2C_DISABLE(hi2c);
|
||||
|
||||
/* Enable wakeup from stop mode */
|
||||
hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
|
||||
|
||||
__HAL_I2C_ENABLE(hi2c);
|
||||
|
||||
hi2c->State = HAL_I2C_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the I2C fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
|
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C3 pins fast mode plus driving capability can be enabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Enable fast mode plus driving capability for selected pin */
|
||||
SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the I2C fast mode plus driving capability.
|
||||
* @param ConfigFastModePlus Selects the pin.
|
||||
* This parameter can be one of the @ref I2CEx_FastModePlus values
|
||||
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
|
||||
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
|
||||
* on each one of the following pins PB6, PB7, PB8 and PB9.
|
||||
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
|
||||
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
|
||||
* @note For all I2C3 pins fast mode plus driving capability can be disabled
|
||||
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
|
||||
|
||||
/* Disable fast mode plus driving capability for selected pin */
|
||||
CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_i2c_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of I2C HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_I2C_EX_H
|
||||
#define STM32WBxx_HAL_I2C_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
|
||||
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
|
||||
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
|
||||
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
|
||||
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
|
||||
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
|
||||
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
|
||||
* @brief Extended features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
|
||||
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
|
||||
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
|
||||
((FILTER) == I2C_ANALOGFILTER_DISABLE))
|
||||
|
||||
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
|
||||
|
||||
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
|
||||
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private Functions ---------------------------------------------------------*/
|
||||
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
|
||||
* @{
|
||||
*/
|
||||
/* Private functions are defined in stm32wbxx_hal_i2c_ex.c file */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_I2C_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,746 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_ipcc.c
|
||||
* @author MCD Application Team
|
||||
* @brief IPCC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Inter-Processor communication controller
|
||||
* peripherals (IPCC).
|
||||
* + Initialization and de-initialization functions
|
||||
* + Configuration, notification and interrupts handling
|
||||
* + Peripheral State and Error functions
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The IPCC HAL driver can be used as follows:
|
||||
|
||||
(#) Declare a IPCC_HandleTypeDef handle structure, for example: IPCC_HandleTypeDef hipcc;
|
||||
(#) Initialize the IPCC low level resources by implementing the HAL_IPCC_MspInit() API:
|
||||
(##) Enable the IPCC interface clock
|
||||
(##) NVIC configuration if you need to use interrupt process
|
||||
(+++) Configure the IPCC interrupt priority
|
||||
(+++) Enable the NVIC IPCC IRQ
|
||||
|
||||
(#) Initialize the IPCC registers by calling the HAL_IPCC_Init() API which trig
|
||||
HAL_IPCC_MspInit().
|
||||
|
||||
(#) Implement the interrupt callbacks for transmission and reception to use the driver in interrupt mode
|
||||
|
||||
(#) Associate those callback to the corresponding channel and direction using HAL_IPCC_ConfigChannel().
|
||||
This is the interrupt mode.
|
||||
If no callback are configured for a given channel and direction, it is up to the user to poll the
|
||||
status of the communication (polling mode).
|
||||
|
||||
(#) Notify the other MCU when a message is available in a chosen channel
|
||||
or when a message has been retrieved from a chosen channel by calling
|
||||
the HAL_IPCC_NotifyCPU() API.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IPCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_IPCC_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup IPCC_Private_Constants IPCC Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define IPCC_ALL_RX_BUF 0x0000003FU /*!< Mask for all RX buffers. */
|
||||
#define IPCC_ALL_TX_BUF 0x003F0000U /*!< Mask for all TX buffers. */
|
||||
#define CHANNEL_INDEX_Msk 0x0000000FU /*!< Mask the channel index to avoid overflow */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup IPCC_Private_Functions IPCC Private Functions
|
||||
* @{
|
||||
*/
|
||||
void IPCC_MaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
void IPCC_UnmaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
void IPCC_SetDefaultCallbacks(IPCC_HandleTypeDef *hipcc);
|
||||
void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IPCC_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IPCC_Exported_Functions_Group1
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..] This subsection provides a set of functions allowing to initialize and
|
||||
deinitialize the IPCC peripheral:
|
||||
|
||||
(+) User must Implement HAL_IPCC_MspInit() function in which he configures
|
||||
all related peripherals resources (CLOCK and NVIC ).
|
||||
|
||||
(+) Call the function HAL_IPCC_Init() to configure the IPCC register.
|
||||
|
||||
(+) Call the function HAL_PKA_DeInit() to restore the default configuration
|
||||
of the selected IPCC peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the IPCC peripheral.
|
||||
* @param hipcc IPCC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc)
|
||||
{
|
||||
HAL_StatusTypeDef err = HAL_OK;
|
||||
|
||||
/* Check the IPCC handle allocation */
|
||||
if (hipcc != NULL)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
|
||||
|
||||
IPCC_CommonTypeDef *currentInstance = IPCC_C1;
|
||||
|
||||
if (hipcc->State == HAL_IPCC_STATE_RESET)
|
||||
{
|
||||
/* Init the low level hardware : CLOCK, NVIC */
|
||||
HAL_IPCC_MspInit(hipcc);
|
||||
}
|
||||
|
||||
/* Reset all registers of the current cpu to default state */
|
||||
IPCC_Reset_Register(currentInstance);
|
||||
|
||||
/* Activate the interrupts */
|
||||
currentInstance->CR |= (IPCC_CR_RXOIE | IPCC_CR_TXFIE);
|
||||
|
||||
/* Clear callback pointers */
|
||||
IPCC_SetDefaultCallbacks(hipcc);
|
||||
|
||||
/* Reset all callback notification request */
|
||||
hipcc->callbackRequest = 0;
|
||||
|
||||
hipcc->State = HAL_IPCC_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
err = HAL_ERROR;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the IPCC peripheral.
|
||||
* @param hipcc IPCC handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IPCC_DeInit(IPCC_HandleTypeDef *hipcc)
|
||||
{
|
||||
HAL_StatusTypeDef err = HAL_OK;
|
||||
|
||||
/* Check the IPCC handle allocation */
|
||||
if (hipcc != NULL)
|
||||
{
|
||||
assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
|
||||
IPCC_CommonTypeDef *currentInstance = IPCC_C1;
|
||||
|
||||
/* Set the state to busy */
|
||||
hipcc->State = HAL_IPCC_STATE_BUSY;
|
||||
|
||||
/* Reset all registers of the current cpu to default state */
|
||||
IPCC_Reset_Register(currentInstance);
|
||||
|
||||
/* Clear callback pointers */
|
||||
IPCC_SetDefaultCallbacks(hipcc);
|
||||
|
||||
/* Reset all callback notification request */
|
||||
hipcc->callbackRequest = 0;
|
||||
|
||||
/* DeInit the low level hardware : CLOCK, NVIC */
|
||||
HAL_IPCC_MspDeInit(hipcc);
|
||||
|
||||
hipcc->State = HAL_IPCC_STATE_RESET;
|
||||
}
|
||||
else
|
||||
{
|
||||
err = HAL_ERROR;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the IPCC MSP.
|
||||
* @param hipcc IPCC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IPCC_MspInit(IPCC_HandleTypeDef *hipcc)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hipcc);
|
||||
|
||||
/* NOTE : This function should not be modified. When the callback is needed
|
||||
the HAL_IPCC_MspInit should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief IPCC MSP DeInit
|
||||
* @param hipcc IPCC handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hipcc);
|
||||
|
||||
/* NOTE : This function should not be modified. When the callback is needed
|
||||
the HAL_IPCC_MspDeInit should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup IPCC_Exported_Functions_Group2
|
||||
* @brief Configuration, notification and Irq handling functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions to allow two MCU to communicate.
|
||||
|
||||
(#) For a given channel (from 0 to IPCC_CHANNEL_NUMBER), for a given direction
|
||||
IPCC_CHANNEL_DIR_TX or IPCC_CHANNEL_DIR_RX, you can choose to communicate
|
||||
in polling mode or in interrupt mode using IPCC.
|
||||
By default, the IPCC HAL driver handle the communication in polling mode.
|
||||
By setting a callback for a channel/direction, this communication use
|
||||
the interrupt mode.
|
||||
|
||||
(#) Polling mode:
|
||||
(++) To transmit information, use HAL_IPCC_NotifyCPU() with
|
||||
IPCC_CHANNEL_DIR_TX. To know when the other processor has handled
|
||||
the notification, poll the communication using HAL_IPCC_NotifyCPU
|
||||
with IPCC_CHANNEL_DIR_TX.
|
||||
|
||||
(++) To receive information, poll the status of the communication with
|
||||
HAL_IPCC_GetChannelStatus with IPCC_CHANNEL_DIR_RX. To notify the other
|
||||
processor that the information has been received, use HAL_IPCC_NotifyCPU
|
||||
with IPCC_CHANNEL_DIR_RX.
|
||||
|
||||
(#) Interrupt mode:
|
||||
(++) Configure a callback for the channel and the direction using HAL_IPCC_ConfigChannel().
|
||||
This callback will be triggered under interrupt.
|
||||
|
||||
(++) To transmit information, use HAL_IPCC_NotifyCPU() with
|
||||
IPCC_CHANNEL_DIR_TX. The callback configured with HAL_IPCC_ConfigChannel() and
|
||||
IPCC_CHANNEL_DIR_TX will be triggered once the communication has been handled by the
|
||||
other processor.
|
||||
|
||||
(++) To receive information, the callback configured with HAL_IPCC_ConfigChannel() and
|
||||
IPCC_CHANNEL_DIR_RX will be triggered on reception of a communication.To notify the other
|
||||
processor that the information has been received, use HAL_IPCC_NotifyCPU
|
||||
with IPCC_CHANNEL_DIR_RX.
|
||||
|
||||
(++) HAL_IPCC_TX_IRQHandler must be added to the IPCC TX IRQHandler
|
||||
|
||||
(++) HAL_IPCC_RX_IRQHandler must be added to the IPCC RX IRQHandler
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Activate the callback notification on receive/transmit interrupt
|
||||
* @param hipcc IPCC handle
|
||||
* @param ChannelIndex Channel number
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
||||
* @param ChannelDir Channel direction
|
||||
* @param cb Interrupt callback
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb)
|
||||
{
|
||||
HAL_StatusTypeDef err = HAL_OK;
|
||||
|
||||
/* Check the IPCC handle allocation */
|
||||
if (hipcc != NULL)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
|
||||
|
||||
/* Check IPCC state */
|
||||
if (hipcc->State == HAL_IPCC_STATE_READY)
|
||||
{
|
||||
/* Set callback and register masking information */
|
||||
if (ChannelDir == IPCC_CHANNEL_DIR_TX)
|
||||
{
|
||||
hipcc->ChannelCallbackTx[ChannelIndex] = cb;
|
||||
hipcc->callbackRequest |= (IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
|
||||
}
|
||||
else
|
||||
{
|
||||
hipcc->ChannelCallbackRx[ChannelIndex] = cb;
|
||||
hipcc->callbackRequest |= (IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
|
||||
}
|
||||
|
||||
/* Unmask only the channels in reception (Transmission channel mask/unmask is done in HAL_IPCC_NotifyCPU) */
|
||||
if (ChannelDir == IPCC_CHANNEL_DIR_RX)
|
||||
{
|
||||
IPCC_UnmaskInterrupt(ChannelIndex, ChannelDir);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
err = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
err = HAL_ERROR;
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Remove the callback notification on receive/transmit interrupt
|
||||
* @param hipcc IPCC handle
|
||||
* @param ChannelIndex Channel number
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
||||
* @param ChannelDir Channel direction
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
|
||||
{
|
||||
HAL_StatusTypeDef err = HAL_OK;
|
||||
|
||||
/* Check the IPCC handle allocation */
|
||||
if (hipcc != NULL)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
|
||||
|
||||
/* Check IPCC state */
|
||||
if (hipcc->State == HAL_IPCC_STATE_READY)
|
||||
{
|
||||
/* Set default callback and register masking information */
|
||||
if (ChannelDir == IPCC_CHANNEL_DIR_TX)
|
||||
{
|
||||
hipcc->ChannelCallbackTx[ChannelIndex] = HAL_IPCC_TxCallback;
|
||||
hipcc->callbackRequest &= ~(IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
|
||||
}
|
||||
else
|
||||
{
|
||||
hipcc->ChannelCallbackRx[ChannelIndex] = HAL_IPCC_RxCallback;
|
||||
hipcc->callbackRequest &= ~(IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
|
||||
}
|
||||
|
||||
/* Mask the interrupt */
|
||||
IPCC_MaskInterrupt(ChannelIndex, ChannelDir);
|
||||
}
|
||||
else
|
||||
{
|
||||
err = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
err = HAL_ERROR;
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get state of IPCC channel
|
||||
* @param hipcc IPCC handle
|
||||
* @param ChannelIndex Channel number
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
||||
* @param ChannelDir Channel direction
|
||||
* @retval Channel status
|
||||
*/
|
||||
IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
|
||||
{
|
||||
uint32_t channel_state;
|
||||
IPCC_CommonTypeDef *currentInstance = IPCC_C1;
|
||||
IPCC_CommonTypeDef *otherInstance = IPCC_C2;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
|
||||
|
||||
/* Read corresponding channel depending of the MCU and the direction */
|
||||
if (ChannelDir == IPCC_CHANNEL_DIR_TX)
|
||||
{
|
||||
channel_state = (currentInstance->SR) & (IPCC_SR_CH1F_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
|
||||
}
|
||||
else
|
||||
{
|
||||
channel_state = (otherInstance->SR) & (IPCC_SR_CH1F_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
|
||||
}
|
||||
|
||||
return (channel_state == 0UL) ? IPCC_CHANNEL_STATUS_FREE : IPCC_CHANNEL_STATUS_OCCUPIED ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Notify remote processor
|
||||
* @param hipcc IPCC handle
|
||||
* @param ChannelIndex Channel number
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
||||
* @param ChannelDir Channel direction
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
|
||||
{
|
||||
HAL_StatusTypeDef err = HAL_OK;
|
||||
uint32_t mask;
|
||||
IPCC_CommonTypeDef *currentInstance = IPCC_C1;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IPCC_ALL_INSTANCE(hipcc->Instance));
|
||||
|
||||
/* Check if IPCC is initiliased */
|
||||
if (hipcc->State == HAL_IPCC_STATE_READY)
|
||||
{
|
||||
/* For IPCC_CHANNEL_DIR_TX, set the status. For IPCC_CHANNEL_DIR_RX, clear the status */
|
||||
currentInstance->SCR |= ((ChannelDir == IPCC_CHANNEL_DIR_TX) ? IPCC_SCR_CH1S : IPCC_SCR_CH1C) << (ChannelIndex & CHANNEL_INDEX_Msk) ;
|
||||
|
||||
/* Unmask interrupt if the callback is requested */
|
||||
mask = ((ChannelDir == IPCC_CHANNEL_DIR_TX) ? IPCC_MR_CH1FM_Msk : IPCC_MR_CH1OM_Msk) << (ChannelIndex & CHANNEL_INDEX_Msk) ;
|
||||
if ((hipcc->callbackRequest & mask) == mask)
|
||||
{
|
||||
IPCC_UnmaskInterrupt(ChannelIndex, ChannelDir);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
err = HAL_ERROR;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IPCC_IRQ_Handler_and_Callbacks
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function handles IPCC Tx Free interrupt request.
|
||||
* @param hipcc IPCC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef *const hipcc)
|
||||
{
|
||||
uint32_t irqmask;
|
||||
uint32_t bit_pos;
|
||||
uint32_t ch_count = 0U;
|
||||
IPCC_CommonTypeDef *currentInstance = IPCC_C1;
|
||||
|
||||
/* check the Tx free channels which are not masked */
|
||||
irqmask = ~(currentInstance->MR) & IPCC_ALL_TX_BUF;
|
||||
irqmask = irqmask & ~(currentInstance->SR << IPCC_MR_CH1FM_Pos);
|
||||
|
||||
while (irqmask != 0UL) /* if several bits are set, it loops to serve all of them */
|
||||
{
|
||||
bit_pos = 1UL << (IPCC_MR_CH1FM_Pos + (ch_count & CHANNEL_INDEX_Msk));
|
||||
|
||||
if ((irqmask & bit_pos) != 0U)
|
||||
{
|
||||
/* mask the channel Free interrupt */
|
||||
currentInstance->MR |= bit_pos;
|
||||
if (hipcc->ChannelCallbackTx[ch_count] != NULL)
|
||||
{
|
||||
hipcc->ChannelCallbackTx[ch_count](hipcc, ch_count, IPCC_CHANNEL_DIR_TX);
|
||||
}
|
||||
irqmask = irqmask & ~(bit_pos);
|
||||
}
|
||||
ch_count++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles IPCC Rx Occupied interrupt request.
|
||||
* @param hipcc : IPCC handle
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc)
|
||||
{
|
||||
uint32_t irqmask;
|
||||
uint32_t bit_pos;
|
||||
uint32_t ch_count = 0U;
|
||||
IPCC_CommonTypeDef *currentInstance = IPCC_C1;
|
||||
IPCC_CommonTypeDef *otherInstance = IPCC_C2;
|
||||
|
||||
/* check the Rx occupied channels which are not masked */
|
||||
irqmask = ~(currentInstance->MR) & IPCC_ALL_RX_BUF;
|
||||
irqmask = irqmask & otherInstance->SR;
|
||||
|
||||
while (irqmask != 0UL) /* if several bits are set, it loops to serve all of them */
|
||||
{
|
||||
bit_pos = 1UL << (ch_count & CHANNEL_INDEX_Msk);
|
||||
|
||||
if ((irqmask & bit_pos) != 0U)
|
||||
{
|
||||
/* mask the channel occupied interrupt */
|
||||
currentInstance->MR |= bit_pos;
|
||||
if (hipcc->ChannelCallbackRx[ch_count] != NULL)
|
||||
{
|
||||
hipcc->ChannelCallbackRx[ch_count](hipcc, ch_count, IPCC_CHANNEL_DIR_RX);
|
||||
}
|
||||
irqmask = irqmask & ~(bit_pos);
|
||||
}
|
||||
ch_count++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Rx occupied callback
|
||||
* @param hipcc IPCC handle
|
||||
* @param ChannelIndex Channel number
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
||||
* @param ChannelDir Channel direction
|
||||
*/
|
||||
__weak void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hipcc);
|
||||
UNUSED(ChannelIndex);
|
||||
UNUSED(ChannelDir);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_IPCC_RxCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Tx free callback
|
||||
* @param hipcc IPCC handle
|
||||
* @param ChannelIndex Channel number
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
||||
* @param ChannelDir Channel direction
|
||||
*/
|
||||
__weak void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hipcc);
|
||||
UNUSED(ChannelIndex);
|
||||
UNUSED(ChannelDir);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_IPCC_TxCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IPCC_Exported_Functions_Group3
|
||||
* @brief IPCC Peripheral State and Error functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral State and Error functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the IPCC handle state.
|
||||
* @param hipcc IPCC handle
|
||||
* @retval IPCC handle state
|
||||
*/
|
||||
HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc)
|
||||
{
|
||||
return hipcc->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IPCC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Mask IPCC interrupts.
|
||||
* @param ChannelIndex Channel number
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
||||
* @param ChannelDir Channel direction
|
||||
*/
|
||||
void IPCC_MaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
|
||||
{
|
||||
IPCC_CommonTypeDef *currentInstance = IPCC_C1;
|
||||
if (ChannelDir == IPCC_CHANNEL_DIR_TX)
|
||||
{
|
||||
/* Mask interrupt */
|
||||
currentInstance->MR |= (IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Mask interrupt */
|
||||
currentInstance->MR |= (IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief Unmask IPCC interrupts.
|
||||
* @param ChannelIndex Channel number
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
||||
* @param ChannelDir Channel direction
|
||||
*/
|
||||
void IPCC_UnmaskInterrupt(uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir)
|
||||
{
|
||||
IPCC_CommonTypeDef *currentInstance = IPCC_C1;
|
||||
if (ChannelDir == IPCC_CHANNEL_DIR_TX)
|
||||
{
|
||||
/* Unmask interrupt */
|
||||
currentInstance->MR &= ~(IPCC_MR_CH1FM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Unmask interrupt */
|
||||
currentInstance->MR &= ~(IPCC_MR_CH1OM_Msk << (ChannelIndex & CHANNEL_INDEX_Msk));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset all callbacks of the handle to NULL.
|
||||
* @param hipcc IPCC handle
|
||||
*/
|
||||
void IPCC_SetDefaultCallbacks(IPCC_HandleTypeDef *hipcc)
|
||||
{
|
||||
uint32_t i;
|
||||
/* Set all callbacks to default */
|
||||
for (i = 0; i < IPCC_CHANNEL_NUMBER; i++)
|
||||
{
|
||||
hipcc->ChannelCallbackRx[i] = HAL_IPCC_RxCallback;
|
||||
hipcc->ChannelCallbackTx[i] = HAL_IPCC_TxCallback;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset IPCC register to default value for the concerned instance.
|
||||
* @param Instance pointer to register
|
||||
*/
|
||||
void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance)
|
||||
{
|
||||
/* Disable RX and TX interrupts */
|
||||
Instance->CR = 0x00000000U;
|
||||
|
||||
/* Mask RX and TX interrupts */
|
||||
Instance->MR = (IPCC_ALL_TX_BUF | IPCC_ALL_RX_BUF);
|
||||
|
||||
/* Clear RX status */
|
||||
Instance->SCR = IPCC_ALL_RX_BUF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_IPCC_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,263 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_ipcc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of Mailbox HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_IPCC_H
|
||||
#define STM32WBxx_HAL_IPCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IPCC IPCC
|
||||
* @brief IPCC HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IPCC_Exported_Constants IPCC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IPCC_Channel IPCC Channel
|
||||
* @{
|
||||
*/
|
||||
#define IPCC_CHANNEL_1 0x00000000U
|
||||
#define IPCC_CHANNEL_2 0x00000001U
|
||||
#define IPCC_CHANNEL_3 0x00000002U
|
||||
#define IPCC_CHANNEL_4 0x00000003U
|
||||
#define IPCC_CHANNEL_5 0x00000004U
|
||||
#define IPCC_CHANNEL_6 0x00000005U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IPCC_Exported_Types IPCC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL IPCC State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IPCC_STATE_RESET = 0x00U, /*!< IPCC not yet initialized or disabled */
|
||||
HAL_IPCC_STATE_READY = 0x01U, /*!< IPCC initialized and ready for use */
|
||||
HAL_IPCC_STATE_BUSY = 0x02U /*!< IPCC internal processing is ongoing */
|
||||
} HAL_IPCC_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IPCC channel direction structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IPCC_CHANNEL_DIR_TX = 0x00U, /*!< Channel direction Tx is used by an MCU to transmit */
|
||||
IPCC_CHANNEL_DIR_RX = 0x01U /*!< Channel direction Rx is used by an MCU to receive */
|
||||
} IPCC_CHANNELDirTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IPCC channel status structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IPCC_CHANNEL_STATUS_FREE = 0x00U, /*!< Means that a new msg can be posted on that channel */
|
||||
IPCC_CHANNEL_STATUS_OCCUPIED = 0x01U /*!< An MCU has posted a msg the other MCU hasn't retrieved */
|
||||
} IPCC_CHANNELStatusTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IPCC handle structure definition
|
||||
*/
|
||||
typedef struct __IPCC_HandleTypeDef
|
||||
{
|
||||
IPCC_TypeDef *Instance; /*!< IPCC registers base address */
|
||||
void (* ChannelCallbackRx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); /*!< Rx Callback registration table */
|
||||
void (* ChannelCallbackTx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir); /*!< Tx Callback registration table */
|
||||
uint32_t callbackRequest; /*!< Store information about callback notification by channel */
|
||||
__IO HAL_IPCC_StateTypeDef State; /*!< IPCC State: initialized or not */
|
||||
} IPCC_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IPCC callback typedef
|
||||
*/
|
||||
typedef void ChannelCb(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IPCC_Exported_Macros IPCC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the specified interrupt.
|
||||
* @param __HANDLE__ specifies the IPCC Handle
|
||||
* @param __CHDIRECTION__ specifies the channels Direction
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
|
||||
* @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
|
||||
*/
|
||||
#define __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__) \
|
||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
||||
((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_RXOIE) : \
|
||||
((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_TXFIE))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified interrupt.
|
||||
* @param __HANDLE__ specifies the IPCC Handle
|
||||
* @param __CHDIRECTION__ specifies the channels Direction
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
|
||||
* @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
|
||||
*/
|
||||
#define __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__) \
|
||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
||||
((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_RXOIE) : \
|
||||
((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_TXFIE))
|
||||
|
||||
/**
|
||||
* @brief Mask the specified interrupt.
|
||||
* @param __HANDLE__ specifies the IPCC Handle
|
||||
* @param __CHDIRECTION__ specifies the channels Direction
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
|
||||
* @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
|
||||
* @param __CHINDEX__ specifies the channels number:
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
||||
*/
|
||||
#define __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
|
||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
||||
((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
|
||||
((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
|
||||
|
||||
/**
|
||||
* @brief Unmask the specified interrupt.
|
||||
* @param __HANDLE__ specifies the IPCC Handle
|
||||
* @param __CHDIRECTION__ specifies the channels Direction
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
|
||||
* @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
|
||||
* @param __CHINDEX__ specifies the channels number:
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IPCC_CHANNEL_1: IPCC Channel 1
|
||||
* @arg IPCC_CHANNEL_2: IPCC Channel 2
|
||||
* @arg IPCC_CHANNEL_3: IPCC Channel 3
|
||||
* @arg IPCC_CHANNEL_4: IPCC Channel 4
|
||||
* @arg IPCC_CHANNEL_5: IPCC Channel 5
|
||||
* @arg IPCC_CHANNEL_6: IPCC Channel 6
|
||||
*/
|
||||
#define __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
|
||||
(((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
|
||||
((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
|
||||
((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IPCC_Exported_Functions IPCC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
/** @defgroup IPCC_Exported_Functions_Group1 Initialization and deinitialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc);
|
||||
HAL_StatusTypeDef HAL_IPCC_DeInit(IPCC_HandleTypeDef *hipcc);
|
||||
void HAL_IPCC_MspInit(IPCC_HandleTypeDef *hipcc);
|
||||
void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IPCC_Exported_Functions_Group2 Communication functions
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb);
|
||||
HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IPCC_Exported_Functions_Group3 Peripheral State and Error functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ****************************************/
|
||||
HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IPCC_IRQ_Handler_and_Callbacks Peripheral IRQ Handler and Callbacks
|
||||
* @{
|
||||
*/
|
||||
/* IRQHandler and Callbacks used in non blocking modes ************************/
|
||||
void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef *const hipcc);
|
||||
void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc);
|
||||
void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_IPCC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,954 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IRDA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_IRDA_H
|
||||
#define STM32WBxx_HAL_IRDA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Types IRDA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IRDA Init Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
|
||||
The baud rate register is computed using the following formula:
|
||||
Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
|
||||
where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
|
||||
|
||||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref IRDA_Word_Length */
|
||||
|
||||
uint32_t Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref IRDA_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref IRDA_Transfer_Mode */
|
||||
|
||||
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
|
||||
to achieve low-power frequency.
|
||||
@note Prescaler value 0 is forbidden */
|
||||
|
||||
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
|
||||
This parameter can be a value of @ref IRDA_Low_Power */
|
||||
|
||||
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the IRDA clock source.
|
||||
This parameter can be a value of @ref IRDA_ClockPrescaler. */
|
||||
|
||||
} IRDA_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA State definition
|
||||
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
|
||||
* - gState contains IRDA state information related to global Handle management
|
||||
* and also information related to Tx operations.
|
||||
* gState value coding follow below described bitmap :
|
||||
* b7-b6 Error information
|
||||
* 00 : No Error
|
||||
* 01 : (Not Used)
|
||||
* 10 : Timeout
|
||||
* 11 : Error
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized. HAL IRDA Init function already called)
|
||||
* b4-b3 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b2 Intrinsic process state
|
||||
* 0 : Ready
|
||||
* 1 : Busy (IP busy with some configuration or internal operations)
|
||||
* b1 (not used)
|
||||
* x : Should be set to 0
|
||||
* b0 Tx state
|
||||
* 0 : Ready (no Tx operation ongoing)
|
||||
* 1 : Busy (Tx operation ongoing)
|
||||
* - RxState contains information related to Rx operations.
|
||||
* RxState value coding follow below described bitmap :
|
||||
* b7-b6 (not used)
|
||||
* xx : Should be set to 00
|
||||
* b5 IP initilisation status
|
||||
* 0 : Reset (IP not initialized)
|
||||
* 1 : Init done (IP not initialized)
|
||||
* b4-b2 (not used)
|
||||
* xxx : Should be set to 000
|
||||
* b1 Rx state
|
||||
* 0 : Ready (no Rx operation ongoing)
|
||||
* 1 : Busy (Rx operation ongoing)
|
||||
* b0 (not used)
|
||||
* x : Should be set to 0.
|
||||
*/
|
||||
typedef uint32_t HAL_IRDA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA clock sources definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
|
||||
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
|
||||
IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
|
||||
IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */
|
||||
IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */
|
||||
} IRDA_ClockSourceTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IRDA handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __IRDA_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
{
|
||||
USART_TypeDef *Instance; /*!< USART registers base address */
|
||||
|
||||
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
|
||||
|
||||
uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
|
||||
|
||||
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
|
||||
|
||||
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
|
||||
|
||||
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
|
||||
|
||||
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
|
||||
|
||||
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
|
||||
|
||||
uint16_t Mask; /*!< USART RX RDR register mask */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< Locking object */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
|
||||
and also related to Tx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
|
||||
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
|
||||
|
||||
uint32_t ErrorCode; /*!< IRDA Error code */
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
|
||||
|
||||
void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
|
||||
|
||||
void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
|
||||
|
||||
void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
|
||||
|
||||
void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
|
||||
|
||||
void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
|
||||
|
||||
void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
|
||||
|
||||
void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
|
||||
|
||||
|
||||
void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
} IRDA_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL IRDA Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
|
||||
HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
|
||||
HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
|
||||
HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
|
||||
HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
|
||||
HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
|
||||
HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
|
||||
HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
|
||||
|
||||
HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
|
||||
HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
|
||||
|
||||
} HAL_IRDA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL IRDA Callback pointer definition
|
||||
*/
|
||||
typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
|
||||
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State_Definition IRDA State Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
|
||||
Value is allowed for gState and RxState */
|
||||
#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
|
||||
Value is allowed for RxState only */
|
||||
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
|
||||
Not to be used for neither gState nor RxState.
|
||||
Value is result of combination (Or) between gState and RxState values */
|
||||
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
|
||||
Value is allowed for gState only */
|
||||
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
|
||||
Value is allowed for gState only */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
|
||||
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Word_Length IRDA Word Length
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
|
||||
#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
|
||||
#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Parity IRDA Parity
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */
|
||||
#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
|
||||
#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */
|
||||
#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */
|
||||
#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Low_Power IRDA Low Power
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */
|
||||
#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_ClockPrescaler Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
|
||||
#define IRDA_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
|
||||
#define IRDA_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
|
||||
#define IRDA_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
|
||||
#define IRDA_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
|
||||
#define IRDA_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
|
||||
#define IRDA_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
|
||||
#define IRDA_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
|
||||
#define IRDA_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
|
||||
#define IRDA_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
|
||||
#define IRDA_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
|
||||
#define IRDA_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_State IRDA State
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */
|
||||
#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Mode IRDA Mode
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */
|
||||
#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */
|
||||
#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */
|
||||
#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */
|
||||
#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
|
||||
#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
|
||||
#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Flags IRDA Flags
|
||||
* Elements values convention: 0xXXXX
|
||||
* - 0xXXXX : Flag mask in the ISR register
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */
|
||||
#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */
|
||||
#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */
|
||||
#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */
|
||||
#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */
|
||||
#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF /*!< IRDA transmit data register empty */
|
||||
#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */
|
||||
#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< IRDA read data register not empty */
|
||||
#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */
|
||||
#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */
|
||||
#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */
|
||||
#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
|
||||
* Elements values convention: 0000ZZZZ0XXYYYYYb
|
||||
* - YYYYY : Interrupt source position in the XX register (5bits)
|
||||
* - XX : Interrupt source register (2bits)
|
||||
* - 01: CR1 register
|
||||
* - 10: CR2 register
|
||||
* - 11: CR3 register
|
||||
* - ZZZZ : Flag position in the ISR register(4bits)
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */
|
||||
#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */
|
||||
#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */
|
||||
#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */
|
||||
#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */
|
||||
|
||||
/* Elements values convention: 000000000XXYYYYYb
|
||||
- YYYYY : Interrupt source position in the XX register (5bits)
|
||||
- XX : Interrupt source register (2bits)
|
||||
- 01: CR1 register
|
||||
- 10: CR2 register
|
||||
- 11: CR3 register */
|
||||
#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */
|
||||
|
||||
/* Elements values convention: 0000ZZZZ00000000b
|
||||
- ZZZZ : Flag position in the ISR register(4bits) */
|
||||
#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */
|
||||
#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */
|
||||
#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
|
||||
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
|
||||
#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
|
||||
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
|
||||
#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
|
||||
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */
|
||||
#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */
|
||||
#define IRDA_CR_POS 5U /*!< IRDA control register position */
|
||||
#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */
|
||||
#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset IRDA handle state.
|
||||
* @param __HANDLE__ IRDA handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
|
||||
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
|
||||
} while(0)
|
||||
#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/** @brief Flush the IRDA DR register.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
|
||||
do{ \
|
||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
|
||||
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Clear the specified IRDA pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref IRDA_CLEAR_PEF
|
||||
* @arg @ref IRDA_CLEAR_FEF
|
||||
* @arg @ref IRDA_CLEAR_NEF
|
||||
* @arg @ref IRDA_CLEAR_OREF
|
||||
* @arg @ref IRDA_CLEAR_TCF
|
||||
* @arg @ref IRDA_CLEAR_IDLEF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/** @brief Clear the IRDA PE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
|
||||
|
||||
|
||||
/** @brief Clear the IRDA FE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
|
||||
|
||||
/** @brief Clear the IRDA NE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
|
||||
|
||||
/** @brief Clear the IRDA ORE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
|
||||
|
||||
/** @brief Clear the IRDA IDLE pending flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
|
||||
|
||||
/** @brief Check whether the specified IRDA flag is set or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
|
||||
* @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
|
||||
* @arg @ref IRDA_FLAG_BUSY Busy flag
|
||||
* @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
|
||||
* @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
|
||||
* @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
|
||||
* @arg @ref IRDA_FLAG_TC Transmission Complete flag
|
||||
* @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
|
||||
* @arg @ref IRDA_FLAG_ORE OverRun Error flag
|
||||
* @arg @ref IRDA_FLAG_NE Noise Error flag
|
||||
* @arg @ref IRDA_FLAG_FE Framing Error flag
|
||||
* @arg @ref IRDA_FLAG_PE Parity Error flag
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
|
||||
/** @brief Enable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
/** @brief Disable the specified IRDA interrupt.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
|
||||
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
|
||||
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_ORE OverRun Error interrupt
|
||||
* @arg @ref IRDA_IT_NE Noise Error interrupt
|
||||
* @arg @ref IRDA_IT_FE Framing Error interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
|
||||
* @arg @ref IRDA_IT_TC Transmission complete interrupt
|
||||
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
|
||||
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
|
||||
* @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
|
||||
* @arg @ref IRDA_IT_PE Parity Error interrupt
|
||||
* @retval The new state of __IT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
|
||||
(((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
|
||||
(__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
|
||||
* to clear the corresponding interrupt
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
|
||||
* @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
|
||||
|
||||
|
||||
/** @brief Set a specific IRDA request flag.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __REQ__ specifies the request flag to set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
|
||||
* @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
|
||||
* @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
|
||||
|
||||
/** @brief Enable the IRDA one bit sample method.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
|
||||
|
||||
/** @brief Disable the IRDA one bit sample method.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
|
||||
|
||||
/** @brief Enable UART/USART associated to IRDA Handle.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
|
||||
|
||||
/** @brief Disable UART/USART associated to IRDA Handle.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Compute the mask to apply to retrieve the received data
|
||||
* according to the word length and to the parity bits activation.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
|
||||
*/
|
||||
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
|
||||
do { \
|
||||
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x01FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x00FF ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
} \
|
||||
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
|
||||
{ \
|
||||
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x007F ; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x003F ; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__HANDLE__)->Mask = 0x0000U; \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
|
||||
* @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
|
||||
|
||||
/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
|
||||
* @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
|
||||
* @retval True or False
|
||||
*/
|
||||
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA frame length is valid.
|
||||
* @param __LENGTH__ IRDA frame length.
|
||||
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
|
||||
((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
|
||||
((__LENGTH__) == IRDA_WORDLENGTH_9B))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA frame parity is valid.
|
||||
* @param __PARITY__ IRDA frame parity.
|
||||
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
|
||||
((__PARITY__) == IRDA_PARITY_EVEN) || \
|
||||
((__PARITY__) == IRDA_PARITY_ODD))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA communication mode is valid.
|
||||
* @param __MODE__ IRDA communication mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA power mode is valid.
|
||||
* @param __MODE__ IRDA power mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
|
||||
((__MODE__) == IRDA_POWERMODE_NORMAL))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA clock Prescaler is valid.
|
||||
* @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
|
||||
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
|
||||
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA state is valid.
|
||||
* @param __STATE__ IRDA state mode.
|
||||
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
|
||||
((__STATE__) == IRDA_STATE_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA associated UART/USART mode is valid.
|
||||
* @param __MODE__ IRDA associated UART/USART mode.
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
|
||||
((__MODE__) == IRDA_MODE_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA sampling rate is valid.
|
||||
* @param __ONEBIT__ IRDA sampling rate.
|
||||
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
|
||||
((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA DMA TX mode is valid.
|
||||
* @param __DMATX__ IRDA DMA TX mode.
|
||||
* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
|
||||
((__DMATX__) == IRDA_DMA_TX_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA DMA RX mode is valid.
|
||||
* @param __DMARX__ IRDA DMA RX mode.
|
||||
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
|
||||
((__DMARX__) == IRDA_DMA_RX_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Ensure that IRDA request is valid.
|
||||
* @param __PARAM__ IRDA request.
|
||||
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
|
||||
*/
|
||||
#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
|
||||
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
|
||||
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include IRDA HAL Extended module */
|
||||
#include "stm32wbxx_hal_irda_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* IO operation functions *****************************************************/
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
|
||||
/* Transfer Abort functions */
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
|
||||
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions ************************************************/
|
||||
|
||||
/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
|
||||
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_IRDA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_irda_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IRDA HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_IRDA_EX_H
|
||||
#define STM32WBxx_HAL_IRDA_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IRDAEx IRDAEx
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Report the IRDA clock source.
|
||||
* @param __HANDLE__ specifies the IRDA Handle.
|
||||
* @param __CLOCKSOURCE__ output variable.
|
||||
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
|
||||
*/
|
||||
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
|
||||
do { \
|
||||
if((__HANDLE__)->Instance == USART1) \
|
||||
{ \
|
||||
switch(__HAL_RCC_GET_USART1_SOURCE()) \
|
||||
{ \
|
||||
case RCC_USART1CLKSOURCE_PCLK2: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_HSI: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_SYSCLK: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
|
||||
break; \
|
||||
case RCC_USART1CLKSOURCE_LSE: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
|
||||
break; \
|
||||
default: \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
break; \
|
||||
} \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
|
||||
} \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_IRDA_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,264 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @brief IWDG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent Watchdog (IWDG) peripheral:
|
||||
* + Initialization and Start functions
|
||||
* + IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IWDG Generic features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
|
||||
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
|
||||
if the main clock fails.
|
||||
|
||||
(+) Once the IWDG is started, the LSI is forced ON and both can not be
|
||||
disabled. The counter starts counting down from the reset value (0xFFF).
|
||||
When it reaches the end of count value (0x000) a reset signal is
|
||||
generated (IWDG reset).
|
||||
|
||||
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
|
||||
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
|
||||
prevented.
|
||||
|
||||
(+) The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
|
||||
reset occurs.
|
||||
|
||||
(+) Debug mode : When the microcontroller enters debug mode (core halted),
|
||||
the IWDG counter either continues to work normally or stops, depending
|
||||
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
|
||||
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
|
||||
|
||||
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
|
||||
The IWDG timeout may vary due to LSI frequency dispersion. STM32WBxx
|
||||
devices provide the capability to measure the LSI frequency (LSI clock
|
||||
connected internally to TIM16 CH1 input capture). The measured value
|
||||
can be used to have an IWDG timeout with an acceptable accuracy.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Use IWDG using HAL_IWDG_Init() function to :
|
||||
(+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
|
||||
clock is forced ON and IWDG counter starts downcounting.
|
||||
(+) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
|
||||
IWDG_WINR.
|
||||
(+) Configure the IWDG prescaler and counter reload value. This reload
|
||||
value will be loaded in the IWDG counter each time the watchdog is
|
||||
reloaded, then the IWDG will start counting down from this value.
|
||||
(+) wait for status flags to be reset
|
||||
(+) Depending on window parameter:
|
||||
(++) If Window Init parameter is same as Window register value,
|
||||
nothing more is done but reload counter value in order to exit
|
||||
function withy exact time base.
|
||||
(++) Else modify Window register. This will automatically reload
|
||||
watchdog counter.
|
||||
|
||||
(#) Then the application program must refresh the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
HAL_IWDG_Refresh() function.
|
||||
|
||||
*** IWDG HAL driver macros list ***
|
||||
====================================
|
||||
[..]
|
||||
Below the list of most used macros in IWDG HAL driver:
|
||||
(+) __HAL_IWDG_START: Enable the IWDG peripheral
|
||||
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
|
||||
the reload register
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
/** @addtogroup IWDG
|
||||
* @brief IWDG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Defines IWDG Private Defines
|
||||
* @{
|
||||
*/
|
||||
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
|
||||
higher prescaler (256), and according to LSI variation, we need to wait at
|
||||
least 6 cycles so 48 ms. */
|
||||
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group1
|
||||
* @brief Initialization and Start functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Start functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the IWDG according to the specified parameters in the
|
||||
IWDG_InitTypeDef of associated handle.
|
||||
(+) Manage Window option.
|
||||
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
|
||||
is reloaded in order to exit function with correct time base.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the IWDG according to the specified parameters in the
|
||||
* IWDG_InitTypeDef and start watchdog. Before exiting function,
|
||||
* watchdog is refreshed in order to have correct time base.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Check the IWDG handle allocation */
|
||||
if (hiwdg == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
|
||||
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
|
||||
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
|
||||
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
|
||||
|
||||
/* Enable IWDG. LSI is turned on automaticaly */
|
||||
__HAL_IWDG_START(hiwdg);
|
||||
|
||||
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
|
||||
0x5555 in KR */
|
||||
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
|
||||
|
||||
/* Write to IWDG registers the Prescaler & Reload values to work with */
|
||||
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
|
||||
hiwdg->Instance->RLR = hiwdg->Init.Reload;
|
||||
|
||||
/* Check pending flag, if previous update not done, return timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait for register to be updated */
|
||||
while (hiwdg->Instance->SR != 0x00u)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* If window parameter is different than current value, modify window
|
||||
register */
|
||||
if (hiwdg->Instance->WINR != hiwdg->Init.Window)
|
||||
{
|
||||
/* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
|
||||
even if window feature is disabled, Watchdog will be reloaded by writing
|
||||
windows register */
|
||||
hiwdg->Instance->WINR = hiwdg->Init.Window;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reload IWDG counter with value defined in the reload register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
}
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup IWDG_Exported_Functions_Group2
|
||||
* @brief IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Refresh the IWDG.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Refresh the IWDG.
|
||||
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified IWDG module.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
|
||||
{
|
||||
/* Reload IWDG counter with value defined in the reload register */
|
||||
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,241 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of IWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_IWDG_H
|
||||
#define STM32WBxx_HAL_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Types IWDG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
|
||||
This parameter can be a value of @ref IWDG_Prescaler */
|
||||
|
||||
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
|
||||
|
||||
} IWDG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief IWDG Handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
IWDG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
|
||||
} IWDG_HandleTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Prescaler IWDG Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
|
||||
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
|
||||
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
|
||||
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
|
||||
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
|
||||
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
|
||||
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Window_option IWDG Window option
|
||||
* @{
|
||||
*/
|
||||
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the IWDG peripheral.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Reload IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/Start functions ********************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
|
||||
* @{
|
||||
*/
|
||||
/* I/O operation functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Constants IWDG Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief IWDG Key Register BitMask
|
||||
*/
|
||||
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
|
||||
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
|
||||
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup IWDG_Private_Macros IWDG Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
|
||||
|
||||
/**
|
||||
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
|
||||
* @param __HANDLE__ IWDG handle
|
||||
* @retval None
|
||||
*/
|
||||
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG prescaler value.
|
||||
* @param __PRESCALER__ IWDG prescaler value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_8) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_16) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_32) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_64) || \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
|
||||
((__PRESCALER__) == IWDG_PRESCALER_256))
|
||||
|
||||
/**
|
||||
* @brief Check IWDG reload value.
|
||||
* @param __RELOAD__ IWDG reload value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
|
||||
|
||||
/**
|
||||
* @brief Check IWDG window value.
|
||||
* @param __WINDOW__ IWDG window value
|
||||
* @retval None
|
||||
*/
|
||||
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_IWDG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,607 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_lcd.c
|
||||
* @author MCD Application Team
|
||||
* @brief LCD Controller HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the LCD Controller (LCD) peripheral:
|
||||
* + Initialization/de-initialization methods
|
||||
* + I/O operation methods
|
||||
* + Peripheral State methods
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] The LCD HAL driver can be used as follows:
|
||||
|
||||
(#) Declare a LCD_HandleTypeDef handle structure.
|
||||
|
||||
-@- The frequency generator allows you to achieve various LCD frame rates
|
||||
starting from an LCD input clock frequency (LCDCLK) which can vary
|
||||
from 32 kHz up to 1 MHz.
|
||||
|
||||
(#) Initialize the LCD low level resources by implementing the HAL_LCD_MspInit() API:
|
||||
|
||||
(++) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows:
|
||||
(+++) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and
|
||||
selected clock source (HSE, LSI or LSE)
|
||||
|
||||
(++) LCD pins configuration:
|
||||
(+++) Enable the clock for the LCD GPIOs.
|
||||
(+++) Configure these LCD pins as alternate function no-pull.
|
||||
(++) Enable the LCD interface clock.
|
||||
|
||||
|
||||
(#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias,
|
||||
Voltage Source, Dead Time, Pulse On Duration, Contrast, High drive and Multiplexer
|
||||
Segment in the Init structure of the LCD handle.
|
||||
|
||||
(#) Initialize the LCD registers by calling the HAL_LCD_Init() API.
|
||||
|
||||
-@- The HAL_LCD_Init() API configures also the low level Hardware GPIO, CLOCK, ...etc)
|
||||
by calling the customized HAL_LCD_MspInit() API.
|
||||
-@- After calling the HAL_LCD_Init() the LCD RAM memory is cleared
|
||||
|
||||
(#) Optionally you can update the LCD configuration using these macros:
|
||||
(++) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros
|
||||
(++) Voltage output buffer using __HAL_LCD_VOLTAGE_BUFFER_ENABLE() and __HAL_LCD_VOLTAGE_BUFFER_DISABLE() macros
|
||||
(++) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro
|
||||
(++) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro
|
||||
(++) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro
|
||||
(++) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro
|
||||
|
||||
(#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called
|
||||
more time to update the different LCD RAM registers before calling
|
||||
HAL_LCD_UpdateDisplayRequest() API.
|
||||
|
||||
(#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory.
|
||||
|
||||
(#) When LCD RAM memory is updated enable the update display request using
|
||||
the HAL_LCD_UpdateDisplayRequest() API.
|
||||
|
||||
[..] LCD and low power modes:
|
||||
(#) The LCD remain active during Sleep, Low Power run, Low Power Sleep and
|
||||
STOP modes.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_LCD_MODULE_ENABLED
|
||||
|
||||
/** @defgroup LCD LCD
|
||||
* @brief LCD HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup LCD_Private_Defines LCD Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_TIMEOUT_VALUE 1000U
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup LCD_Exported_Functions LCD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Exported_Functions_Group1 Initialization/de-initialization methods
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the LCD peripheral according to the specified parameters
|
||||
* in the LCD_InitStruct and initialize the associated handle.
|
||||
* @note This function can be used only when the LCD is disabled.
|
||||
* @param hlcd LCD handle
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t counter;
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
/* Check the LCD handle allocation */
|
||||
if (hlcd == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check function parameters */
|
||||
assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
|
||||
assert_param(IS_LCD_PRESCALER(hlcd->Init.Prescaler));
|
||||
assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider));
|
||||
assert_param(IS_LCD_DUTY(hlcd->Init.Duty));
|
||||
assert_param(IS_LCD_BIAS(hlcd->Init.Bias));
|
||||
assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource));
|
||||
assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration));
|
||||
assert_param(IS_LCD_HIGH_DRIVE(hlcd->Init.HighDrive));
|
||||
assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime));
|
||||
assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast));
|
||||
assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency));
|
||||
assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode));
|
||||
assert_param(IS_LCD_MUX_SEGMENT(hlcd->Init.MuxSegment));
|
||||
|
||||
if (hlcd->State == HAL_LCD_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hlcd->Lock = HAL_UNLOCKED;
|
||||
|
||||
/* Initialize the low level hardware (MSP) */
|
||||
HAL_LCD_MspInit(hlcd);
|
||||
}
|
||||
|
||||
hlcd->State = HAL_LCD_STATE_BUSY;
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_LCD_DISABLE(hlcd);
|
||||
|
||||
/* Clear the LCD_RAM registers and enable the display request by setting the UDR bit
|
||||
in the LCD_SR register */
|
||||
for (counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER7; counter++)
|
||||
{
|
||||
hlcd->Instance->RAM[counter] = 0;
|
||||
}
|
||||
/* Enable the display request */
|
||||
/* hlcd->Instance->SR |= LCD_SR_UDR */
|
||||
/* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency:
|
||||
Set PS[3:0] bits according to hlcd->Init.Prescaler value
|
||||
Set DIV[3:0] bits according to hlcd->Init.Divider value
|
||||
Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value
|
||||
Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value
|
||||
Set DEAD[2:0] bits according to hlcd->Init.DeadTime value
|
||||
Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value
|
||||
Set CC[2:0] bits according to hlcd->Init.Contrast value
|
||||
Set HD bit according to hlcd->Init.HighDrive value */
|
||||
MODIFY_REG(hlcd->Instance->FCR, \
|
||||
(LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK | LCD_FCR_BLINKF | \
|
||||
LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC | LCD_FCR_HD), \
|
||||
(hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \
|
||||
hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive));
|
||||
|
||||
/* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register
|
||||
This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK
|
||||
domain. It is cleared by hardware when writing to the LCD_FCR register.*/
|
||||
status = LCD_WaitForSynchro(hlcd);
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Configure the LCD Duty, Bias, Voltage Source, Dead Time, Pulse On Duration and Contrast:
|
||||
Set DUTY[2:0] bits according to hlcd->Init.Duty value
|
||||
Set BIAS[1:0] bits according to hlcd->Init.Bias value
|
||||
Set VSEL bit according to hlcd->Init.VoltageSource value
|
||||
Set MUX_SEG bit according to hlcd->Init.MuxSegment value */
|
||||
MODIFY_REG(hlcd->Instance->CR, \
|
||||
(LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \
|
||||
(hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment));
|
||||
|
||||
/* Enable the peripheral */
|
||||
__HAL_LCD_ENABLE(hlcd);
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait Until the LCD is enabled */
|
||||
while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
|
||||
{
|
||||
hlcd->ErrorCode = HAL_LCD_ERROR_ENS;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/*!< Wait Until the LCD Booster is ready */
|
||||
while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
|
||||
{
|
||||
hlcd->ErrorCode = HAL_LCD_ERROR_RDY;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Initialize the LCD state */
|
||||
hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
|
||||
hlcd->State = HAL_LCD_STATE_READY;
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the LCD peripheral.
|
||||
* @param hlcd LCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd)
|
||||
{
|
||||
/* Check the LCD handle allocation */
|
||||
if (hlcd == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
|
||||
|
||||
hlcd->State = HAL_LCD_STATE_BUSY;
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
HAL_LCD_MspDeInit(hlcd);
|
||||
|
||||
hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
|
||||
hlcd->State = HAL_LCD_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hlcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the LCD MSP.
|
||||
* @param hlcd LCD handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hlcd);
|
||||
|
||||
/* NOTE: This function should not be modified, when the callback is needed,
|
||||
the HAL_LCD_MspDeInit it to be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the LCD MSP.
|
||||
* @param hlcd LCD handle
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hlcd);
|
||||
|
||||
/* NOTE: This function should not be modified, when the callback is needed,
|
||||
the HAL_LCD_MspInit is to be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Exported_Functions_Group2 IO operation methods
|
||||
* @brief LCD RAM functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] Using its double buffer memory the LCD controller ensures the coherency of the
|
||||
displayed information without having to use interrupts to control LCD_RAM
|
||||
modification.
|
||||
The application software can access the first buffer level (LCD_RAM) through
|
||||
the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API,
|
||||
it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API.
|
||||
This UDR flag (update display request) requests the updated information to be
|
||||
moved into the second buffer level (LCD_DISPLAY).
|
||||
This operation is done synchronously with the frame (at the beginning of the
|
||||
next frame), until the update is completed, the LCD_RAM is write protected and
|
||||
the UDR flag stays high.
|
||||
Once the update is completed another flag (UDD - Update Display Done) is set and
|
||||
generates an interrupt if the UDDIE bit in the LCD_FCR register is set.
|
||||
The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one
|
||||
even frame.
|
||||
The update will not occur (UDR = 1 and UDD = 0) until the display is
|
||||
enabled (LCDEN = 1).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write a word in the specific LCD RAM.
|
||||
* @param hlcd LCD handle
|
||||
* @param RAMRegisterIndex specifies the LCD RAM Register.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_RAM_REGISTER0: LCD RAM Register 0
|
||||
* @arg LCD_RAM_REGISTER1: LCD RAM Register 1
|
||||
* @arg LCD_RAM_REGISTER2: LCD RAM Register 2
|
||||
* @arg LCD_RAM_REGISTER3: LCD RAM Register 3
|
||||
* @arg LCD_RAM_REGISTER4: LCD RAM Register 4
|
||||
* @arg LCD_RAM_REGISTER5: LCD RAM Register 5
|
||||
* @arg LCD_RAM_REGISTER6: LCD RAM Register 6
|
||||
* @arg LCD_RAM_REGISTER7: LCD RAM Register 7
|
||||
* @arg LCD_RAM_REGISTER8: LCD RAM Register 8
|
||||
* @arg LCD_RAM_REGISTER9: LCD RAM Register 9
|
||||
* @arg LCD_RAM_REGISTER10: LCD RAM Register 10
|
||||
* @arg LCD_RAM_REGISTER11: LCD RAM Register 11
|
||||
* @arg LCD_RAM_REGISTER12: LCD RAM Register 12
|
||||
* @arg LCD_RAM_REGISTER13: LCD RAM Register 13
|
||||
* @arg LCD_RAM_REGISTER14: LCD RAM Register 14
|
||||
* @arg LCD_RAM_REGISTER15: LCD RAM Register 15
|
||||
* @param RAMRegisterMask specifies the LCD RAM Register Data Mask.
|
||||
* @param Data specifies LCD Data Value to be written.
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
HAL_LCD_StateTypeDef state = hlcd->State;
|
||||
|
||||
if ((state == HAL_LCD_STATE_READY) || (state == HAL_LCD_STATE_BUSY))
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LCD_RAM_REGISTER(RAMRegisterIndex));
|
||||
|
||||
if (hlcd->State == HAL_LCD_STATE_READY)
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hlcd);
|
||||
hlcd->State = HAL_LCD_STATE_BUSY;
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/*!< Wait Until the LCD is ready */
|
||||
while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
|
||||
{
|
||||
hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hlcd);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy the new Data bytes to LCD RAM register */
|
||||
MODIFY_REG(hlcd->Instance->RAM[RAMRegisterIndex], ~(RAMRegisterMask), Data);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the LCD RAM registers.
|
||||
* @param hlcd LCD handle
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t counter;
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
HAL_LCD_StateTypeDef state = hlcd->State;
|
||||
|
||||
if ((state == HAL_LCD_STATE_READY) || (state == HAL_LCD_STATE_BUSY))
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hlcd);
|
||||
|
||||
hlcd->State = HAL_LCD_STATE_BUSY;
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/*!< Wait Until the LCD is ready */
|
||||
while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
|
||||
{
|
||||
hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hlcd);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
/* Clear the LCD_RAM registers */
|
||||
for (counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
|
||||
{
|
||||
hlcd->Instance->RAM[counter] = 0;
|
||||
}
|
||||
|
||||
/* Update the LCD display */
|
||||
status = HAL_LCD_UpdateDisplayRequest(hlcd);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Update Display Request.
|
||||
* @param hlcd LCD handle
|
||||
* @note Each time software modifies the LCD_RAM it must set the UDR bit to
|
||||
* transfer the updated data to the second level buffer.
|
||||
* The UDR bit stays set until the end of the update and during this
|
||||
* time the LCD_RAM is write protected.
|
||||
* @note When the display is disabled, the update is performed for all
|
||||
* LCD_DISPLAY locations.
|
||||
* When the display is enabled, the update is performed only for locations
|
||||
* for which commons are active (depending on DUTY). For example if
|
||||
* DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Clear the Update Display Done flag before starting the update display request */
|
||||
__HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD);
|
||||
|
||||
/* Enable the display request */
|
||||
hlcd->Instance->SR |= LCD_SR_UDR;
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/*!< Wait Until the LCD display is done */
|
||||
while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
|
||||
{
|
||||
hlcd->ErrorCode = HAL_LCD_ERROR_UDD;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hlcd);
|
||||
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
hlcd->State = HAL_LCD_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hlcd);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods
|
||||
* @brief LCD State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the LCD:
|
||||
(+) HAL_LCD_GetState() API can be helpful to check in run-time the state of the LCD peripheral State.
|
||||
(+) HAL_LCD_GetError() API to return the LCD error code.
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the LCD handle state.
|
||||
* @param hlcd LCD handle
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd)
|
||||
{
|
||||
/* Return LCD handle state */
|
||||
return hlcd->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the LCD error code.
|
||||
* @param hlcd LCD handle
|
||||
* @retval LCD Error Code
|
||||
*/
|
||||
uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd)
|
||||
{
|
||||
return hlcd->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Private_Functions LCD Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Wait until the LCD FCR register is synchronized in the LCDCLK domain.
|
||||
* This function must be called after any write operation to LCD_FCR register.
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Get timeout */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Loop until FCRSF flag is set */
|
||||
while (__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE)
|
||||
{
|
||||
hlcd->ErrorCode = HAL_LCD_ERROR_FCRSF;
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_LCD_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,768 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_lcd.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of LCD Controller HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_LCD_H
|
||||
#define STM32WBxx_HAL_LCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup LCD_Exported_Types LCD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief LCD Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Prescaler; /*!< Configures the LCD Prescaler.
|
||||
This parameter can be one value of @ref LCD_Prescaler */
|
||||
uint32_t Divider; /*!< Configures the LCD Divider.
|
||||
This parameter can be one value of @ref LCD_Divider */
|
||||
uint32_t Duty; /*!< Configures the LCD Duty.
|
||||
This parameter can be one value of @ref LCD_Duty */
|
||||
uint32_t Bias; /*!< Configures the LCD Bias.
|
||||
This parameter can be one value of @ref LCD_Bias */
|
||||
uint32_t VoltageSource; /*!< Selects the LCD Voltage source.
|
||||
This parameter can be one value of @ref LCD_Voltage_Source */
|
||||
uint32_t Contrast; /*!< Configures the LCD Contrast.
|
||||
This parameter can be one value of @ref LCD_Contrast */
|
||||
uint32_t DeadTime; /*!< Configures the LCD Dead Time.
|
||||
This parameter can be one value of @ref LCD_DeadTime */
|
||||
uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
|
||||
This parameter can be one value of @ref LCD_PulseOnDuration */
|
||||
uint32_t HighDrive; /*!< Enable or disable the low resistance divider.
|
||||
This parameter can be one value of @ref LCD_HighDrive */
|
||||
uint32_t BlinkMode; /*!< Configures the LCD Blink Mode.
|
||||
This parameter can be one value of @ref LCD_BlinkMode */
|
||||
uint32_t BlinkFrequency; /*!< Configures the LCD Blink frequency.
|
||||
This parameter can be one value of @ref LCD_BlinkFrequency */
|
||||
uint32_t MuxSegment; /*!< Enable or disable mux segment.
|
||||
This parameter can be one value of @ref LCD_MuxSegment */
|
||||
} LCD_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL LCD State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_LCD_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
|
||||
HAL_LCD_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_LCD_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
|
||||
HAL_LCD_STATE_TIMEOUT = 0x03, /*!< Timeout state */
|
||||
HAL_LCD_STATE_ERROR = 0x04 /*!< Error */
|
||||
} HAL_LCD_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief UART handle Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
LCD_TypeDef *Instance; /* LCD registers base address */
|
||||
|
||||
LCD_InitTypeDef Init; /* LCD communication parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /* Locking object */
|
||||
|
||||
__IO HAL_LCD_StateTypeDef State; /* LCD communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /* LCD Error code */
|
||||
|
||||
} LCD_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup LCD_Exported_Constants LCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_ErrorCode LCD Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_LCD_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_LCD_ERROR_FCRSF (0x00000001U) /*!< Synchro flag timeout error */
|
||||
#define HAL_LCD_ERROR_UDR (0x00000002U) /*!< Update display request flag timeout error */
|
||||
#define HAL_LCD_ERROR_UDD (0x00000004U) /*!< Update display done flag timeout error */
|
||||
#define HAL_LCD_ERROR_ENS (0x00000008U) /*!< LCD enabled status flag timeout error */
|
||||
#define HAL_LCD_ERROR_RDY (0x00000010U) /*!< LCD Booster ready timeout error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Prescaler LCD Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define LCD_PRESCALER_1 (0x00000000U) /*!< CLKPS = LCDCLK */
|
||||
#define LCD_PRESCALER_2 (0x00400000U) /*!< CLKPS = LCDCLK/2 */
|
||||
#define LCD_PRESCALER_4 (0x00800000U) /*!< CLKPS = LCDCLK/4 */
|
||||
#define LCD_PRESCALER_8 (0x00C00000U) /*!< CLKPS = LCDCLK/8 */
|
||||
#define LCD_PRESCALER_16 (0x01000000U) /*!< CLKPS = LCDCLK/16 */
|
||||
#define LCD_PRESCALER_32 (0x01400000U) /*!< CLKPS = LCDCLK/32 */
|
||||
#define LCD_PRESCALER_64 (0x01800000U) /*!< CLKPS = LCDCLK/64 */
|
||||
#define LCD_PRESCALER_128 (0x01C00000U) /*!< CLKPS = LCDCLK/128 */
|
||||
#define LCD_PRESCALER_256 (0x02000000U) /*!< CLKPS = LCDCLK/256 */
|
||||
#define LCD_PRESCALER_512 (0x02400000U) /*!< CLKPS = LCDCLK/512 */
|
||||
#define LCD_PRESCALER_1024 (0x02800000U) /*!< CLKPS = LCDCLK/1024 */
|
||||
#define LCD_PRESCALER_2048 (0x02C00000U) /*!< CLKPS = LCDCLK/2048 */
|
||||
#define LCD_PRESCALER_4096 (0x03000000U) /*!< CLKPS = LCDCLK/4096 */
|
||||
#define LCD_PRESCALER_8192 (0x03400000U) /*!< CLKPS = LCDCLK/8192 */
|
||||
#define LCD_PRESCALER_16384 (0x03800000U) /*!< CLKPS = LCDCLK/16384 */
|
||||
#define LCD_PRESCALER_32768 (0x03C00000U) /*!< CLKPS = LCDCLK/32768 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Divider LCD Divider
|
||||
* @{
|
||||
*/
|
||||
#define LCD_DIVIDER_16 (0x00000000U) /*!< LCD frequency = CLKPS/16 */
|
||||
#define LCD_DIVIDER_17 (0x00040000U) /*!< LCD frequency = CLKPS/17 */
|
||||
#define LCD_DIVIDER_18 (0x00080000U) /*!< LCD frequency = CLKPS/18 */
|
||||
#define LCD_DIVIDER_19 (0x000C0000U) /*!< LCD frequency = CLKPS/19 */
|
||||
#define LCD_DIVIDER_20 (0x00100000U) /*!< LCD frequency = CLKPS/20 */
|
||||
#define LCD_DIVIDER_21 (0x00140000U) /*!< LCD frequency = CLKPS/21 */
|
||||
#define LCD_DIVIDER_22 (0x00180000U) /*!< LCD frequency = CLKPS/22 */
|
||||
#define LCD_DIVIDER_23 (0x001C0000U) /*!< LCD frequency = CLKPS/23 */
|
||||
#define LCD_DIVIDER_24 (0x00200000U) /*!< LCD frequency = CLKPS/24 */
|
||||
#define LCD_DIVIDER_25 (0x00240000U) /*!< LCD frequency = CLKPS/25 */
|
||||
#define LCD_DIVIDER_26 (0x00280000U) /*!< LCD frequency = CLKPS/26 */
|
||||
#define LCD_DIVIDER_27 (0x002C0000U) /*!< LCD frequency = CLKPS/27 */
|
||||
#define LCD_DIVIDER_28 (0x00300000U) /*!< LCD frequency = CLKPS/28 */
|
||||
#define LCD_DIVIDER_29 (0x00340000U) /*!< LCD frequency = CLKPS/29 */
|
||||
#define LCD_DIVIDER_30 (0x00380000U) /*!< LCD frequency = CLKPS/30 */
|
||||
#define LCD_DIVIDER_31 (0x003C0000U) /*!< LCD frequency = CLKPS/31 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LCD_Duty LCD Duty
|
||||
* @{
|
||||
*/
|
||||
#define LCD_DUTY_STATIC (0x00000000U) /*!< Static duty */
|
||||
#define LCD_DUTY_1_2 (LCD_CR_DUTY_0) /*!< 1/2 duty */
|
||||
#define LCD_DUTY_1_3 (LCD_CR_DUTY_1) /*!< 1/3 duty */
|
||||
#define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty */
|
||||
#define LCD_DUTY_1_8 (LCD_CR_DUTY_2) /*!< 1/8 duty */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LCD_Bias LCD Bias
|
||||
* @{
|
||||
*/
|
||||
#define LCD_BIAS_1_4 (0x00000000U) /*!< 1/4 Bias */
|
||||
#define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */
|
||||
#define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Voltage_Source LCD Voltage Source
|
||||
* @{
|
||||
*/
|
||||
#define LCD_VOLTAGESOURCE_INTERNAL (0x00000000U) /*!< Internal voltage source for the LCD */
|
||||
#define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL /*!< External voltage source for the LCD */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Interrupts LCD Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define LCD_IT_SOF LCD_FCR_SOFIE
|
||||
#define LCD_IT_UDD LCD_FCR_UDDIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_PulseOnDuration LCD Pulse On Duration
|
||||
* @{
|
||||
*/
|
||||
#define LCD_PULSEONDURATION_0 (0x00000000U) /*!< Pulse ON duration = 0 pulse */
|
||||
#define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0) /*!< Pulse ON duration = 1/CK_PS */
|
||||
#define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1) /*!< Pulse ON duration = 2/CK_PS */
|
||||
#define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS */
|
||||
#define LCD_PULSEONDURATION_4 (LCD_FCR_PON_2) /*!< Pulse ON duration = 4/CK_PS */
|
||||
#define LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS */
|
||||
#define LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS */
|
||||
#define LCD_PULSEONDURATION_7 (LCD_FCR_PON) /*!< Pulse ON duration = 7/CK_PS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LCD_DeadTime LCD Dead Time
|
||||
* @{
|
||||
*/
|
||||
#define LCD_DEADTIME_0 (0x00000000U) /*!< No dead Time */
|
||||
#define LCD_DEADTIME_1 (LCD_FCR_DEAD_0) /*!< One Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_2 (LCD_FCR_DEAD_1) /*!< Two Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_4 (LCD_FCR_DEAD_2) /*!< Four Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_7 (LCD_FCR_DEAD) /*!< Seven Phase between different couple of Frame */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_BlinkMode LCD Blink Mode
|
||||
* @{
|
||||
*/
|
||||
#define LCD_BLINKMODE_OFF (0x00000000U) /*!< Blink disabled */
|
||||
#define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */
|
||||
#define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1) /*!< Blink enabled on SEG[0], all COM (up to
|
||||
8 pixels according to the programmed duty) */
|
||||
#define LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK) /*!< Blink enabled on all SEG and all COM (all pixels) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_BlinkFrequency LCD Blink Frequency
|
||||
* @{
|
||||
*/
|
||||
#define LCD_BLINKFREQUENCY_DIV8 (0x00000000U) /*!< The Blink frequency = fLCD/8 */
|
||||
#define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/16 */
|
||||
#define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/32 */
|
||||
#define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64 */
|
||||
#define LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2) /*!< The Blink frequency = fLCD/128 */
|
||||
#define LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/256 */
|
||||
#define LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/512 */
|
||||
#define LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF) /*!< The Blink frequency = fLCD/1024 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Contrast LCD Contrast
|
||||
* @{
|
||||
*/
|
||||
#define LCD_CONTRASTLEVEL_0 (0x00000000U) /*!< Maximum Voltage = 2.60V */
|
||||
#define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0) /*!< Maximum Voltage = 2.73V */
|
||||
#define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1) /*!< Maximum Voltage = 2.86V */
|
||||
#define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V */
|
||||
#define LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2) /*!< Maximum Voltage = 3.12V */
|
||||
#define LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.26V */
|
||||
#define LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.40V */
|
||||
#define LCD_CONTRASTLEVEL_7 (LCD_FCR_CC) /*!< Maximum Voltage = 3.55V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_RAMRegister LCD RAMRegister
|
||||
* @{
|
||||
*/
|
||||
#define LCD_RAM_REGISTER0 (0x00000000U) /*!< LCD RAM Register 0 */
|
||||
#define LCD_RAM_REGISTER1 (0x00000001U) /*!< LCD RAM Register 1 */
|
||||
#define LCD_RAM_REGISTER2 (0x00000002U) /*!< LCD RAM Register 2 */
|
||||
#define LCD_RAM_REGISTER3 (0x00000003U) /*!< LCD RAM Register 3 */
|
||||
#define LCD_RAM_REGISTER4 (0x00000004U) /*!< LCD RAM Register 4 */
|
||||
#define LCD_RAM_REGISTER5 (0x00000005U) /*!< LCD RAM Register 5 */
|
||||
#define LCD_RAM_REGISTER6 (0x00000006U) /*!< LCD RAM Register 6 */
|
||||
#define LCD_RAM_REGISTER7 (0x00000007U) /*!< LCD RAM Register 7 */
|
||||
#define LCD_RAM_REGISTER8 (0x00000008U) /*!< LCD RAM Register 8 */
|
||||
#define LCD_RAM_REGISTER9 (0x00000009U) /*!< LCD RAM Register 9 */
|
||||
#define LCD_RAM_REGISTER10 (0x0000000AU) /*!< LCD RAM Register 10 */
|
||||
#define LCD_RAM_REGISTER11 (0x0000000BU) /*!< LCD RAM Register 11 */
|
||||
#define LCD_RAM_REGISTER12 (0x0000000CU) /*!< LCD RAM Register 12 */
|
||||
#define LCD_RAM_REGISTER13 (0x0000000DU) /*!< LCD RAM Register 13 */
|
||||
#define LCD_RAM_REGISTER14 (0x0000000EU) /*!< LCD RAM Register 14 */
|
||||
#define LCD_RAM_REGISTER15 (0x0000000FU) /*!< LCD RAM Register 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_HighDrive LCD High Drive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_HIGHDRIVE_DISABLE ((uint32_t)0x00000000) /*!< High drive disabled */
|
||||
#define LCD_HIGHDRIVE_ENABLE (LCD_FCR_HD) /*!< High drive enabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_MuxSegment LCD Mux Segment
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_MUXSEGMENT_DISABLE (0x00000000U) /*!< SEG pin multiplexing disabled */
|
||||
#define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG) /*!< SEG[31:28] are multiplexed with SEG[43:40] */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Flag_Definition LCD Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define LCD_FLAG_ENS LCD_SR_ENS /*!< LCD enabled status */
|
||||
#define LCD_FLAG_SOF LCD_SR_SOF /*!< Start of frame flag */
|
||||
#define LCD_FLAG_UDR LCD_SR_UDR /*!< Update display request */
|
||||
#define LCD_FLAG_UDD LCD_SR_UDD /*!< Update display done */
|
||||
#define LCD_FLAG_RDY LCD_SR_RDY /*!< Ready flag */
|
||||
#define LCD_FLAG_FCRSF LCD_SR_FCRSR /*!< LCD Frame Control Register Synchronization flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup LCD_Exported_Macros LCD Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset LCD handle state.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
|
||||
|
||||
/** @brief Enable the LCD peripheral.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
|
||||
|
||||
/** @brief Disable the LCD peripheral.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)
|
||||
|
||||
/** @brief Enable the low resistance divider.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @note Displays with high internal resistance may need a longer drive time to
|
||||
* achieve satisfactory contrast. This function is useful in this case if
|
||||
* some additional power consumption can be tolerated.
|
||||
* @note When this mode is enabled, the PulseOn Duration (PON) have to be
|
||||
* programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__) \
|
||||
do { \
|
||||
SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Disable the low resistance divider.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__) \
|
||||
do { \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Enable the voltage output buffer for higher driving capability.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_VOLTAGE_BUFFER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
|
||||
|
||||
/** @brief Disable the voltage output buffer for higher driving capability.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_VOLTAGE_BUFFER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_BUFEN)
|
||||
|
||||
/**
|
||||
* @brief Configure the LCD pulse on duration.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __DURATION__ specifies the LCD pulse on duration in terms of
|
||||
* CK_PS (prescaled LCD clock period) pulses.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_PULSEONDURATION_0: 0 pulse
|
||||
* @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
|
||||
* @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
|
||||
* @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
|
||||
* @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
|
||||
* @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
|
||||
* @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
|
||||
* @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__) \
|
||||
do { \
|
||||
MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Configure the LCD dead time.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __DEADTIME__ specifies the LCD dead time.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_DEADTIME_0: No dead Time
|
||||
* @arg LCD_DEADTIME_1: One Phase between different couple of Frame
|
||||
* @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
|
||||
* @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
|
||||
* @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
|
||||
* @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
|
||||
* @arg LCD_DEADTIME_6: Six Phase between different couple of Frame
|
||||
* @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__) \
|
||||
do { \
|
||||
MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Configure the LCD contrast.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __CONTRAST__ specifies the LCD Contrast.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
|
||||
* @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
|
||||
* @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
|
||||
* @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
|
||||
* @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
|
||||
* @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
|
||||
* @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
|
||||
* @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__) \
|
||||
do { \
|
||||
MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Configure the LCD Blink mode and Blink frequency.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __BLINKMODE__ specifies the LCD blink mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_BLINKMODE_OFF: Blink disabled
|
||||
* @arg LCD_BLINKMODE_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
|
||||
* @arg LCD_BLINKMODE_SEG0_ALLCOM: Blink enabled on SEG[0], all COM (up to 8
|
||||
* pixels according to the programmed duty)
|
||||
* @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM
|
||||
* (all pixels)
|
||||
* @param __BLINKFREQUENCY__ specifies the LCD blink frequency.
|
||||
* @arg LCD_BLINKFREQUENCY_DIV8: The Blink frequency = fLcd/8
|
||||
* @arg LCD_BLINKFREQUENCY_DIV16: The Blink frequency = fLcd/16
|
||||
* @arg LCD_BLINKFREQUENCY_DIV32: The Blink frequency = fLcd/32
|
||||
* @arg LCD_BLINKFREQUENCY_DIV64: The Blink frequency = fLcd/64
|
||||
* @arg LCD_BLINKFREQUENCY_DIV128: The Blink frequency = fLcd/128
|
||||
* @arg LCD_BLINKFREQUENCY_DIV256: The Blink frequency = fLcd/256
|
||||
* @arg LCD_BLINKFREQUENCY_DIV512: The Blink frequency = fLcd/512
|
||||
* @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__) \
|
||||
do { \
|
||||
MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Enable the specified LCD interrupt.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __INTERRUPT__ specifies the LCD interrupt source to be enabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_IT_SOF: Start of Frame Interrupt
|
||||
* @arg LCD_IT_UDD: Update Display Done Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
do { \
|
||||
SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Disable the specified LCD interrupt.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __INTERRUPT__ specifies the LCD interrupt source to be disabled.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_IT_SOF: Start of Frame Interrupt
|
||||
* @arg LCD_IT_UDD: Update Display Done Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
|
||||
do { \
|
||||
CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
|
||||
LCD_WaitForSynchro(__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
/** @brief Check whether the specified LCD interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __IT__ specifies the LCD interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_IT_SOF: Start of Frame Interrupt
|
||||
* @arg LCD_IT_UDD: Update Display Done Interrupt.
|
||||
* @note If the device is in STOP mode (PCLK not provided) UDD will not
|
||||
* generate an interrupt even if UDDIE = 1.
|
||||
* If the display is not enabled the UDD interrupt will never occur.
|
||||
* @retval The state of __IT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
|
||||
|
||||
/** @brief Check whether the specified LCD flag is set or not.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
|
||||
* @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR
|
||||
* goes from 0 to 1. On deactivation it reflects the real status of
|
||||
* LCD so it becomes 0 at the end of the last displayed frame.
|
||||
* @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
|
||||
* the beginning of a new frame, at the same time as the display data is
|
||||
* updated.
|
||||
* @arg LCD_FLAG_UDR: Update Display Request flag.
|
||||
* @arg LCD_FLAG_UDD: Update Display Done flag.
|
||||
* @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
|
||||
* of the step-up converter.
|
||||
* @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
|
||||
* This flag is set by hardware each time the LCD_FCR register is updated
|
||||
* in the LCDCLK domain.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the specified LCD pending flag.
|
||||
* @param __HANDLE__ specifies the LCD Handle.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LCD_FLAG_SOF: Start of Frame Interrupt
|
||||
* @arg LCD_FLAG_UDD: Update Display Done Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->CLR, (__FLAG__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/** @addtogroup LCD_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization methods **********************************/
|
||||
/** @addtogroup LCD_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
|
||||
HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
|
||||
void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
|
||||
void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* IO operation methods *******************************************************/
|
||||
/** @addtogroup LCD_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data);
|
||||
HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
|
||||
HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State methods **************************************************/
|
||||
/** @addtogroup LCD_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd);
|
||||
uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup LCD_Private_Macros LCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_2) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_4) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_8) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_16) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_32) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_64) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_128) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_256) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_512) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_1024) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_2048) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_4096) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_8192) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_16384) || \
|
||||
((__PRESCALER__) == LCD_PRESCALER_32768))
|
||||
|
||||
#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_17) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_18) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_19) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_20) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_21) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_22) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_23) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_24) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_25) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_26) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_27) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_28) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_29) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_30) || \
|
||||
((__DIVIDER__) == LCD_DIVIDER_31))
|
||||
|
||||
#define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC) || \
|
||||
((__DUTY__) == LCD_DUTY_1_2) || \
|
||||
((__DUTY__) == LCD_DUTY_1_3) || \
|
||||
((__DUTY__) == LCD_DUTY_1_4) || \
|
||||
((__DUTY__) == LCD_DUTY_1_8))
|
||||
|
||||
#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
|
||||
((__BIAS__) == LCD_BIAS_1_2) || \
|
||||
((__BIAS__) == LCD_BIAS_1_3))
|
||||
|
||||
#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
|
||||
((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))
|
||||
|
||||
|
||||
#define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_1) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_2) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_3) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_4) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_5) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_6) || \
|
||||
((__DURATION__) == LCD_PULSEONDURATION_7))
|
||||
|
||||
#define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \
|
||||
((__TIME__) == LCD_DEADTIME_1) || \
|
||||
((__TIME__) == LCD_DEADTIME_2) || \
|
||||
((__TIME__) == LCD_DEADTIME_3) || \
|
||||
((__TIME__) == LCD_DEADTIME_4) || \
|
||||
((__TIME__) == LCD_DEADTIME_5) || \
|
||||
((__TIME__) == LCD_DEADTIME_6) || \
|
||||
((__TIME__) == LCD_DEADTIME_7))
|
||||
|
||||
#define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF) || \
|
||||
((__MODE__) == LCD_BLINKMODE_SEG0_COM0) || \
|
||||
((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM) || \
|
||||
((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))
|
||||
|
||||
#define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
|
||||
((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))
|
||||
|
||||
#define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
|
||||
((__CONTRAST__) == LCD_CONTRASTLEVEL_7))
|
||||
|
||||
#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER1) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER2) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER3) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER4) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER5) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER6) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER7) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER8) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER9) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER10) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER11) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER12) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER13) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER14) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER15))
|
||||
|
||||
#define IS_LCD_HIGH_DRIVE(__VALUE__) (((__VALUE__) == LCD_HIGHDRIVE_DISABLE) || \
|
||||
((__VALUE__) == LCD_HIGHDRIVE_ENABLE))
|
||||
|
||||
#define IS_LCD_MUX_SEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
|
||||
((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @addtogroup LCD_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_LCD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,760 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_lptim.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of LPTIM HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_LPTIM_H
|
||||
#define STM32WBxx_HAL_LPTIM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (LPTIM1) || defined (LPTIM2)
|
||||
|
||||
/** @addtogroup LPTIM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief LPTIM Clock configuration definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Source; /*!< Selects the clock source.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Source */
|
||||
|
||||
uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Prescaler */
|
||||
|
||||
} LPTIM_ClockConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM Clock configuration definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
|
||||
if the ULPTIM input is selected.
|
||||
Note: This parameter is used only when Ultra low power clock source is used.
|
||||
Note: If the polarity is configured on 'both edges', an auxiliary clock
|
||||
(one of the Low power oscillator) must be active.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Polarity */
|
||||
|
||||
uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
|
||||
Note: This parameter is used only when Ultra low power clock source is used.
|
||||
This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
|
||||
|
||||
} LPTIM_ULPClockConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM Trigger configuration definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Source; /*!< Selects the Trigger source.
|
||||
This parameter can be a value of @ref LPTIM_Trigger_Source */
|
||||
|
||||
uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
|
||||
Note: This parameter is used only when an external trigger is used.
|
||||
This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
|
||||
|
||||
uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
|
||||
Note: This parameter is used only when an external trigger is used.
|
||||
This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
|
||||
} LPTIM_TriggerConfigTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM Initialization Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
|
||||
|
||||
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */
|
||||
|
||||
LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
|
||||
|
||||
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
|
||||
This parameter can be a value of @ref LPTIM_Output_Polarity */
|
||||
|
||||
uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
|
||||
values is done immediately or after the end of current period.
|
||||
This parameter can be a value of @ref LPTIM_Updating_Mode */
|
||||
|
||||
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
|
||||
or each external event.
|
||||
This parameter can be a value of @ref LPTIM_Counter_Source */
|
||||
|
||||
uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
|
||||
This parameter can be a value of @ref LPTIM_Input1_Source */
|
||||
|
||||
uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
|
||||
Note: This parameter is used only for encoder feature so is used only
|
||||
for LPTIM1 instance.
|
||||
This parameter can be a value of @ref LPTIM_Input2_Source */
|
||||
} LPTIM_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL LPTIM State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
|
||||
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
|
||||
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
|
||||
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
|
||||
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
|
||||
} HAL_LPTIM_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief LPTIM handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __LPTIM_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
{
|
||||
LPTIM_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
|
||||
|
||||
HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< LPTIM locking object */
|
||||
|
||||
__IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
|
||||
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */
|
||||
void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */
|
||||
void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */
|
||||
void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */
|
||||
void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */
|
||||
void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */
|
||||
void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */
|
||||
void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */
|
||||
void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
} LPTIM_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL LPTIM Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */
|
||||
HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */
|
||||
HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */
|
||||
HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */
|
||||
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */
|
||||
HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */
|
||||
HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */
|
||||
HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */
|
||||
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */
|
||||
} HAL_LPTIM_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL TIM Callback pointer definition
|
||||
*/
|
||||
typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */
|
||||
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
|
||||
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_PRESCALER_DIV1 0x00000000U
|
||||
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
|
||||
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
|
||||
#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
|
||||
#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
|
||||
#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
|
||||
#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
|
||||
#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
|
||||
#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
|
||||
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
|
||||
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
|
||||
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U
|
||||
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
|
||||
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
|
||||
#define LPTIM_TRIGSOURCE_0 0x00000000U
|
||||
#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
|
||||
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
|
||||
#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
|
||||
#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
|
||||
#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
|
||||
#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
|
||||
#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
|
||||
#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
|
||||
#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
|
||||
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
|
||||
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
|
||||
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_UPDATE_IMMEDIATE 0x00000000U
|
||||
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
|
||||
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U /*!< For LPTIM1 and LPTIM2 */
|
||||
#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_OR_0 /*!< For LPTIM1 and LPTIM2 */
|
||||
#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM2 */
|
||||
#define LPTIM_INPUT1SOURCE_COMP1_COMP2 LPTIM_OR_OR /*!< For LPTIM2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U /*!< For LPTIM1 */
|
||||
#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_OR_1 /*!< For LPTIM1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
|
||||
#define LPTIM_FLAG_UP LPTIM_ISR_UP
|
||||
#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
|
||||
#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
|
||||
#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
|
||||
#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
|
||||
#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
|
||||
#define LPTIM_IT_UP LPTIM_IER_UPIE
|
||||
#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
|
||||
#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
|
||||
#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
|
||||
#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
|
||||
#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset LPTIM handle state.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enable the LPTIM peripheral.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
|
||||
|
||||
/**
|
||||
* @brief Disable the LPTIM peripheral.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @note The following sequence is required to solve LPTIM disable HW limitation.
|
||||
* Please check Errata Sheet ES0335 for more details under "MCU may remain
|
||||
* stuck in LPTIM interrupt when entering Stop mode" section.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
|
||||
|
||||
/**
|
||||
* @brief Start the LPTIM peripheral in Continuous mode.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
|
||||
/**
|
||||
* @brief Start the LPTIM peripheral in single mode.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
|
||||
|
||||
/**
|
||||
* @brief Reset the LPTIM Counter register in synchronous mode.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
|
||||
|
||||
/**
|
||||
* @brief Reset after read of the LPTIM Counter register in asynchronous mode.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
|
||||
|
||||
/**
|
||||
* @brief Write the passed parameter in the Autoreload register.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __VALUE__ Autoreload value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Write the passed parameter in the Compare register.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __VALUE__ Compare value
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified LPTIM flag is set or not.
|
||||
* @param __HANDLE__ LPTIM handle
|
||||
* @param __FLAG__ LPTIM flag to check
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
|
||||
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
|
||||
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
|
||||
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
|
||||
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
|
||||
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
|
||||
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
|
||||
* @retval The state of the specified flag (SET or RESET).
|
||||
*/
|
||||
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clear the specified LPTIM flag.
|
||||
* @param __HANDLE__ LPTIM handle.
|
||||
* @param __FLAG__ LPTIM flag to clear.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
|
||||
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
|
||||
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
|
||||
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
|
||||
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
|
||||
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
|
||||
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Enable the specified LPTIM interrupt.
|
||||
* @param __HANDLE__ LPTIM handle.
|
||||
* @param __INTERRUPT__ LPTIM interrupt to set.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the specified LPTIM interrupt.
|
||||
* @param __HANDLE__ LPTIM handle.
|
||||
* @param __INTERRUPT__ LPTIM interrupt to set.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified LPTIM interrupt source is enabled or not.
|
||||
* @param __HANDLE__ LPTIM handle.
|
||||
* @param __INTERRUPT__ LPTIM interrupt to check.
|
||||
* This parameter can be a value of:
|
||||
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
|
||||
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
|
||||
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
|
||||
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
|
||||
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
|
||||
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
|
||||
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
|
||||
* @retval Interrupt status.
|
||||
*/
|
||||
|
||||
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
|
||||
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* MSP functions *************************************************************/
|
||||
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* Start/Stop operation functions *********************************************/
|
||||
/* ################################# PWM Mode ################################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################# One Pulse Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################## Set once Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
|
||||
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################### Encoder Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################# Time out Mode ##############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* ############################## Counter Mode ###############################*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
|
||||
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* Reading operation functions ************************************************/
|
||||
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
|
||||
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* LPTIM IRQ functions *******************************************************/
|
||||
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* CallBack functions ********************************************************/
|
||||
void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Types LPTIM Private Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
|
||||
((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
|
||||
|
||||
|
||||
#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
|
||||
((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
|
||||
|
||||
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
|
||||
|
||||
#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
|
||||
((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
|
||||
|
||||
#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
|
||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
|
||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
|
||||
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
|
||||
|
||||
#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
|
||||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
|
||||
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
|
||||
|
||||
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
|
||||
((__TRIG__) == LPTIM_TRIGSOURCE_7))
|
||||
|
||||
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
|
||||
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
|
||||
((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
|
||||
|
||||
#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
|
||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
|
||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
|
||||
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
|
||||
|
||||
#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
|
||||
((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
|
||||
|
||||
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
|
||||
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
|
||||
|
||||
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
|
||||
|
||||
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
|
||||
|
||||
#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
|
||||
|
||||
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
|
||||
|
||||
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
((((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
|
||||
|| \
|
||||
(((__INSTANCE__) == LPTIM2) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
|
||||
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
|
||||
|
||||
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
|
||||
(((__INSTANCE__) == LPTIM1) && \
|
||||
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
|
||||
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
|
||||
* @{
|
||||
*/
|
||||
void LPTIM_Disable(LPTIM_HandleTypeDef *lptim);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LPTIM1 || LPTIM2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_LPTIM_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,941 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_pcd.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_PCD_H
|
||||
#define STM32WBxx_HAL_PCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_ll_usb.h"
|
||||
|
||||
#if defined (USB)
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Types PCD Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PCD State structure definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCD_STATE_RESET = 0x00,
|
||||
HAL_PCD_STATE_READY = 0x01,
|
||||
HAL_PCD_STATE_ERROR = 0x02,
|
||||
HAL_PCD_STATE_BUSY = 0x03,
|
||||
HAL_PCD_STATE_TIMEOUT = 0x04
|
||||
} PCD_StateTypeDef;
|
||||
|
||||
/* Device LPM suspend state */
|
||||
typedef enum
|
||||
{
|
||||
LPM_L0 = 0x00, /* on */
|
||||
LPM_L1 = 0x01, /* LPM L1 sleep */
|
||||
LPM_L2 = 0x02, /* suspend */
|
||||
LPM_L3 = 0x03, /* off */
|
||||
} PCD_LPM_StateTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PCD_LPM_L0_ACTIVE = 0x00, /* on */
|
||||
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
|
||||
} PCD_LPM_MsgTypeDef;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
PCD_BCD_ERROR = 0xFF,
|
||||
PCD_BCD_CONTACT_DETECTION = 0xFE,
|
||||
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
|
||||
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
|
||||
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
|
||||
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
|
||||
|
||||
} PCD_BCD_MsgTypeDef;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
typedef USB_TypeDef PCD_TypeDef;
|
||||
typedef USB_CfgTypeDef PCD_InitTypeDef;
|
||||
typedef USB_EPTypeDef PCD_EPTypeDef;
|
||||
|
||||
|
||||
/**
|
||||
* @brief PCD Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
typedef struct __PCD_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
{
|
||||
PCD_TypeDef *Instance; /*!< Register base address */
|
||||
PCD_InitTypeDef Init; /*!< PCD required parameters */
|
||||
__IO uint8_t USB_Address; /*!< USB Address */
|
||||
PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
|
||||
PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
|
||||
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
|
||||
__IO PCD_StateTypeDef State; /*!< PCD communication state */
|
||||
__IO uint32_t ErrorCode; /*!< PCD Error code */
|
||||
uint32_t Setup[12]; /*!< Setup packet buffer */
|
||||
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
|
||||
uint32_t BESL;
|
||||
|
||||
|
||||
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
void *pData; /*!< Pointer to upper stack Handler */
|
||||
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
|
||||
void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
|
||||
void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
|
||||
void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
|
||||
void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
|
||||
void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
|
||||
void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
|
||||
|
||||
void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
|
||||
void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
|
||||
void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
|
||||
void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
|
||||
void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
|
||||
void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
|
||||
|
||||
void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
} PCD_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PCD HAL Extended module */
|
||||
#include "stm32wbxx_hal_pcd_ex.h"
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Constants PCD Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Speed PCD Speed
|
||||
* @{
|
||||
*/
|
||||
#define PCD_SPEED_FULL 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_PHY_Module PCD PHY Module
|
||||
* @{
|
||||
*/
|
||||
#define PCD_PHY_ULPI 1U
|
||||
#define PCD_PHY_EMBEDDED 2U
|
||||
#define PCD_PHY_UTMI 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_Error_Code_definition PCD Error Code definition
|
||||
* @brief PCD Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PCD_Exported_Macros PCD Exported Macros
|
||||
* @brief macros to handle interrupts and specific clock configurations
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
|
||||
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
|
||||
|
||||
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
|
||||
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
|
||||
* @brief HAL USB OTG PCD Callback ID enumeration definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
|
||||
HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
|
||||
HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
|
||||
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
|
||||
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
|
||||
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
|
||||
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
|
||||
|
||||
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
|
||||
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
|
||||
|
||||
} HAL_PCD_CallbackIDTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
|
||||
* @brief HAL USB OTG PCD Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
|
||||
typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
|
||||
typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
|
||||
typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
|
||||
typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
|
||||
typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
|
||||
typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
|
||||
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
|
||||
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Peripheral State functions ************************************************/
|
||||
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup PCD_Private_Constants PCD Private Constants
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#define USB_WAKEUP_EXTI_LINE (0x1U << 28) /*!< USB FS EXTI Line WakeUp Interrupt */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
|
||||
* @{
|
||||
*/
|
||||
#define PCD_EP0MPS_64 DEP0CTL_MPS_64
|
||||
#define PCD_EP0MPS_32 DEP0CTL_MPS_32
|
||||
#define PCD_EP0MPS_16 DEP0CTL_MPS_16
|
||||
#define PCD_EP0MPS_08 DEP0CTL_MPS_8
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_ENDP PCD ENDP
|
||||
* @{
|
||||
*/
|
||||
#define PCD_ENDP0 0U
|
||||
#define PCD_ENDP1 1U
|
||||
#define PCD_ENDP2 2U
|
||||
#define PCD_ENDP3 3U
|
||||
#define PCD_ENDP4 4U
|
||||
#define PCD_ENDP5 5U
|
||||
#define PCD_ENDP6 6U
|
||||
#define PCD_ENDP7 7U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
|
||||
* @{
|
||||
*/
|
||||
#define PCD_SNG_BUF 0U
|
||||
#define PCD_DBL_BUF 1U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup PCD_Private_Macros PCD Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/******************** Bit definition for USB_COUNTn_RX register *************/
|
||||
#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
|
||||
#define USB_CNTRX_BLSIZE (0x1U << 15)
|
||||
|
||||
/* SetENDPOINT */
|
||||
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
|
||||
|
||||
/* GetENDPOINT */
|
||||
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
|
||||
|
||||
/* ENDPOINT transfer */
|
||||
#define USB_EP0StartXfer USB_EPStartXfer
|
||||
|
||||
/**
|
||||
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wType Endpoint Type.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||
((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
|
||||
|
||||
/**
|
||||
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval Endpoint Type
|
||||
*/
|
||||
#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
|
||||
|
||||
/**
|
||||
* @brief free buffer used from the application realizing it to the line
|
||||
* toggles bit SW_BUF in the double buffered endpoint register
|
||||
* @param USBx USB device.
|
||||
* @param bEpNum, bDir
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \
|
||||
if ((bDir) == 0U) \
|
||||
{ \
|
||||
/* OUT double buffered endpoint */ \
|
||||
PCD_TX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
else if ((bDir) == 1U) \
|
||||
{ \
|
||||
/* IN double buffered endpoint */ \
|
||||
PCD_RX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wState new state
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG2; \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_TX_STATUS */
|
||||
|
||||
/**
|
||||
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wState new state
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_RX_STATUS */
|
||||
|
||||
/**
|
||||
* @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wStaterx new state.
|
||||
* @param wStatetx new state.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||
} \
|
||||
/* toggle first bit ? */ \
|
||||
if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG2; \
|
||||
} \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_TXRX_STATUS */
|
||||
|
||||
/**
|
||||
* @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
|
||||
* /STAT_RX[1:0])
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval status
|
||||
*/
|
||||
#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
|
||||
#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
|
||||
|
||||
/**
|
||||
* @brief sets directly the VALID tx/rx-status into the endpoint register
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
|
||||
#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
|
||||
|
||||
/**
|
||||
* @brief checks stall condition in an endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval TRUE = endpoint in stall condition.
|
||||
*/
|
||||
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
|
||||
== USB_EP_TX_STALL)
|
||||
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
|
||||
== USB_EP_RX_STALL)
|
||||
|
||||
/**
|
||||
* @brief set & clear EP_KIND bit.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_KIND(USBx, bEpNum) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
|
||||
} while(0) /* PCD_SET_EP_KIND */
|
||||
|
||||
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_CLEAR_EP_KIND */
|
||||
|
||||
/**
|
||||
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
|
||||
#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
|
||||
|
||||
/**
|
||||
* @brief Sets/clears directly EP_KIND bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
|
||||
#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
|
||||
|
||||
/**
|
||||
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_CLEAR_RX_EP_CTR */
|
||||
|
||||
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
|
||||
} while(0) /* PCD_CLEAR_TX_EP_CTR */
|
||||
|
||||
/**
|
||||
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_RX_DTOG(USBx, bEpNum) do { \
|
||||
register uint16_t _wEPVal; \
|
||||
\
|
||||
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
|
||||
} while(0) /* PCD_RX_DTOG */
|
||||
|
||||
#define PCD_TX_DTOG(USBx, bEpNum) do { \
|
||||
register uint16_t _wEPVal; \
|
||||
\
|
||||
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
|
||||
} while(0) /* PCD_TX_DTOG */
|
||||
/**
|
||||
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
|
||||
\
|
||||
if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
|
||||
{ \
|
||||
PCD_RX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
} while(0) /* PCD_CLEAR_RX_DTOG */
|
||||
|
||||
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
|
||||
\
|
||||
if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
|
||||
{ \
|
||||
PCD_TX_DTOG((USBx), (bEpNum)); \
|
||||
} \
|
||||
} while(0) /* PCD_CLEAR_TX_DTOG */
|
||||
|
||||
/**
|
||||
* @brief Sets address in an endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param bAddr Address.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
|
||||
\
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
|
||||
} while(0) /* PCD_SET_EP_ADDRESS */
|
||||
|
||||
/**
|
||||
* @brief Gets address in an endpoint register.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
|
||||
|
||||
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
|
||||
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
|
||||
|
||||
/**
|
||||
* @brief sets address of the tx/rx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wAddr address to be set (must be word aligned).
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \
|
||||
register uint16_t *_wRegVal; \
|
||||
register uint32_t _wRegBase = (uint32_t)USBx; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
|
||||
*_wRegVal = ((wAddr) >> 1) << 1; \
|
||||
} while(0) /* PCD_SET_EP_TX_ADDRESS */
|
||||
|
||||
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \
|
||||
register uint16_t *_wRegVal; \
|
||||
register uint32_t _wRegBase = (uint32_t)USBx; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
|
||||
*_wRegVal = ((wAddr) >> 1) << 1; \
|
||||
} while(0) /* PCD_SET_EP_RX_ADDRESS */
|
||||
|
||||
/**
|
||||
* @brief Gets address of the tx/rx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval address of the buffer.
|
||||
*/
|
||||
#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
|
||||
#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
|
||||
|
||||
/**
|
||||
* @brief Sets counter of rx buffer with no. of blocks.
|
||||
* @param pdwReg Register pointer
|
||||
* @param wCount Counter.
|
||||
* @param wNBlocks no. of Blocks.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \
|
||||
(wNBlocks) = (wCount) >> 5; \
|
||||
*(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
|
||||
} while(0) /* PCD_CALC_BLK32 */
|
||||
|
||||
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \
|
||||
(wNBlocks) = (wCount) >> 1; \
|
||||
if (((wCount) & 0x1U) != 0U) \
|
||||
{ \
|
||||
(wNBlocks)++; \
|
||||
} \
|
||||
*(pdwReg) = (uint16_t)((wNBlocks) << 10); \
|
||||
} while(0) /* PCD_CALC_BLK2 */
|
||||
|
||||
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \
|
||||
uint32_t wNBlocks; \
|
||||
if ((wCount) == 0U) \
|
||||
{ \
|
||||
*(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
|
||||
*(pdwReg) |= USB_CNTRX_BLSIZE; \
|
||||
} \
|
||||
else if((wCount) < 62U) \
|
||||
{ \
|
||||
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
PCD_CALC_BLK32((pdwReg),(wCount), wNBlocks); \
|
||||
} \
|
||||
} while(0) /* PCD_SET_EP_CNT_RX_REG */
|
||||
|
||||
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \
|
||||
register uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
uint16_t *pdwReg; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
pdwReg = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
|
||||
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief sets counter for the tx/rx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wCount Counter value.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \
|
||||
register uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
uint16_t *_wRegVal; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
|
||||
*_wRegVal = (uint16_t)(wCount); \
|
||||
} while(0)
|
||||
|
||||
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \
|
||||
register uint32_t _wRegBase = (uint32_t)(USBx); \
|
||||
uint16_t *_wRegVal; \
|
||||
\
|
||||
_wRegBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wRegVal = (uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
|
||||
PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief gets counter of the tx buffer.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
|
||||
#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
|
||||
|
||||
/**
|
||||
* @brief Sets buffer 0/1 address in a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wBuf0Addr buffer 0 address.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \
|
||||
PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF0_ADDR */
|
||||
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \
|
||||
PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF1_ADDR */
|
||||
|
||||
/**
|
||||
* @brief Sets addresses in a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param wBuf0Addr: buffer 0 address.
|
||||
* @param wBuf1Addr = buffer 1 address.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \
|
||||
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
|
||||
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF_ADDR */
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
|
||||
#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 address of a double buffer endpoint.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @param bDir endpoint dir EP_DBUF_OUT = OUT
|
||||
* EP_DBUF_IN = IN
|
||||
* @param wCount: Counter value
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \
|
||||
if ((bDir) == 0U) \
|
||||
/* OUT endpoint */ \
|
||||
{ \
|
||||
PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
if ((bDir) == 1U) \
|
||||
{ \
|
||||
/* IN endpoint */ \
|
||||
PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
|
||||
} \
|
||||
} \
|
||||
} while(0) /* SetEPDblBuf0Count*/
|
||||
|
||||
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \
|
||||
register uint32_t _wBase = (uint32_t)(USBx); \
|
||||
uint16_t *_wEPRegVal; \
|
||||
\
|
||||
if ((bDir) == 0U) \
|
||||
{ \
|
||||
/* OUT endpoint */ \
|
||||
PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
if ((bDir) == 1U) \
|
||||
{ \
|
||||
/* IN endpoint */ \
|
||||
_wBase += (uint32_t)(USBx)->BTABLE; \
|
||||
_wEPRegVal = (uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
|
||||
*_wEPRegVal = (uint16_t)(wCount); \
|
||||
} \
|
||||
} \
|
||||
} while(0) /* SetEPDblBuf1Count */
|
||||
|
||||
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \
|
||||
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
|
||||
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
|
||||
} while(0) /* PCD_SET_EP_DBUF_CNT */
|
||||
|
||||
/**
|
||||
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
|
||||
* @param USBx USB peripheral instance register address.
|
||||
* @param bEpNum Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
|
||||
#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_PCD_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,334 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_pcd_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief PCD Extended HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the USB Peripheral Controller:
|
||||
* + Extended features functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCDEx PCDEx
|
||||
* @brief PCD Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
|
||||
#if defined (USB)
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @brief PCDEx control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended features functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Update FIFO configuration
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure PMA for EP
|
||||
* @param hpcd Device instance
|
||||
* @param ep_addr endpoint address
|
||||
* @param ep_kind endpoint Kind
|
||||
* USB_SNG_BUF: Single Buffer used
|
||||
* USB_DBL_BUF: Double Buffer used
|
||||
* @param pmaadress: EP address in The PMA: In case of single buffer endpoint
|
||||
* this parameter is 16-bit value providing the address
|
||||
* in PMA allocated to endpoint.
|
||||
* In case of double buffer endpoint this parameter
|
||||
* is a 32-bit value providing the endpoint buffer 0 address
|
||||
* in the LSB part of 32-bit value and endpoint buffer 1 address
|
||||
* in the MSB part of 32-bit value.
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
|
||||
uint16_t ep_addr,
|
||||
uint16_t ep_kind,
|
||||
uint32_t pmaadress)
|
||||
{
|
||||
PCD_EPTypeDef *ep;
|
||||
|
||||
/* initialize ep structure*/
|
||||
if ((0x80U & ep_addr) == 0x80U)
|
||||
{
|
||||
ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &hpcd->OUT_ep[ep_addr];
|
||||
}
|
||||
|
||||
/* Here we check if the endpoint is single or double Buffer*/
|
||||
if (ep_kind == PCD_SNG_BUF)
|
||||
{
|
||||
/* Single Buffer */
|
||||
ep->doublebuffer = 0U;
|
||||
/* Configure the PMA */
|
||||
ep->pmaadress = (uint16_t)pmaadress;
|
||||
}
|
||||
else /* USB_DBL_BUF */
|
||||
{
|
||||
/* Double Buffer Endpoint */
|
||||
ep->doublebuffer = 1U;
|
||||
/* Configure the PMA */
|
||||
ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU);
|
||||
ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Activate BatteryCharging feature.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
hpcd->battery_charging_active = 1U;
|
||||
|
||||
/* Enable DCD : Data Contact Detect */
|
||||
USBx->BCDR &= ~(USB_BCDR_PDEN);
|
||||
USBx->BCDR &= ~(USB_BCDR_SDEN);
|
||||
USBx->BCDR |= USB_BCDR_DCDEN;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivate BatteryCharging feature.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
hpcd->battery_charging_active = 0U;
|
||||
|
||||
USBx->BCDR &= ~(USB_BCDR_BCDEN);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle BatteryCharging Process.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait Detect flag or a timeout is happen*/
|
||||
while ((USBx->BCDR & USB_BCDR_DCDET) == 0U)
|
||||
{
|
||||
/* Check for the Timeout */
|
||||
if ((HAL_GetTick() - tickstart) > 1000U)
|
||||
{
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
HAL_Delay(200U);
|
||||
|
||||
/* Data Pin Contact ? Check Detect flag */
|
||||
if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET)
|
||||
{
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
/* Primary detection: checks if connected to Standard Downstream Port
|
||||
(without charging capability) */
|
||||
USBx->BCDR &= ~(USB_BCDR_DCDEN);
|
||||
HAL_Delay(50U);
|
||||
USBx->BCDR |= (USB_BCDR_PDEN);
|
||||
HAL_Delay(50U);
|
||||
|
||||
/* If Charger detect ? */
|
||||
if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET)
|
||||
{
|
||||
/* Start secondary detection to check connection to Charging Downstream
|
||||
Port or Dedicated Charging Port */
|
||||
USBx->BCDR &= ~(USB_BCDR_PDEN);
|
||||
HAL_Delay(50U);
|
||||
USBx->BCDR |= (USB_BCDR_SDEN);
|
||||
HAL_Delay(50U);
|
||||
|
||||
/* If CDP ? */
|
||||
if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET)
|
||||
{
|
||||
/* Dedicated Downstream Port DCP */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Charging Downstream Port CDP */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
else /* NO */
|
||||
{
|
||||
/* Standard Downstream Port */
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
/* Battery Charging capability discovery finished Start Enumeration */
|
||||
(void)HAL_PCDEx_DeActivateBCD(hpcd);
|
||||
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
|
||||
hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
|
||||
#else
|
||||
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
|
||||
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Activate LPM feature.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
hpcd->lpm_active = 1U;
|
||||
hpcd->LPM_State = LPM_L0;
|
||||
|
||||
USBx->LPMCSR |= USB_LPMCSR_LMPEN;
|
||||
USBx->LPMCSR |= USB_LPMCSR_LPMACK;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deactivate LPM feature.
|
||||
* @param hpcd PCD handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
|
||||
{
|
||||
USB_TypeDef *USBx = hpcd->Instance;
|
||||
|
||||
hpcd->lpm_active = 0U;
|
||||
|
||||
USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN);
|
||||
USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Send LPM message to user layer callback.
|
||||
* @param hpcd PCD handle
|
||||
* @param msg LPM message
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hpcd);
|
||||
UNUSED(msg);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_PCDEx_LPM_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Send BatteryCharging message to user layer callback.
|
||||
* @param hpcd PCD handle
|
||||
* @param msg LPM message
|
||||
* @retval HAL status
|
||||
*/
|
||||
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hpcd);
|
||||
UNUSED(msg);
|
||||
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_PCDEx_BCD_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) */
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_pcd_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PCD HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_PCD_EX_H
|
||||
#define STM32WBxx_HAL_PCD_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
#if defined (USB)
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PCDEx
|
||||
* @{
|
||||
*/
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd,
|
||||
uint16_t ep_addr,
|
||||
uint16_t ep_kind,
|
||||
uint32_t pmaadress);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
|
||||
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
|
||||
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
|
||||
|
||||
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
|
||||
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* defined (USB) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32WBxx_HAL_PCD_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,558 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_pka.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PKA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_PKA_H
|
||||
#define STM32WBxx_HAL_PKA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
|
||||
|
||||
/** @addtogroup PKA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup PKA_Exported_Types PKA Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_state_structure_definition HAL state structure definition
|
||||
* @brief HAL State structures definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PKA_STATE_RESET = 0x00U, /*!< PKA not yet initialized or disabled */
|
||||
HAL_PKA_STATE_READY = 0x01U, /*!< PKA initialized and ready for use */
|
||||
HAL_PKA_STATE_BUSY = 0x02U, /*!< PKA internal processing is ongoing */
|
||||
HAL_PKA_STATE_ERROR = 0x03U, /*!< PKA error state */
|
||||
}
|
||||
HAL_PKA_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
/** @defgroup HAL_callback_id HAL callback ID enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_PKA_OPERATION_COMPLETE_CB_ID = 0x00U, /*!< PKA End of operation callback ID */
|
||||
HAL_PKA_ERROR_CB_ID = 0x01U, /*!< PKA Error callback ID */
|
||||
HAL_PKA_MSPINIT_CB_ID = 0x02U, /*!< PKA Msp Init callback ID */
|
||||
HAL_PKA_MSPDEINIT_CB_ID = 0x03U /*!< PKA Msp DeInit callback ID */
|
||||
} HAL_PKA_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
||||
|
||||
/** @defgroup PKA_Error_Code_definition PKA Error Code definition
|
||||
* @brief PKA Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_PKA_ERROR_NONE (0x00000000U)
|
||||
#define HAL_PKA_ERROR_ADDRERR (0x00000001U)
|
||||
#define HAL_PKA_ERROR_RAMERR (0x00000002U)
|
||||
#define HAL_PKA_ERROR_TIMEOUT (0x00000004U)
|
||||
#define HAL_PKA_ERROR_OPERATION (0x00000008U)
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_PKA_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PKA_handle_Structure_definition PKA handle Structure definition
|
||||
* @brief PKA handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __PKA_HandleTypeDef
|
||||
{
|
||||
PKA_TypeDef *Instance; /*!< Register base address */
|
||||
__IO HAL_PKA_StateTypeDef State; /*!< PKA state */
|
||||
__IO uint32_t ErrorCode; /*!< PKA Error code */
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */
|
||||
void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Error callback */
|
||||
void (* MspInitCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA Msp DeInit callback */
|
||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
||||
} PKA_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
/** @defgroup PKA_Callback_definition PKA Callback pointer definition
|
||||
* @brief PKA Callback pointer definition
|
||||
* @{
|
||||
*/
|
||||
typedef void (*pPKA_CallbackTypeDef)(PKA_HandleTypeDef *hpka); /*!< Pointer to a PKA callback function */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
||||
/** @defgroup PKA_Operation PKA operation structure definition
|
||||
* @brief Input and output data definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t scalarMulSize; /*!< Number of element in scalarMul array */
|
||||
uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */
|
||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
||||
const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
||||
const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
||||
const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
||||
const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */
|
||||
const uint32_t *pMontgomeryParam; /*!< Pointer to Montgomery parameter (Array of modulusSize/4 elements) */
|
||||
} PKA_ECCMulFastModeInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t scalarMulSize; /*!< Number of element in scalarMul array */
|
||||
uint32_t modulusSize; /*!< Number of element in modulus, coefA, pointX and pointY arrays */
|
||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
||||
const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
||||
const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
||||
const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
||||
const uint8_t *scalarMul; /*!< Pointer to scalar multiplier k (Array of scalarMulSize elements) */
|
||||
} PKA_ECCMulInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t modulusSize; /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */
|
||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
||||
const uint8_t *coefA; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
||||
const uint8_t *coefB; /*!< Pointer to curve coefficient b (Array of modulusSize elements) */
|
||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
||||
const uint8_t *pointX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
||||
const uint8_t *pointY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
||||
} PKA_PointCheckInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t size; /*!< Number of element in popA array */
|
||||
const uint8_t *pOpDp; /*!< Pointer to operand dP (Array of size/2 elements) */
|
||||
const uint8_t *pOpDq; /*!< Pointer to operand dQ (Array of size/2 elements) */
|
||||
const uint8_t *pOpQinv; /*!< Pointer to operand qinv (Array of size/2 elements) */
|
||||
const uint8_t *pPrimeP; /*!< Pointer to prime p (Array of size/2 elements) */
|
||||
const uint8_t *pPrimeQ; /*!< Pointer to prime Q (Array of size/2 elements) */
|
||||
const uint8_t *popA; /*!< Pointer to operand A (Array of size elements) */
|
||||
} PKA_RSACRTExpInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t primeOrderSize; /*!< Number of element in primeOrder array */
|
||||
uint32_t modulusSize; /*!< Number of element in modulus array */
|
||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
||||
const uint8_t *coef; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
||||
const uint8_t *basePointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */
|
||||
const uint8_t *basePointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */
|
||||
const uint8_t *pPubKeyCurvePtX; /*!< Pointer to public-key curve point xQ (Array of modulusSize elements) */
|
||||
const uint8_t *pPubKeyCurvePtY; /*!< Pointer to public-key curve point yQ (Array of modulusSize elements) */
|
||||
const uint8_t *RSign; /*!< Pointer to signature part r (Array of primeOrderSize elements) */
|
||||
const uint8_t *SSign; /*!< Pointer to signature part s (Array of primeOrderSize elements) */
|
||||
const uint8_t *hash; /*!< Pointer to hash of the message e (Array of primeOrderSize elements) */
|
||||
const uint8_t *primeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */
|
||||
} PKA_ECDSAVerifInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t primeOrderSize; /*!< Number of element in primeOrder array */
|
||||
uint32_t modulusSize; /*!< Number of element in modulus array */
|
||||
uint32_t coefSign; /*!< Curve coefficient a sign */
|
||||
const uint8_t *coef; /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
|
||||
const uint8_t *modulus; /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
|
||||
const uint8_t *integer; /*!< Pointer to random integer k (Array of primeOrderSize elements) */
|
||||
const uint8_t *basePointX; /*!< Pointer to curve base point xG (Array of modulusSize elements) */
|
||||
const uint8_t *basePointY; /*!< Pointer to curve base point yG (Array of modulusSize elements) */
|
||||
const uint8_t *hash; /*!< Pointer to hash of the message (Array of primeOrderSize elements) */
|
||||
const uint8_t *privateKey; /*!< Pointer to private key d (Array of primeOrderSize elements) */
|
||||
const uint8_t *primeOrder; /*!< Pointer to order of the curve n (Array of primeOrderSize elements) */
|
||||
} PKA_ECDSASignInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t *RSign; /*!< Pointer to signature part r (Array of modulusSize elements) */
|
||||
uint8_t *SSign; /*!< Pointer to signature part s (Array of modulusSize elements) */
|
||||
} PKA_ECDSASignOutTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t *ptX; /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
|
||||
uint8_t *ptY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
|
||||
} PKA_ECDSASignOutExtParamTypeDef, PKA_ECCMulOutTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t expSize; /*!< Number of element in pExp array */
|
||||
uint32_t OpSize; /*!< Number of element in pOp1 and pMod arrays */
|
||||
const uint8_t *pExp; /*!< Pointer to Exponent (Array of expSize elements) */
|
||||
const uint8_t *pOp1; /*!< Pointer to Operand (Array of OpSize elements) */
|
||||
const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */
|
||||
} PKA_ModExpInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t expSize; /*!< Number of element in pExp and pMontgomeryParam arrays */
|
||||
uint32_t OpSize; /*!< Number of element in pOp1 and pMod arrays */
|
||||
const uint8_t *pExp; /*!< Pointer to Exponent (Array of expSize elements) */
|
||||
const uint8_t *pOp1; /*!< Pointer to Operand (Array of OpSize elements) */
|
||||
const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */
|
||||
const uint32_t *pMontgomeryParam; /*!< Pointer to Montgomery parameter (Array of expSize/4 elements) */
|
||||
} PKA_ModExpFastModeInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t size; /*!< Number of element in pOp1 array */
|
||||
const uint8_t *pOp1; /*!< Pointer to Operand (Array of size elements) */
|
||||
} PKA_MontgomeryParamInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t size; /*!< Number of element in pOp1 and pOp2 arrays */
|
||||
const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */
|
||||
const uint32_t *pOp2; /*!< Pointer to Operand 2 (Array of size elements) */
|
||||
} PKA_AddInTypeDef, PKA_SubInTypeDef, PKA_MulInTypeDef, PKA_CmpInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t size; /*!< Number of element in pOp1 array */
|
||||
const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */
|
||||
const uint8_t *pMod; /*!< Pointer to modulus value n (Array of size*4 elements) */
|
||||
} PKA_ModInvInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t OpSize; /*!< Number of element in pOp1 array */
|
||||
uint32_t modSize; /*!< Number of element in pMod array */
|
||||
const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of OpSize elements) */
|
||||
const uint8_t *pMod; /*!< Pointer to modulus value n (Array of modSize elements) */
|
||||
} PKA_ModRedInTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t size; /*!< Number of element in pOp1 and pOp2 arrays */
|
||||
const uint32_t *pOp1; /*!< Pointer to Operand 1 (Array of size elements) */
|
||||
const uint32_t *pOp2; /*!< Pointer to Operand 2 (Array of size elements) */
|
||||
const uint8_t *pOp3; /*!< Pointer to Operand 3 (Array of size*4 elements) */
|
||||
} PKA_ModAddInTypeDef, PKA_ModSubInTypeDef, PKA_MontgomeryMulInTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PKA_Exported_Constants PKA Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PKA_Mode PKA mode
|
||||
* @{
|
||||
*/
|
||||
#define PKA_MODE_MONTGOMERY_PARAM (0x00000001U)
|
||||
#define PKA_MODE_MODULAR_EXP (0x00000000U)
|
||||
#define PKA_MODE_MODULAR_EXP_FAST_MODE (0x00000002U)
|
||||
#define PKA_MODE_ECC_MUL (0x00000020U)
|
||||
#define PKA_MODE_ECC_MUL_FAST_MODE (0x00000022U)
|
||||
#define PKA_MODE_ECDSA_SIGNATURE (0x00000024U)
|
||||
#define PKA_MODE_ECDSA_VERIFICATION (0x00000026U)
|
||||
#define PKA_MODE_POINT_CHECK (0x00000028U)
|
||||
#define PKA_MODE_RSA_CRT_EXP (0x00000007U)
|
||||
#define PKA_MODE_MODULAR_INV (0x00000008U)
|
||||
#define PKA_MODE_ARITHMETIC_ADD (0x00000009U)
|
||||
#define PKA_MODE_ARITHMETIC_SUB (0x0000000AU)
|
||||
#define PKA_MODE_ARITHMETIC_MUL (0x0000000BU)
|
||||
#define PKA_MODE_COMPARISON (0x0000000CU)
|
||||
#define PKA_MODE_MODULAR_RED (0x0000000DU)
|
||||
#define PKA_MODE_MODULAR_ADD (0x0000000EU)
|
||||
#define PKA_MODE_MODULAR_SUB (0x0000000FU)
|
||||
#define PKA_MODE_MONTGOMERY_MUL (0x00000010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PKA_Interrupt_configuration_definition PKA Interrupt configuration definition
|
||||
* @brief PKA Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define PKA_IT_PROCEND PKA_CR_PROCENDIE
|
||||
#define PKA_IT_ADDRERR PKA_CR_ADDRERRIE
|
||||
#define PKA_IT_RAMERR PKA_CR_RAMERRIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PKA_Flag_definition PKA Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define PKA_FLAG_PROCEND PKA_SR_PROCENDF
|
||||
#define PKA_FLAG_ADDRERR PKA_SR_ADDRERRF
|
||||
#define PKA_FLAG_RAMERR PKA_SR_RAMERRF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PKA_Exported_Macros PKA Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset PKA handle state.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_PKA_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PKA_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/** @brief Enable the specified PKA interrupt.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
|
||||
* @arg @ref PKA_IT_ADDRERR Address error interrupt enable
|
||||
* @arg @ref PKA_IT_RAMERR RAM error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PKA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified PKA interrupt.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @param __INTERRUPT__ specifies the interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
|
||||
* @arg @ref PKA_IT_ADDRERR Address error interrupt enable
|
||||
* @arg @ref PKA_IT_RAMERR RAM error interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PKA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified PKA interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @param __INTERRUPT__ specifies the PKA interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
|
||||
* @arg @ref PKA_IT_ADDRERR Address error interrupt enable
|
||||
* @arg @ref PKA_IT_RAMERR RAM error interrupt enable
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET)
|
||||
*/
|
||||
#define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified PKA flag is set or not.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PKA_FLAG_PROCEND End Of Operation
|
||||
* @arg @ref PKA_FLAG_ADDRERR Address error
|
||||
* @arg @ref PKA_FLAG_RAMERR RAM error
|
||||
* @retval The new state of __FLAG__ (SET or RESET)
|
||||
*/
|
||||
#define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
|
||||
|
||||
/** @brief Clear the PKA pending flags which are cleared by writing 1 in a specific bit.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref PKA_FLAG_PROCEND End Of Operation
|
||||
* @arg @ref PKA_FLAG_ADDRERR Address error
|
||||
* @arg @ref PKA_FLAG_RAMERR RAM error
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PKA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
|
||||
|
||||
/** @brief Enable the specified PKA peripheral.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PKA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
|
||||
|
||||
/** @brief Disable the specified PKA peripheral.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PKA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
|
||||
|
||||
/** @brief Start a PKA operation.
|
||||
* @param __HANDLE__ specifies the PKA Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PKA_START(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, PKA_CR_START))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PKA_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PKA_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions *****************************/
|
||||
HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka);
|
||||
HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka);
|
||||
void HAL_PKA_MspInit(PKA_HandleTypeDef *hpka);
|
||||
void HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka);
|
||||
|
||||
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PKA_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
/* High Level Functions *******************************************************/
|
||||
HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in);
|
||||
void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
|
||||
void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
|
||||
uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in);
|
||||
void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in);
|
||||
uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMulFastMode(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ECCMulFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in);
|
||||
void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in);
|
||||
HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in);
|
||||
void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in);
|
||||
void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
|
||||
|
||||
HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka);
|
||||
void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka);
|
||||
void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka);
|
||||
void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka);
|
||||
void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup PKA_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State and Error functions ***************************************/
|
||||
HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka);
|
||||
uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_PKA_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,711 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @brief PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @addtogroup PWR_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Register_Reset_Values PWR Register Reset Values
|
||||
* @{
|
||||
*/
|
||||
/* Definitions of PWR registers reset value */
|
||||
#define PWR_CR1_RESET_VALUE (0x00000200U)
|
||||
#define PWR_CR2_RESET_VALUE (0x00000000U)
|
||||
#define PWR_CR3_RESET_VALUE (0x00008000U)
|
||||
#define PWR_CR4_RESET_VALUE (0x00000000U)
|
||||
#define PWR_CR5_RESET_VALUE (0x00004204U)
|
||||
#define PWR_PUCRA_RESET_VALUE (0x00000000U)
|
||||
#define PWR_PDCRA_RESET_VALUE (0x00000000U)
|
||||
#define PWR_PUCRB_RESET_VALUE (0x00000000U)
|
||||
#define PWR_PDCRB_RESET_VALUE (0x00000000U)
|
||||
#define PWR_PUCRC_RESET_VALUE (0x00000000U)
|
||||
#define PWR_PDCRC_RESET_VALUE (0x00000000U)
|
||||
#define PWR_PUCRD_RESET_VALUE (0x00000000U)
|
||||
#define PWR_PDCRD_RESET_VALUE (0x00000000U)
|
||||
#define PWR_PUCRE_RESET_VALUE (0x00000000U)
|
||||
#define PWR_PDCRE_RESET_VALUE (0x00000000U)
|
||||
#define PWR_PUCRH_RESET_VALUE (0x00000000U)
|
||||
#define PWR_PDCRH_RESET_VALUE (0x00000000U)
|
||||
#define PWR_C2CR1_RESET_VALUE (0x00000000U)
|
||||
#define PWR_C2CR3_RESET_VALUE (0x00008000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DeInit(void)
|
||||
{
|
||||
/* Apply reset values to all PWR registers */
|
||||
/* Note: Update of each register required since PWR global reset is not */
|
||||
/* available at RCC level on this STM32 serie. */
|
||||
LL_PWR_WriteReg(CR1, PWR_CR1_RESET_VALUE);
|
||||
LL_PWR_WriteReg(CR2, PWR_CR2_RESET_VALUE);
|
||||
LL_PWR_WriteReg(CR3, PWR_CR3_RESET_VALUE);
|
||||
LL_PWR_WriteReg(CR4, PWR_CR4_RESET_VALUE);
|
||||
LL_PWR_WriteReg(CR5, PWR_CR5_RESET_VALUE);
|
||||
LL_PWR_WriteReg(PUCRA, PWR_PUCRA_RESET_VALUE);
|
||||
LL_PWR_WriteReg(PDCRA, PWR_PDCRA_RESET_VALUE);
|
||||
LL_PWR_WriteReg(PUCRB, PWR_PUCRB_RESET_VALUE);
|
||||
LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE);
|
||||
LL_PWR_WriteReg(PUCRC, PWR_PUCRC_RESET_VALUE);
|
||||
LL_PWR_WriteReg(PDCRC, PWR_PDCRC_RESET_VALUE);
|
||||
LL_PWR_WriteReg(PUCRD, PWR_PUCRD_RESET_VALUE);
|
||||
LL_PWR_WriteReg(PDCRD, PWR_PDCRD_RESET_VALUE);
|
||||
LL_PWR_WriteReg(PUCRE, PWR_PUCRE_RESET_VALUE);
|
||||
LL_PWR_WriteReg(PDCRE, PWR_PDCRE_RESET_VALUE);
|
||||
LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE);
|
||||
LL_PWR_WriteReg(PDCRH, PWR_PDCRH_RESET_VALUE);
|
||||
LL_PWR_WriteReg(C2CR1, PWR_C2CR1_RESET_VALUE);
|
||||
LL_PWR_WriteReg(C2CR3, PWR_C2CR3_RESET_VALUE);
|
||||
|
||||
/* Clear all flags */
|
||||
LL_PWR_WriteReg(SCR,
|
||||
LL_PWR_SCR_CC2HF
|
||||
| LL_PWR_SCR_C802AF
|
||||
| LL_PWR_SCR_CBLEAF
|
||||
| LL_PWR_SCR_CCRPEF
|
||||
| LL_PWR_SCR_C802WUF
|
||||
| LL_PWR_SCR_CBLEWUF
|
||||
| LL_PWR_SCR_CBORHF
|
||||
| LL_PWR_SCR_CSMPSFBF
|
||||
| LL_PWR_SCR_CWUF
|
||||
);
|
||||
|
||||
LL_PWR_WriteReg(EXTSCR,
|
||||
LL_PWR_EXTSCR_CCRPF
|
||||
| LL_PWR_EXTSCR_C2CSSF
|
||||
| LL_PWR_EXTSCR_C1CSSF
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable access to the backup domain
|
||||
* (RTC registers, RTC backup data registers).
|
||||
* @note After reset, the backup domain is protected against
|
||||
* possible unwanted write accesses.
|
||||
* @note RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
|
||||
* In order to set or modify the RTC clock, the backup domain access must be
|
||||
* disabled.
|
||||
* @note LSEON bit that switches on and off the LSE crystal belongs as well to the
|
||||
* back-up domain.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable access to the backup domain
|
||||
* (RTC registers, RTC backup data registers).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
|
||||
[..]
|
||||
*** PVD configuration ***
|
||||
=========================
|
||||
[..]
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a
|
||||
threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
|
||||
(+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
|
||||
than the PVD threshold. This event is internally connected to the EXTI
|
||||
line16 and can generate an interrupt if enabled. This is done through
|
||||
__HAL_PVD_EXTI_ENABLE_IT() macro.
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
|
||||
*** WakeUp pin configuration ***
|
||||
================================
|
||||
[..]
|
||||
(+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode.
|
||||
The polarity of these pins can be set to configure event detection on high
|
||||
level (rising edge) or low level (falling edge).
|
||||
|
||||
*** Low Power modes configuration ***
|
||||
=====================================
|
||||
[..]
|
||||
The devices feature 8 low-power modes:
|
||||
|
||||
(+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
|
||||
|
||||
(+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
|
||||
(+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
|
||||
|
||||
(+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
|
||||
(+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
|
||||
(+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
|
||||
|
||||
(+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on.
|
||||
(+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
|
||||
|
||||
(+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
|
||||
|
||||
|
||||
*** Low-power run mode ***
|
||||
==========================
|
||||
[..]
|
||||
(+) Entry: (from main run mode)
|
||||
(++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz.
|
||||
(+) Exit:
|
||||
(++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
|
||||
then can the system clock frequency be increased above 2 MHz.
|
||||
|
||||
*** Sleep mode / Low-power sleep mode ***
|
||||
=========================================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
|
||||
in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
|
||||
(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
|
||||
(++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
|
||||
In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
|
||||
(+) WFI Exit:
|
||||
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) or any wake-up event.
|
||||
|
||||
(+) WFE Exit:
|
||||
(++) Any wake-up event such as an EXTI line configured in event mode.
|
||||
|
||||
[..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event,
|
||||
the MCU is in Low-power Run mode.
|
||||
|
||||
*** Stop 0, Stop 1 and Stop 2 modes ***
|
||||
===============================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
|
||||
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0, HAL_PWREx_EnterSTOP1Mode() for mode 1, HAL_PWREx_EnterSTOP2Mode() for mode 2
|
||||
or for porting reasons HAL_PWR_EnterSTOPMode().
|
||||
|
||||
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
|
||||
(++) PWR_MAINREGULATOR_ON: Regulator in main mode (STOP0 mode)
|
||||
(++) PWR_LOWPOWERREGULATOR_ON: Regulator in low-power mode (STOP1 mode)
|
||||
(+) Exit (interrupt or event-triggered, specified when entering STOP mode):
|
||||
(++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
|
||||
(++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
|
||||
(+) WFI Exit:
|
||||
(++) Any EXTI Line (Internal or External) configured in Interrupt mode.
|
||||
(++) Some specific communication peripherals (USART, LPUART, I2C) interrupts
|
||||
when programmed in wakeup mode.
|
||||
(+) WFE Exit:
|
||||
(++) Any EXTI Line (Internal or External) configured in Event mode.
|
||||
|
||||
[..]
|
||||
When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
|
||||
depending on the LPR bit setting.
|
||||
When exiting Stop 2 mode, the MCU is in Run mode.
|
||||
|
||||
*** Standby mode ***
|
||||
====================
|
||||
[..] The Standby mode offers two options:
|
||||
(+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
|
||||
SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers
|
||||
and Standby circuitry.
|
||||
(+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
|
||||
SRAM and register contents are lost except for the RTC registers, RTC backup registers
|
||||
and Standby circuitry.
|
||||
|
||||
(++) Entry:
|
||||
(+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
|
||||
SRAM1 and register contents are lost except for registers in the Backup domain and
|
||||
Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
|
||||
To enable this feature, the user can resort to HAL_PWREx_EnableBKRAMContentRetention() API
|
||||
to set RRS bit.
|
||||
(++) Exit:
|
||||
(+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
|
||||
external reset in NRST pin, IWDG reset.
|
||||
[..] After waking up from Standby mode, program execution restarts in the same way as after a Reset.
|
||||
|
||||
|
||||
*** Shutdown mode ***
|
||||
======================
|
||||
[..]
|
||||
In Shutdown mode,
|
||||
voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
|
||||
SRAM and registers contents are lost except for backup domain registers.
|
||||
(+) Entry:
|
||||
The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
|
||||
(+) Exit:
|
||||
(++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
|
||||
external reset in NRST pin.
|
||||
[..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
|
||||
|
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..]
|
||||
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||||
Wakeup event, a tamper event or a time-stamp event, without depending on
|
||||
an external interrupt (Auto-wakeup mode).
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
|
||||
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
|
||||
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to configure the RTC to detect the tamper or time stamp event using the
|
||||
HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
|
||||
|
||||
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
|
||||
configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
|
||||
* @param sConfigPVD pointer to a PWR_PVDTypeDef structure that contains the PVD
|
||||
* configuration information.
|
||||
* @note Refer to the electrical characteristics of your device datasheet for
|
||||
* more details about the voltage thresholds corresponding to each
|
||||
* detection level.
|
||||
* @note If "sConfigPVD->Mode" is set to PVD_MODE_IT,
|
||||
* wake-up target is set by default to wake-up target CPU1.
|
||||
* To select wake-up target to CPU2, additional configuration must be
|
||||
* performed using macro "__HAL_PWR_PVD_EXTIC2_ENABLE_IT()"
|
||||
* (and optionally, to select CPU2 only (not both CPU1 and CPU2):
|
||||
* "__HAL_PWR_PVD_EXTI_DISABLE_IT()").
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
|
||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
|
||||
|
||||
/* Set PLS bits according to PVDLevel value */
|
||||
MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
|
||||
|
||||
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
||||
|
||||
/* Note: On STM32WB serie, power PVD event is not available on AIEC lines */
|
||||
/* (only interruption is available through AIEC line 16). */
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_IT(); /*CPU1*/
|
||||
__HAL_PWR_PVD_EXTIC2_DISABLE_IT(); /*CPU2*/
|
||||
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
|
||||
|
||||
/* Configure interrupt mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
|
||||
{
|
||||
/* Set CPU1 as wakeup target */
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT();
|
||||
}
|
||||
|
||||
/* Configure the edge */
|
||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
|
||||
}
|
||||
|
||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnablePVD(void)
|
||||
{
|
||||
/* Enable the power voltage detector */
|
||||
SET_BIT(PWR->CR2, PWR_CR2_PVDE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisablePVD(void)
|
||||
{
|
||||
/* Disable the power voltage detector */
|
||||
CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the WakeUp PINx functionality.
|
||||
* @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
|
||||
* This parameter can be one of the following legacy values which set the default polarity
|
||||
* i.e. detection on high level (rising edge):
|
||||
* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
|
||||
*
|
||||
* or one of the following value where the user can explicitly specify the enabled pin and
|
||||
* the chosen polarity:
|
||||
* @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
|
||||
* @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
|
||||
* @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
|
||||
* @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
|
||||
* @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
|
||||
* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
|
||||
{
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
|
||||
|
||||
/* Specifies the Wake-Up pin polarity for the event detection
|
||||
(rising or falling edge) */
|
||||
MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
|
||||
|
||||
/* Enable wake-up pin */
|
||||
SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1: An event on PA0 PIN wakes-up the system from Standby mode.
|
||||
* @arg PWR_WAKEUP_PIN2: An event on PC13 PIN wakes-up the system from Standby mode.
|
||||
* @arg PWR_WAKEUP_PIN3: An event on PC12 PIN wakes-up the system from Standby mode.
|
||||
* @arg PWR_WAKEUP_PIN4: An event on PA2 PIN wakes-up the system from Standby mode.
|
||||
* @arg PWR_WAKEUP_PIN5: An event on PC5 PIN wakes-up the system from Standby mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
|
||||
CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enter Sleep or Low-power Sleep mode.
|
||||
* @note In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
|
||||
* @param Regulator Specifies the regulator state in Sleep/Low-power Sleep mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
|
||||
* @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode)
|
||||
* @note Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet
|
||||
* in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set
|
||||
* to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
|
||||
* Flash in power-down mode in setting the SLEEP_PD bit in FLASH_ACR register.
|
||||
* Additionally, the clock frequency must be reduced below 2 MHz.
|
||||
* Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must
|
||||
* be done before calling HAL_PWR_EnterSLEEPMode() API.
|
||||
* @note When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in
|
||||
* Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.
|
||||
* @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
|
||||
* @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
|
||||
* @note When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||||
* the interrupt wake up source.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||||
|
||||
/* Set Regulator parameter */
|
||||
if (Regulator == PWR_MAINREGULATOR_ON)
|
||||
{
|
||||
/* If in low-power run mode at this point, exit it */
|
||||
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
|
||||
{
|
||||
if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK)
|
||||
{
|
||||
return ;
|
||||
}
|
||||
}
|
||||
/* Regulator now in main mode. */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If in run mode, first move to low-power run mode.
|
||||
The system clock frequency must be below 2 MHz at this point. */
|
||||
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
|
||||
{
|
||||
HAL_PWREx_EnableLowPowerRunMode();
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enter Stop mode
|
||||
* @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
|
||||
* on devices where only "Stop mode" is mentioned with main or low power regulator ON.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
|
||||
* the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
|
||||
* (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
|
||||
* after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
|
||||
* only to the peripheral requesting it.
|
||||
* SRAM1, SRAM2 and register contents are preserved.
|
||||
* The BOR is available.
|
||||
* The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).
|
||||
* @note When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
|
||||
* the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
|
||||
* is set; the MSI oscillator is selected if STOPWUCK is cleared.
|
||||
* @note When the voltage regulator operates in low power mode (Stop 1), an additional
|
||||
* startup delay is incurred when waking up.
|
||||
* By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @note According to system power policy, system entering in Stop mode
|
||||
* is depending on other CPU power mode.
|
||||
* @param Regulator Specifies the regulator state in Stop mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
|
||||
* @arg @ref PWR_LOWPOWERREGULATOR_ON Stop 1 mode (low power regulator ON)
|
||||
* @param STOPEntry Specifies Stop 0, Stop 1 or Stop 2 mode is entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction.
|
||||
* @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
|
||||
if(Regulator == PWR_LOWPOWERREGULATOR_ON)
|
||||
{
|
||||
HAL_PWREx_EnterSTOP1Mode(STOPEntry);
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_PWREx_EnterSTOP0Mode(STOPEntry);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enter Standby mode.
|
||||
* @note In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched
|
||||
* off. The voltage regulator is disabled, except when BKRAM content is preserved
|
||||
* in which case the regulator is in low-power mode.
|
||||
* SRAM and register contents are lost except for registers in the Backup domain and
|
||||
* Standby circuitry. BKRAM content can be preserved if the bit RRS is set in PWR_CR3 register.
|
||||
* To enable this feature, the user can resort to HAL_PWREx_EnableBKRAMContentRetention() API
|
||||
* to set RRS bit.
|
||||
* The BOR is available.
|
||||
* @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
|
||||
* HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
|
||||
* Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
|
||||
* same.
|
||||
* These states are effective in Standby mode only if APC bit is set through
|
||||
* HAL_PWREx_EnablePullUpPullDownConfig() API.
|
||||
* @note According to system power policy, system entering in Standby mode
|
||||
* is depending on other CPU power mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Set Stand-by mode */
|
||||
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY);
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
|
||||
/* Following code is executed after wake up if system did not go to STANDBY
|
||||
mode according to system power policy */
|
||||
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* Setting this bit is useful when the processor is expected to run only on
|
||||
* interruptions handling.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||||
* @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable CORTEX M4 SEVONPEND bit.
|
||||
* @note Set SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSEVOnPend(void)
|
||||
{
|
||||
/* Set SEVONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable CORTEX M4 SEVONPEND bit.
|
||||
* @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSEVOnPend(void)
|
||||
{
|
||||
/* Clear SEVONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief PWR PVD interrupt callback
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWR_PVDCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified; when the callback is needed,
|
||||
the HAL_PWR_PVDCallback can be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,498 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_PWR_H
|
||||
#define STM32WBxx_HAL_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/* Include low level driver */
|
||||
#include "stm32wbxx_ll_pwr.h"
|
||||
#include "stm32wbxx_ll_exti.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR PWR
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Types PWR Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PWR PVD configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
|
||||
This parameter can be a value of @ref PWR_PVD_detection_level. */
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWR_PVD_Mode. */
|
||||
}PWR_PVDTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Constants PWR Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level Power Voltage Detector Level selection
|
||||
* @note Refer datasheet for selection voltage value
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVDLEVEL_0 (0x00000000U) /*!< PVD threshold around 2.0 V */
|
||||
#define PWR_PVDLEVEL_1 ( PWR_CR2_PLS_0) /*!< PVD threshold around 2.2 V */
|
||||
#define PWR_PVDLEVEL_2 ( PWR_CR2_PLS_1 ) /*!< PVD threshold around 2.4 V */
|
||||
#define PWR_PVDLEVEL_3 ( PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /*!< PVD threshold around 2.5 V */
|
||||
#define PWR_PVDLEVEL_4 (PWR_CR2_PLS_2 ) /*!< PVD threshold around 2.6 V */
|
||||
#define PWR_PVDLEVEL_5 (PWR_CR2_PLS_2 | PWR_CR2_PLS_0) /*!< PVD threshold around 2.8 V */
|
||||
#define PWR_PVDLEVEL_6 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 ) /*!< PVD threshold around 2.9 V */
|
||||
#define PWR_PVDLEVEL_7 (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0) /*!< External input analog voltage (compared internally to VREFINT) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode
|
||||
* @{
|
||||
*/
|
||||
/* Note: On STM32WB serie, power PVD event is not available on AIEC lines */
|
||||
/* (only interruption is available through AIEC line 16). */
|
||||
#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */
|
||||
|
||||
#define PWR_PVD_MODE_IT_RISING (PVD_MODE_IT | PVD_RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_FALLING (PVD_MODE_IT | PVD_FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_RISING_FALLING (PVD_MODE_IT | PVD_RISING_FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Note: On STM32WB serie, power PVD event is not available on AIEC lines */
|
||||
/* (only interruption is available through AIEC line 16). */
|
||||
|
||||
/** @defgroup PWR_Low_Power_Mode_Selection PWR Low Power Mode Selection
|
||||
* @{
|
||||
*/
|
||||
#define PWR_LOWPOWERMODE_STOP0 (0x00000000u) /*!< Stop 0: stop mode with main regulator */
|
||||
#define PWR_LOWPOWERMODE_STOP1 (PWR_CR1_LPMS_0) /*!< Stop 1: stop mode with low power regulator */
|
||||
#define PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1) /*!< Stop 2: stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/
|
||||
#define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */
|
||||
#define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2) /*!< Shutdown mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_ON (0x00000000U) /*!< Regulator in main mode */
|
||||
#define PWR_LOWPOWERREGULATOR_ON (PWR_CR1_LPR) /*!< Regulator in low-power mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */
|
||||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
|
||||
* @{
|
||||
*/
|
||||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */
|
||||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Defines PWR Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line
|
||||
* @{
|
||||
*/
|
||||
#define PWR_EXTI_LINE_PVD (LL_EXTI_LINE_16) /*!< External interrupt line 16 Connected to the PWR PVD */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
|
||||
* @{
|
||||
*/
|
||||
/* Note: On STM32WB serie, power PVD event is not available on AIEC lines */
|
||||
/* (only interruption is available through AIEC line 16). */
|
||||
#define PVD_MODE_IT (0x00010000U) /*!< Mask for interruption yielded by PVD threshold crossing */
|
||||
#define PVD_RISING_EDGE (0x00000001U) /*!< Mask for rising edge set as PVD trigger */
|
||||
#define PVD_FALLING_EDGE (0x00000002U) /*!< Mask for falling edge set as PVD trigger */
|
||||
#define PVD_RISING_FALLING_EDGE (0x00000003U) /*!< Mask for rising and falling edges set as PVD trigger */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Macros PWR Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Check whether or not a specific PWR flag is set.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
*
|
||||
* /--------------------------------SR1-------------------------------/
|
||||
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 1.
|
||||
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 2.
|
||||
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 3.
|
||||
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 4.
|
||||
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 5.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_BHWF BLE_Host WakeUp Flag
|
||||
* @arg @ref PWR_FLAG_FRCBYPI SMPS Forced in Bypass Interrupt Flag
|
||||
* @arg @ref PWR_FLAG_RFPHASEI Radio Phase Interrupt Flag
|
||||
* @arg @ref PWR_FLAG_BLEACTI BLE Activity Interrupt Flag
|
||||
* @arg @ref PWR_FLAG_802ACTI 802.15.4 Activity Interrupt Flag
|
||||
* @arg @ref PWR_FLAG_HOLDC2I CPU2 on-Hold Interrupt Flag
|
||||
* @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
|
||||
* the internal wakeup line.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_SMPSRDYF SMPS Ready Flag
|
||||
* @arg @ref PWR_FLAG_SMPSBYPF SMPS Bypass Flag
|
||||
*
|
||||
* /--------------------------------SR2-------------------------------/
|
||||
* @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
|
||||
* low-power regulator is ready.
|
||||
* @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
|
||||
* regulator is ready in main mode or is in low-power mode.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
|
||||
* in the selected voltage range or is still changing to the required voltage level.
|
||||
* @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
|
||||
* below or above the selected PVD threshold.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
|
||||
* is below or above PVM1 threshold (applicable when USB feature is supported).
|
||||
* @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
|
||||
* is below or above PVM3 threshold.
|
||||
*
|
||||
* /----------------------------EXTSCR--------------------------/
|
||||
* @arg @ref PWR_FLAG_STOP System Stop Flag for CPU1.
|
||||
* @arg @ref PWR_FLAG_SB System Standby Flag for CPU1.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_C2STOP System Stop Flag for CPU2.
|
||||
* @arg @ref PWR_FLAG_C2SB System Standby Flag for CPU2.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_CRITICAL_RF_PHASE Critical radio system phase flag.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_C1DEEPSLEEP CPU1 DeepSleep Flag.
|
||||
* @arg @ref PWR_FLAG_C2DEEPSLEEP CPU2 DeepSleep Flag.
|
||||
*
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1U) ?\
|
||||
(PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
|
||||
((((((uint8_t)(__FLAG__)) >> 5U) == 2U)) ?\
|
||||
(PWR->SR2 & (1U << ((__FLAG__) & 31U))) :\
|
||||
(PWR->EXTSCR & (1U << ((__FLAG__) & 31U))) ) )
|
||||
|
||||
|
||||
/** @brief Clear a specific PWR flag.
|
||||
* @note Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_SB}
|
||||
* and flags {PWR_FLAG_C2STOP, PWR_FLAG_C2SB} are grouped:
|
||||
* clearing of one flag also clears the other one.
|
||||
* @param __FLAG__ specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
*
|
||||
* /--------------------------------SCR (SRR)------------------------------/
|
||||
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 1.
|
||||
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 2.
|
||||
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 3.
|
||||
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 4.
|
||||
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
|
||||
* was received from the WKUP pin 5.
|
||||
* @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_BHWF Clear BLE_Host Wakeup Flag.
|
||||
* @arg @ref PWR_FLAG_FRCBYPI Clear SMPS Forced in Bypass Interrupt Flag.
|
||||
* @arg @ref PWR_FLAG_RFPHASEI RF Phase Interrupt Clear.
|
||||
* @arg @ref PWR_FLAG_BLEACTI BLE Activity Interrupt Clear.
|
||||
* @arg @ref PWR_FLAG_802ACTI 802.15.4. Activity Interrupt Clear.
|
||||
* @arg @ref PWR_FLAG_HOLDC2I CPU2 on-Hold Interrupt Clear.
|
||||
*
|
||||
* /----------------------------EXTSCR--------------------------/
|
||||
* @arg @ref PWR_FLAG_STOP System Stop Flag for CPU1.
|
||||
* @arg @ref PWR_FLAG_SB System Standby Flag for CPU1.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_C2STOP System Stop Flag for CPU2.
|
||||
* @arg @ref PWR_FLAG_C2SB System Standby Flag for CPU2.
|
||||
*
|
||||
* @arg @ref PWR_FLAG_CRITICAL_RF_PHASE RF phase Flag.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1U) ?\
|
||||
( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
|
||||
(PWR->SCR = (__FLAG__)) : (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) :\
|
||||
( (((uint8_t)(__FLAG__)) == PWR_FLAG_CRITICAL_RF_PHASE) ?\
|
||||
SET_BIT (PWR->EXTSCR, PWR_EXTSCR_CCRPF) : ( ((((uint8_t)((__FLAG__)) & 31U) <= PWR_EXTSCR_C1STOPF_Pos) ?\
|
||||
SET_BIT (PWR->EXTSCR, PWR_EXTSCR_C1CSSF): SET_BIT (PWR->EXTSCR, PWR_EXTSCR_C2CSSF)) ) ))
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/* Note: On STM32WB serie, power PVD event is not available on AIEC lines */
|
||||
/* (only interruption is available through AIEC line 16). */
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Rising Trigger.
|
||||
* @note PVD flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVD voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising Trigger.
|
||||
* @note PVD flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVD voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Falling Trigger.
|
||||
* @note PVD flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVD voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Falling Trigger.
|
||||
* @note PVD flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVD voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Check whether or not the PVD EXTI interrupt flag is set.
|
||||
* @retval EXTI PVD Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @brief Clear the PVD EXTI interrupt flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVD)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Macros PWR Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
|
||||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
|
||||
|
||||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING) ||\
|
||||
((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
|
||||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING))
|
||||
|
||||
|
||||
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
|
||||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
|
||||
|
||||
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || \
|
||||
((ENTRY) == PWR_SLEEPENTRY_WFE))
|
||||
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || \
|
||||
((ENTRY) == PWR_STOPENTRY_WFE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include PWR HAL Extended module */
|
||||
#include "stm32wbxx_hal_pwr_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization and de-initialization functions *******************************/
|
||||
void HAL_PWR_DeInit(void);
|
||||
|
||||
void HAL_PWR_EnableBkUpAccess(void);
|
||||
void HAL_PWR_DisableBkUpAccess(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
|
||||
void HAL_PWR_EnablePVD(void);
|
||||
void HAL_PWR_DisablePVD(void);
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
|
||||
void HAL_PWR_EnterSTANDBYMode(void);
|
||||
|
||||
void HAL_PWR_PVDCallback(void);
|
||||
void HAL_PWR_EnableSleepOnExit(void);
|
||||
void HAL_PWR_DisableSleepOnExit(void);
|
||||
|
||||
void HAL_PWR_EnableSEVOnPend(void);
|
||||
void HAL_PWR_DisableSEVOnPend(void);
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32WBxx_HAL_PWR_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,886 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of PWR HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_PWR_EX_H
|
||||
#define STM32WBxx_HAL_PWR_EX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx PWREx
|
||||
* @brief PWR Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief PWR PVM configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PVMType; /*!< PVMType: Specifies which voltage is monitored and against which threshold.
|
||||
This parameter can be a value of @ref PWREx_PVM_Type.
|
||||
@arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported).
|
||||
@arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
|
||||
*/
|
||||
|
||||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref PWREx_PVM_Mode. */
|
||||
uint32_t WakeupTarget; /*!< Specifies the Wakeup Target
|
||||
This parameter can be a value of @ref PWREx_WakeUpTarget_Definition */
|
||||
}PWR_PVMTypeDef;
|
||||
|
||||
/**
|
||||
* @brief PWR SMPS step down configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t StartupCurrent; /*!< SMPS step down converter supply startup current selection.
|
||||
This parameter can be a value of @ref PWREx_SMPS_STARTUP_CURRENT. */
|
||||
|
||||
uint32_t OutputVoltage; /*!< SMPS step down converter output voltage scaling voltage level.
|
||||
This parameter can be a value of @ref PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL */
|
||||
}PWR_SMPSTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WUP_POLARITY_SHIFT 0x05U /*!< Internal constant used to retrieve wakeup pin polarity */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWREx_WakeUp_Pins PWR wake-up pins
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
|
||||
|
||||
#define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
|
||||
#define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
|
||||
#define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
|
||||
#define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
|
||||
#define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Literals kept for legacy purpose */
|
||||
#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
|
||||
#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
|
||||
|
||||
/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PIN_POLARITY_HIGH 0x00000000U
|
||||
#define PWR_PIN_POLARITY_LOW 0x00000001U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
|
||||
#define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVM_Mode PWR PVM interrupt and event mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVM_MODE_NORMAL (0x00000000U) /*!< basic mode is used */
|
||||
|
||||
#define PWR_PVM_MODE_IT_RISING (PVM_MODE_IT | PVM_RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVM_MODE_IT_FALLING (PVM_MODE_IT | PVM_FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVM_MODE_IT_RISING_FALLING (PVM_MODE_IT | PVM_RISING_FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define PWR_PVM_MODE_EVENT_RISING (PVM_MODE_EVT | PVM_RISING_EDGE) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVM_MODE_EVENT_FALLING (PVM_MODE_EVT | PVM_FALLING_EDGE) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVM_MODE_EVENT_RISING_FALLING (PVM_MODE_EVT | PVM_RISING_FALLING_EDGE) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Flash_PowerDown Flash Power Down modes
|
||||
* @{
|
||||
*/
|
||||
#define PWR_FLASHPD_LPRUN PWR_CR1_FPDR /*!< Enable Flash power down in low power run mode */
|
||||
#define PWR_FLASHPD_LPSLEEP PWR_CR1_FPDS /*!< Enable Flash power down in low power sleep mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
|
||||
* @{
|
||||
*/
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */
|
||||
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
|
||||
* @{
|
||||
*/
|
||||
#define PWR_BATTERY_CHARGING_RESISTOR_5 (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */
|
||||
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR4_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
|
||||
* @{
|
||||
*/
|
||||
#define PWR_BATTERY_CHARGING_DISABLE (0x00000000U)
|
||||
#define PWR_BATTERY_CHARGING_ENABLE PWR_CR4_VBE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_GPIO_BIT_0 PWR_PUCRC_PC0 /*!< GPIO port I/O pin 0 */
|
||||
#define PWR_GPIO_BIT_1 PWR_PUCRC_PC1 /*!< GPIO port I/O pin 1 */
|
||||
#define PWR_GPIO_BIT_2 PWR_PUCRC_PC2 /*!< GPIO port I/O pin 2 */
|
||||
#define PWR_GPIO_BIT_3 PWR_PUCRC_PC3 /*!< GPIO port I/O pin 3 */
|
||||
#define PWR_GPIO_BIT_4 PWR_PUCRC_PC4 /*!< GPIO port I/O pin 4 */
|
||||
#define PWR_GPIO_BIT_5 PWR_PUCRC_PC5 /*!< GPIO port I/O pin 5 */
|
||||
#define PWR_GPIO_BIT_6 PWR_PUCRC_PC6 /*!< GPIO port I/O pin 6 */
|
||||
#define PWR_GPIO_BIT_7 PWR_PUCRC_PC7 /*!< GPIO port I/O pin 7 */
|
||||
#define PWR_GPIO_BIT_8 PWR_PUCRC_PC8 /*!< GPIO port I/O pin 8 */
|
||||
#define PWR_GPIO_BIT_9 PWR_PUCRC_PC9 /*!< GPIO port I/O pin 9 */
|
||||
#define PWR_GPIO_BIT_10 PWR_PUCRC_PC10 /*!< GPIO port I/O pin 10 */
|
||||
#define PWR_GPIO_BIT_11 PWR_PUCRC_PC11 /*!< GPIO port I/O pin 11 */
|
||||
#define PWR_GPIO_BIT_12 PWR_PUCRC_PC12 /*!< GPIO port I/O pin 12 */
|
||||
#define PWR_GPIO_BIT_13 PWR_PUCRC_PC13 /*!< GPIO port I/O pin 14 */
|
||||
#define PWR_GPIO_BIT_14 PWR_PDCRC_PC14 /*!< GPIO port I/O pin 14 */
|
||||
#define PWR_GPIO_BIT_15 PWR_PUCRC_PC15 /*!< GPIO port I/O pin 15 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_GPIO GPIO port
|
||||
* @{
|
||||
*/
|
||||
#define PWR_GPIO_A 0x00000000U /*!< GPIO port A */
|
||||
#define PWR_GPIO_B 0x00000001U /*!< GPIO port B */
|
||||
#define PWR_GPIO_C 0x00000002U /*!< GPIO port C */
|
||||
#define PWR_GPIO_D 0x00000003U /*!< GPIO port D */
|
||||
#define PWR_GPIO_E 0x00000004U /*!< GPIO port E */
|
||||
#define PWR_GPIO_H 0x00000007U /*!< GPIO port H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_BOR_CONFIGURATION BOR configuration
|
||||
* @{
|
||||
*/
|
||||
#define PWR_BOR_SYSTEM_RESET (LL_PWR_BOR_SYSTEM_RESET) /*!< BOR will generate a system reset */
|
||||
#define PWR_BOR_SMPS_FORCE_BYPASS (LL_PWR_BOR_SMPS_FORCE_BYPASS) /*!< BOR will for SMPS step down converter in bypass mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_SMPS_OPERATING_MODES SMPS step down converter operating modes
|
||||
* @{
|
||||
*/
|
||||
/* Note: Literals values are defined from register SR2 bits SMPSF and SMPSBF */
|
||||
/* but they are also used as register CR5 bits SMPSEN and SMPSBEN, */
|
||||
/* as used by all SMPS operating mode functions targetting different */
|
||||
/* registers: */
|
||||
/* "LL_PWR_SMPS_SetMode()", "LL_PWR_SMPS_GetMode()" */
|
||||
/* and "LL_PWR_SMPS_GetEffectiveMode()". */
|
||||
#define PWR_SMPS_BYPASS (PWR_SR2_SMPSBF) /*!< SMPS step down in bypass mode */
|
||||
#define PWR_SMPS_STEP_DOWN (PWR_SR2_SMPSF) /*!< SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_SMPS_STARTUP_CURRENT SMPS step down converter supply startup current selection
|
||||
* @{
|
||||
*/
|
||||
#define PWR_SMPS_STARTUP_CURRENT_80MA (0x00000000U) /*!< SMPS step down converter supply startup current 80mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_100MA ( PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 100mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_120MA ( PWR_CR5_SMPSSC_1 ) /*!< SMPS step down converter supply startup current 120mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_140MA ( PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 140mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_160MA (PWR_CR5_SMPSSC_2 ) /*!< SMPS step down converter supply startup current 160mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_180MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 180mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_200MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 ) /*!< SMPS step down converter supply startup current 200mA */
|
||||
#define PWR_SMPS_STARTUP_CURRENT_220MA (PWR_CR5_SMPSSC_2 | PWR_CR5_SMPSSC_1 | PWR_CR5_SMPSSC_0) /*!< SMPS step down converter supply startup current 220mA */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL SMPS step down converter output voltage scaling voltage level
|
||||
* @{
|
||||
*/
|
||||
/* Note: SMPS voltage is trimmed during device production to control
|
||||
the actual voltage level variation from device to device. */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V20 (0x00000000U) /*!< SMPS step down converter supply output voltage 1.20V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V25 ( PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.25V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V30 ( PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.30V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V35 ( PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.35V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V40 ( PWR_CR5_SMPSVOS_2 ) /*!< SMPS step down converter supply output voltage 1.40V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V45 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.45V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V50 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.50V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V55 ( PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.55V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V60 (PWR_CR5_SMPSVOS_3 ) /*!< SMPS step down converter supply output voltage 1.60V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V65 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.65V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V70 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.70V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V75 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_1 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.75V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V80 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 ) /*!< SMPS step down converter supply output voltage 1.80V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V85 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_0) /*!< SMPS step down converter supply output voltage 1.85V */
|
||||
#define PWR_SMPS_OUTPUT_VOLTAGE_1V90 (PWR_CR5_SMPSVOS_3 | PWR_CR5_SMPSVOS_2 | PWR_CR5_SMPSVOS_1 ) /*!< SMPS step down converter supply output voltage 1.90V */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Flag PWR Status Flags
|
||||
* Elements values convention: 0000 0000 0XXY YYYYb
|
||||
* - Y YYYY : Flag position in the XX register (5 bits)
|
||||
* - XX : Status register (2 bits)
|
||||
* - 01: SR1 register
|
||||
* - 10: SR2 register
|
||||
* - 11: C2_SCR register
|
||||
* The only exception is PWR_FLAG_WUF, encompassing all
|
||||
* wake-up flags and set to PWR_SR1_WUF.
|
||||
* @{
|
||||
*/
|
||||
/*--------------------------------SR1-------------------------------*/
|
||||
#define PWR_FLAG_WUF1 (0x0020U) /*!< Wakeup event on wakeup pin 1 */
|
||||
#define PWR_FLAG_WUF2 (0x0021U) /*!< Wakeup event on wakeup pin 2 */
|
||||
#define PWR_FLAG_WUF3 (0x0022U) /*!< Wakeup event on wakeup pin 3 */
|
||||
#define PWR_FLAG_WUF4 (0x0023U) /*!< Wakeup event on wakeup pin 4 */
|
||||
#define PWR_FLAG_WUF5 (0x0024U) /*!< Wakeup event on wakeup pin 5 */
|
||||
#define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
|
||||
|
||||
#define PWR_FLAG_BHWF (0x0028U) /*!< BLE_Host WakeUp Flag */
|
||||
#define PWR_FLAG_FRCBYPI (0x0029U) /*!< SMPS Forced in Bypass Interrupt Flag */
|
||||
|
||||
#define PWR_FLAG_RFPHASEI (0x002BU) /*!< Radio Phase Interrupt Flag */
|
||||
#define PWR_FLAG_BLEACTI (0x002CU) /*!< BLE Activity Interrupt Flag */
|
||||
#define PWR_FLAG_802ACTI (0x002DU) /*!< 802.15.4 Activity Interrupt Flag */
|
||||
#define PWR_FLAG_HOLDC2I (0x002EU) /*!< CPU2 on-Hold Interrupt Flag */
|
||||
#define PWR_FLAG_WUFI (0x002FU) /*!< Wakeup on internal wakeup line */
|
||||
|
||||
/*--------------------------------SR2-------------------------------*/
|
||||
#define PWR_FLAG_SMPSRDYF (0x0040U) /*!< SMPS Ready Flag */
|
||||
#define PWR_FLAG_SMPSBYPF (0x0041U) /*!< SMPS Bypass Flag */
|
||||
|
||||
#define PWR_FLAG_REGLPS (0x0048U) /*!< Low-power regulator start flag */
|
||||
#define PWR_FLAG_REGLPF (0x0049U) /*!< Low-power regulator flag */
|
||||
|
||||
#define PWR_FLAG_VOSF (0x004AU) /*!< Voltage scaling flag */
|
||||
#define PWR_FLAG_PVDO (0x004BU) /*!< Power Voltage Detector output flag */
|
||||
|
||||
#define PWR_FLAG_PVMO1 (0x004CU) /*!< Power Voltage Monitoring 1 output flag */
|
||||
#define PWR_FLAG_PVMO3 (0x004EU) /*!< Power Voltage Monitoring 3 output flag */
|
||||
|
||||
/*------------------------------EXTSCR---------------------------*/
|
||||
#define PWR_FLAG_SB (0x0068U) /*!< System Standby flag for CPU1 */
|
||||
#define PWR_FLAG_STOP (0x0069U) /*!< System Stop flag for CPU1 */
|
||||
|
||||
#define PWR_FLAG_C2SB (0x006AU) /*!< System Standby flag for CPU2 */
|
||||
#define PWR_FLAG_C2STOP (0x006BU) /*!< System Stop flag for CPU2 */
|
||||
|
||||
#define PWR_FLAG_CRITICAL_RF_PHASE (0x006DU) /*!< Critical radio system phase flag */
|
||||
#define PWR_FLAG_C1DEEPSLEEP (0x006EU) /*!< CPU1 DeepSleep Flag */
|
||||
#define PWR_FLAG_C2DEEPSLEEP (0x006FU) /*!< CPU2 DeepSleep Flag */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_WakeUpTarget_Definition PWR Wakeup Target Definition
|
||||
* @{
|
||||
*/
|
||||
#define PWR_WAKEUPTARGET_CPU1 (0x00000001U)
|
||||
#define PWR_WAKEUPTARGET_CPU2 (0x00000002U)
|
||||
#define PWR_WAKEUPTARGET_ALL_CPU (PWR_WAKEUPTARGET_CPU1 | PWR_WAKEUPTARGET_CPU2)
|
||||
#define PWR_WAKEUPTARGET_RF (0x00000004U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Core_Select PWREx Core definition
|
||||
* @{
|
||||
*/
|
||||
#define PWR_CORE_CPU1 (0x00000000U)
|
||||
#define PWR_CORE_CPU2 (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup PWR_Private_Defines PWR Private Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
|
||||
* @{
|
||||
*/
|
||||
#define PWR_EXTI_LINE_PVM1 (LL_EXTI_LINE_31) /*!< External interrupt line 31 Connected to PVM1 */
|
||||
#define PWR_EXTI_LINE_PVM3 (LL_EXTI_LINE_33) /*!< External interrupt line 33 Connected to PVM3 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
|
||||
* @{
|
||||
*/
|
||||
/* Note: On STM32WB serie, power PVD event is not available on AIEC lines */
|
||||
/* (only interruption is available through AIEC line 16). */
|
||||
#define PVM_MODE_IT (0x00010000U) /*!< Mask for interruption yielded by PVM threshold crossing */
|
||||
#define PVM_MODE_EVT (0x00020000U) /*!< Mask for event yielded by PVM threshold crossing */
|
||||
#define PVM_RISING_EDGE (0x00000001U) /*!< Mask for rising edge set as PVM trigger */
|
||||
#define PVM_FALLING_EDGE (0x00000002U) /*!< Mask for falling edge set as PVM trigger */
|
||||
#define PVM_RISING_FALLING_EDGE (0x00000003U) /*!< Mask for rising and falling edges set as PVM trigger */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Extended Interrupt C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Extended Interrupt C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Event C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Event C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTIC2_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Event C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Event C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTIC2_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Extended Interrupt Rising Trigger.
|
||||
* @note PVM1 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt Rising Trigger.
|
||||
* @note PVM1 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM1 Extended Interrupt Falling Trigger.
|
||||
* @note PVM1 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt Falling Trigger.
|
||||
* @note PVM1 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM1 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief PVM1 EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
|
||||
* @retval EXTI PVM1 Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_GET_FLAG() LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
/**
|
||||
* @brief Clear the PVM1 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVM1)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Extended Interrupt C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Extended Interrupt C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTIC2_ENABLE_IT() LL_C2_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTIC2_DISABLE_IT() LL_C2_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Event C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Event C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTIC2_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Event C1 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Event C2 Line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTIC2_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Extended Interrupt Rising Trigger.
|
||||
* @note PVM3 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt Rising Trigger.
|
||||
* @note PVM3 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Enable the PVM3 Extended Interrupt Falling Trigger.
|
||||
* @note PVM3 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt Falling Trigger.
|
||||
* @note PVM3 flag polarity is inverted compared to EXTI line, therefore
|
||||
* EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief PVM3 EXTI line configuration: set rising & falling edge trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE() \
|
||||
do { \
|
||||
__HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Generate a Software interrupt on selected EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
|
||||
* @retval EXTI PVM3 Line Status.
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_GET_FLAG() LL_EXTI_ReadFlag_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
/**
|
||||
* @brief Clear the PVM3 EXTI flag.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configure the main internal regulator output voltage.
|
||||
* @param __REGULATOR__ specifies the regulator output voltage to achieve
|
||||
* a tradeoff between performance and power consumption.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
|
||||
* typical output voltage at 1.2 V,
|
||||
* system frequency up to 64 MHz.
|
||||
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
|
||||
* typical output voltage at 1.0 V,
|
||||
* system frequency up to 16 MHz.
|
||||
* @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
|
||||
* whether or not VOSF flag is cleared when moving from range 2 to range 1. User
|
||||
* may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief Wakeup BLE controller from its sleep mode
|
||||
* @note This bit is automatically reset when 802.15.4 controller
|
||||
* exit its sleep mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_C2_PWR_WAKEUP_BLE() LL_C2_PWR_WakeUp_BLE()
|
||||
|
||||
/**
|
||||
* @brief Wakeup 802.15.4 controller from its sleep mode
|
||||
* @note This bit is automatically reset when 802.15.4 controller
|
||||
* exit its sleep mode.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_C2_PWR_WAKEUP_802_15_4() LL_C2_PWR_WakeUp_802_15_4()
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros --------------------------------------------------------*/
|
||||
/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
|
||||
((PIN) == PWR_WAKEUP_PIN1_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN2_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN3_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN4_LOW) || \
|
||||
((PIN) == PWR_WAKEUP_PIN5_LOW))
|
||||
|
||||
#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \
|
||||
((POLARITY) == PWR_PIN_POLARITY_LOW))
|
||||
|
||||
|
||||
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
|
||||
((TYPE) == PWR_PVM_3))
|
||||
|
||||
#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\
|
||||
((MODE) == PWR_PVM_MODE_IT_RISING) ||\
|
||||
((MODE) == PWR_PVM_MODE_IT_FALLING) ||\
|
||||
((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\
|
||||
((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\
|
||||
((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\
|
||||
((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))
|
||||
|
||||
#define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00u) && \
|
||||
(((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00u))
|
||||
|
||||
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
|
||||
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
|
||||
|
||||
|
||||
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
|
||||
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
|
||||
|
||||
#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
|
||||
((CHARGING) == PWR_BATTERY_CHARGING_ENABLE))
|
||||
|
||||
|
||||
#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
|
||||
|
||||
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
|
||||
((GPIO) == PWR_GPIO_B) ||\
|
||||
((GPIO) == PWR_GPIO_C) ||\
|
||||
((GPIO) == PWR_GPIO_D) ||\
|
||||
((GPIO) == PWR_GPIO_E) ||\
|
||||
((GPIO) == PWR_GPIO_H))
|
||||
|
||||
#define IS_PWR_SMPS_MODE(SMPS_MODE) (((SMPS_MODE) == PWR_SMPS_BYPASS) ||\
|
||||
((SMPS_MODE) == PWR_SMPS_STEP_DOWN))
|
||||
|
||||
#define IS_PWR_SMPS_STARTUP_CURRENT(SMPS_STARTUP_CURRENT) (((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_80MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_100MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_120MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_140MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_160MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_180MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_200MA) ||\
|
||||
((SMPS_STARTUP_CURRENT) == PWR_SMPS_STARTUP_CURRENT_220MA))
|
||||
|
||||
#define IS_PWR_SMPS_OUTPUT_VOLTAGE(SMPS_OUTPUT_VOLTAGE) (((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V20) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V25) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V30) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V35) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V40) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V45) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V50) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V55) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V60) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V65) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V70) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V75) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V80) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V85) ||\
|
||||
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V90))
|
||||
|
||||
#define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
|
||||
|
||||
#define IS_PWR_CORE_HOLD_RELEASE(CPU) ((CPU) == PWR_CORE_CPU2)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Peripheral Control functions **********************************************/
|
||||
uint32_t HAL_PWREx_GetVoltageRange(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
|
||||
|
||||
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
|
||||
void HAL_PWREx_DisableBatteryCharging(void);
|
||||
|
||||
void HAL_PWREx_EnableVddUSB(void);
|
||||
void HAL_PWREx_DisableVddUSB(void);
|
||||
|
||||
void HAL_PWREx_EnableInternalWakeUpLine(void);
|
||||
void HAL_PWREx_DisableInternalWakeUpLine(void);
|
||||
|
||||
void HAL_PWREx_EnableBORH_SMPSBypassIT(void);
|
||||
void HAL_PWREx_DisableBORH_SMPSBypassIT(void);
|
||||
void HAL_PWREx_EnableRFPhaseIT(void);
|
||||
void HAL_PWREx_DisableRFPhaseIT(void);
|
||||
void HAL_PWREx_EnableBLEActivityIT(void);
|
||||
void HAL_PWREx_DisableBLEActivityIT(void);
|
||||
void HAL_PWREx_Enable802ActivityIT(void);
|
||||
void HAL_PWREx_Disable802ActivityIT(void);
|
||||
void HAL_PWREx_EnableHOLDC2IT(void);
|
||||
void HAL_PWREx_DisableHOLDC2IT(void);
|
||||
|
||||
void HAL_PWREx_HoldCore(uint32_t CPU);
|
||||
void HAL_PWREx_ReleaseCore(uint32_t CPU);
|
||||
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
|
||||
HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
|
||||
void HAL_PWREx_EnablePullUpPullDownConfig(void);
|
||||
void HAL_PWREx_DisablePullUpPullDownConfig(void);
|
||||
|
||||
void HAL_PWREx_SetBORConfig(uint32_t BORConfiguration);
|
||||
uint32_t HAL_PWREx_GetBORConfig(void);
|
||||
|
||||
void HAL_PWREx_EnableSRAMRetention(void);
|
||||
void HAL_PWREx_DisableSRAMRetention(void);
|
||||
|
||||
void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode);
|
||||
void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode);
|
||||
|
||||
void HAL_PWREx_EnablePVM1(void);
|
||||
void HAL_PWREx_DisablePVM1(void);
|
||||
|
||||
void HAL_PWREx_EnablePVM3(void);
|
||||
void HAL_PWREx_DisablePVM3(void);
|
||||
|
||||
HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
|
||||
|
||||
HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS);
|
||||
void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode);
|
||||
uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void);
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void HAL_PWREx_EnableWakeUpPin(uint32_t WakeUpPinPolarity, uint32_t wakeupTarget);
|
||||
uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
|
||||
HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void HAL_PWREx_EnableLowPowerRunMode(void);
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
|
||||
|
||||
void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
|
||||
void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
|
||||
void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
|
||||
void HAL_PWREx_EnterSHUTDOWNMode(void);
|
||||
|
||||
void HAL_PWREx_PVD_PVM_IRQHandler(void);
|
||||
|
||||
void HAL_PWREx_PVM1Callback(void);
|
||||
void HAL_PWREx_PVM3Callback(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32WBxx_HAL_PWR_EX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,708 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_qspi.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of QSPI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_QSPI_H
|
||||
#define STM32WBxx_HAL_QSPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2)
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Exported_Types QSPI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief QSPI Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
|
||||
This parameter can be a number between 0 and 255 */
|
||||
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
|
||||
This parameter can be a value between 1 and 16 */
|
||||
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
|
||||
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
|
||||
This parameter can be a value of @ref QSPI_SampleShifting */
|
||||
uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
|
||||
required to address the flash memory. The flash capacity can be up to 4GB
|
||||
(addressed using 32 bits) in indirect mode, but the addressable space in
|
||||
memory-mapped mode is limited to 256MB
|
||||
This parameter can be a number between 0 and 31 */
|
||||
uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
|
||||
of clock cycles which the chip select must remain high between commands.
|
||||
This parameter can be a value of @ref QSPI_ChipSelectHighTime */
|
||||
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
|
||||
This parameter can be a value of @ref QSPI_ClockMode */
|
||||
}QSPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL QSPI State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
|
||||
HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
|
||||
HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
|
||||
HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
|
||||
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
|
||||
HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
|
||||
HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
|
||||
HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
|
||||
HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
|
||||
}HAL_QSPI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __QSPI_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
{
|
||||
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
|
||||
QSPI_InitTypeDef Init; /* QSPI communication parameters */
|
||||
uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
|
||||
__IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
|
||||
__IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
|
||||
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
|
||||
__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
|
||||
__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
|
||||
DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
|
||||
__IO HAL_LockTypeDef Lock; /* Locking object */
|
||||
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
|
||||
__IO uint32_t ErrorCode; /* QSPI Error code */
|
||||
uint32_t Timeout; /* Timeout for the QSPI memory access */
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
|
||||
#endif
|
||||
}QSPI_HandleTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Command structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Instruction; /* Specifies the Instruction to be sent
|
||||
This parameter can be a value (8-bit) between 0x00 and 0xFF */
|
||||
uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
|
||||
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
|
||||
uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
|
||||
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
|
||||
uint32_t AddressSize; /* Specifies the Address Size
|
||||
This parameter can be a value of @ref QSPI_AddressSize */
|
||||
uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
|
||||
This parameter can be a value of @ref QSPI_AlternateBytesSize */
|
||||
uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
|
||||
This parameter can be a number between 0 and 31 */
|
||||
uint32_t InstructionMode; /* Specifies the Instruction Mode
|
||||
This parameter can be a value of @ref QSPI_InstructionMode */
|
||||
uint32_t AddressMode; /* Specifies the Address Mode
|
||||
This parameter can be a value of @ref QSPI_AddressMode */
|
||||
uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
|
||||
This parameter can be a value of @ref QSPI_AlternateBytesMode */
|
||||
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
|
||||
This parameter can be a value of @ref QSPI_DataMode */
|
||||
uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
|
||||
This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
|
||||
until end of memory)*/
|
||||
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
|
||||
This parameter can be a value of @ref QSPI_DdrMode */
|
||||
uint32_t SIOOMode; /* Specifies the send instruction only once mode
|
||||
This parameter can be a value of @ref QSPI_SIOOMode */
|
||||
}QSPI_CommandTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Auto Polling mode configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
|
||||
This parameter can be any value between 0 and 0xFFFFFFFF */
|
||||
uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
|
||||
This parameter can be any value between 0 and 0xFFFFFFFF */
|
||||
uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
|
||||
This parameter can be any value between 0 and 0xFFFF */
|
||||
uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
|
||||
This parameter can be any value between 1 and 4 */
|
||||
uint32_t MatchMode; /* Specifies the method used for determining a match.
|
||||
This parameter can be a value of @ref QSPI_MatchMode */
|
||||
uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
|
||||
This parameter can be a value of @ref QSPI_AutomaticStop */
|
||||
}QSPI_AutoPollingTypeDef;
|
||||
|
||||
/**
|
||||
* @brief QSPI Memory Mapped mode configuration structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
|
||||
This parameter can be any value between 0 and 0xFFFF */
|
||||
uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
|
||||
This parameter can be a value of @ref QSPI_TimeOutActivation */
|
||||
}QSPI_MemoryMappedTypeDef;
|
||||
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL QSPI Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */
|
||||
HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */
|
||||
HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */
|
||||
HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */
|
||||
HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */
|
||||
HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */
|
||||
HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */
|
||||
HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */
|
||||
HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */
|
||||
HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */
|
||||
|
||||
HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */
|
||||
HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */
|
||||
}HAL_QSPI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL QSPI Callback pointer definition
|
||||
*/
|
||||
typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_ErrorCode QSPI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
|
||||
#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
|
||||
#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
|
||||
#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
|
||||
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
|
||||
#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_ClockMode QSPI Clock Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
|
||||
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AddressSize QSPI Address Size
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
|
||||
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
|
||||
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
|
||||
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
|
||||
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
|
||||
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
|
||||
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AddressMode QSPI Address Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
|
||||
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
|
||||
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
|
||||
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
|
||||
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
|
||||
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
|
||||
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_DataMode QSPI Data Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DATA_NONE 0x00000000U /*!<No data*/
|
||||
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
|
||||
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
|
||||
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_DdrMode QSPI DDR Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
|
||||
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
|
||||
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_MatchMode QSPI Match Mode
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
|
||||
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
|
||||
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
|
||||
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Flags QSPI Flags
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
|
||||
#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
|
||||
#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
|
||||
#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
|
||||
#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
|
||||
#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Interrupts QSPI Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
|
||||
#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
|
||||
#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
|
||||
#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
|
||||
#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
|
||||
* @brief QSPI Timeout definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
|
||||
* @{
|
||||
*/
|
||||
/** @brief Reset QSPI handle state.
|
||||
* @param __HANDLE__ : QSPI handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
|
||||
(__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/** @brief Enable the QSPI peripheral.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
|
||||
|
||||
/** @brief Disable the QSPI peripheral.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
|
||||
|
||||
/** @brief Enable the specified QSPI interrupt.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
|
||||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
|
||||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
|
||||
|
||||
|
||||
/** @brief Disable the specified QSPI interrupt.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
|
||||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
|
||||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
|
||||
|
||||
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_IT_TO: QSPI Timeout interrupt
|
||||
* @arg QSPI_IT_SM: QSPI Status match interrupt
|
||||
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
|
||||
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
|
||||
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the selected QSPI flag is set or not.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @param __FLAG__ : specifies the QSPI flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
|
||||
* @arg QSPI_FLAG_TO: QSPI Timeout flag
|
||||
* @arg QSPI_FLAG_SM: QSPI Status match flag
|
||||
* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
|
||||
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
|
||||
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
|
||||
|
||||
/** @brief Clears the specified QSPI's flag status.
|
||||
* @param __HANDLE__ : specifies the QSPI Handle.
|
||||
* @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
|
||||
* This parameter can be one of the following values:
|
||||
* @arg QSPI_FLAG_TO: QSPI Timeout flag
|
||||
* @arg QSPI_FLAG_SM: QSPI Status match flag
|
||||
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
|
||||
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup QSPI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* IO operation functions *****************************************************/
|
||||
/* QSPI IRQ handler method */
|
||||
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI indirect mode */
|
||||
HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
|
||||
HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
|
||||
|
||||
/* QSPI status flag polling mode */
|
||||
HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
|
||||
|
||||
/* QSPI memory-mapped mode */
|
||||
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
|
||||
|
||||
/* Callback functions in non-blocking modes ***********************************/
|
||||
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI indirect mode */
|
||||
void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI status flag polling mode */
|
||||
void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
/* QSPI memory-mapped mode */
|
||||
void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
|
||||
|
||||
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
|
||||
/* QSPI callback registering/unregistering */
|
||||
HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup QSPI_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control and State functions ************************************/
|
||||
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
|
||||
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
|
||||
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
|
||||
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
|
||||
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of exported functions -------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup QSPI_Private_Macros QSPI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
|
||||
|
||||
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U))
|
||||
|
||||
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
|
||||
((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
|
||||
|
||||
#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
|
||||
|
||||
#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
|
||||
((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
|
||||
|
||||
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
|
||||
((CLKMODE) == QSPI_CLOCK_MODE_3))
|
||||
|
||||
#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
|
||||
|
||||
#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
|
||||
((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
|
||||
((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
|
||||
((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
|
||||
|
||||
#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
|
||||
((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
|
||||
((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
|
||||
((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
|
||||
|
||||
#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
|
||||
|
||||
#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
|
||||
((MODE) == QSPI_INSTRUCTION_1_LINE) || \
|
||||
((MODE) == QSPI_INSTRUCTION_2_LINES) || \
|
||||
((MODE) == QSPI_INSTRUCTION_4_LINES))
|
||||
|
||||
#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
|
||||
((MODE) == QSPI_ADDRESS_1_LINE) || \
|
||||
((MODE) == QSPI_ADDRESS_2_LINES) || \
|
||||
((MODE) == QSPI_ADDRESS_4_LINES))
|
||||
|
||||
#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
|
||||
((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
|
||||
((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
|
||||
((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
|
||||
|
||||
#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
|
||||
((MODE) == QSPI_DATA_1_LINE) || \
|
||||
((MODE) == QSPI_DATA_2_LINES) || \
|
||||
((MODE) == QSPI_DATA_4_LINES))
|
||||
|
||||
#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
|
||||
((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
|
||||
|
||||
#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
|
||||
((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
|
||||
|
||||
#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
|
||||
|
||||
#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
|
||||
|
||||
#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
|
||||
((MODE) == QSPI_MATCH_MODE_OR))
|
||||
|
||||
#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
|
||||
((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
|
||||
|
||||
#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
|
||||
((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
|
||||
|
||||
#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* End of private macros -----------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_QSPI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,814 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_rng.c
|
||||
* @author MCD Application Team
|
||||
* @brief RNG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Random Number Generator (RNG) peripheral:
|
||||
* + Initialization and configuration functions
|
||||
* + Peripheral Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The RNG HAL driver can be used as follows:
|
||||
|
||||
(#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
|
||||
in HAL_RNG_MspInit().
|
||||
(#) Activate the RNG peripheral using HAL_RNG_Init() function.
|
||||
(#) Wait until the 32 bit Random Number Generator contains a valid
|
||||
random data using (polling/interrupt) mode.
|
||||
(#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
|
||||
|
||||
##### Callback registration #####
|
||||
==================================
|
||||
|
||||
[..]
|
||||
The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1
|
||||
allows the user to configure dynamically the driver callbacks.
|
||||
|
||||
[..]
|
||||
Use Function @ref HAL_RNG_RegisterCallback() to register a user callback.
|
||||
Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks:
|
||||
(+) ErrorCallback : RNG Error Callback.
|
||||
(+) MspInitCallback : RNG MspInit.
|
||||
(+) MspDeInitCallback : RNG MspDeInit.
|
||||
This function takes as parameters the HAL peripheral handle, the Callback ID
|
||||
and a pointer to the user callback function.
|
||||
|
||||
[..]
|
||||
Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default
|
||||
weak (surcharged) function.
|
||||
@ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
(+) ErrorCallback : RNG Error Callback.
|
||||
(+) MspInitCallback : RNG MspInit.
|
||||
(+) MspDeInitCallback : RNG MspDeInit.
|
||||
|
||||
[..]
|
||||
For specific callback ReadyDataCallback, use dedicated register callbacks:
|
||||
respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback().
|
||||
|
||||
[..]
|
||||
By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET
|
||||
all callbacks are set to the corresponding weak (surcharged) functions:
|
||||
example @ref HAL_RNG_ErrorCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init()
|
||||
and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
|
||||
|
||||
[..]
|
||||
Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only.
|
||||
Exception done MspInit/MspDeInit that can be registered/unregistered
|
||||
in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user)
|
||||
MspInit/DeInit callbacks can be used during the Init/DeInit.
|
||||
In that case first register the MspInit/MspDeInit user callbacks
|
||||
using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit()
|
||||
or @ref HAL_RNG_Init() function.
|
||||
|
||||
[..]
|
||||
When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registration feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (RNG)
|
||||
|
||||
/** @addtogroup RNG
|
||||
* @brief RNG HAL module driver.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Constants RNG Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define RNG_TIMEOUT_VALUE 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private functions prototypes ----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup RNG_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RNG_Exported_Functions_Group1
|
||||
* @brief Initialization and configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and configuration functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Initialize the RNG according to the specified parameters
|
||||
in the RNG_InitTypeDef and create the associated handle
|
||||
(+) DeInitialize the RNG peripheral
|
||||
(+) Initialize the RNG MSP
|
||||
(+) DeInitialize RNG MSP
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the RNG peripheral and creates the associated handle.
|
||||
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Check the RNG handle allocation */
|
||||
if (hrng == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance));
|
||||
assert_param(IS_RNG_CED(hrng->Init.ClockErrorDetection));
|
||||
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
if (hrng->State == HAL_RNG_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hrng->Lock = HAL_UNLOCKED;
|
||||
|
||||
hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */
|
||||
hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
|
||||
if (hrng->MspInitCallback == NULL)
|
||||
{
|
||||
hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
|
||||
}
|
||||
|
||||
/* Init the low level hardware */
|
||||
hrng->MspInitCallback(hrng);
|
||||
}
|
||||
#else
|
||||
if (hrng->State == HAL_RNG_STATE_RESET)
|
||||
{
|
||||
/* Allocate lock resource and initialize it */
|
||||
hrng->Lock = HAL_UNLOCKED;
|
||||
|
||||
/* Init the low level hardware */
|
||||
HAL_RNG_MspInit(hrng);
|
||||
}
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_BUSY;
|
||||
|
||||
/* Clock Error Detection Configuration */
|
||||
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection);
|
||||
|
||||
/* Enable the RNG Peripheral */
|
||||
__HAL_RNG_ENABLE(hrng);
|
||||
|
||||
/* Initialize the RNG state */
|
||||
hrng->State = HAL_RNG_STATE_READY;
|
||||
|
||||
/* Initialise the error code */
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_NONE;
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the RNG peripheral.
|
||||
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Check the RNG handle allocation */
|
||||
if (hrng == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Clear Clock Error Detection bit */
|
||||
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CED);
|
||||
/* Disable the RNG Peripheral */
|
||||
CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
|
||||
|
||||
/* Clear RNG interrupt status flags */
|
||||
CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
|
||||
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
if (hrng->MspDeInitCallback == NULL)
|
||||
{
|
||||
hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
|
||||
}
|
||||
|
||||
/* DeInit the low level hardware */
|
||||
hrng->MspDeInitCallback(hrng);
|
||||
#else
|
||||
/* DeInit the low level hardware */
|
||||
HAL_RNG_MspDeInit(hrng);
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/* Update the RNG state */
|
||||
hrng->State = HAL_RNG_STATE_RESET;
|
||||
|
||||
/* Initialise the error code */
|
||||
hrng->ErrorCode = HAL_RNG_ERROR_NONE;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
/* Return the function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the RNG MSP.
|
||||
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hrng);
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_RNG_MspInit must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitializes the RNG MSP.
|
||||
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hrng);
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_RNG_MspDeInit must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User RNG Callback
|
||||
* To be used instead of the weak predefined callback
|
||||
* @param hrng RNG handle
|
||||
* @param CallbackID ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
|
||||
* @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @param pCallback pointer to the Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hrng);
|
||||
|
||||
if (HAL_RNG_STATE_READY == hrng->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_RNG_ERROR_CB_ID :
|
||||
hrng->ErrorCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_RNG_MSPINIT_CB_ID :
|
||||
hrng->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_RNG_MSPDEINIT_CB_ID :
|
||||
hrng->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (HAL_RNG_STATE_RESET == hrng->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_RNG_MSPINIT_CB_ID :
|
||||
hrng->MspInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_RNG_MSPDEINIT_CB_ID :
|
||||
hrng->MspDeInitCallback = pCallback;
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hrng);
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregister an RNG Callback
|
||||
* RNG callabck is redirected to the weak predefined callback
|
||||
* @param hrng RNG handle
|
||||
* @param CallbackID ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID
|
||||
* @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID
|
||||
* @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hrng);
|
||||
|
||||
if (HAL_RNG_STATE_READY == hrng->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_RNG_ERROR_CB_ID :
|
||||
hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
|
||||
break;
|
||||
|
||||
case HAL_RNG_MSPINIT_CB_ID :
|
||||
hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
|
||||
case HAL_RNG_MSPDEINIT_CB_ID :
|
||||
hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (HAL_RNG_STATE_RESET == hrng->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_RNG_MSPINIT_CB_ID :
|
||||
hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
|
||||
case HAL_RNG_MSPDEINIT_CB_ID :
|
||||
hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */
|
||||
break;
|
||||
|
||||
default :
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hrng);
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register Data Ready RNG Callback
|
||||
* To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback
|
||||
* @param hrng RNG handle
|
||||
* @param pCallback pointer to the Data Ready Callback function
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if (pCallback == NULL)
|
||||
{
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hrng);
|
||||
|
||||
if (HAL_RNG_STATE_READY == hrng->State)
|
||||
{
|
||||
hrng->ReadyDataCallback = pCallback;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hrng);
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister the Data Ready RNG Callback
|
||||
* Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback
|
||||
* @param hrng RNG handle
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hrng);
|
||||
|
||||
if (HAL_RNG_STATE_READY == hrng->State)
|
||||
{
|
||||
hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the error code */
|
||||
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK;
|
||||
/* Return error status */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hrng);
|
||||
return status;
|
||||
}
|
||||
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup RNG_Exported_Functions_Group2
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Get the 32 bit Random number
|
||||
(+) Get the 32 bit Random number with interrupt enabled
|
||||
(+) Handle RNG interrupt request
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Generates a 32-bit random number.
|
||||
* @note Each time the random number data is read the RNG_FLAG_DRDY flag
|
||||
* is automatically cleared.
|
||||
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @param random32bit pointer to generated random number variable if successful.
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hrng);
|
||||
|
||||
/* Check RNG peripheral state */
|
||||
if (hrng->State == HAL_RNG_STATE_READY)
|
||||
{
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_BUSY;
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Check if data register contains valid random data */
|
||||
while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
|
||||
{
|
||||
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
|
||||
{
|
||||
hrng->State = HAL_RNG_STATE_READY;
|
||||
hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT;
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Get a 32bit Random number */
|
||||
hrng->RandomNumber = hrng->Instance->DR;
|
||||
*random32bit = hrng->RandomNumber;
|
||||
|
||||
hrng->State = HAL_RNG_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates a 32-bit random number in interrupt mode.
|
||||
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hrng);
|
||||
|
||||
/* Check RNG peripheral state */
|
||||
if (hrng->State == HAL_RNG_STATE_READY)
|
||||
{
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_BUSY;
|
||||
|
||||
/* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
|
||||
__HAL_RNG_ENABLE_IT(hrng);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handles RNG interrupt request.
|
||||
* @note In the case of a clock error, the RNG is no more able to generate
|
||||
* random numbers because the PLL48CLK clock is not correct. User has
|
||||
* to check that the clock controller is correctly configured to provide
|
||||
* the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
|
||||
* The clock error has no impact on the previously generated
|
||||
* random numbers, and the RNG_DR register contents can be used.
|
||||
* @note In the case of a seed error, the generation of random numbers is
|
||||
* interrupted as long as the SECS bit is '1'. If a number is
|
||||
* available in the RNG_DR register, it must not be used because it may
|
||||
* not have enough entropy. In this case, it is recommended to clear the
|
||||
* SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
|
||||
* the RNG peripheral to reinitialize and restart the RNG.
|
||||
* @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
|
||||
* or CEIS are set.
|
||||
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
|
||||
*/
|
||||
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
uint32_t rngclockerror = 0U;
|
||||
|
||||
/* RNG clock error interrupt occurred */
|
||||
if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
|
||||
{
|
||||
rngclockerror = 1U;
|
||||
}
|
||||
else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
|
||||
{
|
||||
rngclockerror = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nothing to do */
|
||||
}
|
||||
|
||||
if (rngclockerror == 1U)
|
||||
{
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_ERROR;
|
||||
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
/* Call registered Error callback */
|
||||
hrng->ErrorCallback(hrng);
|
||||
#else
|
||||
/* Call legacy weak Error callback */
|
||||
HAL_RNG_ErrorCallback(hrng);
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/* Clear the clock error flag */
|
||||
__HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
|
||||
}
|
||||
|
||||
/* Check RNG data ready interrupt occurred */
|
||||
if (__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
|
||||
{
|
||||
/* Generate random number once, so disable the IT */
|
||||
__HAL_RNG_DISABLE_IT(hrng);
|
||||
|
||||
/* Get the 32bit Random number (DRDY flag automatically cleared) */
|
||||
hrng->RandomNumber = hrng->Instance->DR;
|
||||
|
||||
if (hrng->State != HAL_RNG_STATE_ERROR)
|
||||
{
|
||||
/* Change RNG peripheral state */
|
||||
hrng->State = HAL_RNG_STATE_READY;
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hrng);
|
||||
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
/* Call registered Data Ready callback */
|
||||
hrng->ReadyDataCallback(hrng, hrng->RandomNumber);
|
||||
#else
|
||||
/* Call legacy weak Data Ready callback */
|
||||
HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read latest generated random number.
|
||||
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval random value
|
||||
*/
|
||||
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
return (hrng->RandomNumber);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Data Ready callback in non-blocking mode.
|
||||
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @param random32bit generated random number.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hrng);
|
||||
UNUSED(random32bit);
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_RNG_ReadyDataCallback must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RNG error callbacks.
|
||||
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(hrng);
|
||||
/* NOTE : This function should not be modified. When the callback is needed,
|
||||
function HAL_RNG_ErrorCallback must be implemented in the user file.
|
||||
*/
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup RNG_Exported_Functions_Group3
|
||||
* @brief Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permits to get in run-time the status of the peripheral
|
||||
and the data flow.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the RNG state.
|
||||
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
|
||||
* the configuration information for RNG.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
return hrng->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the RNG handle error code.
|
||||
* @param hrng: pointer to a RNG_HandleTypeDef structure.
|
||||
* @retval RNG Error Code
|
||||
*/
|
||||
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
|
||||
{
|
||||
/* Return RNG Error Code */
|
||||
return hrng->ErrorCode;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* RNG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,378 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_rng.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RNG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_RNG_H
|
||||
#define STM32WBxx_HAL_RNG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (RNG)
|
||||
|
||||
/** @defgroup RNG RNG
|
||||
* @brief RNG HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types RNG Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ClockErrorDetection; /*!< CED Clock error detection */
|
||||
} RNG_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
|
||||
HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
|
||||
HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
|
||||
HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
|
||||
HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
|
||||
|
||||
} HAL_RNG_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __RNG_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
|
||||
{
|
||||
RNG_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
RNG_InitTypeDef Init; /*!< RNG configuration parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< RNG locking object */
|
||||
|
||||
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< RNG Error code */
|
||||
|
||||
uint32_t RandomNumber; /*!< Last Generated RNG Data */
|
||||
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */
|
||||
void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */
|
||||
|
||||
void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */
|
||||
void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
} RNG_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL RNG Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */
|
||||
|
||||
HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */
|
||||
HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */
|
||||
|
||||
} HAL_RNG_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL RNG Callback pointer definition
|
||||
*/
|
||||
typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */
|
||||
typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */
|
||||
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RNG_Exported_Constants RNG Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
|
||||
* @{
|
||||
*/
|
||||
#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
|
||||
#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
|
||||
#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
|
||||
* @{
|
||||
*/
|
||||
#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
|
||||
#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
|
||||
#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
|
||||
* @{
|
||||
*/
|
||||
#define RNG_CED_ENABLE 0x00000000U /*!< Clock error detection Enabled */
|
||||
#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection Disabled */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Error_Definition RNG Error Definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup RNG_Exported_Macros RNG Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset RNG handle state
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_RNG_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0U)
|
||||
#else
|
||||
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
|
||||
#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Enables the RNG peripheral.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
|
||||
|
||||
/**
|
||||
* @brief Disables the RNG peripheral.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
|
||||
|
||||
/**
|
||||
* @brief Check the selected RNG flag status.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @param __FLAG__ RNG flag
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_FLAG_DRDY: Data ready
|
||||
* @arg RNG_FLAG_CECS: Clock error current status
|
||||
* @arg RNG_FLAG_SECS: Seed error current status
|
||||
* @retval The new state of __FLAG__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/**
|
||||
* @brief Clears the selected RNG flag status.
|
||||
* @param __HANDLE__ RNG handle
|
||||
* @param __FLAG__ RNG flag to clear
|
||||
* @note WARNING: This is a dummy macro for HAL code alignment,
|
||||
* flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
|
||||
|
||||
/**
|
||||
* @brief Enables the RNG interrupts.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
|
||||
|
||||
/**
|
||||
* @brief Disables the RNG interrupts.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified RNG interrupt has occurred or not.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @param __INTERRUPT__ specifies the RNG interrupt status flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_IT_DRDY: Data ready interrupt
|
||||
* @arg RNG_IT_CEI: Clock error interrupt
|
||||
* @arg RNG_IT_SEI: Seed error interrupt
|
||||
* @retval The new state of __INTERRUPT__ (SET or RESET).
|
||||
*/
|
||||
#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Clear the RNG interrupt status flags.
|
||||
* @param __HANDLE__ RNG Handle
|
||||
* @param __INTERRUPT__ specifies the RNG interrupt status flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RNG_IT_CEI: Clock error interrupt
|
||||
* @arg RNG_IT_SEI: Seed error interrupt
|
||||
* @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RNG_Exported_Functions RNG Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
|
||||
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
|
||||
|
||||
HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
|
||||
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
|
||||
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
|
||||
|
||||
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
|
||||
void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
|
||||
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RNG_Private_Macros RNG Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
|
||||
((IT) == RNG_IT_SEI))
|
||||
|
||||
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
|
||||
((FLAG) == RNG_FLAG_CECS) || \
|
||||
((FLAG) == RNG_FLAG_SECS))
|
||||
|
||||
/**
|
||||
* @brief Verify the RNG Clock Error Detection mode.
|
||||
* @param __MODE__ RNG Clock Error Detection mode
|
||||
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
|
||||
*/
|
||||
#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \
|
||||
((__MODE__) == RNG_CED_DISABLE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* RNG */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* STM32WBxx_HAL_RNG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,981 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of RTC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_RTC_H
|
||||
#define STM32WBxx_HAL_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/* Include low level driver */
|
||||
#include "stm32wbxx_ll_exti.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Types RTC Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
|
||||
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
|
||||
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
|
||||
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
|
||||
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
|
||||
|
||||
}HAL_RTCStateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Configuration Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
||||
|
||||
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
|
||||
|
||||
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
|
||||
|
||||
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
|
||||
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
|
||||
|
||||
uint32_t OutPutRemap; /*!< Specifies the remap for RTC output.
|
||||
This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */
|
||||
|
||||
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
|
||||
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
|
||||
|
||||
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
|
||||
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
|
||||
}RTC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
|
||||
|
||||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
|
||||
|
||||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
|
||||
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
|
||||
This parameter corresponds to a time unit range between [0-1] Second
|
||||
with [1 Sec / SecondFraction +1] granularity */
|
||||
|
||||
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
|
||||
corresponding to Synchronous pre-scaler factor value (PREDIV_S)
|
||||
This parameter corresponds to a time unit range between [0-1] Second
|
||||
with [1 Sec / SecondFraction +1] granularity.
|
||||
This field will be used only by HAL_RTC_GetTime function */
|
||||
|
||||
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
|
||||
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
|
||||
|
||||
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
|
||||
in CR register to store the operation.
|
||||
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
|
||||
}RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
|
||||
|
||||
uint8_t Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
|
||||
|
||||
}RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
|
||||
|
||||
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
||||
|
||||
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
|
||||
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
|
||||
|
||||
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
||||
|
||||
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
|
||||
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint32_t Alarm; /*!< Specifies the alarm .
|
||||
This parameter can be a value of @ref RTC_Alarms_Definitions */
|
||||
}RTC_AlarmTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Handle Structure definition
|
||||
*/
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
typedef struct __RTC_HandleTypeDef
|
||||
#else
|
||||
typedef struct
|
||||
#endif
|
||||
{
|
||||
RTC_TypeDef *Instance; /*!< Register base address */
|
||||
|
||||
RTC_InitTypeDef Init; /*!< RTC required parameters */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< RTC locking object */
|
||||
|
||||
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
|
||||
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */
|
||||
|
||||
void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */
|
||||
|
||||
void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */
|
||||
|
||||
void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */
|
||||
|
||||
void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */
|
||||
|
||||
void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */
|
||||
|
||||
void (* Tamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 3 Event callback */
|
||||
|
||||
void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */
|
||||
|
||||
void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */
|
||||
|
||||
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
|
||||
|
||||
}RTC_HandleTypeDef;
|
||||
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief HAL LPTIM Callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */
|
||||
HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */
|
||||
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC TimeStamp Event Callback ID */
|
||||
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC WakeUp Timer Event Callback ID */
|
||||
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */
|
||||
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
|
||||
HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */
|
||||
HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */
|
||||
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */
|
||||
}HAL_RTC_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief HAL RTC Callback pointer definition
|
||||
*/
|
||||
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Constants RTC Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Hour_Formats RTC Hour Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U)
|
||||
#define RTC_HOURFORMAT_12 ((uint32_t)RTC_CR_FMT)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U)
|
||||
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)RTC_CR_POL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)
|
||||
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000U)
|
||||
#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U)
|
||||
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)RTC_CR_SUB1H)
|
||||
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)RTC_CR_ADD1H)
|
||||
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U)
|
||||
#define RTC_STOREOPERATION_SET ((uint32_t)RTC_CR_BKP)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FORMAT_BIN ((uint32_t)0x000000000U)
|
||||
#define RTC_FORMAT_BCD ((uint32_t)0x000000001U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Coded in BCD format */
|
||||
#define RTC_MONTH_JANUARY ((uint8_t)0x01U)
|
||||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
|
||||
#define RTC_MONTH_MARCH ((uint8_t)0x03U)
|
||||
#define RTC_MONTH_APRIL ((uint8_t)0x04U)
|
||||
#define RTC_MONTH_MAY ((uint8_t)0x05U)
|
||||
#define RTC_MONTH_JUNE ((uint8_t)0x06U)
|
||||
#define RTC_MONTH_JULY ((uint8_t)0x07U)
|
||||
#define RTC_MONTH_AUGUST ((uint8_t)0x08U)
|
||||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
|
||||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)
|
||||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
|
||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
|
||||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
|
||||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
|
||||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
|
||||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
|
||||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
|
||||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
|
||||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U)
|
||||
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
|
||||
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
|
||||
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
|
||||
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
|
||||
#define RTC_ALARMMASK_ALL ((uint32_t) (RTC_ALARMMASK_NONE | \
|
||||
RTC_ALARMMASK_DATEWEEKDAY | \
|
||||
RTC_ALARMMASK_HOURS | \
|
||||
RTC_ALARMMASK_MINUTES | \
|
||||
RTC_ALARMMASK_SECONDS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARM_A RTC_CR_ALRAE
|
||||
#define RTC_ALARM_B RTC_CR_ALRBE
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U) /*!< All Alarm SS fields are masked.
|
||||
There is no comparison on sub seconds
|
||||
for Alarm */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are don't care in Alarm
|
||||
comparison. Only SS[0] is compared. */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] are don't care in Alarm
|
||||
comparison. Only SS[1:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)) /*!< SS[14:3] are don't care in Alarm
|
||||
comparison. Only SS[2:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] are don't care in Alarm
|
||||
comparison. Only SS[3:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)) /*!< SS[14:5] are don't care in Alarm
|
||||
comparison. Only SS[4:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)) /*!< SS[14:6] are don't care in Alarm
|
||||
comparison. Only SS[5:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)) /*!< SS[14:7] are don't care in Alarm
|
||||
` comparison. Only SS[6:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] are don't care in Alarm
|
||||
comparison. Only SS[7:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:9] are don't care in Alarm
|
||||
comparison. Only SS[8:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:10] are don't care in Alarm
|
||||
comparison. Only SS[9:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:11] are don't care in Alarm
|
||||
comparison. Only SS[10:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t) (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:12] are don't care in Alarm
|
||||
comparison.Only SS[11:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:13] are don't care in Alarm
|
||||
comparison. Only SS[12:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14] is don't care in Alarm
|
||||
comparison.Only SS[13:0] are compared */
|
||||
#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match
|
||||
to activate alarm. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) /*!< Enable Timestamp Interrupt */
|
||||
#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) /*!< Enable Wakeup timer Interrupt */
|
||||
#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) /*!< Enable Alarm A Interrupt */
|
||||
#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) /*!< Enable Alarm B Interrupt */
|
||||
#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /*!< Enable all Tamper Interrupt */
|
||||
#if defined(RTC_TAMPER1_SUPPORT)
|
||||
#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt */
|
||||
#endif
|
||||
#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
|
||||
#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
|
||||
#if defined(RTC_TAMPER1_SUPPORT)
|
||||
#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
|
||||
#endif
|
||||
#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
|
||||
#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
|
||||
#if defined(RTC_ISR_ITSF)
|
||||
#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
|
||||
#endif
|
||||
#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
|
||||
#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
|
||||
#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
|
||||
#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
|
||||
#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
|
||||
#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
|
||||
#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)
|
||||
#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)
|
||||
#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)
|
||||
#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Macros RTC Exported Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset RTC handle state
|
||||
* @param __HANDLE__ RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
|
||||
(__HANDLE__)->State = HAL_RTC_STATE_RESET;\
|
||||
(__HANDLE__)->MspInitCallback = NULL;\
|
||||
(__HANDLE__)->MspDeInitCallback = NULL;\
|
||||
}while(0)
|
||||
#else
|
||||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
|
||||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @brief Disable the write protection for RTC registers.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xCAU; \
|
||||
(__HANDLE__)->Instance->WPR = 0x53U; \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Enable the write protection for RTC registers.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
|
||||
do{ \
|
||||
(__HANDLE__)->Instance->WPR = 0xFFU; \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMA peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC ALARMB peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC ALARMB peripheral.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
|
||||
|
||||
/**
|
||||
* @brief Enable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Disable the RTC Alarm interrupt.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != 0U)? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_IT_ALRA: Alarm A interrupt
|
||||
* @arg RTC_IT_ALRB: Alarm B interrupt
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Get the selected RTC Alarm's flag status.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC Alarm Flag sources to check.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @arg RTC_FLAG_ALRBF
|
||||
* @arg RTC_FLAG_ALRAWF
|
||||
* @arg RTC_FLAG_ALRBWF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm's pending flags.
|
||||
* @param __HANDLE__ specifies the RTC handle.
|
||||
* @param __FLAG__ specifies the RTC Alarm Flag sources to clear.
|
||||
* This parameter can be:
|
||||
* @arg RTC_FLAG_ALRAF
|
||||
* @arg RTC_FLAG_ALRBF
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC Alarm associated Exti line by core 1.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable interrupt on the RTC Alarm associated Exti line by core 2.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTIC2_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC Alarm associated Exti line by core 1.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Disable interrupt on the RTC Alarm associated Exti line by core 2.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTIC2_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC Alarm associated Exti line by core 1.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Enable event on the RTC Alarm associated Exti line by core 2.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTIC2_ENABLE_EVENT() (EXTI->C2EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC Alarm associated Exti line by core 1.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Disable event on the RTC Alarm associated Exti line by core 2.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTIC2_DISABLE_EVENT() (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/*----------------------------*/
|
||||
/**
|
||||
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
|
||||
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0U)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or notby core 1.
|
||||
* @retval Line Status.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not by core 2.
|
||||
* @retval Line Status.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTIC2_GET_FLAG() (EXTI->PR2 & RTC_EXTI_LINE_ALARM_EVENT)
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm associated Exti line flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/**
|
||||
* @brief Clear the RTC Alarm associated Exti line flag.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTIC2_CLEAR_FLAG() (EXTI->PR2 = (RTC_EXTI_LINE_ALARM_EVENT))
|
||||
|
||||
/*----------------------------*/
|
||||
/**
|
||||
* @brief Generate a Software interrupt on RTC Alarm associated Exti line.
|
||||
* @retval None.
|
||||
*/
|
||||
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
|
||||
/*----------------------------*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include RTC HAL Extended module */
|
||||
#include "stm32wbxx_hal_rtc_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup RTC_Exported_Functions RTC Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @{
|
||||
*/
|
||||
/* Initialization and de-initialization functions ****************************/
|
||||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
|
||||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
|
||||
|
||||
/* Callbacks Register/UnRegister functions ***********************************/
|
||||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
|
||||
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
|
||||
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
|
||||
* @{
|
||||
*/
|
||||
/* RTC Time and Date functions ************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
|
||||
* @{
|
||||
*/
|
||||
/* RTC Alarm functions ********************************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
|
||||
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
|
||||
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
|
||||
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
|
||||
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
|
||||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions *************************************************/
|
||||
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @defgroup RTC_Private_Constants RTC Private Constants
|
||||
* @{
|
||||
*/
|
||||
/* Masks Definition */
|
||||
#define RTC_TR_RESERVED_MASK ((uint32_t) (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
|
||||
RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
|
||||
RTC_TR_SU))
|
||||
#define RTC_DR_RESERVED_MASK ((uint32_t) (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
|
||||
RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \
|
||||
RTC_DR_DU))
|
||||
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
|
||||
#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF))
|
||||
|
||||
#define RTC_TIMEOUT_VALUE 1000U
|
||||
|
||||
#define RTC_EXTI_LINE_ALARM_EVENT (LL_EXTI_LINE_17) /*!< External interrupt line connected to the RTC Alarm event */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Private_Macros RTC Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
|
||||
((FORMAT) == RTC_HOURFORMAT_24))
|
||||
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
|
||||
((POL) == RTC_OUTPUT_POLARITY_LOW))
|
||||
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
|
||||
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
|
||||
|
||||
#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
|
||||
((REMAP) == RTC_OUTPUT_REMAP_POS1))
|
||||
|
||||
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
|
||||
((PM) == RTC_HOURFORMAT12_PM))
|
||||
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
|
||||
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
|
||||
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
|
||||
((OPERATION) == RTC_STOREOPERATION_SET))
|
||||
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
|
||||
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99U)
|
||||
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1U) && ((MONTH) <= (uint32_t)12U))
|
||||
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1U) && ((DATE) <= (uint32_t)31U))
|
||||
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t)0U) && ((DATE) <= (uint32_t)31U))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
|
||||
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
|
||||
|
||||
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0U)
|
||||
|
||||
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
|
||||
((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
|
||||
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FU)
|
||||
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFFU)
|
||||
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0U) && ((HOUR) <= (uint32_t)12U))
|
||||
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23U)
|
||||
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59U)
|
||||
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions -------------------------------------------------------------*/
|
||||
/** @defgroup RTC_Private_Functions RTC Private Functions
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
|
||||
uint8_t RTC_ByteToBcd2(uint8_t Value);
|
||||
uint8_t RTC_Bcd2ToByte(uint8_t Value);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_RTC_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,961 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32wbxx_hal_sai.h
|
||||
* @author MCD Application Team
|
||||
* @brief Header file of SAI HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2019 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32WBxx_HAL_SAI_H
|
||||
#define STM32WBxx_HAL_SAI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32wbxx_hal_def.h"
|
||||
|
||||
/** @addtogroup STM32WBxx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SAI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/** @defgroup SAI_Exported_Types SAI Exported Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HAL State structures definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */
|
||||
HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */
|
||||
HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */
|
||||
HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
|
||||
HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */
|
||||
} HAL_SAI_StateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SAI Callback prototype
|
||||
*/
|
||||
typedef void (*SAIcallback)(void);
|
||||
|
||||
/** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition
|
||||
* @brief SAI PDM Init structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
FunctionalState Activation; /*!< Enable/disable PDM interface */
|
||||
uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
|
||||
uint32_t ClockEnable; /*!< Specifies which clock must be enabled.
|
||||
This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
|
||||
} SAI_PdmInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
|
||||
* @brief SAI Init Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
|
||||
This parameter can be a value of @ref SAI_Block_Mode */
|
||||
|
||||
uint32_t Synchro; /*!< Specifies SAI Block synchronization
|
||||
This parameter can be a value of @ref SAI_Block_Synchronization */
|
||||
|
||||
uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
|
||||
for BlockA and BlockB
|
||||
This parameter can be a value of @ref SAI_Block_SyncExt
|
||||
@note If both audio blocks of same SAI are used, this parameter has
|
||||
to be set to the same value for each audio block */
|
||||
|
||||
uint32_t MckOutput; /*!< Specifies whether master clock output will be generated or not.
|
||||
This parameter can be a value of @ref SAI_Block_MckOutput */
|
||||
|
||||
uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
|
||||
This parameter can be a value of @ref SAI_Block_Output_Drive
|
||||
@note This value has to be set before enabling the audio block
|
||||
but after the audio block configuration. */
|
||||
|
||||
uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
|
||||
This parameter can be a value of @ref SAI_Block_NoDivider
|
||||
@note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
|
||||
should be aligned to a number equal to a power of 2, from 8 to 256.
|
||||
If bit NODIV in the SAI_xCR1 register is set, the frame length can
|
||||
take any of the values from 8 to 256. */
|
||||
|
||||
uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
|
||||
This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
|
||||
|
||||
uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
|
||||
This parameter can be a value of @ref SAI_Audio_Frequency */
|
||||
|
||||
uint32_t Mckdiv; /*!< Specifies the master clock divider.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 63.
|
||||
@note This parameter is used only if AudioFrequency is set to
|
||||
SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
|
||||
|
||||
uint32_t MckOverSampling; /*!< Specifies the master clock oversampling.
|
||||
This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
|
||||
|
||||
uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
|
||||
This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
|
||||
|
||||
uint32_t CompandingMode; /*!< Specifies the companding mode type.
|
||||
This parameter can be a value of @ref SAI_Block_Companding_Mode */
|
||||
|
||||
uint32_t TriState; /*!< Specifies the companding mode type.
|
||||
This parameter can be a value of @ref SAI_TRIState_Management */
|
||||
|
||||
SAI_PdmInitTypeDef PdmInit; /*!< Specifies the PDM configuration. */
|
||||
|
||||
/* This part of the structure is automatically filled if your are using the high level initialisation
|
||||
function HAL_SAI_InitProtocol */
|
||||
|
||||
uint32_t Protocol; /*!< Specifies the SAI Block protocol.
|
||||
This parameter can be a value of @ref SAI_Block_Protocol */
|
||||
|
||||
uint32_t DataSize; /*!< Specifies the SAI Block data size.
|
||||
This parameter can be a value of @ref SAI_Block_Data_Size */
|
||||
|
||||
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
|
||||
|
||||
uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
|
||||
This parameter can be a value of @ref SAI_Block_Clock_Strobing */
|
||||
} SAI_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
|
||||
* @brief SAI Frame Init structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
|
||||
This parameter must be a number between Min_Data = 8 and Max_Data = 256.
|
||||
@note If master clock MCLK_x pin is declared as an output, the frame length
|
||||
should be aligned to a number equal to power of 2 in order to keep
|
||||
in an audio frame, an integer number of MCLK pulses by bit Clock. */
|
||||
|
||||
uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
|
||||
This Parameter specifies the length in number of bit clock (SCK + 1)
|
||||
of the active level of FS signal in audio frame.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
|
||||
|
||||
uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.
|
||||
This parameter can be a value of @ref SAI_Block_FS_Definition */
|
||||
|
||||
uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.
|
||||
This parameter can be a value of @ref SAI_Block_FS_Polarity */
|
||||
|
||||
uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
|
||||
This parameter can be a value of @ref SAI_Block_FS_Offset */
|
||||
|
||||
} SAI_FrameInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
|
||||
* @brief SAI Block Slot Init Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
|
||||
This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
|
||||
|
||||
uint32_t SlotSize; /*!< Specifies the Slot Size.
|
||||
This parameter can be a value of @ref SAI_Block_Slot_Size */
|
||||
|
||||
uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.
|
||||
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
|
||||
|
||||
uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
|
||||
This parameter can be a value of @ref SAI_Block_Slot_Active */
|
||||
} SAI_SlotInitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
|
||||
* @brief SAI handle Structure definition
|
||||
* @{
|
||||
*/
|
||||
typedef struct __SAI_HandleTypeDef
|
||||
{
|
||||
SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
|
||||
|
||||
SAI_InitTypeDef Init; /*!< SAI communication parameters */
|
||||
|
||||
SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */
|
||||
|
||||
SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
|
||||
|
||||
uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */
|
||||
|
||||
uint16_t XferSize; /*!< SAI transfer size */
|
||||
|
||||
uint16_t XferCount; /*!< SAI transfer counter */
|
||||
|
||||
DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
|
||||
|
||||
SAIcallback mutecallback; /*!< SAI mute callback */
|
||||
|
||||
void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< SAI locking object */
|
||||
|
||||
__IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
|
||||
|
||||
__IO uint32_t ErrorCode; /*!< SAI Error code */
|
||||
|
||||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
|
||||
void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */
|
||||
void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */
|
||||
void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */
|
||||
void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */
|
||||
void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */
|
||||
void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */
|
||||
void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */
|
||||
#endif
|
||||
} SAI_HandleTypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief SAI callback ID enumeration definition
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */
|
||||
HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */
|
||||
HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */
|
||||
HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */
|
||||
HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */
|
||||
HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */
|
||||
HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */
|
||||
} HAL_SAI_CallbackIDTypeDef;
|
||||
|
||||
/**
|
||||
* @brief SAI callback pointer definition
|
||||
*/
|
||||
typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/** @defgroup SAI_Exported_Constants SAI Exported Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Error_Code SAI Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */
|
||||
#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */
|
||||
#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */
|
||||
#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */
|
||||
#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */
|
||||
#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */
|
||||
#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */
|
||||
#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */
|
||||
#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */
|
||||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
|
||||
#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_SyncExt SAI External synchronisation
|
||||
* @{
|
||||
*/
|
||||
#define SAI_SYNCEXT_DISABLE 0U
|
||||
#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
|
||||
#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output
|
||||
* @{
|
||||
*/
|
||||
#define SAI_MCK_OUTPUT_DISABLE 0x00000000U
|
||||
#define SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Protocol SAI Supported protocol
|
||||
* @{
|
||||
*/
|
||||
#define SAI_I2S_STANDARD 0U
|
||||
#define SAI_I2S_MSBJUSTIFIED 1U
|
||||
#define SAI_I2S_LSBJUSTIFIED 2U
|
||||
#define SAI_PCM_LONG 3U
|
||||
#define SAI_PCM_SHORT 4U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Protocol_DataSize SAI protocol data size
|
||||
* @{
|
||||
*/
|
||||
#define SAI_PROTOCOL_DATASIZE_16BIT 0U
|
||||
#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
|
||||
#define SAI_PROTOCOL_DATASIZE_24BIT 2U
|
||||
#define SAI_PROTOCOL_DATASIZE_32BIT 3U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
|
||||
* @{
|
||||
*/
|
||||
#define SAI_AUDIO_FREQUENCY_192K 192000U
|
||||
#define SAI_AUDIO_FREQUENCY_96K 96000U
|
||||
#define SAI_AUDIO_FREQUENCY_48K 48000U
|
||||
#define SAI_AUDIO_FREQUENCY_44K 44100U
|
||||
#define SAI_AUDIO_FREQUENCY_32K 32000U
|
||||
#define SAI_AUDIO_FREQUENCY_22K 22050U
|
||||
#define SAI_AUDIO_FREQUENCY_16K 16000U
|
||||
#define SAI_AUDIO_FREQUENCY_11K 11025U
|
||||
#define SAI_AUDIO_FREQUENCY_8K 8000U
|
||||
#define SAI_AUDIO_FREQUENCY_MCKDIV 0U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
|
||||
* @{
|
||||
*/
|
||||
#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U
|
||||
#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
|
||||
* @{
|
||||
*/
|
||||
#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1
|
||||
#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Mode SAI Block Mode
|
||||
* @{
|
||||
*/
|
||||
#define SAI_MODEMASTER_TX 0x00000000U
|
||||
#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0
|
||||
#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1
|
||||
#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Protocol SAI Block Protocol
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FREE_PROTOCOL 0x00000000U
|
||||
#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0
|
||||
#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Data_Size SAI Block Data Size
|
||||
* @{
|
||||
*/
|
||||
#define SAI_DATASIZE_8 SAI_xCR1_DS_1
|
||||
#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
|
||||
#define SAI_DATASIZE_16 SAI_xCR1_DS_2
|
||||
#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
|
||||
#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
|
||||
#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FIRSTBIT_MSB 0x00000000U
|
||||
#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
|
||||
* @{
|
||||
*/
|
||||
#define SAI_CLOCKSTROBING_FALLINGEDGE 0U
|
||||
#define SAI_CLOCKSTROBING_RISINGEDGE 1U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
|
||||
* @{
|
||||
*/
|
||||
#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */
|
||||
#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */
|
||||
#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */
|
||||
#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
|
||||
* @{
|
||||
*/
|
||||
#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U
|
||||
#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
|
||||
* @{
|
||||
*/
|
||||
#define SAI_MASTERDIVIDER_ENABLE 0x00000000U
|
||||
#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FS_STARTFRAME 0x00000000U
|
||||
#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FS_ACTIVE_LOW 0x00000000U
|
||||
#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FS_FIRSTBIT 0x00000000U
|
||||
#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
|
||||
* @{
|
||||
*/
|
||||
#define SAI_SLOTSIZE_DATASIZE 0x00000000U
|
||||
#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0
|
||||
#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
|
||||
* @{
|
||||
*/
|
||||
#define SAI_SLOT_NOTACTIVE 0x00000000U
|
||||
#define SAI_SLOTACTIVE_0 0x00000001U
|
||||
#define SAI_SLOTACTIVE_1 0x00000002U
|
||||
#define SAI_SLOTACTIVE_2 0x00000004U
|
||||
#define SAI_SLOTACTIVE_3 0x00000008U
|
||||
#define SAI_SLOTACTIVE_4 0x00000010U
|
||||
#define SAI_SLOTACTIVE_5 0x00000020U
|
||||
#define SAI_SLOTACTIVE_6 0x00000040U
|
||||
#define SAI_SLOTACTIVE_7 0x00000080U
|
||||
#define SAI_SLOTACTIVE_8 0x00000100U
|
||||
#define SAI_SLOTACTIVE_9 0x00000200U
|
||||
#define SAI_SLOTACTIVE_10 0x00000400U
|
||||
#define SAI_SLOTACTIVE_11 0x00000800U
|
||||
#define SAI_SLOTACTIVE_12 0x00001000U
|
||||
#define SAI_SLOTACTIVE_13 0x00002000U
|
||||
#define SAI_SLOTACTIVE_14 0x00004000U
|
||||
#define SAI_SLOTACTIVE_15 0x00008000U
|
||||
#define SAI_SLOTACTIVE_ALL 0x0000FFFFU
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
|
||||
* @{
|
||||
*/
|
||||
#define SAI_STEREOMODE 0x00000000U
|
||||
#define SAI_MONOMODE SAI_xCR1_MONO
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_TRIState_Management SAI TRIState Management
|
||||
* @{
|
||||
*/
|
||||
#define SAI_OUTPUT_NOTRELEASED 0x00000000U
|
||||
#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
|
||||
#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0
|
||||
#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1
|
||||
#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
|
||||
#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
|
||||
* @{
|
||||
*/
|
||||
#define SAI_NOCOMPANDING 0x00000000U
|
||||
#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1
|
||||
#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
|
||||
#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
|
||||
#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
|
||||
* @{
|
||||
*/
|
||||
#define SAI_ZERO_VALUE 0x00000000U
|
||||
#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
|
||||
* @{
|
||||
*/
|
||||
#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE
|
||||
#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE
|
||||
#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE
|
||||
#define SAI_IT_FREQ SAI_xIMR_FREQIE
|
||||
#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE
|
||||
#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE
|
||||
#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR
|
||||
#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET
|
||||
#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG
|
||||
#define SAI_FLAG_FREQ SAI_xSR_FREQ
|
||||
#define SAI_FLAG_CNRDY SAI_xSR_CNRDY
|
||||
#define SAI_FLAG_AFSDET SAI_xSR_AFSDET
|
||||
#define SAI_FLAG_LFSDET SAI_xSR_LFSDET
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
|
||||
* @{
|
||||
*/
|
||||
#define SAI_FIFOSTATUS_EMPTY 0x00000000U
|
||||
#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
|
||||
#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
|
||||
#define SAI_FIFOSTATUS_HALFFULL 0x00030000U
|
||||
#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
|
||||
#define SAI_FIFOSTATUS_FULL 0x00050000U
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/** @defgroup SAI_Exported_Macros SAI Exported Macros
|
||||
* @brief macros to handle interrupts and specific configurations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @brief Reset SAI handle state.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
|
||||
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \
|
||||
(__HANDLE__)->State = HAL_SAI_STATE_RESET; \
|
||||
(__HANDLE__)->MspInitCallback = NULL; \
|
||||
(__HANDLE__)->MspDeInitCallback = NULL; \
|
||||
} while(0)
|
||||
#else
|
||||
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
|
||||
#endif
|
||||
|
||||
/** @brief Enable the specified SAI interrupts.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
|
||||
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
|
||||
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
|
||||
* @arg SAI_IT_FREQ: FIFO request interrupt enable
|
||||
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
|
||||
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
|
||||
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
|
||||
|
||||
/** @brief Disable the specified SAI interrupts.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
|
||||
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
|
||||
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
|
||||
* @arg SAI_IT_FREQ: FIFO request interrupt enable
|
||||
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
|
||||
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
|
||||
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
|
||||
|
||||
/** @brief Check whether the specified SAI interrupt source is enabled or not.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @param __INTERRUPT__ specifies the SAI interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
|
||||
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
|
||||
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
|
||||
* @arg SAI_IT_FREQ: FIFO request interrupt enable
|
||||
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
|
||||
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
|
||||
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
|
||||
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
|
||||
|
||||
/** @brief Check whether the specified SAI flag is set or not.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
|
||||
* @arg SAI_FLAG_MUTEDET: Mute detection flag.
|
||||
* @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
|
||||
* @arg SAI_FLAG_FREQ: FIFO request flag.
|
||||
* @arg SAI_FLAG_CNRDY: Codec not ready flag.
|
||||
* @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
|
||||
* @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
|
||||
|
||||
/** @brief Clear the specified SAI pending flag.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @param __FLAG__ specifies the flag to check.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
|
||||
* @arg SAI_FLAG_MUTEDET: Clear Mute detection
|
||||
* @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
|
||||
* @arg SAI_FLAG_FREQ: Clear FIFO request
|
||||
* @arg SAI_FLAG_CNRDY: Clear Codec not ready
|
||||
* @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
|
||||
* @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
|
||||
|
||||
/** @brief Enable SAI.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
|
||||
|
||||
/** @brief Disable SAI.
|
||||
* @param __HANDLE__ specifies the SAI Handle.
|
||||
* @retval None
|
||||
*/
|
||||
#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Include SAI HAL Extension module */
|
||||
#include "stm32wbxx_hal_sai_ex.h"
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup SAI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Initialization/de-initialization functions ********************************/
|
||||
/** @addtogroup SAI_Exported_Functions_Group1
|
||||
* @{
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
|
||||
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
|
||||
|
||||
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
|
||||
/* SAI callbacks register/unregister functions ********************************/
|
||||
HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai,
|
||||
HAL_SAI_CallbackIDTypeDef CallbackID,
|
||||
pSAI_CallbackTypeDef pCallback);
|
||||
HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai,
|
||||
HAL_SAI_CallbackIDTypeDef CallbackID);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* I/O operation functions ***************************************************/
|
||||
/** @addtogroup SAI_Exported_Functions_Group2
|
||||
* @{
|
||||
*/
|
||||
/* Blocking mode: Polling */
|
||||
HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
|
||||
|
||||
/* Non-Blocking mode: Interrupt */
|
||||
HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
|
||||
|
||||
/* Non-Blocking mode: DMA */
|
||||
HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
|
||||
|
||||
/* Abort function */
|
||||
HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
|
||||
|
||||
/* Mute management */
|
||||
HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
|
||||
HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
|
||||
HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
|
||||
HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
|
||||
|
||||
/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
|
||||
void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
|
||||
void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup SAI_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State functions ************************************************/
|
||||
HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
|
||||
uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @defgroup SAI_Private_Macros SAI Private Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
|
||||
((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
|
||||
((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
|
||||
|
||||
#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\
|
||||
((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
|
||||
((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
|
||||
((PROTOCOL) == SAI_PCM_LONG) ||\
|
||||
((PROTOCOL) == SAI_PCM_SHORT))
|
||||
|
||||
#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\
|
||||
((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
|
||||
((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\
|
||||
((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
|
||||
|
||||
#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
|
||||
((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
|
||||
((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
|
||||
((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
|
||||
((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
|
||||
|
||||
#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
|
||||
((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
|
||||
|
||||
#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U))
|
||||
|
||||
#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
|
||||
(((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))
|
||||
|
||||
#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
|
||||
((MODE) == SAI_MODEMASTER_RX) || \
|
||||
((MODE) == SAI_MODESLAVE_TX) || \
|
||||
((MODE) == SAI_MODESLAVE_RX))
|
||||
|
||||
#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
|
||||
((PROTOCOL) == SAI_AC97_PROTOCOL) || \
|
||||
((PROTOCOL) == SAI_SPDIF_PROTOCOL))
|
||||
|
||||
#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
|
||||
((DATASIZE) == SAI_DATASIZE_10) || \
|
||||
((DATASIZE) == SAI_DATASIZE_16) || \
|
||||
((DATASIZE) == SAI_DATASIZE_20) || \
|
||||
((DATASIZE) == SAI_DATASIZE_24) || \
|
||||
((DATASIZE) == SAI_DATASIZE_32))
|
||||
|
||||
#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
|
||||
((BIT) == SAI_FIRSTBIT_LSB))
|
||||
|
||||
#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
|
||||
((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
|
||||
|
||||
#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
|
||||
((SYNCHRO) == SAI_SYNCHRONOUS) || \
|
||||
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
|
||||
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
|
||||
|
||||
#define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
|
||||
((VALUE) == SAI_MCK_OUTPUT_DISABLE))
|
||||
|
||||
#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
|
||||
((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
|
||||
|
||||
#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
|
||||
((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
|
||||
|
||||
#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
|
||||
|
||||
#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
|
||||
((VALUE) == SAI_LAST_SENT_VALUE))
|
||||
|
||||
#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
|
||||
((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
|
||||
((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
|
||||
((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
|
||||
((MODE) == SAI_ALAW_2CPL_COMPANDING))
|
||||
|
||||
#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
|
||||
((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
|
||||
((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
|
||||
((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
|
||||
((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
|
||||
|
||||
#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
|
||||
((STATE) == SAI_OUTPUT_RELEASED))
|
||||
|
||||
#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
|
||||
((MODE) == SAI_STEREOMODE))
|
||||
|
||||
#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
|
||||
|
||||
#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
|
||||
|
||||
#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
|
||||
((SIZE) == SAI_SLOTSIZE_16B) || \
|
||||
((SIZE) == SAI_SLOTSIZE_32B))
|
||||
|
||||
#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
|
||||
|
||||
#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
|
||||
((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
|
||||
|
||||
#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
|
||||
((POLARITY) == SAI_FS_ACTIVE_HIGH))
|
||||
|
||||
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
|
||||
((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
|
||||
|
||||
#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
|
||||
|
||||
#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
|
||||
|
||||
#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/** @defgroup SAI_Private_Functions SAI Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32WBxx_HAL_SAI_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
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Reference in New Issue