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Target_NUVOTON: Add ARM_LIB_STACK and ARM_LIB_HEAP section 

Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
pull/9766/head
deepikabhavnani 2019-02-19 14:35:49 -06:00 committed by Deepika
parent c91d35ccc8
commit 2a192509c3
5 changed files with 107 additions and 70 deletions
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32
targets/TARGET_NUVOTON/TARGET_M451/device/TOOLCHAIN_ARM_MICRO/M453.sct
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@ -1,43 +1,47 @@
#! armcc -E
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00040000
#define MBED_APP_SIZE 0x00040000
#endif
#define MBED_RAM_START 0x20000000
#define MBED_RAM_SIZE 0x00008000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
LR_IROM1 MBED_APP_START {
ER_IROM1 MBED_APP_START { ; load address = execution address
#define VECTOR_SIZE (4*(16 + 64))
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE {
ARM_LIB_STACK MBED_RAM_START EMPTY MBED_BOOT_STACK_SIZE {
}
/* VTOR[TBLOFF] alignment requires:
*
* 1. Minumum 32-word
* 2. Rounding up to the next power of two of table size
*/
ER_IRAMVEC AlignExpr(+0, 512) EMPTY (4*(16 + 64)) { ; Reserve for vectors
ER_IRAMVEC AlignExpr(+0, 512) EMPTY VECTOR_SIZE { ; Reserve for vectors
}
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x8000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) ; 256 KB APROM
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20008000) ; 32 KB SRAM
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_START + MBED_RAM_SIZE)) ; 32 KB SRAM

39
targets/TARGET_NUVOTON/TARGET_M480/device/TOOLCHAIN_ARM_MICRO/M487.sct
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@ -1,30 +1,35 @@
#! armcc -E
; 512 KB APROM
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00080000
#define MBED_APP_SIZE 0x00080000
#endif
; 160 KB SRAM
#define MBED_RAM_START 0x20000000
#define MBED_RAM_SIZE 0x00028000
#define SPIM_CCM_START 0x20020000
#define SPIM_CCM_END 0x20028000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define VECTOR_SIZE (4*(16 + 96))
#define SPIM_CCM_START 0x20020000
#define SPIM_CCM_END 0x20028000
LR_IROM1 MBED_APP_START {
ER_IROM1 MBED_APP_START { ; load address = execution address
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE {
ARM_LIB_STACK MBED_RAM_START EMPTY MBED_BOOT_STACK_SIZE {
}
/* VTOR[TBLOFF] alignment requires:
@ -32,18 +37,18 @@ LR_IROM1 MBED_APP_START {
* 1. Minumum 32-word
* 2. Rounding up to the next power of two of table size
*/
ER_IRAMVEC AlignExpr(+0, 512) EMPTY (4*(16 + 96)) { ; Reserve for vectors
ER_IRAMVEC AlignExpr(+0, 512) EMPTY VECTOR_SIZE { ; Reserve for vectors
}
RW_m_crash_data AlignExpr(+0, 0x100) EMPTY 0x100 { ; Reserve for crash data storage
RW_m_crash_data AlignExpr(+0, 0x100) EMPTY 0x100 { ; Reserve for crash data storage
}
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x28000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) ; 512 KB APROM
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20028000) ; 160 KB SRAM
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_START + MBED_RAM_SIZE)) ; 160 KB SRAM

36
targets/TARGET_NUVOTON/TARGET_NANO100/device/TOOLCHAIN_ARM_MICRO/NANO130.sct
View File

@ -1,27 +1,41 @@
#! armcc -E
; 512 KB APROM
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00020000
#endif
; 64 KB SRAM (internal)
#define MBED_RAM_START 0x20000000
#define MBED_RAM_SIZE 0x4000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
LR_IROM1 0x00000000 {
ER_IROM1 0x00000000 { ; load address = execution address
#define VECTOR_SIZE (4*(16 + 142))
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE {
ARM_LIB_STACK MBED_RAM_START EMPTY MBED_BOOT_STACK_SIZE {
}
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x4000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
; Extern SRAM for HEAP
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= 0x00020000) ; 128 KB APROM
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20004000) ; 16 KB SRAM
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) ; 512 KB APROM
ScatterAssert(ImageLimit(RW_IRAM1) <= (MBED_RAM_START + MBED_RAM_SIZE)) ; 64 KB SRAM (internal)

41
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_SUPPORTED/NUC472.sct
View File

@ -1,26 +1,36 @@
#! armcc -E
; 512 KB APROM
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00080000
#define MBED_APP_SIZE 0x00080000
#endif
; 64 KB SRAM (internal)
#define MBED_RAM_START 0x20000000
#define MBED_RAM_SIZE 0x00010000
; 1 MB SRAM (external)
#define MBED_RAM1_START 0x60000000
#define MBED_RAM1_SIZE 0x00100000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
LR_IROM1 MBED_APP_START {
ER_IROM1 MBED_APP_START { ; load address = execution address
#define VECTOR_SIZE (4*(16 + 142))
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE {
ARM_LIB_STACK MBED_RAM_START EMPTY MBED_BOOT_STACK_SIZE {
}
/* VTOR[TBLOFF] alignment requires:
@ -28,23 +38,22 @@ LR_IROM1 MBED_APP_START {
* 1. Minumum 32-word
* 2. Rounding up to the next power of two of table size
*/
ER_IRAMVEC AlignExpr(+0, 1024) EMPTY (4*(16 + 142)) { ; Reserve for vectors
ER_IRAMVEC AlignExpr(+0, 1024) EMPTY VECTOR_SIZE { ; Reserve for vectors
}
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
.ANY (+RW +ZI)
}
; Too large to place into internal SRAM. So place into external SRAM instead.
ER_XRAM1 0x60000000 {
ER_XRAM1 MBED_RAM1_START {
*sal-stack-lwip* (+ZI)
}
; Extern SRAM for HEAP
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x60000000 + 0x100000 - AlignExpr(ImageLimit(ER_XRAM1), 16)) {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM1_START + MBED_RAM1_SIZE - AlignExpr(ImageLimit(ER_XRAM1), 16)) {
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) ; 512 KB APROM
ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal)
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x60100000) ; 1 MB SRAM (external)
ScatterAssert(ImageLimit(RW_IRAM1) <= (MBED_RAM_START + MBED_RAM_SIZE)) ; 64 KB SRAM (internal)
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM1_START + MBED_RAM1_SIZE)) ; 1 MB SRAM (external)

29
targets/TARGET_NUVOTON/TARGET_NUC472/device/TOOLCHAIN_ARM_MICRO/TARGET_NU_XRAM_UNSUPPORTED/NUC472.sct
View File

@ -1,26 +1,32 @@
#! armcc -E
; 512 KB APROM
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#define MBED_APP_START 0x00000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x00080000
#define MBED_APP_SIZE 0x00080000
#endif
; 64 KB SRAM (internal)
#define MBED_RAM_START 0x20000000
#define MBED_RAM_SIZE 0x00010000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
LR_IROM1 MBED_APP_START {
ER_IROM1 MBED_APP_START { ; load address = execution address
#define VECTOR_SIZE (4*(16 + 142))
LR_IROM1 MBED_APP_START MBED_APP_SIZE {
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*(RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
ARM_LIB_STACK 0x20000000 EMPTY MBED_BOOT_STACK_SIZE {
ARM_LIB_STACK MBED_RAM_START EMPTY MBED_BOOT_STACK_SIZE {
}
/* VTOR[TBLOFF] alignment requires:
@ -28,17 +34,16 @@ LR_IROM1 MBED_APP_START {
* 1. Minumum 32-word
* 2. Rounding up to the next power of two of table size
*/
ER_IRAMVEC AlignExpr(+0, 1024) EMPTY (4*(16 + 142)) { ; Reserve for vectors
ER_IRAMVEC AlignExpr(+0, 1024) EMPTY VECTOR_SIZE { ; Reserve for vectors
}
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
.ANY (+RW +ZI)
}
; Extern SRAM for HEAP
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x10000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
}
ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) ; 512 KB APROM
ScatterAssert(ImageLimit(RW_IRAM1) <= 0x20010000) ; 64 KB SRAM (internal)
ScatterAssert(ImageLimit(RW_IRAM1) <= (MBED_RAM_START + MBED_RAM_SIZE)) ; 64 KB SRAM (internal)