Filter numbers 14 to 27 are reserved for dual CAN configuration.
However, CAN3 operates in single CAN configuration according to the
reference manual).
CAN_2 and CAN_3 are enum and not #define and this causes compilation error with GCC_ARM
Instead put back the test of CAN_NUM (which are defined in can_device.h).
Ensure all instance memory blocks meet 4 byte alignment requirement
without relying on compiler's or liker's optional settings:
- gpioMemory[] for adi_gpio_Init()
- aRtcDevMem0[] for adi_rtc_Open()
- i2c_Mem[] or I2C_Mem[] for adi_i2c_Open()
- spi_Mem0[], spi_Mem1[], spi_Mem2[] or SPI_Mem[] for adi_spi_Open()
Add RSF synchro during init
Set a better WakeUp clock for long wake up period in order to stay in sleep mode
Use rtc_isenabled function before init as rtc_init is called at each set_time call
- Maintain compatible code for ARM 5 and ARM 6 while default alignment
settings differ.
- Instance memory containing memory pointers must be 4 byte aligned for
all compilers regardless compilers' settings.
- uint32_t is recommended to replace uint8_t for instance memory
declaration because uint32_t guarantee 4 byte alignment.
Based on the Mbed OS website the A3 is connected to "DAC", however there
is no define for DAC. In order to get the Realtek RTL8195AM to even compile
with mbed-os-example-client now, we must have the A3 defined - it is one of
the standard Arduine header pins. Therefore, setting it as NC.
A4-A5 are not connected either, so adding them as "NC" as well.
Realtek will hopefully push a proper fix sooner or later, if there is a
more meaningful define for the A3 pin. They do state however that the
A0-A3 pins are not GPIO capable anyway.
Ref: https://os.mbed.com/platforms/Realtek-RTL8195AM/
1. move ota region 1 from 0x00b000 to 0x040000
2. move ota region 2 from 0x0c0000 to 0x120000
3. refactor bootloader header as follows:
uint32_t tag;
uint32_t ver;
uint64_t timestamp;
uint32_t size;
uint8_t hash[32];
uint8_t campaign[16];
uint32_t crc32;
where,
a. hash is the sha256 checksum of the payload.
b. crc32 is the crc32 checksum of headers from tag to campaign.
4. Call NVIC_SystemReset for soft reset.
Signed-off-by: Tony Wu <tung7970@gmail.com>
signals are lost. It was observed at last for tests-api-spi ci-test-shield's
test.
This patch introduce usage of sdk5 origin implementation in which
sd_nvic_critical_region_enter/exit is calling each time critical region
is enter/exit. This fixes the issue.
Timer code was written based on integer multiple HF clock frequencies. EFR32 doesn't conform to that (38.4), and so the timestamp ticks were off by 1%. Enough to trip up some CI tests on TB_SENSE_12 (#5496)
- serial_init, serial_free and serial_baud function moved from serial_device.c (specific to each STM32 family) to serial_api.c (common STM32 file)
- default baudrate value was hardcoded to 9600
- Value is set now to MBED_CONF_PLATFORM_STDIO_BAUD_RATE for STDIO
- Value is set now to MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE for other use
- UART init will not be stopped before calling serial_baud function
This patch handles the case of SPI slave mode without MISO (NC).
In case MISO is not connected, we consider that SPI will be configured in
3 wires mode (CLK / MOSI / CS, but no MISO). In this case, the MOSI line
is bi-directional : SPI_DIRECTION_1LINE.
But as this is not supported yet in slave mode, we force it to
SPI_DIRECTION_2LINES. In this case slave SPI will receive data on MOSI
but nothing will be sent back to master as MISO is not connected.
Old lp_ticker handles past event, but it has a bug with premature go-off.
The bug can re-produce on mbed-os-tests-mbed_drivers-lp_timeout/mbed-os-tests-mbed_hal-lp_us_tickers (mbed-os commit: 9c1fd48529).
Because upper layer (mbed-os/hal/mbed_ticker_api.c) has handled past event, this code can be removed from lp_ticker.
The similar fix also applies to us_ticker.
Re-casting with tmp the uint8_t* pData pointer to uint16_t* brings a
memory corruption and typically can corrupt the size parameter. This
is fixed with this commit.
STM32 Internal ticket reference : 39116
Fixed issues raised from ARM PR review and removed the unsupported platform.
- Fixed an issue where the TRNG is read even though it may not be ready;
- Added configuration to ensure the buffering mode is disabled so only 8-bit bytes are generated;
- Moved the TRNG device handle into the trng_t structure.
Removed undefined spi slave related functions.
- Added error checking for trng_get_bytes function;
- Added curly brackets to single line conditions for some files;
- Changed rx and tx buffers in serial module as local variables;
- Removed some unused code and some minor formatting corrections;
- Minor i2c & spi updates for github pull request;
- Added function definition for spi_master_block_write.
Added default delay and sample times for the ADC during initialization.
- Added code to clear stack variable in trng_get_bytes upon exiting the
function;
- Remove lp ticker functionality as the timer hardware does not satisfy
lp timer requirements.
Added a check for the STUCK bit before reading the RNG data register to ensure there are no hardware faults.
- Removed .mbedignore to work around some exporter issues;
- Added #includes to some of the driver data C files for them to build on their own.
For api usage like DigitalOut led(LED1, 1) the hal function gpio_write()
sets the output before f. gpio_mode() is called. gpio_mode() clears the
output as it take never writen parameters (gpio_cfg_t.init_hight).
This patch use internal hardware register of GPIO output instedad of above paramiter latch
for retaining proper writen state.
The Page size has been set to 1 byte instead of the previous 256.
Although 256 is the physical page size, the driver supports
writing 1 byte at a time.
The computation of the sector number in GetSector for 2MB flash sizes
consists in adding an extra constant for 2MB dual bank (12 as in
ADDR_FLASH_SECTOR_12), then going through the same address check as if it
was an address of the first sector.
That means that we need to modify tmp and address as if it was a first bank
address, which we're doing here by sub_stracting 0x100000 delta.
Three main issues:
1) The 0x13 special case section in write data in ncs36510_i2c.c didn't have a write++ command.
2) In the same write function, the WDAT8 command was put before the 0x13 section and this is not correct
3) Needed to add wait_us(0) before and after the register writes for apparent clock domain crossing delay times until registers are stable in HW
There were also a handful of other tweaks related to general code maintenance and moving some status register checks to the proper locations.
TIMER2_7_IRQ is shared among several timer sources, including
us_ticker. Raising TIMER2_7_IRQ pending bit will trigger the timer
interrupt, but the timer interrupt handler will not know which timer
source this interrupt is for. This patch sets timer load value to one
tick and force us_ticker to fire almost "immediately".
TIMER2_7_IRQ is handled through a common interrupt handler, and
is automatically cleared. Therefore, there is no need to clear IRQ.
The underlying timer HAL treats load value as micro-seconds and does
conversion internally. Therefore, simply pass micro-seconds to timer
HAL without converting to tick first.
Signed-off-by: Tony Wu <tung7970@gmail.com>
Cribbed from 4bf42f2e20
I'm not sure if if there are any copyright issues here with what is
effectively a set of config files. A few folks have been bugging me (and
the redbear folks) for these changes, so I wanted them somewhere
centralized.
The generic Flash support for L4 and L0 families is already there,
but was not activated by default on 2 recentely added boards:
DISCO_L475VG_IOT01A and DISCO_L072CZ_LRWAN1
This is done now.
HAL_RNG_GetRandomNumber is a deprecated API and replaced here with
a call to HAL_RNG_GenerateRandomNumber.
Doing so, we also rework the driver to use the 4 bytes returned by a call
to HAL_RNG_GenerateRandomNumber instead of 1 byte out of 4.
HAL_RNG_GenerateRandomNumber was not returning any error code, so now
we can also check the return code.
Remove redundant memory regions, and merge multiple RAM regions into one
to solve ielftool zero padding issue.
The side effect is less control over object files placement. It's all up
to linker's best effort.
Signed-off-by: Tony Wu <tonywu@realtek.com>
lp_ticker driver is the known registered user of RTC handler API.
In case, a lp_ticker is set in the past, the lp_ticker_fire_interrupt
will be called which itself sets the RTC interrupt as pending by calling
NVIC_SetPendingIRQ(RTC_WKUP_IRQn). This all happens without actual
programing of the RTC wake-up.
As a result the RTC HW and corresponding HAL layer doesn't expect an
interrupt to happen and will not call HAL_RTCEx_WakeUpTimerEventCallback.
To sove this situation, we will not use HAL_RTCEx_WakeUpTimerEventCallback
weak definition but rather call handler whenever an RTC interrupt fires.
Change implementation of timeout to one that is using us_ticker hal.
Timeout is now configurable by I2C_TIMEOUT_VALUE_US macro and this
value will be imported if will be defined externaly.
- Added curly brackets to single line conditions in gpio_qpi.c and gpio_irq_api.c;
- Changed rx and tx buffers in serial module as local variables;
- Minor i2c & spi updates for github pull request;
- Added function definition for spi_master_block_write.
- Added a configuration call in trng_init to make sure the TRNG buffering mode is disabled, so only 8-bit bytes are returned;
- Moved the TRNG device handle into the trng_t structure;
- Fixed some formatting errors in the adc driver.
Fix ARMC6 guard typo introduced in commit 4f3f0cc9cc (Make Realtek link)
While at it, remove redundant ISR_STACK_SIZE assignment for ARMCC.
Signed-off-by: Tony Wu <tonywu@realtek.com>
Target of LPC1769 links to mbed LPC1768.
The PinNames.h has conditional compile for the pin names.
LWIP lpc17xx emac driver modified to allow LPC1769 target
Fixes#5115.
`analogin_read_u16` returns a value in the range `0x0000 - 0xFFF0`
since the resolution of the ADC is 12 bits. However, in
`analogin_read` this value gets divided by `0xFFFF` assuming the range
is `0x0000-0xFFFF`. This causes a small error in the value returned by
`AnalogIn::read` for the EFM32 target.
The allocation of GPIOTE channels for DigitalIn is unwanted behavior.
This caused early run-out of channels for InterruptPin.
This patch replacing input configuration that is using gpiote driver by configuration that is
using gpio hal.
Previous the voltage range was set to 1.2 from SoC internal reference source.
This caused problem with testing. It is unexpected that range is much
shorter than vdd as well.
The voltage range was extended using SoC build in analog prescaler (set to 1/3).
From RM:
32.3.2.6 Interrupts during IAP
The on-chip flash memory is not accessible during erase/write operations. When the user
application code starts executing the interrupt vectors from the user flash area are active.
The user should either disable interrupts, or ensure that user interrupt vectors are active in
RAM and that the interrupt handlers reside in RAM, before making a flash erase/write IAP
call. The IAP code does not use or disable interrupts.
The use of mktime was causing a fault when called in interrupt handler because on GCC it lock the mutex protecting the environment, To overcome this issue, this patch add dedicated routine to convert a time_t into a tm and vice versa.
In the process mktime has been optimized and is now an order of magnitude faster than the routines present in the C library.
commit f7bc126 (Re-work Rtl8195AM ticker) tried to address ticker drifting
issue, but in fact broke ticker functionality. This patch adjusts us_ticker
porting to unbreak it, and to fix the following tests:
mbed-os-tests-mbed_drivers-ticker
mbed-os-tests-mbed_drivers-timeout
mbed-os-tests-mbedmicro-rtos-mbed-isr
mbed-os-features-frameworks-utest-tests-unit_tests-minimal_async_scheduler
mbed-os-features-frameworks-utest-tests-unit_tests-case_control_async
mbed-os-features-frameworks-utest-tests-unit_tests-case_async_validate
Changes are:
1. Dont disable timer after every us_ticker interrupt. That basically
breaks ticker functionality.
2. Fine-tune us to tick conversion macro. Previous conversion method
yields 1 tick drift every 2 ms.
3. Remove special placement of ticker objects. No longer necessary.
Signed-off-by: Tony Wu <tonywu@realtek.com>
As reported by MBED user Fran6Jack:
I2C bus are usually 5V tolerant on all STM32 processor.
If an external device on the I2C bus requires 5V operation,
we usually acheive it by using 5V external pull-ups on the bus.
Since signaling uses open-drain output on I2C for both signal SCL and SDA
any 5V tolerant MCU will work on a 5V I2C bus. Having pull-up activated on a 5V externally pull bus, cause the pin to clamp on the STM32 die diode and could damage the IC (There is a note in STM32 datasheet specifying this issue).
It is understood by all the community that I2C bus should always be
externally pulled by physical resistor. I2C initialization should then
be ALWAYS OpenDrainNoPull by default.
Up to now, this I2C driver was setting pull up by default as it helps
basic testing, like 1 master and 1 slave, conencted with 2 wires without
any external pull ups. This will not work anymore after this commit and
applications tests or examples needs to be modified to explicitely
configure pull ups ... But it is safer to follow reference manual
guidelines.
When the RTOS is present and the tickless mode is not implemented, it is
expected that the next tick issued by the Systick timer will wake up the MCU.
However nothing prevents an implementation of the ARM architecture to gate the
systick clock signal upon sleep entry.
Therefore on those targets sleep shall be prohibited if the RTOS is present and the
tickless mode is not implemented.
To ease life of porters , a new option has been added in the device add list:
STCLK_OF_DURING_SLEEP. This option expose that the target turn of the systick
clock during sleep.
Targets which exhibit such behavior shall add this define in their device_has list.
There was some interesting stuff here.
* ARMC6 treats assembly the same as GNU, but has a different startup
function, so we branch the asm there
* Incorrect discriminant, probably copied from other ports
Add NOPs after deep sleep to prevent unexpected behavior. It appears
that the first one or two instructions after deep sleep do not get
executed properly.
Note - This is a temporary workaround. For a more robust solution
the NCS36510 needs to investigate the root cause of this issue.
The NCS36510 is not suitable for tickless, since its LP ticker cannot
be scheduled fast enough. This is because it takes four 32KHz clock
cycles before these writes take effect - ~120us.
Decrease the interrupt stack from 2k down to 1k so there is enough
ram to build all the tests with tickless enabled. In general, targets
should not need an interrupt stack greater than 1k with mbed-os.
Some Cortex-M0 devices, such as the nrf51, don't have the SysTick.
Instead, these targets use a software interrupt to simulate SysTick.
Add the hooks in the tickless code to support these devices. Targets
which do not have SysTick should now define NO_SYSTICK in targets.json
and implement mbed_get_m0_tick_irqn to add os suport.
This patch also removes os tick handling from the existing devices
(nrf51) since this is now handled in common code.
IAR 8.x compiler throws error for emac_interface_t constructor
rtw_emac.cpp@220,0: [Pe1790]: the default constructor of "emac_interface"
cannot be referenced -- it is a deleted function
Error is because new object is created of structure with constant member.
Resolved it by using malloc instead new.
Rather than Unlocking flash during flash object creation, and leaving
the flash possibly continuously unlocked a(s object might bever be freed),
we decide to Unlock then Lock again at each erase or program call.
Fixing regression introduced in commit
"Ticker: add fire interrupt now function".
In above mentioned commit, the management of timestamp being in the past
has been moved to higher layer (hal/mbed_ticker_api.c), but the reset of
oc_int was missing when implementing the new us_ticker_fire_interrupt
function - which is fixed now.
After reset the MCR register content needs to be restored so we're
introducing the can_registers_init function to be called at the first
init stage, but also after reset. We also store the can frequency to
go through the initialisation phase again.
In order to apply the same mode in case of reset, we store the current
requested mode in the HAL structure.
To make storage in a single place, we also change can_monitor to call
can_mode function as they actually acting on same registers.
Instead of a static object, this will make driver
instantiation more robust and allow to re-use init
configuration on a need basis.
The CANName struct member is actually the CAN registers base address,
which is now available in the CanHandle.Instance field, so we don't need
CANName anymore.
Bilal
bcostm
Adam Heinrich
Edmund Hsu
jeromecoutant
Przemyslaw Stekiel
Prashant Ravi
Steven Cooreman
Martin Kojtal
Boting Ren
Alessandro Angelino
andreas.larsson
Janne Kiiskilä
Mathieu Garivet
Mahadevan Mahesh
Tony Wu
Andrzej Puzdrowski
Helmut Tschemernjak
Veijo Pesonen
Laurent MEUNIER
Jimmy Brisson
ccli8
sarahmarshy
Michael Kaplan
gorazd
Marko Fabo
Dave Wu
cyliangtw
Steven Cooreman
Bartek Szatkowski
Bartosz Szatkowski
Marcus Chang
Ashok Rao
Yuguo Zou
danclement
Jammu Kekkonen
johnny
Andrea Corrado
Kevin Gilbert
Anna Bridge
amq
misodengaku
Piotr Grygorczuk
iotvietmember
maclobdell
Pavel Sorejs
Roberto Spelta
Pierre-Marie Ancele
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Nabil Elqatib
Chris Snow
Seppe Stas
Vincent Coubard
Russ Butler
mbedNoobNinja
Deepika
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