mirror of https://github.com/ARMmbed/mbed-os.git
NUCLEO_L496ZG minor update
parent
6912a9dc0d
commit
dde615b8a8
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@ -258,8 +258,8 @@ const PinMap PinMap_UART_TX[] = {
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{PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
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{PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
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{PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO D1
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{PG_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
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{PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX
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{PG_7, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX
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{PG_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
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{NC, NC, 0}
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};
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@ -266,6 +266,15 @@ typedef enum {
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SPI_CS = D10,
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PWM_OUT = D9,
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USB_OTG_FS_SOF = PA_8,
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USB_OTG_FS_VBUS = PA_9,
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USB_OTG_FS_ID = PA_10,
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USB_OTG_FS_DM = PA_11,
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USB_OTG_FS_DP = PA_12,
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USB_OTG_FS_NOE_ALT = PA_13,
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USB_OTG_FS_SOF_ALT = PA_14,
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USB_OTG_FS_NOE = PC_9,
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// Not connected
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NC = (int)0xFFFFFFFF
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} PinName;
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@ -190,10 +190,10 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
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return 0; // FAIL
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}
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@ -217,6 +217,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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/* Select HSI as clock source for LPUART1 */
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RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
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RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
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if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
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return 0; // FAIL
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}
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// Output clock on MCO1 pin(PA8) for debugging purpose
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#if DEBUG_MCO == 2
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if (bypass == 0)
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@ -289,6 +296,13 @@ uint8_t SetSysClock_PLL_HSI(void)
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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/* Select HSI as clock source for LPUART1 */
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RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
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RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
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if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
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return 0; // FAIL
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}
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// Output clock on MCO1 pin(PA8) for debugging purpose
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#if DEBUG_MCO == 3
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HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
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@ -322,7 +336,6 @@ uint8_t SetSysClock_PLL_MSI(void)
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
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RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
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RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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@ -342,11 +355,6 @@ uint8_t SetSysClock_PLL_MSI(void)
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
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/* Select LSE as clock source for LPUART1 */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
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PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
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// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
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@ -357,6 +365,13 @@ uint8_t SetSysClock_PLL_MSI(void)
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return 0; // FAIL
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}
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/* Select LSE as clock source for LPUART1 */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
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PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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// Output clock on MCO1 pin(PA8) for debugging purpose
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#if DEBUG_MCO == 4
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HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
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