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NUCLEO_L496ZG Use correct linker script for IAR

pull/4650/head
Pierre-Marie Ancele 2017-07-04 09:43:57 +02:00
parent 2290847876
commit 7c6c710ee1
2 changed files with 37 additions and 68 deletions
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37
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/stm32l496xx.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x2003FFFF;
define symbol __ICFEDIT_region_SRAM2_start__ = 0x10000000;
define symbol __ICFEDIT_region_SRAM2_end__ = 0x1000FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region SRAM2_region = mem:[from __ICFEDIT_region_SRAM2_start__ to __ICFEDIT_region_SRAM2_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in SRAM2_region { };

68
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/TOOLCHAIN_IAR/stm32l496xx_flash.icf
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@ -1,68 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
define symbol __ICFEDIT_region_ROM_TARA_start__ = 0x08080000; /* TARA Lite Demo */
define symbol __ICFEDIT_region_ROM_TARA_end__ = 0x080BFFFF;
define symbol __ICFEDIT_region_ROM_TGFX_start__ = 0x080C0000; /* TGFX Lite Demo */
define symbol __ICFEDIT_region_ROM_TGFX_end__ = 0x080FE7FF;
define symbol __ICFEDIT_region_ROM_While1_start__ = 0x080FE800;
define symbol __ICFEDIT_region_ROM_While1_end__ = 0x080FFDFF;
define symbol __ICFEDIT_calibration_data_start__ = 0x080FFE00;
define symbol __ICFEDIT_calibration_data_end__ = 0x080FFFFF;
/*-Quad-SPI Memory Regions-*/
define symbol __ICFEDIT_region_QSPI_start__ = 0x90000000;
define symbol __ICFEDIT_region_QSPI_end__ = 0x9013FFFF; /* 1.3 Mbytes for STemWin */
define symbol __ICFEDIT_region_QSPI_TARA_start__ = 0x90140000;
define symbol __ICFEDIT_region_QSPI_TARA_end__ = 0x90499FFF; /* 3.4 Mbytes for third parties demo */
define symbol __ICFEDIT_region_QSPI_TGFX_start__ = 0x9049A000;
define symbol __ICFEDIT_region_QSPI_TGFX_end__ = 0x907FFFFF; /* 3.3 Mbytes for third parties demo */
define symbol __ICFEDIT_region_SRAM1_start__ = 0x20000000;
define symbol __ICFEDIT_region_SRAM1_end__ = 0x2003FFFF;
define symbol __ICFEDIT_region_SRAM2_start__ = 0x10000000;
define symbol __ICFEDIT_region_SRAM2_end__ = 0x1000FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region ROM_TARA_region = mem:[from __ICFEDIT_region_ROM_TARA_start__ to __ICFEDIT_region_ROM_TARA_end__];
define region ROM_TGFX_region = mem:[from __ICFEDIT_region_ROM_TGFX_start__ to __ICFEDIT_region_ROM_TGFX_end__];
define region ROM_While1_region = mem:[from __ICFEDIT_region_ROM_While1_start__ to __ICFEDIT_region_ROM_While1_end__];
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
define region QSPI_TARA_region = mem:[from __ICFEDIT_region_QSPI_TARA_start__ to __ICFEDIT_region_QSPI_TARA_end__];
define region QSPI_TGFX_region = mem:[from __ICFEDIT_region_QSPI_TGFX_start__ to __ICFEDIT_region_QSPI_TGFX_end__];
define region SRAM1_region = mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__];
define region SRAM2_region = mem:[from __ICFEDIT_region_SRAM2_start__ to __ICFEDIT_region_SRAM2_end__];
define region calibration_region = mem:[from __ICFEDIT_calibration_data_start__ to __ICFEDIT_calibration_data_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in ROM_TARA_region { section TARAFlashSection };
place in ROM_TGFX_region { section TGFXFlashSection };
place in ROM_While1_region { section While1Section };
place in QSPI_region { section ExtQSPIFlashSection, section .qspi };
place in QSPI_TARA_region { section TARAResSection };
place in QSPI_TGFX_region { section TGFXResSection };
place in SRAM1_region { readwrite,
block CSTACK, block HEAP };
place in SRAM2_region { };
place in calibration_region {readwrite section .calibration_data };