mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #5260 from tung7970/fix-iar
RTL8195AM - Fix IAR ielftool zero-padding issuepull/5180/merge
Jimmy Brisson
GitHub
commit
d2b762092c
Binary file not shown.
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@ -1,323 +1,213 @@
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/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
//define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||
|
||||
//include "main.icf";
|
||||
/*
|
||||
* Copyright (c) 2013-2017 Realtek Semiconductor Corp.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x000FFFFF;
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||||
define symbol __ICFEDIT_region_TCM_start__ = 0x1FFF0000;
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||||
define symbol __ICFEDIT_region_TCM_end__ = 0x1FFFFFFF;
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||||
define symbol __ICFEDIT_region_ROM_USED_RAM_start__ = 0x10000000;
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define symbol __ICFEDIT_region_ROM_USED_RAM_end__ = 0x10005FFF;
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||||
//define symbol __ICFEDIT_region_RECY_RAM_start__ = 0x10002090;
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||||
//define symbol __ICFEDIT_region_RECY_RAM_end__ = 0x100037FF;
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if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_start__ ) ) {
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define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10007000;
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}
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||||
if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_end__ ) ) {
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define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1006FFFF;
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||||
}
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define symbol __ICFEDIT_region_SDRAM_RAM_start__ = 0x30000000;
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||||
define symbol __ICFEDIT_region_SDRAM_RAM_end__ = 0x301FFFFF;
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|
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = 0x1000;
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define symbol __ICFEDIT_size_heap__ = 0x19000;
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/**** End of ICF editor section. ###ICF###*/
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define symbol __SRAM_start__ = 0x10007000;
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define symbol __SRAM_end__ = 0x1006FFFF;
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define symbol __DTCM_start__ = 0x1FFF0000;
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define symbol __DTCM_end__ = 0x1FFFFFFF;
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define symbol __DRAM_start__ = 0x30000000;
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define symbol __DRAM_end__ = 0x301FFFFF;
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
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define region ROM_USED_RAM_region = mem:[from __ICFEDIT_region_ROM_USED_RAM_start__ to __ICFEDIT_region_ROM_USED_RAM_end__];
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//define region RECY_RAM_region = mem:[from __ICFEDIT_region_RECY_RAM_start__ to __ICFEDIT_region_RECY_RAM_end__];
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define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__];
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define region SDRAM_RAM_region = mem:[from __ICFEDIT_region_SDRAM_RAM_start__ to __ICFEDIT_region_SDRAM_RAM_end__];
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define region TCM_region = mem:[from __DTCM_start__ to __DTCM_end__];
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define region RAM_region = mem:[from __SRAM_start__ to __SRAM_end__] |
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mem:[from __DRAM_start__ to __DRAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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define block CSTACK with alignment = 8, size = 0x1000 { };
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define block HEAP with alignment = 8, size = 0x19000 { };
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//initialize by copy { readwrite };
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//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application
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do not initialize { section .noinit };
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//do not initialize { section * };
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/**
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IMAGE2
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**/
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keep {
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section .image2.ram.data*,
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section .image2.validate.rodata*,
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};
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//place at address mem:__ICFEDIT_intvec_start__ { readonly section .vectors_table };
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define block .image2.table with fixed order {
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section .image2.ram.data*,
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section .image2.validate.rodata*,
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};
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||||
|
||||
define block FPB_REMAP with alignment = 256, fixed order {
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section .fpb.remap*
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};
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/*place in RAM_region { readwrite, block CSTACK, block HEAP };*/
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//place in TCM_region { readwrite };
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||||
define block .text.mbedtls {
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readonly object aes.o,
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readonly object aesni.o,
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readonly object arc4.o,
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readonly object asn1parse.o,
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readonly object asn1write.o,
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readonly object base64.o,
|
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readonly object bignum.o,
|
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readonly object blowfish.o,
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readonly object camellia.o,
|
||||
readonly object ccm.o,
|
||||
readonly object certs.o,
|
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readonly object cipher.o,
|
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readonly object cipher_wrap.o,
|
||||
readonly object cmac.o,
|
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readonly object ctr_drbg.o,
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readonly object debug.o,
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readonly object des.o,
|
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readonly object dhm.o,
|
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readonly object ecdh.o,
|
||||
readonly object ecdsa.o,
|
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readonly object ecjpake.o,
|
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readonly object ecp.o,
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||||
readonly object ecp_curves.o,
|
||||
readonly object entropy.o,
|
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readonly object entropy_poll.o,
|
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readonly object error.o,
|
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readonly object gcm.o,
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readonly object havege.o,
|
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readonly object hmac_drbg.o,
|
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readonly object md.o,
|
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readonly object md2.o,
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readonly object md4.o,
|
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readonly object md5.o,
|
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readonly object md_wrap.o,
|
||||
readonly object memory_buffer_alloc.o,
|
||||
readonly object net_sockets.o,
|
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readonly object oid.o,
|
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readonly object padlock.o,
|
||||
readonly object pem.o,
|
||||
readonly object pk.o,
|
||||
readonly object pk_wrap.o,
|
||||
readonly object pkcs11.o,
|
||||
readonly object pkcs12.o,
|
||||
readonly object pkcs5.o,
|
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readonly object pkparse.o,
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||||
readonly object pkwrite.o,
|
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readonly object platform.o,
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readonly object ripemd160.o,
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readonly object rsa.o,
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readonly object sha1.o,
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readonly object sha256.o,
|
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readonly object sha512.o,
|
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readonly object ssl_cache.o,
|
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readonly object ssl_ciphersuites.o,
|
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readonly object ssl_cli.o,
|
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readonly object ssl_cookie.o,
|
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readonly object ssl_srv.o,
|
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readonly object ssl_ticket.o,
|
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readonly object ssl_tls.o,
|
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readonly object threading.o,
|
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readonly object timing.o,
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readonly object version.o,
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readonly object version_features.o,
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readonly object x509.o,
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readonly object x509_create.o,
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readonly object x509_crl.o,
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readonly object x509_crt.o,
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readonly object x509_csr.o,
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readonly object x509write_crt.o,
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readonly object x509write_csr.o,
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readonly object xtea.o,
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};
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/****************************************
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* ROM Section config *
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****************************************/
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keep { section .rom };
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place at start of ROM_region { section .rom };
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define block .text.sram {
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readonly object rtl8195a_crypto.o,
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readonly object vector_table_M.o,
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readonly object lib_peripheral_mbed_iar.a,
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section .text.sram*,
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};
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/****************************************
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* BD RAM Section config *
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****************************************/
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keep { section .ram_dedecated_vector_table* };
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define block .vector_table with fixed order{section .ram_dedecated_vector_table*};
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define block .text.dram {
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section .text.dram*,
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section .text*,
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section .rodata*,
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section .sdram.text*,
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section .mdns.text*,
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section CODE,
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};
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keep { section .ram_user_define_irq_table* };
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define block .user_vector_table with fixed order{section .ram_user_define_irq_table*};
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define block .data.sram {
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readwrite object rtl8195a_crypto.o,
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readwrite object vector_table_M.o,
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readwrite object lib_peripheral_mbed_iar.a,
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section .data.os.*,
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section .data.sram*,
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section .wlan.data,
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section .wps.data,
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section .ram.otg.data.a,
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section .bfsram.data*,
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};
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keep { section .ram_user_define_data_table* };
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define block .user_data_table with fixed order{section .ram_user_define_data_table*};
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define block .data.dram {
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section .data*,
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section .data.dram*,
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section .sdram.data*,
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section .mdns.data*,
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section .iar.init_table,
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section .iar.dynexit*,
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section DATA,
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section __DLIB_PERTHREAD,
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};
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define block .rom.bss with fixed order{ section .hal.ram.bss* object hal_misc.o,
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section .hal.ram.bss* object hal_pinmux.o,
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section .hal.ram.bss* object diag.o,
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section .hal.ram.bss* object rtl8195a_ssi_rom.o,
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section .hal.ram.bss* object rtl8195a_gpio.o,
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section .hal.ram.bss*,
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section .timer2_7_vector_table.data*,
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section .infra.ram.bss*,
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section .mon.ram.bss*,
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section .wlan_ram_map* object rom_wlan_ram_map.o,
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section .wlan_ram_map*,
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section .libc.ram.bss*,
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};
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define block .data.dtcm {
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section .data.dtcm*,
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};
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keep { section .start.ram.data* };
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define block .ram.start.table with fixed order{ section .start.ram.data* };
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define block .bss.sram {
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zeroinit object rtl8195a_crypto.o,
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section .bss.os.*,
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section .bss.sram*,
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section .bdsram.data*,
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};
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keep { section .image1.validate.rodata* };
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keep { section .infra.ram.data* };
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keep { section .timer.ram.data* };
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keep { section .hal.ram.data* };
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define block .ram_image1.data with fixed order{ section .image1.validate.rodata*,
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section .infra.ram.data*,
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section .timer.ram.data*,
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section .cutb.ram.data*,
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section .hal.ram.data* object rom.o, // for standard libaray __impure_data_ptr
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section .cutc.ram.data*,
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section .hal.ram.data*
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||||
};
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define block .ram_image1.bss with fixed order{ //section .hal.flash.data*,
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section .hal.sdrc.data*
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};
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||||
define block .bss.dram {
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||||
zeroinit,
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section .sdram.bss*,
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||||
};
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||||
|
||||
define block .ram_image1.text with fixed order{ section .hal.ram.text*,
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||||
section .hal.sdrc.text*,
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||||
//section .text* object startup.o,
|
||||
section .infra.ram.text*,
|
||||
};
|
||||
define block .bss.dtcm {
|
||||
zeroinit object lwip_mem.o,
|
||||
zeroinit object lwip_memp.o,
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||||
section .bss.dtcm*,
|
||||
};
|
||||
|
||||
define block IMAGE1 with fixed order { section LOADER };
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||||
define block IMAGE1_DBG with fixed order { block .ram.start.table, block .ram_image1.data, block .ram_image1.bss, block .ram_image1.text };
|
||||
place in TCM_region {
|
||||
section .tcm.heap,
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||||
block .data.dtcm,
|
||||
block .bss.dtcm,
|
||||
};
|
||||
|
||||
place at start of ROM_USED_RAM_region {
|
||||
block .vector_table,
|
||||
block .user_vector_table,
|
||||
block .user_data_table,
|
||||
block .rom.bss,
|
||||
block IMAGE1
|
||||
};
|
||||
place in RAM_region {
|
||||
readonly,
|
||||
block .text.sram,
|
||||
block .text.mbedtls,
|
||||
readwrite,
|
||||
block .data.sram,
|
||||
block .bss.sram,
|
||||
block HEAP,
|
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block CSTACK,
|
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readonly,
|
||||
block .image2.table,
|
||||
block .text.dram,
|
||||
readwrite,
|
||||
block .data.dram,
|
||||
block .bss.dram,
|
||||
block FPB_REMAP,
|
||||
};
|
||||
|
||||
|
||||
keep { section .image2.ram.data* };
|
||||
define block .image2.start.table1 with fixed order{ section .image2.ram.data* };
|
||||
|
||||
keep { section .image2.validate.rodata*, section .custom.validate.rodata* };
|
||||
define block .image2.start.table2 with fixed order{ section .image2.validate.rodata*, section .custom.validate.rodata* };
|
||||
|
||||
define block SHT$$PREINIT_ARRAY { preinit_array };
|
||||
define block SHT$$INIT_ARRAY { init_array };
|
||||
define block CPP_INIT with alignment = 8, fixed order {
|
||||
block SHT$$PREINIT_ARRAY,
|
||||
block SHT$$INIT_ARRAY
|
||||
};
|
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define block FPB_REMAP with alignment = 256,fixed order {
|
||||
section .fpb.remap*
|
||||
};
|
||||
|
||||
define block MBEDTLS_TEXT with alignment = 8, fixed order{
|
||||
section .text* object aes.o,
|
||||
section .text* object aesni.o,
|
||||
section .text* object arc4.o,
|
||||
section .text* object asn1parse.o,
|
||||
section .text* object asn1write.o,
|
||||
section .text* object base64.o,
|
||||
section .text* object bignum.o,
|
||||
section .text* object blowfish.o,
|
||||
section .text* object camellia.o,
|
||||
section .text* object ccm.o,
|
||||
section .text* object certs.o,
|
||||
section .text* object cipher.o,
|
||||
section .text* object cipher_wrap.o,
|
||||
section .text* object cmac.o,
|
||||
section .text* object ctr_drbg.o,
|
||||
section .text* object debug.o,
|
||||
section .text* object des.o,
|
||||
section .text* object dhm.o,
|
||||
section .text* object ecdh.o,
|
||||
section .text* object ecdsa.o,
|
||||
section .text* object ecjpake.o,
|
||||
section .text* object ecp.o,
|
||||
section .text* object ecp_curves.o,
|
||||
section .text* object entropy.o,
|
||||
section .text* object entropy_poll.o,
|
||||
section .text* object error.o,
|
||||
section .text* object gcm.o,
|
||||
section .text* object havege.o,
|
||||
section .text* object hmac_drbg.o,
|
||||
section .text* object md.o,
|
||||
section .text* object md2.o,
|
||||
section .text* object md4.o,
|
||||
section .text* object md5.o,
|
||||
section .text* object md_wrap.o,
|
||||
section .text* object memory_buffer_alloc.o,
|
||||
section .text* object net_sockets.o,
|
||||
section .text* object oid.o,
|
||||
section .text* object padlock.o,
|
||||
section .text* object pem.o,
|
||||
section .text* object pk.o,
|
||||
section .text* object pk_wrap.o,
|
||||
section .text* object pkcs11.o,
|
||||
section .text* object pkcs12.o,
|
||||
section .text* object pkcs5.o,
|
||||
section .text* object pkparse.o,
|
||||
section .text* object pkwrite.o,
|
||||
section .text* object platform.o,
|
||||
section .text* object ripemd160.o,
|
||||
section .text* object rsa.o,
|
||||
section .text* object sha1.o,
|
||||
section .text* object sha256.o,
|
||||
section .text* object sha512.o,
|
||||
section .text* object ssl_cache.o,
|
||||
section .text* object ssl_ciphersuites.o,
|
||||
section .text* object ssl_cli.o,
|
||||
section .text* object ssl_cookie.o,
|
||||
section .text* object ssl_srv.o,
|
||||
section .text* object ssl_ticket.o,
|
||||
section .text* object ssl_tls.o,
|
||||
section .text* object threading.o,
|
||||
section .text* object timing.o,
|
||||
section .text* object version.o,
|
||||
section .text* object version_features.o,
|
||||
section .text* object x509.o,
|
||||
section .text* object x509_create.o,
|
||||
section .text* object x509_crl.o,
|
||||
section .text* object x509_crt.o,
|
||||
section .text* object x509_csr.o,
|
||||
section .text* object x509write_crt.o,
|
||||
section .text* object x509write_csr.o,
|
||||
section .text* object xtea.o,
|
||||
};
|
||||
|
||||
define block .sram1.text with fixed order {
|
||||
block MBEDTLS_TEXT,
|
||||
section .text* object lib_peripheral_mbed_iar.a,
|
||||
};
|
||||
|
||||
define block .sram2.text with fixed order {
|
||||
block .image2.start.table1,
|
||||
block .image2.start.table2,
|
||||
section .mon.ram.text*,
|
||||
section .hal.flash.text*,
|
||||
section .hal.sdrc.text*,
|
||||
section .hal.gpio.text*,
|
||||
section .text*,
|
||||
section .infra.ram.start*,
|
||||
section .rodata*,
|
||||
};
|
||||
|
||||
define block .sram2.data with fixed order {
|
||||
//section .infra.ram.start*,
|
||||
//section .rodata*,
|
||||
//section .wlan.text,
|
||||
//section .wps.text,
|
||||
section CODE,
|
||||
//section .otg.rom.text,
|
||||
section Veneer object startup.o,
|
||||
section __DLIB_PERTHREAD,
|
||||
section .iar.dynexit*,
|
||||
block CPP_INIT,
|
||||
//section .mdns.text
|
||||
};
|
||||
define block .ram.data with fixed order {
|
||||
readwrite, readonly,
|
||||
section .data*,
|
||||
section .wlan.data,
|
||||
section .wps.data,
|
||||
section DATA,
|
||||
section .ram.otg.data.a,
|
||||
section .iar.init_table,
|
||||
//section .mdns.data,
|
||||
//section .data* object lib_peripheral_mbed_iar.a,
|
||||
};
|
||||
|
||||
define block .ram.bss with fixed order {
|
||||
section .bss*,
|
||||
section COMMON,
|
||||
section .bdsram.data*,
|
||||
};
|
||||
|
||||
define block IMAGE2 with fixed order {
|
||||
block .sram1.text,
|
||||
block .ram.data,
|
||||
block .ram.bss
|
||||
};
|
||||
|
||||
define block .bf_data with fixed order{ section .bfsram.data* };
|
||||
define block .heap with fixed order{ section .heap* };
|
||||
define block .stack_dummy with fixed order { section .stack };
|
||||
place at start of BD_RAM_region {
|
||||
block IMAGE2,
|
||||
//block IMAGE1_DBG,
|
||||
//block .ram.bss,
|
||||
//block .bf_data,
|
||||
};
|
||||
|
||||
place at end of BD_RAM_region {
|
||||
block .bf_data,
|
||||
block HEAP,
|
||||
};
|
||||
|
||||
define block SDRAM with fixed order {
|
||||
block .sram2.text,
|
||||
block .sram2.data,
|
||||
section .sdram.text*,
|
||||
section .sdram.data*,
|
||||
section .mdns.text*,
|
||||
section .mdns.data*,
|
||||
block FPB_REMAP
|
||||
};
|
||||
define block SDRBSS with fixed order{
|
||||
section .sdram.bss*
|
||||
};
|
||||
|
||||
place at start of SDRAM_RAM_region {
|
||||
block SDRAM,
|
||||
block SDRBSS,
|
||||
//block IMAGE1_DBG
|
||||
};
|
||||
|
||||
|
||||
/* TCM placement */
|
||||
define overlay TCM_overlay {
|
||||
section .tcm.heap,
|
||||
section .bss object lwip_mem.o,
|
||||
section .bss object lwip_memp.o,
|
||||
block .heap,
|
||||
block .stack_dummy
|
||||
};
|
||||
/* dummy code placement */
|
||||
define overlay TCM_overlay { block IMAGE1_DBG };
|
||||
place at start of TCM_region { overlay TCM_overlay };
|
||||
place at end of TCM_region { block CSTACK};
|
||||
|
||||
define exported symbol __rom_bss_start__ = 0x10000300; // use in rom
|
||||
define exported symbol __rom_bss_end__ = 0x10000bc8; // use in rom
|
||||
define exported symbol __ram_start_table_start__= 0x10000bc8; // use in rom
|
||||
define exported symbol __image1_validate_code__= 0x10000bdc; // needed by ram code
|
||||
define exported symbol _rtl_impure_ptr = 0x10001c60; // for standard library
|
||||
|
||||
define exported symbol __sdio_rom_bss_start__ = 0x1006D000;
|
||||
define exported symbol __sdio_rom_bss_end__ = 0x1006fa10;
|
||||
include "rtl8195a_rom.h";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,740 @@
|
|||
define exported symbol __vectors_table = 0x00000000;
|
||||
define exported symbol Reset_Handler = 0x00000101;
|
||||
define exported symbol NMI_Handler = 0x00000109;
|
||||
define exported symbol HardFault_Handler = 0x0000010d;
|
||||
define exported symbol MemManage_Handler = 0x00000121;
|
||||
define exported symbol BusFault_Handler = 0x00000125;
|
||||
define exported symbol UsageFault_Handler = 0x00000129;
|
||||
define exported symbol HalLogUartInit = 0x00000201;
|
||||
define exported symbol HalSerialPutcRtl8195a = 0x000002d9;
|
||||
define exported symbol HalSerialGetcRtl8195a = 0x00000309;
|
||||
define exported symbol HalSerialGetIsrEnRegRtl8195a = 0x00000329;
|
||||
define exported symbol HalSerialSetIrqEnRegRtl8195a = 0x00000335;
|
||||
define exported symbol HalCpuClkConfig = 0x00000341;
|
||||
define exported symbol HalGetCpuClk = 0x00000355;
|
||||
define exported symbol HalRomInfo = 0x0000039d;
|
||||
define exported symbol HalGetRomInfo = 0x000003b5;
|
||||
define exported symbol HalResetVsr = 0x000003c5;
|
||||
define exported symbol HalDelayUs = 0x00000899;
|
||||
define exported symbol HalNMIHandler = 0x000008e1;
|
||||
define exported symbol HalHardFaultHandler = 0x00000911;
|
||||
define exported symbol HalMemManageHandler = 0x00000c09;
|
||||
define exported symbol HalBusFaultHandler = 0x00000c39;
|
||||
define exported symbol HalUsageFaultHandler = 0x00000c69;
|
||||
define exported symbol HalUart0PinCtrlRtl8195A = 0x00000cfd;
|
||||
define exported symbol HalUart1PinCtrlRtl8195A = 0x00000dc9;
|
||||
define exported symbol HalUart2PinCtrlRtl8195A = 0x00000e9d;
|
||||
define exported symbol HalSPI0PinCtrlRtl8195A = 0x00000f75;
|
||||
define exported symbol HalSPI1PinCtrlRtl8195A = 0x00001015;
|
||||
define exported symbol HalSPI2PinCtrlRtl8195A = 0x000010e5;
|
||||
define exported symbol HalSPI0MCSPinCtrlRtl8195A = 0x000011b5;
|
||||
define exported symbol HalI2C0PinCtrlRtl8195A = 0x00001275;
|
||||
define exported symbol HalI2C1PinCtrlRtl8195A = 0x00001381;
|
||||
define exported symbol HalI2C2PinCtrlRtl8195A = 0x00001459;
|
||||
define exported symbol HalI2C3PinCtrlRtl8195A = 0x00001529;
|
||||
define exported symbol HalI2S0PinCtrlRtl8195A = 0x00001639;
|
||||
define exported symbol HalI2S1PinCtrlRtl8195A = 0x0000176d;
|
||||
define exported symbol HalPCM0PinCtrlRtl8195A = 0x00001845;
|
||||
define exported symbol HalPCM1PinCtrlRtl8195A = 0x00001949;
|
||||
define exported symbol HalSDIODPinCtrlRtl8195A = 0x00001a1d;
|
||||
define exported symbol HalSDIOHPinCtrlRtl8195A = 0x00001a6d;
|
||||
define exported symbol HalMIIPinCtrlRtl8195A = 0x00001ab9;
|
||||
define exported symbol HalWLLEDPinCtrlRtl8195A = 0x00001b51;
|
||||
define exported symbol HalWLANT0PinCtrlRtl8195A = 0x00001c0d;
|
||||
define exported symbol HalWLANT1PinCtrlRtl8195A = 0x00001c61;
|
||||
define exported symbol HalWLBTCOEXPinCtrlRtl8195A = 0x00001cb5;
|
||||
define exported symbol HalWLBTCMDPinCtrlRtl8195A = 0x00001d05;
|
||||
define exported symbol HalNFCPinCtrlRtl8195A = 0x00001d59;
|
||||
define exported symbol HalPWM0PinCtrlRtl8195A = 0x00001da9;
|
||||
define exported symbol HalPWM1PinCtrlRtl8195A = 0x00001ead;
|
||||
define exported symbol HalPWM2PinCtrlRtl8195A = 0x00001fb5;
|
||||
define exported symbol HalPWM3PinCtrlRtl8195A = 0x000020b1;
|
||||
define exported symbol HalETE0PinCtrlRtl8195A = 0x000021b9;
|
||||
define exported symbol HalETE1PinCtrlRtl8195A = 0x000022c1;
|
||||
define exported symbol HalETE2PinCtrlRtl8195A = 0x000023c9;
|
||||
define exported symbol HalETE3PinCtrlRtl8195A = 0x000024d1;
|
||||
define exported symbol HalEGTIMPinCtrlRtl8195A = 0x000025d9;
|
||||
define exported symbol HalSPIFlashPinCtrlRtl8195A = 0x00002679;
|
||||
define exported symbol HalSDRPinCtrlRtl8195A = 0x00002725;
|
||||
define exported symbol HalJTAGPinCtrlRtl8195A = 0x0000280d;
|
||||
define exported symbol HalTRACEPinCtrlRtl8195A = 0x00002861;
|
||||
define exported symbol HalLOGUartPinCtrlRtl8195A = 0x000028b9;
|
||||
define exported symbol HalLOGUartIRPinCtrlRtl8195A = 0x0000291d;
|
||||
define exported symbol HalSICPinCtrlRtl8195A = 0x00002981;
|
||||
define exported symbol HalEEPROMPinCtrlRtl8195A = 0x000029d9;
|
||||
define exported symbol HalDEBUGPinCtrlRtl8195A = 0x00002a31;
|
||||
define exported symbol HalPinCtrlRtl8195A = 0x00002b39;
|
||||
define exported symbol SpicRxCmdRtl8195A = 0x00002e5d;
|
||||
define exported symbol SpicWaitBusyDoneRtl8195A = 0x00002ea5;
|
||||
define exported symbol SpicGetFlashStatusRtl8195A = 0x00002eb5;
|
||||
define exported symbol SpicWaitWipDoneRtl8195A = 0x00002f55;
|
||||
define exported symbol SpicTxCmdRtl8195A = 0x00002f6d;
|
||||
define exported symbol SpicSetFlashStatusRtl8195A = 0x00002fc1;
|
||||
define exported symbol SpicCmpDataForCalibrationRtl8195A = 0x00003049;
|
||||
define exported symbol SpicLoadInitParaFromClockRtl8195A = 0x00003081;
|
||||
define exported symbol SpicInitRtl8195A = 0x000030e5;
|
||||
define exported symbol SpicEraseFlashRtl8195A = 0x000031bd;
|
||||
define exported symbol SpiFlashApp = 0x00003279;
|
||||
define exported symbol HalPeripheralIntrHandle = 0x000033b5;
|
||||
define exported symbol HalSysOnIntrHandle = 0x00003439;
|
||||
define exported symbol HalWdgIntrHandle = 0x00003485;
|
||||
define exported symbol HalTimer0IntrHandle = 0x000034d5;
|
||||
define exported symbol HalTimer1IntrHandle = 0x00003525;
|
||||
define exported symbol HalI2C3IntrHandle = 0x00003575;
|
||||
define exported symbol HalTimer2To7IntrHandle = 0x000035c5;
|
||||
define exported symbol HalSpi0IntrHandle = 0x00003615;
|
||||
define exported symbol HalGpioIntrHandle = 0x00003665;
|
||||
define exported symbol HalUart0IntrHandle = 0x000036b5;
|
||||
define exported symbol HalSpiFlashIntrHandle = 0x00003705;
|
||||
define exported symbol HalUsbOtgIntrHandle = 0x00003755;
|
||||
define exported symbol HalSdioHostIntrHandle = 0x000037a5;
|
||||
define exported symbol HalI2s0OrPcm0IntrHandle = 0x000037f5;
|
||||
define exported symbol HalI2s1OrPcm1IntrHandle = 0x00003845;
|
||||
define exported symbol HalWlDmaIntrHandle = 0x00003895;
|
||||
define exported symbol HalWlProtocolIntrHandle = 0x000038e5;
|
||||
define exported symbol HalCryptoIntrHandle = 0x00003935;
|
||||
define exported symbol HalGmacIntrHandle = 0x00003985;
|
||||
define exported symbol HalGdma0Ch0IntrHandle = 0x000039d5;
|
||||
define exported symbol HalGdma0Ch1IntrHandle = 0x00003a25;
|
||||
define exported symbol HalGdma0Ch2IntrHandle = 0x00003a75;
|
||||
define exported symbol HalGdma0Ch3IntrHandle = 0x00003ac5;
|
||||
define exported symbol HalGdma0Ch4IntrHandle = 0x00003b15;
|
||||
define exported symbol HalGdma0Ch5IntrHandle = 0x00003b65;
|
||||
define exported symbol HalGdma1Ch0IntrHandle = 0x00003bb5;
|
||||
define exported symbol HalGdma1Ch1IntrHandle = 0x00003c05;
|
||||
define exported symbol HalGdma1Ch2IntrHandle = 0x00003c55;
|
||||
define exported symbol HalGdma1Ch3IntrHandle = 0x00003ca5;
|
||||
define exported symbol HalGdma1Ch4IntrHandle = 0x00003cf5;
|
||||
define exported symbol HalGdma1Ch5IntrHandle = 0x00003d45;
|
||||
define exported symbol HalSdioDeviceIntrHandle = 0x00003d95;
|
||||
define exported symbol VectorTableInitRtl8195A = 0x00003de5;
|
||||
define exported symbol VectorTableInitForOSRtl8195A = 0x00004019;
|
||||
define exported symbol VectorIrqRegisterRtl8195A = 0x00004029;
|
||||
define exported symbol VectorIrqUnRegisterRtl8195A = 0x00004091;
|
||||
define exported symbol VectorIrqEnRtl8195A = 0x000040f1;
|
||||
define exported symbol VectorIrqDisRtl8195A = 0x0000418d;
|
||||
define exported symbol _UartRxDmaIrqHandle = 0x0000422d;
|
||||
define exported symbol HalRuartPutCRtl8195a = 0x00004281;
|
||||
define exported symbol HalRuartGetCRtl8195a = 0x0000429d;
|
||||
define exported symbol HalRuartRTSCtrlRtl8195a = 0x000042bd;
|
||||
define exported symbol HalRuartGetDebugValueRtl8195a = 0x000042e1;
|
||||
define exported symbol HalRuartGetIMRRtl8195a = 0x000043e1;
|
||||
define exported symbol HalRuartSetIMRRtl8195a = 0x0000442d;
|
||||
define exported symbol _UartIrqHandle = 0x00004465;
|
||||
define exported symbol HalRuartDmaInitRtl8195a = 0x00004681;
|
||||
define exported symbol HalRuartIntDisableRtl8195a = 0x00004845;
|
||||
define exported symbol HalRuartDeInitRtl8195a = 0x00004855;
|
||||
define exported symbol HalRuartIntEnableRtl8195a = 0x00004985;
|
||||
define exported symbol _UartTxDmaIrqHandle = 0x00004995;
|
||||
define exported symbol HalRuartRegIrqRtl8195a = 0x000049d1;
|
||||
define exported symbol HalRuartAdapterLoadDefRtl8195a = 0x00004a4d;
|
||||
define exported symbol HalRuartTxGdmaLoadDefRtl8195a = 0x00004add;
|
||||
define exported symbol HalRuartRxGdmaLoadDefRtl8195a = 0x00004bc9;
|
||||
define exported symbol RuartLock = 0x00004cc9;
|
||||
define exported symbol RuartUnLock = 0x00004ced;
|
||||
define exported symbol HalRuartIntSendRtl8195a = 0x00004d09;
|
||||
define exported symbol HalRuartDmaSendRtl8195a = 0x00004e35;
|
||||
define exported symbol HalRuartStopSendRtl8195a = 0x00004f89;
|
||||
define exported symbol HalRuartIntRecvRtl8195a = 0x0000504d;
|
||||
define exported symbol HalRuartDmaRecvRtl8195a = 0x000051ad;
|
||||
define exported symbol HalRuartStopRecvRtl8195a = 0x000052cd;
|
||||
define exported symbol RuartIsTimeout = 0x00005385;
|
||||
define exported symbol HalRuartSendRtl8195a = 0x000053b1;
|
||||
define exported symbol HalRuartRecvRtl8195a = 0x00005599;
|
||||
define exported symbol RuartResetRxFifoRtl8195a = 0x00005751;
|
||||
define exported symbol HalRuartResetRxFifoRtl8195a = 0x00005775;
|
||||
define exported symbol HalRuartInitRtl8195a = 0x00005829;
|
||||
define exported symbol HalGdmaOnOffRtl8195a = 0x00005df1;
|
||||
define exported symbol HalGdmaChIsrEnAndDisRtl8195a = 0x00005e0d;
|
||||
define exported symbol HalGdmaChEnRtl8195a = 0x00005e51;
|
||||
define exported symbol HalGdmaChDisRtl8195a = 0x00005e6d;
|
||||
define exported symbol HalGdamChInitRtl8195a = 0x00005e91;
|
||||
define exported symbol HalGdmaChSetingRtl8195a = 0x00005ebd;
|
||||
define exported symbol HalGdmaChBlockSetingRtl8195a = 0x000060dd;
|
||||
define exported symbol HalGdmaChIsrCleanRtl8195a = 0x00006419;
|
||||
define exported symbol HalGdmaChCleanAutoSrcRtl8195a = 0x000064a1;
|
||||
define exported symbol HalGdmaChCleanAutoDstRtl8195a = 0x00006501;
|
||||
define exported symbol HalEFUSEPowerSwitch8195AROM = 0x00006561;
|
||||
define exported symbol HALEFUSEOneByteReadROM = 0x000065f9;
|
||||
define exported symbol HALEFUSEOneByteWriteROM = 0x00006699;
|
||||
define exported symbol __rtl_memcmpb_v1_00 = 0x0000681d;
|
||||
define exported symbol __rtl_random_v1_00 = 0x00006861;
|
||||
define exported symbol __rtl_align_to_be32_v1_00 = 0x00006881;
|
||||
define exported symbol __rtl_memsetw_v1_00 = 0x00006899;
|
||||
define exported symbol __rtl_memsetb_v1_00 = 0x000068ad;
|
||||
define exported symbol __rtl_memcpyw_v1_00 = 0x000068bd;
|
||||
define exported symbol __rtl_memcpyb_v1_00 = 0x000068dd;
|
||||
define exported symbol __rtl_memDump_v1_00 = 0x000068f5;
|
||||
define exported symbol __rtl_AES_set_encrypt_key = 0x00006901;
|
||||
define exported symbol __rtl_cryptoEngine_AES_set_decrypt_key = 0x00006c11;
|
||||
define exported symbol __rtl_cryptoEngine_set_security_mode_v1_00 = 0x00006c95;
|
||||
define exported symbol __rtl_cryptoEngine_init_v1_00 = 0x00006ea9;
|
||||
define exported symbol __rtl_cryptoEngine_exit_v1_00 = 0x00007055;
|
||||
define exported symbol __rtl_cryptoEngine_reset_v1_00 = 0x000070b1;
|
||||
define exported symbol __rtl_cryptoEngine_v1_00 = 0x000070ed;
|
||||
define exported symbol __rtl_crypto_cipher_init_v1_00 = 0x00007c69;
|
||||
define exported symbol __rtl_crypto_cipher_encrypt_v1_00 = 0x00007c89;
|
||||
define exported symbol __rtl_crypto_cipher_decrypt_v1_00 = 0x00007cad;
|
||||
define exported symbol HalSsiPinmuxEnableRtl8195a = 0x00007cd5;
|
||||
define exported symbol HalSsiEnableRtl8195a = 0x00007e45;
|
||||
define exported symbol HalSsiDisableRtl8195a = 0x00007ef9;
|
||||
define exported symbol HalSsiLoadSettingRtl8195a = 0x00007fad;
|
||||
define exported symbol HalSsiSetInterruptMaskRtl8195a = 0x00008521;
|
||||
define exported symbol HalSsiGetInterruptMaskRtl8195a = 0x000085c9;
|
||||
define exported symbol HalSsiSetSclkPolarityRtl8195a = 0x0000863d;
|
||||
define exported symbol HalSsiSetSclkPhaseRtl8195a = 0x00008715;
|
||||
define exported symbol HalSsiWriteRtl8195a = 0x000087e9;
|
||||
define exported symbol HalSsiSetDeviceRoleRtl8195a = 0x00008861;
|
||||
define exported symbol HalSsiSetRxFifoThresholdLevelRtl8195a = 0x000088c9;
|
||||
define exported symbol HalSsiSetTxFifoThresholdLevelRtl8195a = 0x00008941;
|
||||
define exported symbol HalSsiReadRtl8195a = 0x000089b9;
|
||||
define exported symbol HalSsiGetRxFifoLevelRtl8195a = 0x00008a2d;
|
||||
define exported symbol HalSsiGetTxFifoLevelRtl8195a = 0x00008aa5;
|
||||
define exported symbol HalSsiGetStatusRtl8195a = 0x00008b1d;
|
||||
define exported symbol HalSsiWriteableRtl8195a = 0x00008b91;
|
||||
define exported symbol HalSsiReadableRtl8195a = 0x00008c09;
|
||||
define exported symbol HalSsiBusyRtl8195a = 0x00008c81;
|
||||
define exported symbol HalSsiReadInterruptRtl8195a = 0x00008cf9;
|
||||
define exported symbol HalSsiWriteInterruptRtl8195a = 0x00008efd;
|
||||
define exported symbol HalSsiSetSlaveEnableRegisterRtl8195a = 0x00009009;
|
||||
define exported symbol HalSsiGetInterruptStatusRtl8195a = 0x000090d9;
|
||||
define exported symbol HalSsiInterruptEnableRtl8195a = 0x0000914d;
|
||||
define exported symbol HalSsiInterruptDisableRtl8195a = 0x00009299;
|
||||
define exported symbol HalSsiGetRawInterruptStatusRtl8195a = 0x000093e9;
|
||||
define exported symbol HalSsiGetSlaveEnableRegisterRtl8195a = 0x0000945d;
|
||||
define exported symbol HalSsiInitRtl8195a = 0x000094d1;
|
||||
define exported symbol _SsiReadInterrupt = 0x00009ba5;
|
||||
define exported symbol _SsiWriteInterrupt = 0x00009db1;
|
||||
define exported symbol _SsiIrqHandle = 0x00009eb1;
|
||||
define exported symbol HalI2CWrite32 = 0x0000a061;
|
||||
define exported symbol HalI2CRead32 = 0x0000a09d;
|
||||
define exported symbol HalI2CDeInit8195a = 0x0000a0dd;
|
||||
define exported symbol HalI2CSendRtl8195a = 0x0000a1f1;
|
||||
define exported symbol HalI2CReceiveRtl8195a = 0x0000a25d;
|
||||
define exported symbol HalI2CEnableRtl8195a = 0x0000a271;
|
||||
define exported symbol HalI2CIntrCtrl8195a = 0x0000a389;
|
||||
define exported symbol HalI2CReadRegRtl8195a = 0x0000a3a1;
|
||||
define exported symbol HalI2CWriteRegRtl8195a = 0x0000a3b1;
|
||||
define exported symbol HalI2CSetCLKRtl8195a = 0x0000a3c5;
|
||||
define exported symbol HalI2CMassSendRtl8195a = 0x0000a6e9;
|
||||
define exported symbol HalI2CClrIntrRtl8195a = 0x0000a749;
|
||||
define exported symbol HalI2CClrAllIntrRtl8195a = 0x0000a761;
|
||||
define exported symbol HalI2CInit8195a = 0x0000a775;
|
||||
define exported symbol HalI2CDMACtrl8195a = 0x0000aa31;
|
||||
define exported symbol RtkI2CIoCtrl = 0x0000aa61;
|
||||
define exported symbol RtkI2CPowerCtrl = 0x0000aa65;
|
||||
define exported symbol HalI2COpInit = 0x0000aa69;
|
||||
define exported symbol I2CIsTimeout = 0x0000ac65;
|
||||
define exported symbol I2CTXGDMAISRHandle = 0x0000b435;
|
||||
define exported symbol I2CRXGDMAISRHandle = 0x0000b4c1;
|
||||
define exported symbol RtkI2CIrqInit = 0x0000b54d;
|
||||
define exported symbol RtkI2CIrqDeInit = 0x0000b611;
|
||||
define exported symbol RtkI2CPinMuxInit = 0x0000b675;
|
||||
define exported symbol RtkI2CPinMuxDeInit = 0x0000b7c9;
|
||||
define exported symbol RtkI2CDMAInit = 0x0000b955;
|
||||
define exported symbol RtkI2CInit = 0x0000bc95;
|
||||
define exported symbol RtkI2CDMADeInit = 0x0000bdad;
|
||||
define exported symbol RtkI2CDeInit = 0x0000be4d;
|
||||
define exported symbol RtkI2CSendUserAddr = 0x0000bee5;
|
||||
define exported symbol RtkI2CSend = 0x0000c07d;
|
||||
define exported symbol RtkI2CLoadDefault = 0x0000ce51;
|
||||
define exported symbol RtkSalI2COpInit = 0x0000cf21;
|
||||
define exported symbol HalI2SWrite32 = 0x0000cf65;
|
||||
define exported symbol HalI2SRead32 = 0x0000cf85;
|
||||
define exported symbol HalI2SDeInitRtl8195a = 0x0000cfa9;
|
||||
define exported symbol HalI2STxRtl8195a = 0x0000cfc9;
|
||||
define exported symbol HalI2SRxRtl8195a = 0x0000d011;
|
||||
define exported symbol HalI2SEnableRtl8195a = 0x0000d05d;
|
||||
define exported symbol HalI2SIntrCtrlRtl8195a = 0x0000d0b1;
|
||||
define exported symbol HalI2SReadRegRtl8195a = 0x0000d0d1;
|
||||
define exported symbol HalI2SClrIntrRtl8195a = 0x0000d0dd;
|
||||
define exported symbol HalI2SClrAllIntrRtl8195a = 0x0000d0fd;
|
||||
define exported symbol HalI2SInitRtl8195a = 0x0000d11d;
|
||||
define exported symbol GPIO_GetIPPinName_8195a = 0x0000d2e5;
|
||||
define exported symbol GPIO_GetChipPinName_8195a = 0x0000d331;
|
||||
define exported symbol GPIO_PullCtrl_8195a = 0x0000d39d;
|
||||
define exported symbol GPIO_FuncOn_8195a = 0x0000d421;
|
||||
define exported symbol GPIO_FuncOff_8195a = 0x0000d481;
|
||||
define exported symbol GPIO_Int_Mask_8195a = 0x0000d4e9;
|
||||
define exported symbol GPIO_Int_SetType_8195a = 0x0000d511;
|
||||
define exported symbol HAL_GPIO_IrqHandler_8195a = 0x0000d5fd;
|
||||
define exported symbol HAL_GPIO_MbedIrqHandler_8195a = 0x0000d645;
|
||||
define exported symbol HAL_GPIO_UserIrqHandler_8195a = 0x0000d6a1;
|
||||
define exported symbol HAL_GPIO_IntCtrl_8195a = 0x0000d6cd;
|
||||
define exported symbol HAL_GPIO_Init_8195a = 0x0000d805;
|
||||
define exported symbol HAL_GPIO_DeInit_8195a = 0x0000dac1;
|
||||
define exported symbol HAL_GPIO_ReadPin_8195a = 0x0000dbd1;
|
||||
define exported symbol HAL_GPIO_WritePin_8195a = 0x0000dc91;
|
||||
define exported symbol HAL_GPIO_RegIrq_8195a = 0x0000ddad;
|
||||
define exported symbol HAL_GPIO_UnRegIrq_8195a = 0x0000ddf5;
|
||||
define exported symbol HAL_GPIO_UserRegIrq_8195a = 0x0000de15;
|
||||
define exported symbol HAL_GPIO_UserUnRegIrq_8195a = 0x0000def9;
|
||||
define exported symbol HAL_GPIO_MaskIrq_8195a = 0x0000dfc1;
|
||||
define exported symbol HAL_GPIO_UnMaskIrq_8195a = 0x0000e061;
|
||||
define exported symbol HAL_GPIO_IntDebounce_8195a = 0x0000e101;
|
||||
define exported symbol HAL_GPIO_GetIPPinName_8195a = 0x0000e1c1;
|
||||
define exported symbol HAL_GPIO_PullCtrl_8195a = 0x0000e1c9;
|
||||
define exported symbol DumpForOneBytes = 0x0000e259;
|
||||
define exported symbol CmdRomHelp = 0x0000e419;
|
||||
define exported symbol CmdWriteWord = 0x0000e491;
|
||||
define exported symbol CmdDumpHelfWord = 0x0000e505;
|
||||
define exported symbol CmdDumpWord = 0x0000e5f1;
|
||||
define exported symbol CmdDumpByte = 0x0000e6f5;
|
||||
define exported symbol CmdSpiFlashTool = 0x0000e751;
|
||||
define exported symbol GetRomCmdNum = 0x0000e7a9;
|
||||
define exported symbol CmdWriteByte = 0x0000e7ad;
|
||||
define exported symbol Isspace = 0x0000e7ed;
|
||||
define exported symbol Strtoul = 0x0000e801;
|
||||
define exported symbol ArrayInitialize = 0x0000e8b1;
|
||||
define exported symbol GetArgc = 0x0000e8c9;
|
||||
define exported symbol GetArgv = 0x0000e8f9;
|
||||
define exported symbol UartLogCmdExecute = 0x0000e95d;
|
||||
define exported symbol UartLogShowBackSpace = 0x0000e9fd;
|
||||
define exported symbol UartLogRecallOldCmd = 0x0000ea39;
|
||||
define exported symbol UartLogHistoryCmd = 0x0000ea71;
|
||||
define exported symbol UartLogCmdChk = 0x0000eadd;
|
||||
define exported symbol UartLogIrqHandle = 0x0000ebf5;
|
||||
define exported symbol RtlConsolInit = 0x0000ecc5;
|
||||
define exported symbol RtlConsolTaskRom = 0x0000ed49;
|
||||
define exported symbol RtlExitConsol = 0x0000ed79;
|
||||
define exported symbol RtlConsolRom = 0x0000edcd;
|
||||
define exported symbol HalTimerOpInit = 0x0000ee0d;
|
||||
define exported symbol HalTimerIrq2To7Handle = 0x0000ee59;
|
||||
define exported symbol HalGetTimerIdRtl8195a = 0x0000ef09;
|
||||
define exported symbol HalTimerInitRtl8195a = 0x0000ef3d;
|
||||
define exported symbol HalTimerDisRtl8195a = 0x0000f069;
|
||||
define exported symbol HalTimerEnRtl8195a = 0x0000f089;
|
||||
define exported symbol HalTimerReadCountRtl8195a = 0x0000f0a9;
|
||||
define exported symbol HalTimerIrqClearRtl8195a = 0x0000f0bd;
|
||||
define exported symbol HalTimerDumpRegRtl8195a = 0x0000f0d1;
|
||||
define exported symbol VSprintf = 0x0000f129;
|
||||
define exported symbol DiagPrintf = 0x0000f39d;
|
||||
define exported symbol DiagSPrintf = 0x0000f3b9;
|
||||
define exported symbol DiagSnPrintf = 0x0000f3d1;
|
||||
define exported symbol prvDiagPrintf = 0x0000f3ed;
|
||||
define exported symbol prvDiagSPrintf = 0x0000f40d;
|
||||
define exported symbol _memcmp = 0x0000f429;
|
||||
define exported symbol __memcmp = 0x0000f429;
|
||||
define exported symbol _memcpy = 0x0000f465;
|
||||
define exported symbol __memcpy = 0x0000f465;
|
||||
define exported symbol _memset = 0x0000f511;
|
||||
define exported symbol __memset = 0x0000f511;
|
||||
define exported symbol Rand = 0x0000f585;
|
||||
define exported symbol _strncpy = 0x0000f60d;
|
||||
define exported symbol __strncpy = 0x0000f60d;
|
||||
define exported symbol _strcpy = 0x0000f629;
|
||||
define exported symbol __strcpy = 0x0000f629;
|
||||
define exported symbol prvStrCpy = 0x0000f639;
|
||||
define exported symbol _strlen = 0x0000f651;
|
||||
define exported symbol __strlen = 0x0000f651;
|
||||
define exported symbol _strnlen = 0x0000f669;
|
||||
define exported symbol __strnlen = 0x0000f669;
|
||||
define exported symbol prvStrLen = 0x0000f699;
|
||||
define exported symbol _strcmp = 0x0000f6b1;
|
||||
define exported symbol __strcmp = 0x0000f6b1;
|
||||
define exported symbol _strncmp = 0x0000f6d1;
|
||||
define exported symbol __strncmp = 0x0000f6d1;
|
||||
define exported symbol prvStrCmp = 0x0000f719;
|
||||
define exported symbol StrUpr = 0x0000f749;
|
||||
define exported symbol prvAtoi = 0x0000f769;
|
||||
define exported symbol prvStrStr = 0x0000f7bd;
|
||||
define exported symbol _strsep = 0x0000f7d5;
|
||||
define exported symbol __strsep = 0x0000f7d5;
|
||||
define exported symbol skip_spaces = 0x0000f815;
|
||||
define exported symbol skip_atoi = 0x0000f831;
|
||||
define exported symbol _parse_integer_fixup_radix = 0x0000f869;
|
||||
define exported symbol _parse_integer = 0x0000f8bd;
|
||||
define exported symbol __strtoull = 0x0000f915;
|
||||
define exported symbol __strtoll = 0x0000f945;
|
||||
define exported symbol __strtoul = 0x0000f965;
|
||||
define exported symbol __strtol = 0x0000f96d;
|
||||
define exported symbol simple_strtoull = 0x0000f915;
|
||||
define exported symbol simple_strtoll = 0x0000f945;
|
||||
define exported symbol simple_strtoul = 0x0000f965;
|
||||
define exported symbol simple_strtol = 0x0000f96d;
|
||||
define exported symbol __vsscanf = 0x0000f985;
|
||||
define exported symbol __sscanf = 0x0000ff71;
|
||||
define exported symbol div_u64 = 0x0000ff91;
|
||||
define exported symbol div_s64 = 0x0000ff99;
|
||||
define exported symbol div_u64_rem = 0x0000ffa1;
|
||||
define exported symbol div_s64_rem = 0x0000ffb1;
|
||||
define exported symbol __strpbrk = 0x0000ffc1;
|
||||
define exported symbol __strchr = 0x0000ffed;
|
||||
define exported symbol aes_set_key = 0x00010005;
|
||||
define exported symbol aes_encrypt = 0x000103d1;
|
||||
define exported symbol aes_decrypt = 0x000114a5;
|
||||
define exported symbol AES_WRAP = 0x000125c9;
|
||||
define exported symbol AES_UnWRAP = 0x00012701;
|
||||
define exported symbol crc32_get = 0x00012861;
|
||||
define exported symbol arc4_byte = 0x00012895;
|
||||
define exported symbol rt_arc4_init = 0x000128bd;
|
||||
define exported symbol rt_arc4_crypt = 0x00012901;
|
||||
define exported symbol rt_md5_init = 0x000131c1;
|
||||
define exported symbol rt_md5_append = 0x000131f5;
|
||||
define exported symbol rt_md5_final = 0x0001327d;
|
||||
define exported symbol rt_md5_hmac = 0x000132d5;
|
||||
define exported symbol rtw_get_bit_value_from_ieee_value = 0x00013449;
|
||||
define exported symbol rtw_is_cckrates_included = 0x00013475;
|
||||
define exported symbol rtw_is_cckratesonly_included = 0x000134b5;
|
||||
define exported symbol rtw_check_network_type = 0x000134dd;
|
||||
define exported symbol rtw_set_fixed_ie = 0x0001350d;
|
||||
define exported symbol rtw_set_ie = 0x0001352d;
|
||||
define exported symbol rtw_get_ie = 0x0001355d;
|
||||
define exported symbol rtw_set_supported_rate = 0x00013591;
|
||||
define exported symbol rtw_get_rateset_len = 0x00013611;
|
||||
define exported symbol rtw_get_wpa_ie = 0x0001362d;
|
||||
define exported symbol rtw_get_wpa2_ie = 0x000136c9;
|
||||
define exported symbol rtw_get_wpa_cipher_suite = 0x00013701;
|
||||
define exported symbol rtw_get_wpa2_cipher_suite = 0x00013769;
|
||||
define exported symbol rtw_parse_wpa_ie = 0x000137d1;
|
||||
define exported symbol rtw_parse_wpa2_ie = 0x000138ad;
|
||||
define exported symbol rtw_get_sec_ie = 0x00013965;
|
||||
define exported symbol rtw_get_wps_ie = 0x00013a15;
|
||||
define exported symbol rtw_get_wps_attr = 0x00013a99;
|
||||
define exported symbol rtw_get_wps_attr_content = 0x00013b49;
|
||||
define exported symbol rtw_ieee802_11_parse_elems = 0x00013b91;
|
||||
define exported symbol str_2char2num = 0x00013d9d;
|
||||
define exported symbol key_2char2num = 0x00013db9;
|
||||
define exported symbol convert_ip_addr = 0x00013dd1;
|
||||
define exported symbol rom_psk_PasswordHash = 0x00013e9d;
|
||||
define exported symbol rom_psk_CalcGTK = 0x00013ed5;
|
||||
define exported symbol rom_psk_CalcPTK = 0x00013f69;
|
||||
define exported symbol wep_80211_encrypt = 0x00014295;
|
||||
define exported symbol wep_80211_decrypt = 0x000142f5;
|
||||
define exported symbol tkip_micappendbyte = 0x00014389;
|
||||
define exported symbol rtw_secmicsetkey = 0x000143d9;
|
||||
define exported symbol rtw_secmicappend = 0x00014419;
|
||||
define exported symbol rtw_secgetmic = 0x00014435;
|
||||
define exported symbol rtw_seccalctkipmic = 0x0001449d;
|
||||
define exported symbol tkip_phase1 = 0x000145a5;
|
||||
define exported symbol tkip_phase2 = 0x00014725;
|
||||
define exported symbol tkip_80211_encrypt = 0x00014941;
|
||||
define exported symbol tkip_80211_decrypt = 0x000149d5;
|
||||
define exported symbol aes1_encrypt = 0x00014a8d;
|
||||
define exported symbol aesccmp_construct_mic_iv = 0x00014c65;
|
||||
define exported symbol aesccmp_construct_mic_header1 = 0x00014ccd;
|
||||
define exported symbol aesccmp_construct_mic_header2 = 0x00014d21;
|
||||
define exported symbol aesccmp_construct_ctr_preload = 0x00014db5;
|
||||
define exported symbol aes_80211_encrypt = 0x00014e29;
|
||||
define exported symbol aes_80211_decrypt = 0x000151ad;
|
||||
define exported symbol _sha1_process_message_block = 0x000155b9;
|
||||
define exported symbol _sha1_pad_message = 0x00015749;
|
||||
define exported symbol rt_sha1_init = 0x000157e5;
|
||||
define exported symbol rt_sha1_update = 0x00015831;
|
||||
define exported symbol rt_sha1_finish = 0x000158a9;
|
||||
define exported symbol rt_hmac_sha1 = 0x00015909;
|
||||
define exported symbol rom_aes_128_cbc_encrypt = 0x00015a65;
|
||||
define exported symbol rom_aes_128_cbc_decrypt = 0x00015ae1;
|
||||
define exported symbol rom_rijndaelKeySetupEnc = 0x00015b5d;
|
||||
define exported symbol rom_aes_decrypt_init = 0x00015c39;
|
||||
define exported symbol rom_aes_internal_decrypt = 0x00015d15;
|
||||
define exported symbol rom_aes_decrypt_deinit = 0x00016071;
|
||||
define exported symbol rom_aes_encrypt_init = 0x00016085;
|
||||
define exported symbol rom_aes_internal_encrypt = 0x0001609d;
|
||||
define exported symbol rom_aes_encrypt_deinit = 0x00016451;
|
||||
define exported symbol bignum_init = 0x00017b35;
|
||||
define exported symbol bignum_deinit = 0x00017b61;
|
||||
define exported symbol bignum_get_unsigned_bin_len = 0x00017b81;
|
||||
define exported symbol bignum_get_unsigned_bin = 0x00017b85;
|
||||
define exported symbol bignum_set_unsigned_bin = 0x00017c21;
|
||||
define exported symbol bignum_cmp = 0x00017cd1;
|
||||
define exported symbol bignum_cmp_d = 0x00017cd5;
|
||||
define exported symbol bignum_add = 0x00017cfd;
|
||||
define exported symbol bignum_sub = 0x00017d0d;
|
||||
define exported symbol bignum_mul = 0x00017d1d;
|
||||
define exported symbol bignum_exptmod = 0x00017d2d;
|
||||
define exported symbol WPS_realloc = 0x00017d51;
|
||||
define exported symbol os_zalloc = 0x00017d99;
|
||||
define exported symbol rom_hmac_sha256_vector = 0x00017dc1;
|
||||
define exported symbol rom_hmac_sha256 = 0x00017ebd;
|
||||
define exported symbol rom_sha256_vector = 0x00018009;
|
||||
define exported symbol phy_CalculateBitShift = 0x00018221;
|
||||
define exported symbol PHY_SetBBReg_8195A = 0x00018239;
|
||||
define exported symbol PHY_QueryBBReg_8195A = 0x00018279;
|
||||
define exported symbol ROM_odm_QueryRxPwrPercentage = 0x0001829d;
|
||||
define exported symbol ROM_odm_EVMdbToPercentage = 0x000182bd;
|
||||
define exported symbol ROM_odm_SignalScaleMapping_8195A = 0x000182e5;
|
||||
define exported symbol ROM_odm_FalseAlarmCounterStatistics = 0x000183cd;
|
||||
define exported symbol ROM_odm_SetEDCCAThreshold = 0x00018721;
|
||||
define exported symbol ROM_odm_SetTRxMux = 0x00018749;
|
||||
define exported symbol ROM_odm_SetCrystalCap = 0x00018771;
|
||||
define exported symbol ROM_odm_GetDefaultCrytaltalCap = 0x000187d5;
|
||||
define exported symbol ROM_ODM_CfoTrackingReset = 0x000187e9;
|
||||
define exported symbol ROM_odm_CfoTrackingFlow = 0x00018811;
|
||||
define exported symbol curve25519_donna = 0x0001965d;
|
||||
define exported symbol aes_test_alignment_detection = 0x0001a391;
|
||||
define exported symbol aes_mode_reset = 0x0001a3ed;
|
||||
define exported symbol aes_ecb_encrypt = 0x0001a3f9;
|
||||
define exported symbol aes_ecb_decrypt = 0x0001a431;
|
||||
define exported symbol aes_cbc_encrypt = 0x0001a469;
|
||||
define exported symbol aes_cbc_decrypt = 0x0001a579;
|
||||
define exported symbol aes_cfb_encrypt = 0x0001a701;
|
||||
define exported symbol aes_cfb_decrypt = 0x0001a9e5;
|
||||
define exported symbol aes_ofb_crypt = 0x0001acc9;
|
||||
define exported symbol aes_ctr_crypt = 0x0001af7d;
|
||||
define exported symbol aes_encrypt_key128 = 0x0001b289;
|
||||
define exported symbol aes_encrypt_key192 = 0x0001b2a5;
|
||||
define exported symbol aes_encrypt_key256 = 0x0001b2c1;
|
||||
define exported symbol aes_encrypt_key = 0x0001b2e1;
|
||||
define exported symbol aes_decrypt_key128 = 0x0001b351;
|
||||
define exported symbol aes_decrypt_key192 = 0x0001b36d;
|
||||
define exported symbol aes_decrypt_key256 = 0x0001b389;
|
||||
define exported symbol aes_decrypt_key = 0x0001b3a9;
|
||||
define exported symbol aes_init = 0x0001b419;
|
||||
define exported symbol CRYPTO_chacha_20 = 0x0001b41d;
|
||||
define exported symbol CRYPTO_poly1305_init = 0x0001bc25;
|
||||
define exported symbol CRYPTO_poly1305_update = 0x0001bd09;
|
||||
define exported symbol CRYPTO_poly1305_finish = 0x0001bd8d;
|
||||
define exported symbol rom_sha512_starts = 0x0001ceb5;
|
||||
define exported symbol rom_sha512_update = 0x0001d009;
|
||||
define exported symbol rom_sha512_finish = 0x0001d011;
|
||||
define exported symbol rom_sha512 = 0x0001d261;
|
||||
define exported symbol rom_sha512_hmac_starts = 0x0001d299;
|
||||
define exported symbol rom_sha512_hmac_update = 0x0001d35d;
|
||||
define exported symbol rom_sha512_hmac_finish = 0x0001d365;
|
||||
define exported symbol rom_sha512_hmac_reset = 0x0001d3b5;
|
||||
define exported symbol rom_sha512_hmac = 0x0001d3d1;
|
||||
define exported symbol rom_sha512_hkdf = 0x0001d40d;
|
||||
define exported symbol rom_ed25519_gen_keypair = 0x0001d501;
|
||||
define exported symbol rom_ed25519_gen_signature = 0x0001d505;
|
||||
define exported symbol rom_ed25519_verify_signature = 0x0001d51d;
|
||||
define exported symbol rom_ed25519_crypto_sign_seed_keypair = 0x0001d521;
|
||||
define exported symbol rom_ed25519_crypto_sign_detached = 0x0001d579;
|
||||
define exported symbol rom_ed25519_crypto_sign_verify_detached = 0x0001d655;
|
||||
define exported symbol rom_ed25519_ge_double_scalarmult_vartime = 0x0001f86d;
|
||||
define exported symbol rom_ed25519_ge_frombytes_negate_vartime = 0x0001fc35;
|
||||
define exported symbol rom_ed25519_ge_p3_tobytes = 0x000207d5;
|
||||
define exported symbol rom_ed25519_ge_scalarmult_base = 0x00020821;
|
||||
define exported symbol rom_ed25519_ge_tobytes = 0x000209e1;
|
||||
define exported symbol rom_ed25519_sc_muladd = 0x00020a2d;
|
||||
define exported symbol rom_ed25519_sc_reduce = 0x0002603d;
|
||||
define exported symbol __rtl_memchr_v1_00 = 0x00028a4d;
|
||||
define exported symbol __rtl_memcmp_v1_00 = 0x00028ae1;
|
||||
define exported symbol __rtl_memcpy_v1_00 = 0x00028b49;
|
||||
define exported symbol __rtl_memmove_v1_00 = 0x00028bed;
|
||||
define exported symbol __rtl_memset_v1_00 = 0x00028cb5;
|
||||
define exported symbol __rtl_strcat_v1_00 = 0x00028d49;
|
||||
define exported symbol __rtl_strchr_v1_00 = 0x00028d91;
|
||||
define exported symbol __rtl_strcmp_v1_00 = 0x00028e55;
|
||||
define exported symbol __rtl_strcpy_v1_00 = 0x00028ec9;
|
||||
define exported symbol __rtl_strlen_v1_00 = 0x00028f15;
|
||||
define exported symbol __rtl_strncat_v1_00 = 0x00028f69;
|
||||
define exported symbol __rtl_strncmp_v1_00 = 0x00028fc5;
|
||||
define exported symbol __rtl_strncpy_v1_00 = 0x0002907d;
|
||||
define exported symbol __rtl_strstr_v1_00 = 0x000293cd;
|
||||
define exported symbol __rtl_strsep_v1_00 = 0x0002960d;
|
||||
define exported symbol __rtl_strtok_v1_00 = 0x00029619;
|
||||
define exported symbol __rtl__strtok_r_v1_00 = 0x0002962d;
|
||||
define exported symbol __rtl_strtok_r_v1_00 = 0x00029691;
|
||||
define exported symbol __rtl_close_v1_00 = 0x00029699;
|
||||
define exported symbol __rtl_fstat_v1_00 = 0x000296ad;
|
||||
define exported symbol __rtl_isatty_v1_00 = 0x000296c1;
|
||||
define exported symbol __rtl_lseek_v1_00 = 0x000296d5;
|
||||
define exported symbol __rtl_open_v1_00 = 0x000296e9;
|
||||
define exported symbol __rtl_read_v1_00 = 0x000296fd;
|
||||
define exported symbol __rtl_write_v1_00 = 0x00029711;
|
||||
define exported symbol __rtl_sbrk_v1_00 = 0x00029725;
|
||||
define exported symbol __rtl_ltoa_v1_00 = 0x000297bd;
|
||||
define exported symbol __rtl_ultoa_v1_00 = 0x00029855;
|
||||
define exported symbol __rtl_dtoi_v1_00 = 0x000298c5;
|
||||
define exported symbol __rtl_dtoi64_v1_00 = 0x00029945;
|
||||
define exported symbol __rtl_dtoui_v1_00 = 0x000299dd;
|
||||
define exported symbol __rtl_ftol_v1_00 = 0x000299e5;
|
||||
define exported symbol __rtl_itof_v1_00 = 0x00029a51;
|
||||
define exported symbol __rtl_itod_v1_00 = 0x00029ae9;
|
||||
define exported symbol __rtl_i64tod_v1_00 = 0x00029b79;
|
||||
define exported symbol __rtl_uitod_v1_00 = 0x00029c55;
|
||||
define exported symbol __rtl_ftod_v1_00 = 0x00029d2d;
|
||||
define exported symbol __rtl_dtof_v1_00 = 0x00029de9;
|
||||
define exported symbol __rtl_uitof_v1_00 = 0x00029e89;
|
||||
define exported symbol __rtl_fadd_v1_00 = 0x00029f65;
|
||||
define exported symbol __rtl_fsub_v1_00 = 0x0002a261;
|
||||
define exported symbol __rtl_fmul_v1_00 = 0x0002a559;
|
||||
define exported symbol __rtl_fdiv_v1_00 = 0x0002a695;
|
||||
define exported symbol __rtl_dadd_v1_00 = 0x0002a825;
|
||||
define exported symbol __rtl_dsub_v1_00 = 0x0002aed9;
|
||||
define exported symbol __rtl_dmul_v1_00 = 0x0002b555;
|
||||
define exported symbol __rtl_ddiv_v1_00 = 0x0002b8ad;
|
||||
define exported symbol __rtl_dcmpeq_v1_00 = 0x0002be4d;
|
||||
define exported symbol __rtl_dcmplt_v1_00 = 0x0002bebd;
|
||||
define exported symbol __rtl_dcmpgt_v1_00 = 0x0002bf51;
|
||||
define exported symbol __rtl_dcmple_v1_00 = 0x0002c049;
|
||||
define exported symbol __rtl_fcmplt_v1_00 = 0x0002c139;
|
||||
define exported symbol __rtl_fcmpgt_v1_00 = 0x0002c195;
|
||||
define exported symbol __rtl_cos_f32_v1_00 = 0x0002c229;
|
||||
define exported symbol __rtl_sin_f32_v1_00 = 0x0002c435;
|
||||
define exported symbol __rtl_fabs_v1_00 = 0x0002c639;
|
||||
define exported symbol __rtl_fabsf_v1_00 = 0x0002c641;
|
||||
define exported symbol __rtl_dtoa_r_v1_00 = 0x0002c77d;
|
||||
define exported symbol __rom_mallocr_init_v1_00 = 0x0002d7d1;
|
||||
define exported symbol __rtl_free_r_v1_00 = 0x0002d841;
|
||||
define exported symbol __rtl_malloc_r_v1_00 = 0x0002da31;
|
||||
define exported symbol __rtl_realloc_r_v1_00 = 0x0002df55;
|
||||
define exported symbol __rtl_memalign_r_v1_00 = 0x0002e331;
|
||||
define exported symbol __rtl_valloc_r_v1_00 = 0x0002e421;
|
||||
define exported symbol __rtl_pvalloc_r_v1_00 = 0x0002e42d;
|
||||
define exported symbol __rtl_calloc_r_v1_00 = 0x0002e441;
|
||||
define exported symbol __rtl_cfree_r_v1_00 = 0x0002e4a9;
|
||||
define exported symbol __rtl_Balloc_v1_00 = 0x0002e515;
|
||||
define exported symbol __rtl_Bfree_v1_00 = 0x0002e571;
|
||||
define exported symbol __rtl_i2b_v1_00 = 0x0002e585;
|
||||
define exported symbol __rtl_multadd_v1_00 = 0x0002e599;
|
||||
define exported symbol __rtl_mult_v1_00 = 0x0002e629;
|
||||
define exported symbol __rtl_pow5mult_v1_00 = 0x0002e769;
|
||||
define exported symbol __rtl_hi0bits_v1_00 = 0x0002e809;
|
||||
define exported symbol __rtl_d2b_v1_00 = 0x0002e845;
|
||||
define exported symbol __rtl_lshift_v1_00 = 0x0002e901;
|
||||
define exported symbol __rtl_cmp_v1_00 = 0x0002e9bd;
|
||||
define exported symbol __rtl_diff_v1_00 = 0x0002ea01;
|
||||
define exported symbol __rtl_sread_v1_00 = 0x0002eae9;
|
||||
define exported symbol __rtl_seofread_v1_00 = 0x0002eb39;
|
||||
define exported symbol __rtl_swrite_v1_00 = 0x0002eb3d;
|
||||
define exported symbol __rtl_sseek_v1_00 = 0x0002ebc1;
|
||||
define exported symbol __rtl_sclose_v1_00 = 0x0002ec11;
|
||||
define exported symbol __rtl_sbrk_r_v1_00 = 0x0002ec41;
|
||||
define exported symbol __rtl_fflush_r_v1_00 = 0x0002ef8d;
|
||||
define exported symbol __rtl_vfprintf_r_v1_00 = 0x0002f661;
|
||||
define exported symbol __rtl_fpclassifyd = 0x00030c15;
|
||||
define exported symbol CpkClkTbl = 0x00030c68;
|
||||
define exported symbol ROM_IMG1_VALID_PATTEN = 0x00030c80;
|
||||
define exported symbol SpicCalibrationPattern = 0x00030c88;
|
||||
define exported symbol SpicInitCPUCLK = 0x00030c98;
|
||||
define exported symbol BAUDRATE = 0x00030ca8;
|
||||
define exported symbol OVSR = 0x00030d1c;
|
||||
define exported symbol DIV = 0x00030d90;
|
||||
define exported symbol OVSR_ADJ = 0x00030e04;
|
||||
define exported symbol __AES_rcon = 0x00030e78;
|
||||
define exported symbol __AES_Te4 = 0x00030ea0;
|
||||
define exported symbol I2CDmaChNo = 0x000312a0;
|
||||
define exported symbol _GPIO_PinMap_Chip2IP_8195a = 0x000312b4;
|
||||
define exported symbol _GPIO_PinMap_PullCtrl_8195a = 0x0003136c;
|
||||
define exported symbol _GPIO_SWPORT_DDR_TBL = 0x00031594;
|
||||
define exported symbol _GPIO_EXT_PORT_TBL = 0x00031598;
|
||||
define exported symbol _GPIO_SWPORT_DR_TBL = 0x0003159c;
|
||||
define exported symbol UartLogRomCmdTable = 0x000316a0;
|
||||
define exported symbol _HalRuartOp = 0x00031700;
|
||||
define exported symbol _HalGdmaOp = 0x00031760;
|
||||
define exported symbol RTW_WPA_OUI_TYPE = 0x0003540c;
|
||||
define exported symbol WPA_CIPHER_SUITE_NONE = 0x00035410;
|
||||
define exported symbol WPA_CIPHER_SUITE_WEP40 = 0x00035414;
|
||||
define exported symbol WPA_CIPHER_SUITE_TKIP = 0x00035418;
|
||||
define exported symbol WPA_CIPHER_SUITE_CCMP = 0x0003541c;
|
||||
define exported symbol WPA_CIPHER_SUITE_WEP104 = 0x00035420;
|
||||
define exported symbol RSN_CIPHER_SUITE_NONE = 0x00035424;
|
||||
define exported symbol RSN_CIPHER_SUITE_WEP40 = 0x00035428;
|
||||
define exported symbol RSN_CIPHER_SUITE_TKIP = 0x0003542c;
|
||||
define exported symbol RSN_CIPHER_SUITE_CCMP = 0x00035430;
|
||||
define exported symbol RSN_CIPHER_SUITE_WEP104 = 0x00035434;
|
||||
define exported symbol RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x00035444;
|
||||
define exported symbol RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x00035448;
|
||||
define exported symbol RSN_VERSION_BSD = 0x0003544c;
|
||||
define exported symbol rom_wps_Te0 = 0x00035988;
|
||||
define exported symbol rom_wps_rcons = 0x00035d88;
|
||||
define exported symbol rom_wps_Td4s = 0x00035d94;
|
||||
define exported symbol rom_wps_Td0 = 0x00035e94;
|
||||
define exported symbol __rom_b_cut_end__ = 0x0004467c;
|
||||
define exported symbol __rom_c_cut_text_start__ = 0x0004467c;
|
||||
define exported symbol HalInitPlatformLogUartV02 = 0x0004467d;
|
||||
define exported symbol HalReInitPlatformLogUartV02 = 0x0004471d;
|
||||
define exported symbol HalInitPlatformTimerV02 = 0x00044755;
|
||||
define exported symbol HalShowBuildInfoV02 = 0x000447cd;
|
||||
define exported symbol SpicReleaseDeepPowerDownFlashRtl8195A = 0x00044831;
|
||||
define exported symbol HalSpiInitV02 = 0x0004488d;
|
||||
define exported symbol HalBootFlowV02 = 0x00044a29;
|
||||
define exported symbol HalInitialROMCodeGlobalVarV02 = 0x00044ae5;
|
||||
define exported symbol HalResetVsrV02 = 0x00044b41;
|
||||
define exported symbol HalI2CSendRtl8195aV02 = 0x00044ce1;
|
||||
define exported symbol HalI2CSetCLKRtl8195aV02 = 0x00044d59;
|
||||
define exported symbol RtkI2CSendV02 = 0x0004508d;
|
||||
define exported symbol RtkI2CReceiveV02 = 0x000459a1;
|
||||
define exported symbol HalI2COpInitV02 = 0x000461ed;
|
||||
define exported symbol I2CISRHandleV02 = 0x000463e9;
|
||||
define exported symbol RtkSalI2COpInitV02 = 0x00046be1;
|
||||
define exported symbol SpicLoadInitParaFromClockRtl8195AV02 = 0x00046c25;
|
||||
define exported symbol SpiFlashAppV02 = 0x00046c85;
|
||||
define exported symbol SpicInitRtl8195AV02 = 0x00046dc5;
|
||||
define exported symbol SpicEraseFlashRtl8195AV02 = 0x00046ea1;
|
||||
define exported symbol HalTimerIrq2To7HandleV02 = 0x00046f5d;
|
||||
define exported symbol HalTimerIrqRegisterRtl8195aV02 = 0x00046fe1;
|
||||
define exported symbol HalTimerInitRtl8195aV02 = 0x0004706d;
|
||||
define exported symbol HalTimerReadCountRtl8195aV02 = 0x000471b5;
|
||||
define exported symbol HalTimerReLoadRtl8195aV02 = 0x000471d1;
|
||||
define exported symbol HalTimerIrqUnRegisterRtl8195aV02 = 0x0004722d;
|
||||
define exported symbol HalTimerDeInitRtl8195aV02 = 0x000472c1;
|
||||
define exported symbol HalTimerOpInitV02 = 0x000472f9;
|
||||
define exported symbol GPIO_LockV02 = 0x00047345;
|
||||
define exported symbol GPIO_UnLockV02 = 0x00047379;
|
||||
define exported symbol GPIO_Int_Clear_8195aV02 = 0x000473a5;
|
||||
define exported symbol HAL_GPIO_IntCtrl_8195aV02 = 0x000473b5;
|
||||
define exported symbol FindElementIndexV02 = 0x00047541;
|
||||
define exported symbol HalRuartInitRtl8195aV02 = 0x0004756d;
|
||||
define exported symbol DramInit_rom = 0x00047619;
|
||||
define exported symbol ChangeRandSeed_rom = 0x00047979;
|
||||
define exported symbol Sdr_Rand2_rom = 0x00047985;
|
||||
define exported symbol MemTest_rom = 0x000479dd;
|
||||
define exported symbol SdrCalibration_rom = 0x00047a45;
|
||||
define exported symbol SdrControllerInit_rom = 0x00047d99;
|
||||
define exported symbol SDIO_EnterCritical = 0x00047e39;
|
||||
define exported symbol SDIO_ExitCritical = 0x00047e85;
|
||||
define exported symbol SDIO_IRQ_Handler_Rom = 0x00047ec5;
|
||||
define exported symbol SDIO_Interrupt_Init_Rom = 0x00047f31;
|
||||
define exported symbol SDIO_Device_Init_Rom = 0x00047f81;
|
||||
define exported symbol SDIO_Interrupt_DeInit_Rom = 0x00048215;
|
||||
define exported symbol SDIO_Device_DeInit_Rom = 0x00048255;
|
||||
define exported symbol SDIO_Enable_Interrupt_Rom = 0x00048281;
|
||||
define exported symbol SDIO_Disable_Interrupt_Rom = 0x000482a1;
|
||||
define exported symbol SDIO_Clear_ISR_Rom = 0x000482c1;
|
||||
define exported symbol SDIO_Alloc_Rx_Pkt_Rom = 0x000482d9;
|
||||
define exported symbol SDIO_Free_Rx_Pkt_Rom = 0x00048331;
|
||||
define exported symbol SDIO_Recycle_Rx_BD_Rom = 0x00048355;
|
||||
define exported symbol SDIO_RX_IRQ_Handler_BH_Rom = 0x000484f1;
|
||||
define exported symbol SDIO_RxTask_Rom = 0x0004851d;
|
||||
define exported symbol SDIO_Process_H2C_IOMsg_Rom = 0x0004856d;
|
||||
define exported symbol SDIO_Send_C2H_IOMsg_Rom = 0x0004859d;
|
||||
define exported symbol SDIO_Process_RPWM_Rom = 0x000485b5;
|
||||
define exported symbol SDIO_Reset_Cmd_Rom = 0x000485e9;
|
||||
define exported symbol SDIO_Rx_Data_Transaction_Rom = 0x00048611;
|
||||
define exported symbol SDIO_Send_C2H_PktMsg_Rom = 0x00048829;
|
||||
define exported symbol SDIO_Register_Tx_Callback_Rom = 0x000488f5;
|
||||
define exported symbol SDIO_ReadMem_Rom = 0x000488fd;
|
||||
define exported symbol SDIO_WriteMem_Rom = 0x000489a9;
|
||||
define exported symbol SDIO_SetMem_Rom = 0x00048a69;
|
||||
define exported symbol SDIO_TX_Pkt_Handle_Rom = 0x00048b29;
|
||||
define exported symbol SDIO_TX_FIFO_DataReady_Rom = 0x00048c69;
|
||||
define exported symbol SDIO_IRQ_Handler_BH_Rom = 0x00048d95;
|
||||
define exported symbol SDIO_TxTask_Rom = 0x00048e9d;
|
||||
define exported symbol SDIO_TaskUp_Rom = 0x00048eed;
|
||||
define exported symbol SDIO_Boot_Up = 0x00048f55;
|
||||
define exported symbol __rom_c_cut_text_end__ = 0x00049070;
|
||||
define exported symbol __rom_c_cut_rodata_start__ = 0x00049070;
|
||||
define exported symbol BAUDRATE_v02 = 0x00049070;
|
||||
define exported symbol OVSR_v02 = 0x000490fc;
|
||||
define exported symbol DIV_v02 = 0x00049188;
|
||||
define exported symbol OVSR_ADJ_v02 = 0x00049214;
|
||||
define exported symbol SdrDramInfo_rom = 0x000492a0;
|
||||
define exported symbol SdrDramTiming_rom = 0x000492b4;
|
||||
define exported symbol NewVectorTable = 0x10000000;
|
||||
define exported symbol UserIrqFunTable = 0x10000100;
|
||||
define exported symbol UserIrqDataTable = 0x10000200;
|
||||
define exported symbol __rom_bss_start__ = 0x10000300;
|
||||
define exported symbol CfgSysDebugWarn = 0x10000300;
|
||||
define exported symbol CfgSysDebugInfo = 0x10000304;
|
||||
define exported symbol CfgSysDebugErr = 0x10000308;
|
||||
define exported symbol ConfigDebugWarn = 0x1000030c;
|
||||
define exported symbol ConfigDebugInfo = 0x10000310;
|
||||
define exported symbol ConfigDebugErr = 0x10000314;
|
||||
define exported symbol HalTimerOp = 0x10000318;
|
||||
define exported symbol GPIOState = 0x10000334;
|
||||
define exported symbol gTimerRecord = 0x1000034c;
|
||||
define exported symbol SSI_DBG_CONFIG = 0x10000350;
|
||||
define exported symbol _pHAL_Gpio_Adapter = 0x10000354;
|
||||
define exported symbol Timer2To7VectorTable = 0x10000358;
|
||||
define exported symbol rom_wlan_ram_map = 0x100006d4;
|
||||
define exported symbol ROMInfo = 0x10000720;
|
||||
define exported symbol rom_libgloss_ram_map = 0x10000760;
|
||||
define exported symbol __rtl_errno = 0x10000bc4;
|
||||
define exported symbol __rom_bss_end__ = 0x10000bc8;
|
||||
define exported symbol __ram_table_start__ = 0x10000bc8;
|
||||
define exported symbol _rtl_impure_ptr = 0x10001c60;
|
||||
define exported symbol FalseAlmCnt = 0x100006d4;
|
||||
define exported symbol DM_CfoTrack = 0x1000072c;
|
||||
|
|
@ -44,15 +44,25 @@ extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[];
|
|||
|
||||
#elif defined (__ICCARM__)
|
||||
|
||||
#pragma section=".ram.bss"
|
||||
#pragma section=".bss.sram"
|
||||
#pragma section=".bss.dtcm"
|
||||
#pragma section=".bss.dram"
|
||||
|
||||
uint8_t *__bss_start__;
|
||||
uint8_t *__bss_end__;
|
||||
uint8_t *__bss_sram_start__;
|
||||
uint8_t *__bss_sram_end__;
|
||||
uint8_t *__bss_dtcm_start__;
|
||||
uint8_t *__bss_dtcm_end__;
|
||||
uint8_t *__bss_dram_start__;
|
||||
uint8_t *__bss_dram_end__;
|
||||
|
||||
void __iar_data_init_app(void)
|
||||
{
|
||||
__bss_start__ = (uint8_t *)__section_begin(".ram.bss");
|
||||
__bss_end__ = (uint8_t *)__section_end(".ram.bss");
|
||||
__bss_sram_start__ = (uint8_t *)__section_begin(".bss.sram");
|
||||
__bss_sram_end__ = (uint8_t *)__section_end(".bss.sram");
|
||||
__bss_dtcm_start__ = (uint8_t *)__section_begin(".bss.dtcm");
|
||||
__bss_dtcm_end__ = (uint8_t *)__section_end(".bss.dtcm");
|
||||
__bss_dram_start__ = (uint8_t *)__section_begin(".bss.dram");
|
||||
__bss_dram_end__ = (uint8_t *)__section_end(".bss.dram");
|
||||
}
|
||||
|
||||
#else
|
||||
|
|
@ -181,12 +191,10 @@ void PLAT_Init(void)
|
|||
// Clear RAM BSS
|
||||
#if defined (__ICCARM__)
|
||||
__iar_data_init_app();
|
||||
__rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
|
||||
#else
|
||||
#endif
|
||||
__rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__);
|
||||
__rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__);
|
||||
__rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
|
||||
#endif
|
||||
|
||||
extern HAL_TIMER_OP_EXT HalTimerOpExt;
|
||||
__rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));
|
||||
|
|
|
|||
|
|
@ -1,748 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
SECTIONS
|
||||
{
|
||||
__vectors_table = 0x0;
|
||||
Reset_Handler = 0x101;
|
||||
NMI_Handler = 0x109;
|
||||
HardFault_Handler = 0x10d;
|
||||
MemManage_Handler = 0x121;
|
||||
BusFault_Handler = 0x125;
|
||||
UsageFault_Handler = 0x129;
|
||||
HalLogUartInit = 0x201;
|
||||
HalSerialPutcRtl8195a = 0x2d9;
|
||||
HalSerialGetcRtl8195a = 0x309;
|
||||
HalSerialGetIsrEnRegRtl8195a = 0x329;
|
||||
HalSerialSetIrqEnRegRtl8195a = 0x335;
|
||||
HalCpuClkConfig = 0x341;
|
||||
HalGetCpuClk = 0x355;
|
||||
HalRomInfo = 0x39d;
|
||||
HalGetRomInfo = 0x3b5;
|
||||
HalResetVsr = 0x3c5;
|
||||
HalDelayUs = 0x899;
|
||||
HalNMIHandler = 0x8e1;
|
||||
HalHardFaultHandler = 0x911;
|
||||
HalMemManageHandler = 0xc09;
|
||||
HalBusFaultHandler = 0xc39;
|
||||
HalUsageFaultHandler = 0xc69;
|
||||
HalUart0PinCtrlRtl8195A = 0xcfd;
|
||||
HalUart1PinCtrlRtl8195A = 0xdc9;
|
||||
HalUart2PinCtrlRtl8195A = 0xe9d;
|
||||
HalSPI0PinCtrlRtl8195A = 0xf75;
|
||||
HalSPI1PinCtrlRtl8195A = 0x1015;
|
||||
HalSPI2PinCtrlRtl8195A = 0x10e5;
|
||||
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
|
||||
HalI2C0PinCtrlRtl8195A = 0x1275;
|
||||
HalI2C1PinCtrlRtl8195A = 0x1381;
|
||||
HalI2C2PinCtrlRtl8195A = 0x1459;
|
||||
HalI2C3PinCtrlRtl8195A = 0x1529;
|
||||
HalI2S0PinCtrlRtl8195A = 0x1639;
|
||||
HalI2S1PinCtrlRtl8195A = 0x176d;
|
||||
HalPCM0PinCtrlRtl8195A = 0x1845;
|
||||
HalPCM1PinCtrlRtl8195A = 0x1949;
|
||||
HalSDIODPinCtrlRtl8195A = 0x1a1d;
|
||||
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
|
||||
HalMIIPinCtrlRtl8195A = 0x1ab9;
|
||||
HalWLLEDPinCtrlRtl8195A = 0x1b51;
|
||||
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
|
||||
HalWLANT1PinCtrlRtl8195A = 0x1c61;
|
||||
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
|
||||
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
|
||||
HalNFCPinCtrlRtl8195A = 0x1d59;
|
||||
HalPWM0PinCtrlRtl8195A = 0x1da9;
|
||||
HalPWM1PinCtrlRtl8195A = 0x1ead;
|
||||
HalPWM2PinCtrlRtl8195A = 0x1fb5;
|
||||
HalPWM3PinCtrlRtl8195A = 0x20b1;
|
||||
HalETE0PinCtrlRtl8195A = 0x21b9;
|
||||
HalETE1PinCtrlRtl8195A = 0x22c1;
|
||||
HalETE2PinCtrlRtl8195A = 0x23c9;
|
||||
HalETE3PinCtrlRtl8195A = 0x24d1;
|
||||
HalEGTIMPinCtrlRtl8195A = 0x25d9;
|
||||
HalSPIFlashPinCtrlRtl8195A = 0x2679;
|
||||
HalSDRPinCtrlRtl8195A = 0x2725;
|
||||
HalJTAGPinCtrlRtl8195A = 0x280d;
|
||||
HalTRACEPinCtrlRtl8195A = 0x2861;
|
||||
HalLOGUartPinCtrlRtl8195A = 0x28b9;
|
||||
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
|
||||
HalSICPinCtrlRtl8195A = 0x2981;
|
||||
HalEEPROMPinCtrlRtl8195A = 0x29d9;
|
||||
HalDEBUGPinCtrlRtl8195A = 0x2a31;
|
||||
HalPinCtrlRtl8195A = 0x2b39;
|
||||
SpicRxCmdRtl8195A = 0x2e5d;
|
||||
SpicWaitBusyDoneRtl8195A = 0x2ea5;
|
||||
SpicGetFlashStatusRtl8195A = 0x2eb5;
|
||||
SpicWaitWipDoneRtl8195A = 0x2f55;
|
||||
SpicTxCmdRtl8195A = 0x2f6d;
|
||||
SpicSetFlashStatusRtl8195A = 0x2fc1;
|
||||
SpicCmpDataForCalibrationRtl8195A = 0x3049;
|
||||
SpicLoadInitParaFromClockRtl8195A = 0x3081;
|
||||
SpicInitRtl8195A = 0x30e5;
|
||||
SpicEraseFlashRtl8195A = 0x31bd;
|
||||
SpiFlashApp = 0x3279;
|
||||
HalPeripheralIntrHandle = 0x33b5;
|
||||
HalSysOnIntrHandle = 0x3439;
|
||||
HalWdgIntrHandle = 0x3485;
|
||||
HalTimer0IntrHandle = 0x34d5;
|
||||
HalTimer1IntrHandle = 0x3525;
|
||||
HalI2C3IntrHandle = 0x3575;
|
||||
HalTimer2To7IntrHandle = 0x35c5;
|
||||
HalSpi0IntrHandle = 0x3615;
|
||||
HalGpioIntrHandle = 0x3665;
|
||||
HalUart0IntrHandle = 0x36b5;
|
||||
HalSpiFlashIntrHandle = 0x3705;
|
||||
HalUsbOtgIntrHandle = 0x3755;
|
||||
HalSdioHostIntrHandle = 0x37a5;
|
||||
HalI2s0OrPcm0IntrHandle = 0x37f5;
|
||||
HalI2s1OrPcm1IntrHandle = 0x3845;
|
||||
HalWlDmaIntrHandle = 0x3895;
|
||||
HalWlProtocolIntrHandle = 0x38e5;
|
||||
HalCryptoIntrHandle = 0x3935;
|
||||
HalGmacIntrHandle = 0x3985;
|
||||
HalGdma0Ch0IntrHandle = 0x39d5;
|
||||
HalGdma0Ch1IntrHandle = 0x3a25;
|
||||
HalGdma0Ch2IntrHandle = 0x3a75;
|
||||
HalGdma0Ch3IntrHandle = 0x3ac5;
|
||||
HalGdma0Ch4IntrHandle = 0x3b15;
|
||||
HalGdma0Ch5IntrHandle = 0x3b65;
|
||||
HalGdma1Ch0IntrHandle = 0x3bb5;
|
||||
HalGdma1Ch1IntrHandle = 0x3c05;
|
||||
HalGdma1Ch2IntrHandle = 0x3c55;
|
||||
HalGdma1Ch3IntrHandle = 0x3ca5;
|
||||
HalGdma1Ch4IntrHandle = 0x3cf5;
|
||||
HalGdma1Ch5IntrHandle = 0x3d45;
|
||||
HalSdioDeviceIntrHandle = 0x3d95;
|
||||
VectorTableInitRtl8195A = 0x3de5;
|
||||
VectorTableInitForOSRtl8195A = 0x4019;
|
||||
VectorIrqRegisterRtl8195A = 0x4029;
|
||||
VectorIrqUnRegisterRtl8195A = 0x4091;
|
||||
VectorIrqEnRtl8195A = 0x40f1;
|
||||
VectorIrqDisRtl8195A = 0x418d;
|
||||
_UartRxDmaIrqHandle = 0x422d;
|
||||
HalRuartPutCRtl8195a = 0x4281;
|
||||
HalRuartGetCRtl8195a = 0x429d;
|
||||
HalRuartRTSCtrlRtl8195a = 0x42bd;
|
||||
HalRuartGetDebugValueRtl8195a = 0x42e1;
|
||||
HalRuartGetIMRRtl8195a = 0x43e1;
|
||||
HalRuartSetIMRRtl8195a = 0x442d;
|
||||
_UartIrqHandle = 0x4465;
|
||||
HalRuartDmaInitRtl8195a = 0x4681;
|
||||
HalRuartIntDisableRtl8195a = 0x4845;
|
||||
HalRuartDeInitRtl8195a = 0x4855;
|
||||
HalRuartIntEnableRtl8195a = 0x4985;
|
||||
_UartTxDmaIrqHandle = 0x4995;
|
||||
HalRuartRegIrqRtl8195a = 0x49d1;
|
||||
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
|
||||
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
|
||||
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
|
||||
RuartLock = 0x4cc9;
|
||||
RuartUnLock = 0x4ced;
|
||||
HalRuartIntSendRtl8195a = 0x4d09;
|
||||
HalRuartDmaSendRtl8195a = 0x4e35;
|
||||
HalRuartStopSendRtl8195a = 0x4f89;
|
||||
HalRuartIntRecvRtl8195a = 0x504d;
|
||||
HalRuartDmaRecvRtl8195a = 0x51ad;
|
||||
HalRuartStopRecvRtl8195a = 0x52cd;
|
||||
RuartIsTimeout = 0x5385;
|
||||
HalRuartSendRtl8195a = 0x53b1;
|
||||
HalRuartRecvRtl8195a = 0x5599;
|
||||
RuartResetRxFifoRtl8195a = 0x5751;
|
||||
HalRuartResetRxFifoRtl8195a = 0x5775;
|
||||
HalRuartInitRtl8195a = 0x5829;
|
||||
HalGdmaOnOffRtl8195a = 0x5df1;
|
||||
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
|
||||
HalGdmaChEnRtl8195a = 0x5e51;
|
||||
HalGdmaChDisRtl8195a = 0x5e6d;
|
||||
HalGdamChInitRtl8195a = 0x5e91;
|
||||
HalGdmaChSetingRtl8195a = 0x5ebd;
|
||||
HalGdmaChIsrCleanRtl8195a = 0x6419;
|
||||
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
|
||||
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
|
||||
HalEFUSEPowerSwitch8195AROM = 0x6561;
|
||||
HALEFUSEOneByteReadROM = 0x65f9;
|
||||
HALEFUSEOneByteWriteROM = 0x6699;
|
||||
__rtl_memcmpb_v1_00 = 0x681d;
|
||||
__rtl_random_v1_00 = 0x6861;
|
||||
__rtl_align_to_be32_v1_00 = 0x6881;
|
||||
__rtl_memsetw_v1_00 = 0x6899;
|
||||
__rtl_memsetb_v1_00 = 0x68ad;
|
||||
__rtl_memcpyw_v1_00 = 0x68bd;
|
||||
__rtl_memcpyb_v1_00 = 0x68dd;
|
||||
__rtl_memDump_v1_00 = 0x68f5;
|
||||
__rtl_AES_set_encrypt_key = 0x6901;
|
||||
__rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
|
||||
__rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
|
||||
__rtl_cryptoEngine_init_v1_00 = 0x6ea9;
|
||||
__rtl_cryptoEngine_exit_v1_00 = 0x7055;
|
||||
__rtl_cryptoEngine_reset_v1_00 = 0x70b1;
|
||||
__rtl_cryptoEngine_v1_00 = 0x70ed;
|
||||
__rtl_crypto_cipher_init_v1_00 = 0x7c69;
|
||||
__rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
|
||||
__rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
|
||||
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
|
||||
HalSsiEnableRtl8195a = 0x7e45;
|
||||
HalSsiDisableRtl8195a = 0x7ef9;
|
||||
HalSsiLoadSettingRtl8195a = 0x7fad;
|
||||
HalSsiSetInterruptMaskRtl8195a = 0x8521;
|
||||
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
|
||||
HalSsiSetSclkPolarityRtl8195a = 0x863d;
|
||||
HalSsiSetSclkPhaseRtl8195a = 0x8715;
|
||||
HalSsiWriteRtl8195a = 0x87e9;
|
||||
HalSsiSetDeviceRoleRtl8195a = 0x8861;
|
||||
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
|
||||
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
|
||||
HalSsiReadRtl8195a = 0x89b9;
|
||||
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
|
||||
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
|
||||
HalSsiGetStatusRtl8195a = 0x8b1d;
|
||||
HalSsiWriteableRtl8195a = 0x8b91;
|
||||
HalSsiReadableRtl8195a = 0x8c09;
|
||||
HalSsiBusyRtl8195a = 0x8c81;
|
||||
HalSsiReadInterruptRtl8195a = 0x8cf9;
|
||||
HalSsiWriteInterruptRtl8195a = 0x8efd;
|
||||
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
|
||||
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
|
||||
HalSsiInterruptEnableRtl8195a = 0x914d;
|
||||
HalSsiInterruptDisableRtl8195a = 0x9299;
|
||||
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
|
||||
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
|
||||
HalSsiInitRtl8195a = 0x94d1;
|
||||
_SsiReadInterrupt = 0x9ba5;
|
||||
_SsiWriteInterrupt = 0x9db1;
|
||||
_SsiIrqHandle = 0x9eb1;
|
||||
HalI2CWrite32 = 0xa061;
|
||||
HalI2CRead32 = 0xa09d;
|
||||
HalI2CDeInit8195a = 0xa0dd;
|
||||
HalI2CSendRtl8195a = 0xa1f1;
|
||||
HalI2CReceiveRtl8195a = 0xa25d;
|
||||
HalI2CEnableRtl8195a = 0xa271;
|
||||
HalI2CIntrCtrl8195a = 0xa389;
|
||||
HalI2CReadRegRtl8195a = 0xa3a1;
|
||||
HalI2CWriteRegRtl8195a = 0xa3b1;
|
||||
HalI2CSetCLKRtl8195a = 0xa3c5;
|
||||
HalI2CMassSendRtl8195a = 0xa6e9;
|
||||
HalI2CClrIntrRtl8195a = 0xa749;
|
||||
HalI2CClrAllIntrRtl8195a = 0xa761;
|
||||
HalI2CInit8195a = 0xa775;
|
||||
HalI2CDMACtrl8195a = 0xaa31;
|
||||
RtkI2CIoCtrl = 0xaa61;
|
||||
RtkI2CPowerCtrl = 0xaa65;
|
||||
HalI2COpInit = 0xaa69;
|
||||
I2CIsTimeout = 0xac65;
|
||||
I2CTXGDMAISRHandle = 0xb435;
|
||||
I2CRXGDMAISRHandle = 0xb4c1;
|
||||
RtkI2CIrqInit = 0xb54d;
|
||||
RtkI2CIrqDeInit = 0xb611;
|
||||
RtkI2CPinMuxInit = 0xb675;
|
||||
RtkI2CPinMuxDeInit = 0xb7c9;
|
||||
RtkI2CDMAInit = 0xb955;
|
||||
RtkI2CInit = 0xbc95;
|
||||
RtkI2CDMADeInit = 0xbdad;
|
||||
RtkI2CDeInit = 0xbe4d;
|
||||
RtkI2CSendUserAddr = 0xbee5;
|
||||
RtkI2CSend = 0xc07d;
|
||||
RtkI2CLoadDefault = 0xce51;
|
||||
RtkSalI2COpInit = 0xcf21;
|
||||
HalI2SWrite32 = 0xcf65;
|
||||
HalI2SRead32 = 0xcf85;
|
||||
HalI2SDeInitRtl8195a = 0xcfa9;
|
||||
HalI2STxRtl8195a = 0xcfc9;
|
||||
HalI2SRxRtl8195a = 0xd011;
|
||||
HalI2SEnableRtl8195a = 0xd05d;
|
||||
HalI2SIntrCtrlRtl8195a = 0xd0b1;
|
||||
HalI2SReadRegRtl8195a = 0xd0d1;
|
||||
HalI2SClrIntrRtl8195a = 0xd0dd;
|
||||
HalI2SClrAllIntrRtl8195a = 0xd0fd;
|
||||
HalI2SInitRtl8195a = 0xd11d;
|
||||
GPIO_GetIPPinName_8195a = 0xd2e5;
|
||||
GPIO_GetChipPinName_8195a = 0xd331;
|
||||
GPIO_PullCtrl_8195a = 0xd39d;
|
||||
GPIO_FuncOn_8195a = 0xd421;
|
||||
GPIO_FuncOff_8195a = 0xd481;
|
||||
GPIO_Int_Mask_8195a = 0xd4e9;
|
||||
GPIO_Int_SetType_8195a = 0xd511;
|
||||
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
|
||||
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
|
||||
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
|
||||
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
|
||||
HAL_GPIO_Init_8195a = 0xd805;
|
||||
HAL_GPIO_DeInit_8195a = 0xdac1;
|
||||
HAL_GPIO_ReadPin_8195a = 0xdbd1;
|
||||
HAL_GPIO_WritePin_8195a = 0xdc91;
|
||||
HAL_GPIO_RegIrq_8195a = 0xddad;
|
||||
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
|
||||
HAL_GPIO_UserRegIrq_8195a = 0xde15;
|
||||
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
|
||||
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
|
||||
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
|
||||
HAL_GPIO_IntDebounce_8195a = 0xe101;
|
||||
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
|
||||
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
|
||||
DumpForOneBytes = 0xe259;
|
||||
CmdRomHelp = 0xe419;
|
||||
CmdWriteWord = 0xe491;
|
||||
CmdDumpHelfWord = 0xe505;
|
||||
CmdDumpWord = 0xe5f1;
|
||||
CmdDumpByte = 0xe6f5;
|
||||
CmdSpiFlashTool = 0xe751;
|
||||
GetRomCmdNum = 0xe7a9;
|
||||
CmdWriteByte = 0xe7ad;
|
||||
Isspace = 0xe7ed;
|
||||
Strtoul = 0xe801;
|
||||
ArrayInitialize = 0xe8b1;
|
||||
GetArgc = 0xe8c9;
|
||||
GetArgv = 0xe8f9;
|
||||
UartLogCmdExecute = 0xe95d;
|
||||
UartLogShowBackSpace = 0xe9fd;
|
||||
UartLogRecallOldCmd = 0xea39;
|
||||
UartLogHistoryCmd = 0xea71;
|
||||
UartLogCmdChk = 0xeadd;
|
||||
UartLogIrqHandle = 0xebf5;
|
||||
RtlConsolInit = 0xecc5;
|
||||
RtlConsolTaskRom = 0xed49;
|
||||
RtlExitConsol = 0xed79;
|
||||
RtlConsolRom = 0xedcd;
|
||||
HalTimerOpInit = 0xee0d;
|
||||
HalTimerIrq2To7Handle = 0xee59;
|
||||
HalGetTimerIdRtl8195a = 0xef09;
|
||||
HalTimerInitRtl8195a = 0xef3d;
|
||||
HalTimerDisRtl8195a = 0xf069;
|
||||
HalTimerEnRtl8195a = 0xf089;
|
||||
HalTimerReadCountRtl8195a = 0xf0a9;
|
||||
HalTimerIrqClearRtl8195a = 0xf0bd;
|
||||
HalTimerDumpRegRtl8195a = 0xf0d1;
|
||||
VSprintf = 0xf129;
|
||||
DiagPrintf = 0xf39d;
|
||||
DiagSPrintf = 0xf3b9;
|
||||
DiagSnPrintf = 0xf3d1;
|
||||
prvDiagPrintf = 0xf3ed;
|
||||
prvDiagSPrintf = 0xf40d;
|
||||
_memcmp = 0xf429;
|
||||
_memcpy = 0xf465;
|
||||
_memset = 0xf511;
|
||||
Rand = 0xf585;
|
||||
_strncpy = 0xf60d;
|
||||
_strcpy = 0xf629;
|
||||
prvStrCpy = 0xf639;
|
||||
_strlen = 0xf651;
|
||||
_strnlen = 0xf669;
|
||||
prvStrLen = 0xf699;
|
||||
_strcmp = 0xf6b1;
|
||||
_strncmp = 0xf6d1;
|
||||
prvStrCmp = 0xf719;
|
||||
StrUpr = 0xf749;
|
||||
prvAtoi = 0xf769;
|
||||
prvStrStr = 0xf7bd;
|
||||
_strsep = 0xf7d5;
|
||||
skip_spaces = 0xf815;
|
||||
skip_atoi = 0xf831;
|
||||
_parse_integer_fixup_radix = 0xf869;
|
||||
_parse_integer = 0xf8bd;
|
||||
simple_strtoull = 0xf915;
|
||||
simple_strtoll = 0xf945;
|
||||
simple_strtoul = 0xf965;
|
||||
simple_strtol = 0xf96d;
|
||||
_vsscanf = 0xf985;
|
||||
_sscanf = 0xff71;
|
||||
div_u64 = 0xff91;
|
||||
div_s64 = 0xff99;
|
||||
div_u64_rem = 0xffa1;
|
||||
div_s64_rem = 0xffb1;
|
||||
_strpbrk = 0xffc1;
|
||||
_strchr = 0xffed;
|
||||
aes_set_key = 0x10005;
|
||||
aes_encrypt = 0x103d1;
|
||||
aes_decrypt = 0x114a5;
|
||||
AES_WRAP = 0x125c9;
|
||||
AES_UnWRAP = 0x12701;
|
||||
crc32_get = 0x12861;
|
||||
arc4_byte = 0x12895;
|
||||
rt_arc4_init = 0x128bd;
|
||||
rt_arc4_crypt = 0x12901;
|
||||
rt_md5_init = 0x131c1;
|
||||
rt_md5_append = 0x131f5;
|
||||
rt_md5_final = 0x1327d;
|
||||
rt_md5_hmac = 0x132d5;
|
||||
rtw_get_bit_value_from_ieee_value = 0x13449;
|
||||
rtw_is_cckrates_included = 0x13475;
|
||||
rtw_is_cckratesonly_included = 0x134b5;
|
||||
rtw_check_network_type = 0x134dd;
|
||||
rtw_set_fixed_ie = 0x1350d;
|
||||
rtw_set_ie = 0x1352d;
|
||||
rtw_get_ie = 0x1355d;
|
||||
rtw_set_supported_rate = 0x13591;
|
||||
rtw_get_rateset_len = 0x13611;
|
||||
rtw_get_wpa_ie = 0x1362d;
|
||||
rtw_get_wpa2_ie = 0x136c9;
|
||||
rtw_get_wpa_cipher_suite = 0x13701;
|
||||
rtw_get_wpa2_cipher_suite = 0x13769;
|
||||
rtw_parse_wpa_ie = 0x137d1;
|
||||
rtw_parse_wpa2_ie = 0x138ad;
|
||||
rtw_get_sec_ie = 0x13965;
|
||||
rtw_get_wps_ie = 0x13a15;
|
||||
rtw_get_wps_attr = 0x13a99;
|
||||
rtw_get_wps_attr_content = 0x13b49;
|
||||
rtw_ieee802_11_parse_elems = 0x13b91;
|
||||
str_2char2num = 0x13d9d;
|
||||
key_2char2num = 0x13db9;
|
||||
convert_ip_addr = 0x13dd1;
|
||||
rom_psk_PasswordHash = 0x13e9d;
|
||||
rom_psk_CalcGTK = 0x13ed5;
|
||||
rom_psk_CalcPTK = 0x13f69;
|
||||
wep_80211_encrypt = 0x14295;
|
||||
wep_80211_decrypt = 0x142f5;
|
||||
tkip_micappendbyte = 0x14389;
|
||||
rtw_secmicsetkey = 0x143d9;
|
||||
rtw_secmicappend = 0x14419;
|
||||
rtw_secgetmic = 0x14435;
|
||||
rtw_seccalctkipmic = 0x1449d;
|
||||
tkip_phase1 = 0x145a5;
|
||||
tkip_phase2 = 0x14725;
|
||||
tkip_80211_encrypt = 0x14941;
|
||||
tkip_80211_decrypt = 0x149d5;
|
||||
aes1_encrypt = 0x14a8d;
|
||||
aesccmp_construct_mic_iv = 0x14c65;
|
||||
aesccmp_construct_mic_header1 = 0x14ccd;
|
||||
aesccmp_construct_mic_header2 = 0x14d21;
|
||||
aesccmp_construct_ctr_preload = 0x14db5;
|
||||
aes_80211_encrypt = 0x14e29;
|
||||
aes_80211_decrypt = 0x151ad;
|
||||
_sha1_process_message_block = 0x155b9;
|
||||
_sha1_pad_message = 0x15749;
|
||||
rt_sha1_init = 0x157e5;
|
||||
rt_sha1_update = 0x15831;
|
||||
rt_sha1_finish = 0x158a9;
|
||||
rt_hmac_sha1 = 0x15909;
|
||||
rom_aes_128_cbc_encrypt = 0x15a65;
|
||||
rom_aes_128_cbc_decrypt = 0x15ae1;
|
||||
rom_rijndaelKeySetupEnc = 0x15b5d;
|
||||
rom_aes_decrypt_init = 0x15c39;
|
||||
rom_aes_internal_decrypt = 0x15d15;
|
||||
rom_aes_decrypt_deinit = 0x16071;
|
||||
rom_aes_encrypt_init = 0x16085;
|
||||
rom_aes_internal_encrypt = 0x1609d;
|
||||
rom_aes_encrypt_deinit = 0x16451;
|
||||
bignum_init = 0x17b35;
|
||||
bignum_deinit = 0x17b61;
|
||||
bignum_get_unsigned_bin_len = 0x17b81;
|
||||
bignum_get_unsigned_bin = 0x17b85;
|
||||
bignum_set_unsigned_bin = 0x17c21;
|
||||
bignum_cmp = 0x17cd1;
|
||||
bignum_cmp_d = 0x17cd5;
|
||||
bignum_add = 0x17cfd;
|
||||
bignum_sub = 0x17d0d;
|
||||
bignum_mul = 0x17d1d;
|
||||
bignum_exptmod = 0x17d2d;
|
||||
WPS_realloc = 0x17d51;
|
||||
os_zalloc = 0x17d99;
|
||||
rom_hmac_sha256_vector = 0x17dc1;
|
||||
rom_hmac_sha256 = 0x17ebd;
|
||||
rom_sha256_vector = 0x18009;
|
||||
phy_CalculateBitShift = 0x18221;
|
||||
PHY_SetBBReg_8195A = 0x18239;
|
||||
PHY_QueryBBReg_8195A = 0x18279;
|
||||
ROM_odm_QueryRxPwrPercentage = 0x1829d;
|
||||
ROM_odm_EVMdbToPercentage = 0x182bd;
|
||||
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
|
||||
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
|
||||
ROM_odm_SetEDCCAThreshold = 0x18721;
|
||||
ROM_odm_SetTRxMux = 0x18749;
|
||||
ROM_odm_SetCrystalCap = 0x18771;
|
||||
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
|
||||
ROM_ODM_CfoTrackingReset = 0x187e9;
|
||||
ROM_odm_CfoTrackingFlow = 0x18811;
|
||||
curve25519_donna = 0x1965d;
|
||||
aes_test_alignment_detection = 0x1a391;
|
||||
aes_mode_reset = 0x1a3ed;
|
||||
aes_ecb_encrypt = 0x1a3f9;
|
||||
aes_ecb_decrypt = 0x1a431;
|
||||
aes_cbc_encrypt = 0x1a469;
|
||||
aes_cbc_decrypt = 0x1a579;
|
||||
aes_cfb_encrypt = 0x1a701;
|
||||
aes_cfb_decrypt = 0x1a9e5;
|
||||
aes_ofb_crypt = 0x1acc9;
|
||||
aes_ctr_crypt = 0x1af7d;
|
||||
aes_encrypt_key128 = 0x1b289;
|
||||
aes_encrypt_key192 = 0x1b2a5;
|
||||
aes_encrypt_key256 = 0x1b2c1;
|
||||
aes_encrypt_key = 0x1b2e1;
|
||||
aes_decrypt_key128 = 0x1b351;
|
||||
aes_decrypt_key192 = 0x1b36d;
|
||||
aes_decrypt_key256 = 0x1b389;
|
||||
aes_decrypt_key = 0x1b3a9;
|
||||
aes_init = 0x1b419;
|
||||
CRYPTO_chacha_20 = 0x1b41d;
|
||||
CRYPTO_poly1305_init = 0x1bc25;
|
||||
CRYPTO_poly1305_update = 0x1bd09;
|
||||
CRYPTO_poly1305_finish = 0x1bd8d;
|
||||
rom_sha512_starts = 0x1ceb5;
|
||||
rom_sha512_update = 0x1d009;
|
||||
rom_sha512_finish = 0x1d011;
|
||||
rom_sha512 = 0x1d261;
|
||||
rom_sha512_hmac_starts = 0x1d299;
|
||||
rom_sha512_hmac_update = 0x1d35d;
|
||||
rom_sha512_hmac_finish = 0x1d365;
|
||||
rom_sha512_hmac_reset = 0x1d3b5;
|
||||
rom_sha512_hmac = 0x1d3d1;
|
||||
rom_sha512_hkdf = 0x1d40d;
|
||||
rom_ed25519_gen_keypair = 0x1d501;
|
||||
rom_ed25519_gen_signature = 0x1d505;
|
||||
rom_ed25519_verify_signature = 0x1d51d;
|
||||
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
|
||||
rom_ed25519_crypto_sign_detached = 0x1d579;
|
||||
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
|
||||
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
|
||||
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
|
||||
rom_ed25519_ge_p3_tobytes = 0x207d5;
|
||||
rom_ed25519_ge_scalarmult_base = 0x20821;
|
||||
rom_ed25519_ge_tobytes = 0x209e1;
|
||||
rom_ed25519_sc_muladd = 0x20a2d;
|
||||
rom_ed25519_sc_reduce = 0x2603d;
|
||||
__rtl_memchr_v1_00 = 0x28a4d;
|
||||
__rtl_memcmp_v1_00 = 0x28ae1;
|
||||
__rtl_memcpy_v1_00 = 0x28b49;
|
||||
__rtl_memmove_v1_00 = 0x28bed;
|
||||
__rtl_memset_v1_00 = 0x28cb5;
|
||||
__rtl_strcat_v1_00 = 0x28d49;
|
||||
__rtl_strchr_v1_00 = 0x28d91;
|
||||
__rtl_strcmp_v1_00 = 0x28e55;
|
||||
__rtl_strcpy_v1_00 = 0x28ec9;
|
||||
__rtl_strlen_v1_00 = 0x28f15;
|
||||
__rtl_strncat_v1_00 = 0x28f69;
|
||||
__rtl_strncmp_v1_00 = 0x28fc5;
|
||||
__rtl_strncpy_v1_00 = 0x2907d;
|
||||
__rtl_strstr_v1_00 = 0x293cd;
|
||||
__rtl_strsep_v1_00 = 0x2960d;
|
||||
__rtl_strtok_v1_00 = 0x29619;
|
||||
__rtl__strtok_r_v1_00 = 0x2962d;
|
||||
__rtl_strtok_r_v1_00 = 0x29691;
|
||||
__rtl_close_v1_00 = 0x29699;
|
||||
__rtl_fstat_v1_00 = 0x296ad;
|
||||
__rtl_isatty_v1_00 = 0x296c1;
|
||||
__rtl_lseek_v1_00 = 0x296d5;
|
||||
__rtl_open_v1_00 = 0x296e9;
|
||||
__rtl_read_v1_00 = 0x296fd;
|
||||
__rtl_write_v1_00 = 0x29711;
|
||||
__rtl_sbrk_v1_00 = 0x29725;
|
||||
__rtl_ltoa_v1_00 = 0x297bd;
|
||||
__rtl_ultoa_v1_00 = 0x29855;
|
||||
__rtl_dtoi_v1_00 = 0x298c5;
|
||||
__rtl_dtoi64_v1_00 = 0x29945;
|
||||
__rtl_dtoui_v1_00 = 0x299dd;
|
||||
__rtl_ftol_v1_00 = 0x299e5;
|
||||
__rtl_itof_v1_00 = 0x29a51;
|
||||
__rtl_itod_v1_00 = 0x29ae9;
|
||||
__rtl_i64tod_v1_00 = 0x29b79;
|
||||
__rtl_uitod_v1_00 = 0x29c55;
|
||||
__rtl_ftod_v1_00 = 0x29d2d;
|
||||
__rtl_dtof_v1_00 = 0x29de9;
|
||||
__rtl_uitof_v1_00 = 0x29e89;
|
||||
__rtl_fadd_v1_00 = 0x29f65;
|
||||
__rtl_fsub_v1_00 = 0x2a261;
|
||||
__rtl_fmul_v1_00 = 0x2a559;
|
||||
__rtl_fdiv_v1_00 = 0x2a695;
|
||||
__rtl_dadd_v1_00 = 0x2a825;
|
||||
__rtl_dsub_v1_00 = 0x2aed9;
|
||||
__rtl_dmul_v1_00 = 0x2b555;
|
||||
__rtl_ddiv_v1_00 = 0x2b8ad;
|
||||
__rtl_dcmpeq_v1_00 = 0x2be4d;
|
||||
__rtl_dcmplt_v1_00 = 0x2bebd;
|
||||
__rtl_dcmpgt_v1_00 = 0x2bf51;
|
||||
__rtl_dcmple_v1_00 = 0x2c049;
|
||||
__rtl_fcmplt_v1_00 = 0x2c139;
|
||||
__rtl_fcmpgt_v1_00 = 0x2c195;
|
||||
__rtl_cos_f32_v1_00 = 0x2c229;
|
||||
__rtl_sin_f32_v1_00 = 0x2c435;
|
||||
__rtl_fabs_v1_00 = 0x2c639;
|
||||
__rtl_fabsf_v1_00 = 0x2c641;
|
||||
__rtl_dtoa_r_v1_00 = 0x2c77d;
|
||||
__rom_mallocr_init_v1_00 = 0x2d7d1;
|
||||
__rtl_free_r_v1_00 = 0x2d841;
|
||||
__rtl_malloc_r_v1_00 = 0x2da31;
|
||||
__rtl_realloc_r_v1_00 = 0x2df55;
|
||||
__rtl_memalign_r_v1_00 = 0x2e331;
|
||||
__rtl_valloc_r_v1_00 = 0x2e421;
|
||||
__rtl_pvalloc_r_v1_00 = 0x2e42d;
|
||||
__rtl_calloc_r_v1_00 = 0x2e441;
|
||||
__rtl_cfree_r_v1_00 = 0x2e4a9;
|
||||
__rtl_Balloc_v1_00 = 0x2e515;
|
||||
__rtl_Bfree_v1_00 = 0x2e571;
|
||||
__rtl_i2b_v1_00 = 0x2e585;
|
||||
__rtl_multadd_v1_00 = 0x2e599;
|
||||
__rtl_mult_v1_00 = 0x2e629;
|
||||
__rtl_pow5mult_v1_00 = 0x2e769;
|
||||
__rtl_hi0bits_v1_00 = 0x2e809;
|
||||
__rtl_d2b_v1_00 = 0x2e845;
|
||||
__rtl_lshift_v1_00 = 0x2e901;
|
||||
__rtl_cmp_v1_00 = 0x2e9bd;
|
||||
__rtl_diff_v1_00 = 0x2ea01;
|
||||
__rtl_sread_v1_00 = 0x2eae9;
|
||||
__rtl_seofread_v1_00 = 0x2eb39;
|
||||
__rtl_swrite_v1_00 = 0x2eb3d;
|
||||
__rtl_sseek_v1_00 = 0x2ebc1;
|
||||
__rtl_sclose_v1_00 = 0x2ec11;
|
||||
__rtl_sbrk_r_v1_00 = 0x2ec41;
|
||||
__rtl_fflush_r_v1_00 = 0x2ef8d;
|
||||
__rtl_vfprintf_r_v1_00 = 0x2f661;
|
||||
__rtl_fpclassifyd = 0x30c15;
|
||||
CpkClkTbl = 0x30c68;
|
||||
ROM_IMG1_VALID_PATTEN = 0x30c80;
|
||||
SpicCalibrationPattern = 0x30c88;
|
||||
SpicInitCPUCLK = 0x30c98;
|
||||
BAUDRATE = 0x30ca8;
|
||||
OVSR = 0x30d1c;
|
||||
DIV = 0x30d90;
|
||||
OVSR_ADJ = 0x30e04;
|
||||
__AES_rcon = 0x30e78;
|
||||
__AES_Te4 = 0x30ea0;
|
||||
I2CDmaChNo = 0x312a0;
|
||||
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
|
||||
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
|
||||
_GPIO_SWPORT_DDR_TBL = 0x31594;
|
||||
_GPIO_EXT_PORT_TBL = 0x31598;
|
||||
_GPIO_SWPORT_DR_TBL = 0x3159c;
|
||||
UartLogRomCmdTable = 0x316a0;
|
||||
_HalRuartOp = 0x31700;
|
||||
_HalGdmaOp = 0x31760;
|
||||
RTW_WPA_OUI_TYPE = 0x3540c;
|
||||
WPA_CIPHER_SUITE_NONE = 0x35410;
|
||||
WPA_CIPHER_SUITE_WEP40 = 0x35414;
|
||||
WPA_CIPHER_SUITE_TKIP = 0x35418;
|
||||
WPA_CIPHER_SUITE_CCMP = 0x3541c;
|
||||
WPA_CIPHER_SUITE_WEP104 = 0x35420;
|
||||
RSN_CIPHER_SUITE_NONE = 0x35424;
|
||||
RSN_CIPHER_SUITE_WEP40 = 0x35428;
|
||||
RSN_CIPHER_SUITE_TKIP = 0x3542c;
|
||||
RSN_CIPHER_SUITE_CCMP = 0x35430;
|
||||
RSN_CIPHER_SUITE_WEP104 = 0x35434;
|
||||
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
|
||||
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
|
||||
RSN_VERSION_BSD = 0x3544c;
|
||||
rom_wps_Te0 = 0x35988;
|
||||
rom_wps_rcons = 0x35d88;
|
||||
rom_wps_Td4s = 0x35d94;
|
||||
rom_wps_Td0 = 0x35e94;
|
||||
__rom_b_cut_end__ = 0x4467c;
|
||||
__rom_c_cut_text_start__ = 0x4467c;
|
||||
HalInitPlatformLogUartV02 = 0x4467d;
|
||||
HalReInitPlatformLogUartV02 = 0x4471d;
|
||||
HalInitPlatformTimerV02 = 0x44755;
|
||||
HalShowBuildInfoV02 = 0x447cd;
|
||||
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
|
||||
HalSpiInitV02 = 0x4488d;
|
||||
HalBootFlowV02 = 0x44a29;
|
||||
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
|
||||
HalResetVsrV02 = 0x44b41;
|
||||
HalI2CSendRtl8195aV02 = 0x44ce1;
|
||||
HalI2CSetCLKRtl8195aV02 = 0x44d59;
|
||||
RtkI2CSendV02 = 0x4508d;
|
||||
RtkI2CReceiveV02 = 0x459a1;
|
||||
HalI2COpInitV02 = 0x461ed;
|
||||
I2CISRHandleV02 = 0x463e9;
|
||||
RtkSalI2COpInitV02 = 0x46be1;
|
||||
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
|
||||
SpiFlashAppV02 = 0x46c85;
|
||||
SpicInitRtl8195AV02 = 0x46dc5;
|
||||
SpicEraseFlashRtl8195AV02 = 0x46ea1;
|
||||
HalTimerIrq2To7HandleV02 = 0x46f5d;
|
||||
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
|
||||
HalTimerInitRtl8195aV02 = 0x4706d;
|
||||
HalTimerReadCountRtl8195aV02 = 0x471b5;
|
||||
HalTimerReLoadRtl8195aV02 = 0x471d1;
|
||||
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
|
||||
HalTimerDeInitRtl8195aV02 = 0x472c1;
|
||||
HalTimerOpInitV02 = 0x472f9;
|
||||
GPIO_LockV02 = 0x47345;
|
||||
GPIO_UnLockV02 = 0x47379;
|
||||
GPIO_Int_Clear_8195aV02 = 0x473a5;
|
||||
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
|
||||
FindElementIndexV02 = 0x47541;
|
||||
HalRuartInitRtl8195aV02 = 0x4756d;
|
||||
DramInit_rom = 0x47619;
|
||||
ChangeRandSeed_rom = 0x47979;
|
||||
Sdr_Rand2_rom = 0x47985;
|
||||
MemTest_rom = 0x479dd;
|
||||
SdrCalibration_rom = 0x47a45;
|
||||
SdrControllerInit_rom = 0x47d99;
|
||||
SDIO_EnterCritical = 0x47e39;
|
||||
SDIO_ExitCritical = 0x47e85;
|
||||
SDIO_IRQ_Handler_Rom = 0x47ec5;
|
||||
SDIO_Interrupt_Init_Rom = 0x47f31;
|
||||
SDIO_Device_Init_Rom = 0x47f81;
|
||||
SDIO_Interrupt_DeInit_Rom = 0x48215;
|
||||
SDIO_Device_DeInit_Rom = 0x48255;
|
||||
SDIO_Enable_Interrupt_Rom = 0x48281;
|
||||
SDIO_Disable_Interrupt_Rom = 0x482a1;
|
||||
SDIO_Clear_ISR_Rom = 0x482c1;
|
||||
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
|
||||
SDIO_Free_Rx_Pkt_Rom = 0x48331;
|
||||
SDIO_Recycle_Rx_BD_Rom = 0x48355;
|
||||
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
|
||||
SDIO_RxTask_Rom = 0x4851d;
|
||||
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
|
||||
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
|
||||
SDIO_Process_RPWM_Rom = 0x485b5;
|
||||
SDIO_Reset_Cmd_Rom = 0x485e9;
|
||||
SDIO_Rx_Data_Transaction_Rom = 0x48611;
|
||||
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
|
||||
SDIO_Register_Tx_Callback_Rom = 0x488f5;
|
||||
SDIO_ReadMem_Rom = 0x488fd;
|
||||
SDIO_WriteMem_Rom = 0x489a9;
|
||||
SDIO_SetMem_Rom = 0x48a69;
|
||||
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
|
||||
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
|
||||
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
|
||||
SDIO_TxTask_Rom = 0x48e9d;
|
||||
SDIO_TaskUp_Rom = 0x48eed;
|
||||
SDIO_Boot_Up = 0x48f55;
|
||||
__rom_c_cut_text_end__ = 0x49070;
|
||||
__rom_c_cut_rodata_start__ = 0x49070;
|
||||
BAUDRATE_v02 = 0x49070;
|
||||
OVSR_v02 = 0x490fc;
|
||||
DIV_v02 = 0x49188;
|
||||
OVSR_ADJ_v02 = 0x49214;
|
||||
SdrDramInfo_rom = 0x492a0;
|
||||
SdrDramTiming_rom = 0x492b4;
|
||||
SdrDramModeReg_rom = 0x492e8;
|
||||
SdrDramDev_rom = 0x49304;
|
||||
__rom_c_cut_rodata_end__ = 0x49314;
|
||||
NewVectorTable = 0x10000000;
|
||||
UserhandlerTable = 0x10000100;
|
||||
UserIrqDataTable = 0x10000200;
|
||||
__rom_bss_start__ = 0x10000300;
|
||||
CfgSysDebugWarn = 0x10000300;
|
||||
CfgSysDebugInfo = 0x10000304;
|
||||
CfgSysDebugErr = 0x10000308;
|
||||
ConfigDebugWarn = 0x1000030c;
|
||||
ConfigDebugInfo = 0x10000310;
|
||||
ConfigDebugErr = 0x10000314;
|
||||
HalTimerOp = 0x10000318;
|
||||
GPIOState = 0x10000334;
|
||||
gTimerRecord = 0x1000034c;
|
||||
SSI_DBG_CONFIG = 0x10000350;
|
||||
_pHAL_Gpio_Adapter = 0x10000354;
|
||||
Timer2To7VectorTable = 0x10000358;
|
||||
pUartLogCtl = 0x10000384;
|
||||
UartLogBuf = 0x10000388;
|
||||
UartLogCtl = 0x10000408;
|
||||
UartLogHistoryBuf = 0x10000430;
|
||||
ArgvArray = 0x100006ac;
|
||||
rom_wlan_ram_map = 0x100006d4;
|
||||
FalseAlmCnt = 0x100006e0;
|
||||
ROMInfo = 0x10000720;
|
||||
DM_CfoTrack = 0x10000738;
|
||||
rom_libgloss_ram_map = 0x10000760;
|
||||
__rtl_errno = 0x10000bc4;
|
||||
}
|
||||
Loading…
Reference in New Issue