mirror of https://github.com/ARMmbed/mbed-os.git
STM32L496ZG add IAR toolchain
Pierre-Marie Ancele
parent
dc2f29c86e
commit
eea667567e
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@ -0,0 +1,549 @@
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/**
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******************************************************************************
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* @file startup_stm32l496xx.s
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* @author MCD Application Team
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* @version V1.1.1
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* @date 29-April-2016
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* @brief STM32L496xx devices vector table GCC toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address,
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* - Configure the clock system
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M4 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m4
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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.equ BootRAM, 0xF1E0F85F
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr sp, =_estack /* Atollic update: set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors */
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//bl __libc_init_array
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/* Call the application's entry point.*/
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//bl main
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// Calling the crt0 'cold-start' entry point. There __libc_init_array is called
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// and when existing hardware_init_hook() and software_init_hook() before
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// starting main(). software_init_hook() is available and has to be called due
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// to initializsation when using rtos.
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bl _start
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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*
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* @param None
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* @retval : None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex-M4. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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.word WWDG_IRQHandler
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.word PVD_PVM_IRQHandler
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.word TAMP_STAMP_IRQHandler
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.word RTC_WKUP_IRQHandler
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.word FLASH_IRQHandler
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.word RCC_IRQHandler
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.word EXTI0_IRQHandler
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.word EXTI1_IRQHandler
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.word EXTI2_IRQHandler
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.word EXTI3_IRQHandler
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.word EXTI4_IRQHandler
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.word DMA1_Channel1_IRQHandler
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.word DMA1_Channel2_IRQHandler
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.word DMA1_Channel3_IRQHandler
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.word DMA1_Channel4_IRQHandler
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.word DMA1_Channel5_IRQHandler
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.word DMA1_Channel6_IRQHandler
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.word DMA1_Channel7_IRQHandler
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.word ADC1_2_IRQHandler
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.word CAN1_TX_IRQHandler
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.word CAN1_RX0_IRQHandler
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.word CAN1_RX1_IRQHandler
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.word CAN1_SCE_IRQHandler
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.word EXTI9_5_IRQHandler
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.word TIM1_BRK_TIM15_IRQHandler
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.word TIM1_UP_TIM16_IRQHandler
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.word TIM1_TRG_COM_TIM17_IRQHandler
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.word TIM1_CC_IRQHandler
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.word TIM2_IRQHandler
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.word TIM3_IRQHandler
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.word TIM4_IRQHandler
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.word I2C1_EV_IRQHandler
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.word I2C1_ER_IRQHandler
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.word I2C2_EV_IRQHandler
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.word I2C2_ER_IRQHandler
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.word SPI1_IRQHandler
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.word SPI2_IRQHandler
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.word USART1_IRQHandler
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.word USART2_IRQHandler
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.word USART3_IRQHandler
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.word EXTI15_10_IRQHandler
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.word RTC_Alarm_IRQHandler
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.word DFSDM1_FLT3_IRQHandler
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.word TIM8_BRK_IRQHandler
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.word TIM8_UP_IRQHandler
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.word TIM8_TRG_COM_IRQHandler
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.word TIM8_CC_IRQHandler
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.word ADC3_IRQHandler
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.word FMC_IRQHandler
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.word SDMMC1_IRQHandler
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.word TIM5_IRQHandler
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.word SPI3_IRQHandler
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.word UART4_IRQHandler
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.word UART5_IRQHandler
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.word TIM6_DAC_IRQHandler
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.word TIM7_IRQHandler
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.word DMA2_Channel1_IRQHandler
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.word DMA2_Channel2_IRQHandler
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.word DMA2_Channel3_IRQHandler
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.word DMA2_Channel4_IRQHandler
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.word DMA2_Channel5_IRQHandler
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.word DFSDM1_FLT0_IRQHandler
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.word DFSDM1_FLT1_IRQHandler
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.word DFSDM1_FLT2_IRQHandler
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.word COMP_IRQHandler
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.word LPTIM1_IRQHandler
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.word LPTIM2_IRQHandler
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.word OTG_FS_IRQHandler
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.word DMA2_Channel6_IRQHandler
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.word DMA2_Channel7_IRQHandler
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.word LPUART1_IRQHandler
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.word QUADSPI_IRQHandler
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.word I2C3_EV_IRQHandler
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.word I2C3_ER_IRQHandler
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.word SAI1_IRQHandler
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.word SAI2_IRQHandler
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.word SWPMI1_IRQHandler
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.word TSC_IRQHandler
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.word LCD_IRQHandler
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.word 0
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.word RNG_IRQHandler
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.word FPU_IRQHandler
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.word CRS_IRQHandler
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.word I2C4_EV_IRQHandler
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.word I2C4_ER_IRQHandler
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.word DCMI_IRQHandler
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.word CAN2_TX_IRQHandler
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.word CAN2_RX0_IRQHandler
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.word CAN2_RX1_IRQHandler
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.word CAN2_SCE_IRQHandler
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.word DMA2D_IRQHandler
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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.weak NMI_Handler
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.thumb_set NMI_Handler,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler,Default_Handler
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.weak MemManage_Handler
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.thumb_set MemManage_Handler,Default_Handler
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.weak BusFault_Handler
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.thumb_set BusFault_Handler,Default_Handler
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.weak UsageFault_Handler
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.thumb_set UsageFault_Handler,Default_Handler
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.weak SVC_Handler
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.thumb_set SVC_Handler,Default_Handler
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.weak DebugMon_Handler
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.thumb_set DebugMon_Handler,Default_Handler
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.weak PendSV_Handler
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.thumb_set PendSV_Handler,Default_Handler
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.weak SysTick_Handler
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.thumb_set SysTick_Handler,Default_Handler
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.weak WWDG_IRQHandler
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.thumb_set WWDG_IRQHandler,Default_Handler
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.weak PVD_PVM_IRQHandler
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.thumb_set PVD_PVM_IRQHandler,Default_Handler
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.weak TAMP_STAMP_IRQHandler
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.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
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.weak RTC_WKUP_IRQHandler
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.thumb_set RTC_WKUP_IRQHandler,Default_Handler
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.weak FLASH_IRQHandler
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.thumb_set FLASH_IRQHandler,Default_Handler
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.weak RCC_IRQHandler
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.thumb_set RCC_IRQHandler,Default_Handler
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.weak EXTI0_IRQHandler
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.thumb_set EXTI0_IRQHandler,Default_Handler
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.weak EXTI1_IRQHandler
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.thumb_set EXTI1_IRQHandler,Default_Handler
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.weak EXTI2_IRQHandler
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.thumb_set EXTI2_IRQHandler,Default_Handler
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.weak EXTI3_IRQHandler
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.thumb_set EXTI3_IRQHandler,Default_Handler
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.weak EXTI4_IRQHandler
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.thumb_set EXTI4_IRQHandler,Default_Handler
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.weak DMA1_Channel1_IRQHandler
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.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
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.weak DMA1_Channel2_IRQHandler
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.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
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.weak DMA1_Channel3_IRQHandler
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.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
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.weak DMA1_Channel4_IRQHandler
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.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
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.weak DMA1_Channel5_IRQHandler
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.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
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.weak DMA1_Channel6_IRQHandler
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.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
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.weak DMA1_Channel7_IRQHandler
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.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
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.weak ADC1_2_IRQHandler
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.thumb_set ADC1_2_IRQHandler,Default_Handler
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.weak CAN1_TX_IRQHandler
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.thumb_set CAN1_TX_IRQHandler,Default_Handler
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.weak CAN1_RX0_IRQHandler
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.thumb_set CAN1_RX0_IRQHandler,Default_Handler
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.weak CAN1_RX1_IRQHandler
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.thumb_set CAN1_RX1_IRQHandler,Default_Handler
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.weak CAN1_SCE_IRQHandler
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.thumb_set CAN1_SCE_IRQHandler,Default_Handler
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.weak EXTI9_5_IRQHandler
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.thumb_set EXTI9_5_IRQHandler,Default_Handler
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.weak TIM1_BRK_TIM15_IRQHandler
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.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
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.weak TIM1_UP_TIM16_IRQHandler
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.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
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.weak TIM1_TRG_COM_TIM17_IRQHandler
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.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
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.weak TIM1_CC_IRQHandler
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.thumb_set TIM1_CC_IRQHandler,Default_Handler
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.weak TIM2_IRQHandler
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.thumb_set TIM2_IRQHandler,Default_Handler
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.weak TIM3_IRQHandler
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.thumb_set TIM3_IRQHandler,Default_Handler
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.weak TIM4_IRQHandler
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.thumb_set TIM4_IRQHandler,Default_Handler
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.weak I2C1_EV_IRQHandler
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.thumb_set I2C1_EV_IRQHandler,Default_Handler
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.weak I2C1_ER_IRQHandler
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.thumb_set I2C1_ER_IRQHandler,Default_Handler
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.weak I2C2_EV_IRQHandler
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.thumb_set I2C2_EV_IRQHandler,Default_Handler
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.weak I2C2_ER_IRQHandler
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.thumb_set I2C2_ER_IRQHandler,Default_Handler
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.weak SPI1_IRQHandler
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.thumb_set SPI1_IRQHandler,Default_Handler
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.weak SPI2_IRQHandler
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.thumb_set SPI2_IRQHandler,Default_Handler
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.weak USART1_IRQHandler
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.thumb_set USART1_IRQHandler,Default_Handler
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.weak USART2_IRQHandler
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.thumb_set USART2_IRQHandler,Default_Handler
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.weak USART3_IRQHandler
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.thumb_set USART3_IRQHandler,Default_Handler
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.weak EXTI15_10_IRQHandler
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.thumb_set EXTI15_10_IRQHandler,Default_Handler
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.weak RTC_Alarm_IRQHandler
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.thumb_set RTC_Alarm_IRQHandler,Default_Handler
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.weak DFSDM1_FLT3_IRQHandler
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.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
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.weak TIM8_BRK_IRQHandler
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.thumb_set TIM8_BRK_IRQHandler,Default_Handler
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.weak TIM8_UP_IRQHandler
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.thumb_set TIM8_UP_IRQHandler,Default_Handler
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.weak TIM8_TRG_COM_IRQHandler
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.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
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.weak TIM8_CC_IRQHandler
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.thumb_set TIM8_CC_IRQHandler,Default_Handler
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.weak ADC3_IRQHandler
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.thumb_set ADC3_IRQHandler,Default_Handler
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.weak FMC_IRQHandler
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.thumb_set FMC_IRQHandler,Default_Handler
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.weak SDMMC1_IRQHandler
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.thumb_set SDMMC1_IRQHandler,Default_Handler
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.weak TIM5_IRQHandler
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.thumb_set TIM5_IRQHandler,Default_Handler
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.weak SPI3_IRQHandler
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.thumb_set SPI3_IRQHandler,Default_Handler
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.weak UART4_IRQHandler
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.thumb_set UART4_IRQHandler,Default_Handler
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.weak UART5_IRQHandler
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.thumb_set UART5_IRQHandler,Default_Handler
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.weak TIM6_DAC_IRQHandler
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.thumb_set TIM6_DAC_IRQHandler,Default_Handler
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.weak TIM7_IRQHandler
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.thumb_set TIM7_IRQHandler,Default_Handler
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.weak DMA2_Channel1_IRQHandler
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.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
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.weak DMA2_Channel2_IRQHandler
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.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
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.weak DMA2_Channel3_IRQHandler
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.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
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.weak DMA2_Channel4_IRQHandler
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.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
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.weak DMA2_Channel5_IRQHandler
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.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
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.weak DFSDM1_FLT0_IRQHandler
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.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
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.weak DFSDM1_FLT1_IRQHandler
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.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
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.weak DFSDM1_FLT2_IRQHandler
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.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
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.weak COMP_IRQHandler
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.thumb_set COMP_IRQHandler,Default_Handler
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.weak LPTIM1_IRQHandler
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.thumb_set LPTIM1_IRQHandler,Default_Handler
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.weak LPTIM2_IRQHandler
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.thumb_set LPTIM2_IRQHandler,Default_Handler
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.weak OTG_FS_IRQHandler
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.thumb_set OTG_FS_IRQHandler,Default_Handler
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.weak DMA2_Channel6_IRQHandler
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.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
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.weak DMA2_Channel7_IRQHandler
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.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
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.weak LPUART1_IRQHandler
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.thumb_set LPUART1_IRQHandler,Default_Handler
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.weak QUADSPI_IRQHandler
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.thumb_set QUADSPI_IRQHandler,Default_Handler
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.weak I2C3_EV_IRQHandler
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.thumb_set I2C3_EV_IRQHandler,Default_Handler
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||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak SWPMI1_IRQHandler
|
||||
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TSC_IRQHandler
|
||||
.thumb_set TSC_IRQHandler,Default_Handler
|
||||
|
||||
.weak LCD_IRQHandler
|
||||
.thumb_set LCD_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_EV_IRQHandler
|
||||
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_ER_IRQHandler
|
||||
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_IRQHandler
|
||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_TX_IRQHandler
|
||||
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX0_IRQHandler
|
||||
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX1_IRQHandler
|
||||
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_SCE_IRQHandler
|
||||
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||
define symbol __ICFEDIT_region_ROM_TARA_start__ = 0x08080000; /* TARA Lite Demo */
|
||||
define symbol __ICFEDIT_region_ROM_TARA_end__ = 0x080BFFFF;
|
||||
define symbol __ICFEDIT_region_ROM_TGFX_start__ = 0x080C0000; /* TGFX Lite Demo */
|
||||
define symbol __ICFEDIT_region_ROM_TGFX_end__ = 0x080FE7FF;
|
||||
define symbol __ICFEDIT_region_ROM_While1_start__ = 0x080FE800;
|
||||
define symbol __ICFEDIT_region_ROM_While1_end__ = 0x080FFDFF;
|
||||
define symbol __ICFEDIT_calibration_data_start__ = 0x080FFE00;
|
||||
define symbol __ICFEDIT_calibration_data_end__ = 0x080FFFFF;
|
||||
/*-Quad-SPI Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_QSPI_start__ = 0x90000000;
|
||||
define symbol __ICFEDIT_region_QSPI_end__ = 0x9013FFFF; /* 1.3 Mbytes for STemWin */
|
||||
define symbol __ICFEDIT_region_QSPI_TARA_start__ = 0x90140000;
|
||||
define symbol __ICFEDIT_region_QSPI_TARA_end__ = 0x90499FFF; /* 3.4 Mbytes for third parties demo */
|
||||
define symbol __ICFEDIT_region_QSPI_TGFX_start__ = 0x9049A000;
|
||||
define symbol __ICFEDIT_region_QSPI_TGFX_end__ = 0x907FFFFF; /* 3.3 Mbytes for third parties demo */
|
||||
|
||||
define symbol __ICFEDIT_region_SRAM1_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_SRAM1_end__ = 0x2003FFFF;
|
||||
define symbol __ICFEDIT_region_SRAM2_start__ = 0x10000000;
|
||||
define symbol __ICFEDIT_region_SRAM2_end__ = 0x1000FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x2000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region ROM_TARA_region = mem:[from __ICFEDIT_region_ROM_TARA_start__ to __ICFEDIT_region_ROM_TARA_end__];
|
||||
define region ROM_TGFX_region = mem:[from __ICFEDIT_region_ROM_TGFX_start__ to __ICFEDIT_region_ROM_TGFX_end__];
|
||||
define region ROM_While1_region = mem:[from __ICFEDIT_region_ROM_While1_start__ to __ICFEDIT_region_ROM_While1_end__];
|
||||
define region QSPI_region = mem:[from __ICFEDIT_region_QSPI_start__ to __ICFEDIT_region_QSPI_end__];
|
||||
define region QSPI_TARA_region = mem:[from __ICFEDIT_region_QSPI_TARA_start__ to __ICFEDIT_region_QSPI_TARA_end__];
|
||||
define region QSPI_TGFX_region = mem:[from __ICFEDIT_region_QSPI_TGFX_start__ to __ICFEDIT_region_QSPI_TGFX_end__];
|
||||
define region SRAM1_region = mem:[from __ICFEDIT_region_SRAM1_start__ to __ICFEDIT_region_SRAM1_end__];
|
||||
define region SRAM2_region = mem:[from __ICFEDIT_region_SRAM2_start__ to __ICFEDIT_region_SRAM2_end__];
|
||||
|
||||
define region calibration_region = mem:[from __ICFEDIT_calibration_data_start__ to __ICFEDIT_calibration_data_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in ROM_TARA_region { section TARAFlashSection };
|
||||
place in ROM_TGFX_region { section TGFXFlashSection };
|
||||
place in ROM_While1_region { section While1Section };
|
||||
place in QSPI_region { section ExtQSPIFlashSection, section .qspi };
|
||||
place in QSPI_TARA_region { section TARAResSection };
|
||||
place in QSPI_TGFX_region { section TGFXResSection };
|
||||
place in SRAM1_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
place in SRAM2_region { };
|
||||
|
||||
place in calibration_region {readwrite section .calibration_data };
|
||||
Loading…
Reference in New Issue