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Merge pull request #5512 from jeromecoutant/PR_L072 

DISCO_L072CZ_LRWAN1 can use LSE from LORA module
pull/5539/head
Jimmy Brisson 2017-11-20 10:53:20 -06:00 committed by GitHub
parent ac891af2b2 763531921f
commit 800be4e90d
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 2 additions and 3 deletions
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2
targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct → targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_MICRO/stm32l072xz.sct
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@ -27,7 +27,7 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
; STM32L072CZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
LR_IROM1 0x08000000 0x30000 { ; load region size_region
ER_IROM1 0x08000000 0x30000 { ; load address = execution address

2
targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l073xz.sct → targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/TOOLCHAIN_ARM_STD/stm32l072xz.sct
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@ -27,7 +27,7 @@
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
; STM32L072CZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
LR_IROM1 0x08000000 0x30000 { ; load region size_region
ER_IROM1 0x08000000 0x30000 { ; load address = execution address

1
targets/targets.json
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@ -1570,7 +1570,6 @@
"core": "Cortex-M0+",
"extra_labels_add": ["STM32L0", "STM32L072CZ", "STM32L072xx"],
"supported_form_factors": ["ARDUINO", "MORPHO"],
"macros": ["RTC_LSI=1"],
"config": {
"clock_source": {
"help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",