Ticless on STM32 F4 boards causes SPI issue with following PR:
# 11682 Make FPGA tests to pass on CI targets (SPI, analogIn, PWM)
In asynch mode, using interrupts, SPI hardware detect an RX overrun.
Our understanding is that lpticker wrapper latency
causes issue similar to #8714 and #9785,
specially with SPI asynch which use interrupts.
These targets below just support PRNG, not real TRNG. They cannot annouce TRNG.
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M487
- NUMAKER_IOT_M487
On targets without TRNG, to run mbedtls applications which require entropy source,
there are two alternatives to TRNG:
- Custom entropy source:
Define MBEDTLS_ENTROPY_HARDWARE_ALT and provide custom mbedtls_hardware_poll(...)
- NV seed:
1. Define MBEDTLS_ENTROPY_NV_SEED
2. Define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO/MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO and provide custom mbedtls_nv_seed_read(...)/mbedtls_nv_seed_write(...).
3. Don't define MBEDTLS_PSA_INJECT_ENTROPY. Meet mbedtls_psa_inject_entropy(...) undefined and then provide custom one, which must be compatible with mbedtls_nv_seed_read(...)/mbedtls_nv_seed_write(...) above.
4. For development, simulating partial provision process, inject entropy seed via mbedtls_psa_inject_entropy(...) pre-main.
The proposed review fixes by Jerome, cherry-picked in.
(cherry picked from commit fb15f023a9b7b679301b45eaa160ae8cb2e1f23c)
Signed-off-by: Janne Kiiskila <janne.kiiskila@arm.com>
- Enable FLASHIAP for all H7 boards
- Use "TDB_INTERNAL" for all H7 boards
- Define specific internal_base_address only for DISCO_H747I_CM7
(default address is the end of FLASH which is correct for other H7 boards)
- Correct GetSectorBase function with Dual Bank information
Recent measurements have shown that the total wake-up latency can be more
than the 3ms initially set. It was measured as 3,7ms on DISCO_L475VG_IOT01A
target and 3,1ms on NUCLEO_L073RZ target. So set it to 4ms to be on the
safe side.
In this new memory partition, secure program is most simplified and non-secure program can make most use of memory for its large application like Pelion:
- Flash (512KiB in total): 64KiB for secure and 448KiB for nonsecure.
- SRAM (96KiB in total): 8KiB for secure and 88KiB for nonsecure.
Besides, to make secure program fit into 8KiB:
- Decrease boot stack size to 0x600 bytes
- Remove serial support
This is to meet platform name 'NU_PFM_M2351' registered in mbed-os-tools. This tool
uses the platform name as a key to search platform related properties in targets.json.
For example, the property 'forced_reset_timeout' is critical for Greentea test.
Notes:
- CRC and TRNG are disabled on this board since the MCU on this board does not have the required hardware.
- QSPI and QSPIF are temporarily removed due to issues related to supporting the new S25FS512S flash chip we have on this board. These will be enabled as soon as we can get the issues resolved.
https://github.com/ARMmbed/mbed-os/issues/11722
Add 2 targets for DISCO_H747I dualcore:
* DISCO_H747I -> for CM7 core
* DISCO_H747I_CM4 -> for CM4 core
Current restrictions:
* TICKLESS deactivated
* DeepSleep not supported (DeepSleep wrapped to sleep)
Warning: use of the same IP (example I2C1) by both core at the same time is not prevented,
but is strongly not recommended.
Some Hardware Semaphore are use for common IP, to manage concurrent access by both cores: Flash, GPIO, RCC.
Warning: Drag and drop of binary to DISCO_H747I will flash CM7.
In order to flash CM4, one can use STM32 CubeProgrammer tool.
Earlier changes introduced a change to default Arm C6, which does not compile the micro library which is based on Mbed 2. This change fixes the compiler version for NRF51_MICROBIT devices.
Reasons to remove TRNG support:
1. M252 just has 32KiB SRAM and cannot afford mbedtls application.
2. Implementing TRNG HAL with PRNG H/W has security concern.
On Nuvoton targets, lp_ticker_set_interrupt(...) needs around 3 lp-ticker
ticks to take effect. It may miss when current tick and match tick are very
close (see hal/LowPowerTickerWrapper.cpp). Enlarge LPTICKER_DELAY_TICKS to
4 from 3 to address this boundary case.
Without this override, mpu hal will require 5 mpu regions which exceed 4 mpu
regions supported by M252 (see hal/mpu/mbed_mpu_v8m.c). In this scenario,
we will hit assert error but we actually meet stack overrun first due to just
0x400 bytes for emitting error message. The issue doesn’t occur on other
targets such as M487 because it has 8 mpu regions.
static_memory_defines controls the macro MBED_RAM_START AND MBED_RAM_SIZE
when nrf52840 to use softdevice, it need MBED_RAM_START to set the true application ram start
default static_memory_defines is true, so just remove NRF52840 and NRF52832's set
NOTE1: USB UART is partitioned for non-secure world. Secure world still can share
it with limit that its interrupt cannot use in secure world.
NOTE2: In secure world, USB UART is only for Greentea and STDIO. Developers shouldn't
use it for other purposes.
Support secure/non-secure combined build for non-PSA target:
1. In secure post-build, deliver built secure image to TARGET_NU_PREBUILD_SECURE
directory which is to combine later.
2. In non-secure post-build, merge non-secure image with secure image saved in
TARGET_NU_PREBUILD_SECURE directory.
3. In non-secure post-build, user can also drop pre-built secure image saved in
TARGET_NU_PREBUILD_SECURE directory and provide its own by adding the line below
in mbed_app.json:
"target.extra_labels_remove": ["NU_PREBUILD_SECURE"]
1. Create a private target name NU_PFM_M2351_CM which stands for the
NuMaker-PFM-M2351 board and is to be extended.
2. NU_PFM_M2351_NPSA_S/NS target names for non-PSA secure/non-secure targets
respectively.
3. The original target name NUMAKER_PFM_M2351 is recycled and cannot be used.
Use NU_PFM_M2351_S/NS for non-PSA secure/non-secure targets instead.
NOTE: Target name doesn't follow the rule below because online database has
limit of max 20 chars:
NUMAKER_PFM_M2351_PSA/NOPSA_S/NS
Instead, it has the rule:
NU_PFM_M2351_[NPSA_]S/NS
NU_PFM_M2351_S/NS for PSA targets. This is to be consistent with current
PSA target naming. So the resolved target names are:
NU_PFM_M2351_S : PSA secure target
NU_PFM_M2351_NS : PSA non-secure target
NU_PFM_M2351_NPSA_S : Non-PSA secure target
NU_PFM_M2351_NPSA_NS : Non-PSA non-secure target
Removed private TODO file.
Fixed cmsis.h so that renaming of CS and DIR_H is not necessary any more.
Leave pinmap.h unchanged although it should include stdint.h
Moved stdint.h to PinNames.h instead, where it is also used.
Reworked system startup (clock configuration) to be more flexible
(different clock sources for MCLK and SMCLK, configurable clock dividers).
Fixed Copyright headers
Changed default clock settings for MSP432 Launchpad to
MCLK 48 MHz (HFXT) and SMCLK 24 MHz (HFXT)
Remove mbed_rtx.h
Added common mbed_rtx.h file (merge with lastest master)
Added support for IAR toolchain
Fixed some astyle problems.
Added support for ARM C5/C6 toolchains
Small changes to us_ticker implementation after port testing.
Changed default clock configuration to DCO (MCLK 48MHz, SMCLK 24MHz).
De-configured the LFXT crysal, because this made the system_reset() test to time out.
Removed MPU from device_has list. Changed clock source to HFXT.
Reworked startup_msp432p401r.c -> now only one startup file for all compilers.
Changed all linker scripts to delete VECTORS stuff (not needed).
Moved position of MSP432 in targets.json so TI stuff is in one block.
This test requires total latency (tot = h/w + s/w) (wakeup from deepsleep) be
under 1ms. To check the issue, measure total latency on Nuvoton targets:
TARGET EXP(us) EXP+TOL(us) ACT(us)
NANO130 42000 43000 42939
NUC472 42000 43000 42236
M453 42000 43000 43274
M487 42000 43000 42877
M2351 42000 43000 43213
Checking h/w spec, h/w latency (wakeup time from normal power-down mode) on
M487/M2351 is just 1us (n/a on other targets). S/W latency plays the major
part here.
S/W latency relies on system performance. On Nuvoton targets, 'LPTICKER_DELAY_TICKS'
possibly complicates the test. Anyway, to pass the test, add extra 1ms latency
(deep-sleep-latency) in targets.json for Nuvoton targets.
On Nuvoton targets, lp_ticker_set_interrupt(...) needs around 3 lp-ticker
ticks to take effect. It may miss when current tick and match tick are very
close (see hal/LowPowerTickerWrapper.cpp). Enlarge LPTICKER_DELAY_TICKS to
4 from 3 to address this boundary case.
Enables code examples/end user applications to override if necessary
Add BSP_DESIGN_MODUS component by default to all PSOC6 boards. Applications can remove this if necessary.
static_memory_defines controls the macro MBED_RAM_START AND MBED_RAM_SIZE
when nrf52832 to use softdevice, it need MBED_RAM_START to set the true application ram start
For STM32 platforms that embed an OSPI IP, we're offering
a QSPI fallback support with this commit.
When OSPI is supported in mbed, we can consider adding full
OSPI support
This allows to specify which hal version to use for each family.
It can also be used to modify the thread stack size.
Signed-off-by: Vincent Veron <vincent.veron@st.com>
This port is based on :
* CurryGuy ethernet branch :
https://github.com/CurryGuy/mbed-os/tree/feature-stm32h7-emac
* STM32 Cube example :
Applications/LwIP/LwIP_HTTP_Server_Netconn_RTOS example
Signed-off-by: Vincent Veron <vincent.veron@st.com>
M451 series can classify by M45xD/M45xC and M45xG/M45xE. To support this
classification:
1. Create TARGET_M45xD_M45xC and TARGET_M45xG_M45xE targets.
2. Mark NUMAKER_PFM_M453 belongs to TARGET_M45xG_M45xE by 'extra_labels_add'
in targets.json.
3. Fix pin name table according to the classification.
4. Fix pinmap table according to the classification.
This test requires total latency (tot = h/w + s/w) (wakeup from deepsleep) be
under 1ms. To check the issue, measure total latency on Nuvoton targets:
TARGET EXP(us) EXP+TOL(us) ACT(us)
NANO130 42000 43000 42939
NUC472 42000 43000 42236
M453 42000 43000 43274
M487 42000 43000 42877
M2351 42000 43000 43213
Checking h/w spec, h/w latency (wakeup time from normal power-down mode) on
M487/M2351 is just 1us (n/a on other targets). S/W latency plays the major
part here.
S/W latency relies on system performance. On Nuvoton targets, 'LPTICKER_DELAY_TICKS'
possibly complicates the test. Anyway, to pass the test, add extra 1ms latency
(deep-sleep-latency) in targets.json for Nuvoton targets.
Since QSPi is not yet supported by base TARGET_PSOC6,
there is no need to remove the device label from
FUTURE targets that inherit from TARGET_PSOC6.
This will need to be reverted back once the QSPI support
is implemented for Cypress PSOC6 targets.
According to comment in the implementation this target supports the
hardware flow control on UART1 peripheral.
This patch fixes build errors after adding DEVICE_SERIAL_FC guards to
hal/serial_api.h.
On Nuvoton targets, lp_ticker_set_interrupt(...) needs around 3 lp-ticker
ticks to take effect. It may miss when current tick and match tick are very
close (see hal/LowPowerTickerWrapper.cpp). Enlarge LPTICKER_DELAY_TICKS to
4 from 3 to address this boundary case.
Replace the prebuilt CM0+ HEX images with C files that provide the
variable cy_m0p_image placed to the combined ELF image with linker
script. This simplifies build flow of PSoC 6 application and improves
compatibility with IDE export targets. It is still possible to use
the custom prebuilt HEX images for PSA targets that remove CM0P_SLEEP
label and specify the `hex_filename` in targets.json.
Linker scripts are compatible with both scenarios.
Fix device management client compilation on MTB_STM_S2LP
Fixes:
./mbed-cloud-client/mbed-client-pal/Source/Port/Reference-Impl/OS_Specific/mbedOS/ROT/pal_plat_rot.cpp:67:5: error: 'DeviceKey' was not declared in this scope
DeviceKey &devkey = DeviceKey::get_instance();
-Enable MBED_SPLIT_HEAP for K64F and K66F
-Allow GCC_ARM toolchain to utilize remaining 64K memory area
-Make ARM toolchain to start memory filling from 64K region to leave
more space to bigger 192K region.
Watchdog is hardware driver. It interacts with HAL - provides wrapper to interact with the peripheral.
Provides basic functionality: start/stop, get timeout/max timeout.
It is automatically kicked by a timer, according to the timeout set in ctor.
For L0/L4/H7/F7/WB targets that have tickless enabled, remove the tickless from
us ticker and the delay ticks as the C++ wrapper layer is being removed
and replaced by the low layer handling.
For now, the few F4 targets with LPTIM are left with previous configuration
as test results are showing a few instabilities not yet understood.
As the timer code became more generic, coping with initialization on
demand, and variable width and speed us_ticker_api implementations,
wait_us has gradually gotten slower and slower.
Some platforms have reportedly seen overhead of wait_us() increase from
10µs to 30µs. These changes should fully reverse that drop, and even
make it better than ever.
Add fast paths for platforms that provide compile-time information about
us_ticker. Speed and code size is improved further if:
* Timer has >= 2^32 microsecond range, or better still is 32-bit 1MHz.
* Platform implements us_ticker_read() as a macro
* Timer is initialised at boot, rather than first use
The latter initialisation option is the default for STM, as this has
always been the case.
The build tool uses the sector size found in the CMSIS Pack to determine if
the size that can be specified by `target.restrict_size` is enough to fit
all the parts of a given binary. See `target.restrict_size` documentation
in the Mbed OS manual for more information.
The sector size found in the CMSIS Pack is overriden to allow the build
tool to accurately make the decision.
The target's sectors in the CMSIS Pack are defined in 32KB pages.
However, you can erase pages at the 512 byte level.
This commit changes defined sector erase size to 512 bytes instead of
32 Kilobytes.
Time drifting test cases use serial communication with the host and are unstable on CI.
Skip time-drifting test cases if SKIP_TIME_DRIFT_TESTS macro is defined.
The idea for the future is to use FPGA test shield for timing tests instead of host scripts.
Also remove `__ARM_FM` macro which in most cases was used to disable time drifting tests. In other cases replace `__ARM_FM` with `TARGET_ARM_FM` which is more suitable.
This allows Cypress to deliver middleware libraries with
precompiled libraries for SoftFP ahd HardFP, separated by
component-specific sub-directories:
COMPONENT_SOFTFP/TOOLCHAIN_GCC_ARM/libcy_capsense.a
COMPONENT_HARDFP/TOOLCHAIN_GCC_ARM/libcy_capsense.a
- mbed_watchdog_mgr has interface name mbed_wdog_manager_start(),mbed_wdog_manager_stop(),mbed_wdog_manager_kick()
- HwWatchdog is going to attach with LowPowerTIcker for periodic callback functionality
- mbed_wdog_manager_start() will either get start either by BL/RTOS Aps,it reads the timeout value specified via macro and macro gets defined in target.json file.
- mbed_wdog_manager_start() internally configure below HAL hw watchdog with timeout specified via target.json
- mbed_wdog_manager_start() internally divide the timeout(specified in target.json) by the 2 and attach LowPowerTicker with periodic callback of hw_kick()
- mbed_wdog_manager_start() internally create one instance of sw watchdog class,to access the static list data structure of sw watchdog class
- mbed_wdog_manager_kick() function periodically get called and refresh the hw watchdog to avoid watchdog reset
- converted C++ code into C based APIs
- added boolean to control watchdog start and stop
- Added detach from ticker on stop API
- Add preprocessor guard to watchdog api that errors if the reset reason api is not also implemented
- Add RESET_REASON and WATCHDOG to K64F targets.json
- Add watchdog reference implementation
- Adjust memory for SoftDevice
- Enable PRIO=5 for interrupt priority check
- Change NRF_SD_BLE_API_VERSION to 6
- Add handle and buffer for advertising and scanning
- Remove guard for phy update
- Change scatter files and mbed_lib.json for PR #8607
Also addressed:
- removed dependency on legacy config (excluded apply_old_config.h)
- removed legacy pwm and saadc headers
- Arm Compiler 5 linking issue (a band-aid for now... needs to
be properly addressed for peripheral sharing)
- added missing header in SoftDevice file
- top level files ported from TARGET_NORDIC/TARGET_NRF5x/
Also addressed:
- fixed linking issue for gcc
- added support for nRF52-DK builds, but reverted to using nRF52840 sdk_config.h (must be updated)
- introduced "RTC" to targets.json (might need to be removed eventually)
Musca-A1 is a Cortex-M33 based target with security extension enabled.
- ARM_MUSCA_A1 is the non-secure target running mbed-os.
- ARM_MUSCA_A1_S is the secure target running TF-M.
- TF-M sources were imported and patched in previous commits.
- TF-M secure bootloader (McuBoot) for MUSCA_A1 is submitted by a pre-built binary.
- A post-build hook concatenates The secure and non-secure binaries,
signs it and then concatenates the bootloader with the signed binary.
due to partial implementation. Having FUTURE_SEQUANA_M0 and
FUTURE_SEQUANA PSA targets is misleading.
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
In M2351 SPDMC (SMCC) test, it boots from secure code to non-secure bootloader, and finally
to non-secure test code itself. The boot sequence will takes longer than usual. In test
initiation, host will send sync signal 1s after reset device. But due to the longer boot
sequence, test code in device can miss the signal. We enlarge the reset idle time to fix
the issue.
Change the heuristic for selection of CMSE in the tools python, so that
a non-TrustZone ARMv8 build can happen.
Ideally we would have more direct flagging in the targets, but this
refines the heuristic so the necessary behaviour can be easily
achieved.
* DOMAIN_NS=1 is based purely on the `-NS` suffix on the core name.
* Enabling CMSE in the compiler and outputting a secure import library
is now enabled when the core doesn't have an `-NS` suffix by either
the target label `TFM` being present or the flag `trustzone` being set.
This covers the existing ARMv8-M behaviour - TF-M builds have the TFM
label, as per its documentation; M2351 secure builds have no explicit
flagging, so we ensure that the M2351_NS target has the trustzone flag
set, and the out-of-tree secure target inherits that.
Some Nuvoton targets support DEVICE_FLASH but their corresponding COMPONENT_FLASHIAP
supports are not enabled. Enable them:
NUMAKER_PFM_M453
NUMAKER_PFM_M2351
According to their cmsis.h, FPU is present, so change targets.json to
use it.
* ARM_MPS2_M4: already was Cortex-M4F
* ARM_MPS2_M7: Cortex-M7 -> M7FD
* FVP_MPS2_M4: Cortex-M4 -> M4F
* FVP_MPS2_M7: Cortex-M7 -> M7FD
If they do not in fact have FPU, then cmsis.h should be modified to set
`__FPU_PRESENT` to 0. This will currently cause compilation problems
with ARMC6, but I'll be submitting a fix for that.
GeneratedSource folders are BSP specific. No parts of the kit BSP can be reused
as generic chip support package. Remove TARGET_CY8C62XX directory,
and use flat BSP inheritance model:
MCU_PSOC6 -> MCU_PSOC6_M4 -> CY8CKIT_062_WIFI_BT
MCU_PSOC6 -> MCU_PSOC6_M0 -> CY8CKIT_062_WIFI_BT_M0
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN382(ARM_MPS2_M0). Add "IAR" to supported_toolchain list.
Change-Id: I2b2ad7645166c4f973a8baa9c394521514183767
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN383(ARM_MPS2_M0P). Add "IAR" to supported_toolchain list.
Change-Id: Ib2278d34e265e53ad070aecd318ed4e6a355e3c0
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN382(ARM_MPS2_M0). Add "GCC_ARM" to supported_toolchains list.
Change-Id: I7046b698834c82e94015e51eef9a0f5e1315ddaa
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN383(ARM_MPS2_M0P). Add "GCC_ARM" to supported_toolchains list.
Change-Id: I48020b4f0f1b6e0aef3c53f5a3586bc9e9fca9c9
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN385(ARM_MPS2_M3). Add "IAR" to supported_toolchain list.
Change-Id: I038b05b8b21bd146a1568de897ed030ccd52ab79
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN386(ARM_MPS2_M4). Add "IAR" to supported_toolchain list.
Change-Id: I4f43617c870197b9d39a4d4c9c12456adcc6f96f
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add file MPS2.icf and startup_MPS2.S to suppout IAR of the target
AN500(ARM_MPS2_M7). Add "IAR" to supported_toolchain list.
Change-Id: I0b8f018fc937727382b27ea0669940ae6675c834
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN385(ARM_MPS2_M3). Add "GCC_ARM" to supported_toolchains list.
Change-Id: I3110d4ab37a3294488a80a8dc1c929bfd87ce989
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN386(ARM_MPS2_M4). Add "GCC_ARM" to supported_toolchains list.
Change-Id: Ib8cea952e1ce0a5ef11ab623cca6f3786eab56f5
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
Add files MPS2.ld and startup_MPS2.S to support GCC_ARM of the target
AN500(ARM_MPS2_M7). Add "GCC_ARM" to supported_toolchains list.
Change-Id: Ife109e9e1f2ec8e075e566f9d5c2ec7e3c5067f2
Signed-off-by: Shawn Shan <shawn.shan@arm.com>
These file changes provide small fixes for various targets
on MPS2 platform in order to work properly and pass all
Greentea test cases. The __initial_sp has been explicitly set
in the targets' startup files, and also INITIAL_SP has been
given a different value. The values have been extracted from
the specific targets' Application Note documentation.
Affected targets are: ARM_MPS2_M0, ARM_MPS2_M0P, ARM_MPS2_M3,
ARM_MPS2_M4 and ARM_MPS2_M7.
Change-Id: I3d5d0e1ae386cdcc3ba5eb63be929267a257b139
Signed-off-by: Bence Kaposzta <bence.kaposzta@arm.com>
The hal code for this target uses "const volatile" types inside of
structs, which are non-trivially copyable in clang (used by ARMC6). This
causes the build to fail.
Here's the commit that changed this in clang:
a3d727ba77
It seems this was reverteed some time ago in clang, but ARMC6 may not
be up to date.
Please note the heap address of the both the banks must not be contigious else
GCC considers it to be single memory bank and does allocation across the banks,
which might result into hard-fault
New `target.console-uart` option added to indicate whether a target has
a console UART on STDIO_UART_TX/RX/RTS/CTS pins. (The existing option
`target.console-uart-flow-control` indicates whether RTS and or CTS is
available in addition to TX and RX).
The option defaults to true, and is currently true on all platforms. It
only applies if DEVICE_SERIAL is true, so no need to go through and mark
it false for non-SERIAL platforms.
An application can turn off target.console-uart to save ROM/power/etc if
they don't want to use the serial console. If this is turned off, the
console won't be activated for stdin/stdout, but the application is
still free to open `UARTSerial(STDIO_UART_TX, STDIO_UART_RX)`
themselves.
Since commit 12c6b1bd8, the i.MX RT1050 has effectively had its data
cache disabled, as the SDRAM was marked Shareable; for the Cortex-M7,
shareable memory is not cached.
This was done to make the Ethernet driver work without any cache
maintenance code. This commit adds cache maintenance and memory barriers
to the Ethernet driver, and removes the Shareable attribute from the
SDRAM, so the data cache is used again.
Cache code in the base fsl_enet.c driver has not been activated - the
bulk of it is in higher-level Read and Write calls that we're not using,
and there is one flawed invalidate in its initialisation. Instead
imx_emac.cpp takes full cache responsibility.
This commit also marks the SDRAM as read/write-allocate. As the
Cortex-M7 has its "Dynamic read allocate mode" to automatically switch
back to read-allocate in cases where write allocate is working poorly
(eg large memset), this should result in a performance boost with no
downside.
Activating write-allocate is also an attempt to provoke any flaws in
cache maintenance - the Ethernet transmit buffers for example will be
more likely to have a little data in the cache that needs cleaning.
Until the CMSIS pack device name is officially deployed.
then we'll the name as can be found in Keil CMSIS pack
<!-- ************************* Device 'STM32WB55RG' ***************************** -->
<device Dname="STM32WB55RGVx">
<memory id="IROM1" start="0x08000000" size="0x001000000" startup="1" default="1" />
<memory id="IRAM1" start="0x20000000" size="0x000040000" init="0" default="1" />
<algorithm name="CMSIS/Flash/STM32WB_M4.FLM" start="0x08000000" size="0x001000000" default="1" />
<feature type="QFP" n="68"/>
</device>
- move hw_conf.h file to targets/TARGET_STM/TARGET_STM32WB directory as
this is used also out of BLE feature.
- create a dedicated hal_deepsleep function as the behavior in WB is a lot
different from other existing STM32 targets
- update clock tree configuration to directly clock the entire tree @ 32MHz
out of HSE. This is needed as we want to let the M0 core running without
any change on M0-side of clocks when M4 enters /exits deep sleep.
Nuvoton targets below don't provide SPI-bus SD on-board, identified by 'SD' in
target component list. Instead, these targets provide SD-bus SD on-board, identified
by unofficial 'NUSD', driver of which is provided outside mbed-os tree. So 'SD' must
be removed to reflect the truth.
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M487
- NUMAKER_IOT_M487
- NUMAKER_PFM_M2351
Old M2351 CMSIS pack reports single secure ROM/RAM spec. It is updated in new
version which reports secure/non-secure ROM/RAM spec. Override this memory spec
in targets.json regardless of CMSIS.
Added WiFi_Bt CM4 PSA target in mbedos json
Added SPE-NSPE mailbox initialization for CM4 SystemInit
Made similar to FUTURE_SEQUANA configurations
Copied FUTURE_SEQUANA CM0 SPM part for WiFi_Bt smoke test
Added CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Sorted files for new CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Copied files for CY8CKIT_062_WIFI_BT_M0_PSA from FUTURE_SEQUANA
Copied and updated cm0p start files
Corrected according to FUTURE_SEQUANA
Changes to M0 startup files to have SPM started
Fixed implicit declaration warning
Commented interrupts enabling according to FUTURE_SEQUANA flow
Updated prebuild spm_smore CM0 hex for CM4 target
Turned on greentea environment
Used special memory region for common CM0/CM4 data
Updated prebuild CM0 SPM hex
Placed shared memory region for flash operations into SPM shared memory region
Updated cyprotection code and configuration
Start address of protected regions is set by a defined number from target.json
Added masters pcMask configuration
Added support for PSA target to WIFI_BT board
Enabled resources protection for SPM
Aligned RAM usage according to Cypress FlashBoot and CyBootloader
alligned protection config
Added CYW943012P6EVB_01_M0 target
Enlarged heap size, remobed nv_seed
Added heap reservation in linker script from mbed-os
Removed heap size definition
turned on nv_seed config
Removed nv_seed macros
Enabled protection for PSoC6 CM0
Added PSoC6 CM0 PSA readme
Enabled mbed_hal-spm test
Enabled nv_seed and removed unneeded ipc config define
Added SPDX string to feature_ble cypress target files
Removed unneeded supported_toolchains lines for Cypress targets
Disabled protection settings
Corrected flash initialization for PSoC6 CM0 PSA
Changed PSoC6 IPC6 protection for flash
Enabled special flash initialization and enabled protection settings
Updated and added new prebuild PSoC6 CM0 PSA hex files
Disabled HW TRNG and CRC for PSoC6 CM4 PSA target
Added missing const to allow types to match
Updated PSoC6 WIFI_BT_PSA prebuilt directory
Moved PSoC6 shared section usage area definition to begin of ld
Added initial ARM_STD linker and startup files for PSoC6 CM0
Added initial IAR linker and startup files for PSoC6 CM0
Added defines to disable some SPM protection settings for PSoC64
Moved Flash function variables into separate memory region
Added defines for new Public area definition
Updated PSoC6 CM0_PSA hex-files
Due to a bug the LPTIM peripheral can cause interrupts to fire at the
wrong time on the NUCLEO_L073RZ. This patch switches the backend
of the low power ticker to the RTC until this bug is addressed.
I implemented USB Device feature for Renesas mbed boards.
The code referenced the following code as a starting point and is implemented it by inheritting USBPhy same as other boards.
(mbed-os\features\unsupported\USBDevice\targets\TARGET_RENESAS)
Martin Kojtal
Alexandre Bourdiol
Chun-Chieh Li
Giampaolo Mancini
Ryan Morse
amq
Janne Kiiskila
Wajahat Abbas
jeromecoutant
Laurent Meunier
Veijo Pesonen
toyowata
d-kato
Roman Okhrimenko
Anna Bridge
Rohan Fletcher
Kyle Kearney
George Psimenos
Graham Hammond
Ben Cooke
Qinghao Shi
Chris Trowbridge
James Wang
mahanthgouda
Kostiantyn Tkachov
Michal Paszta
Lin Gao
Andreas Terstegge
Hennadiy Kytsun
aqib-ublox
Orest Akymyshyn
Mahesh Mahadevan
Marcelo Salazar
Tony Wu
cyliangtw
Vincent Veron
int_szyk
Ganesh Ramachandran
Chris Snow
Martino Facchin
Seppo Takalo
Reda Maher
maclobdell
Neil Tuttle
Arto Kinnunen
Volodymyr Medvid
Volodymyr Medvid
Filip Jagodzinski
itziar
Teemu Takaluoma
Kevin Bracey
Devaraj Ranganna
Jaeden Amero
Hugues Kamba
Przemyslaw Stekiel
Lingkai Dong
Rajkumar Kanagaraj
Ronny Liu
aglass0fmilk
Steve Cartmell
Lukas Mandak
Steven Cooreman
Bartek Szatkowski
RFulchiero
Desmond Chen
Michael Schwarcz
Guillermo Alonso
petroborys
fred.li
Shawn Shan
Brian Daniels
Cruz Monrreal
Deepika
Leszek Rusinowicz
Ashok Rao
bcostm
David Saada
jk
Oren Cohen
Malavika Sajikumar
Yossi Levy
Evgeni Bolotin
Shuopeng Deng
Oleg Kapshii
Senthil Ramakrishnan
Russ Butler
Moran Peker
Moran Peker
Lei Zhang
Amir Cohen
Donatien Garnier
panyz0725@thundersoft.com
TomoYamanaka