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Merge pull request #11354 from kyle-cypress/pr/pdl-linker-script 

Update linker scripts based on latest PDL 1.3
pull/11382/head
Martin Kojtal 2019-08-30 07:10:32 +02:00 committed by GitHub
parent ea582f3e11 bf00ebe409
commit 68054861e8
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
26 changed files with 329 additions and 294 deletions
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37
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.50
;* \version 2.60
;*
;* Linker file for the ARMCC.
;*
@ -42,16 +42,21 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000
#endif
;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START
;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image.
;*
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_ROM_SIZE)
@ -59,11 +64,10 @@
#endif
;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE
;* will be calculate by the system.
;*
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_RAM_START)
@ -78,6 +82,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
@ -133,17 +138,9 @@
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
; Size and start address of the Cortex-M0+ application image
#define FLASH_CM0P_SIZE 0x2000
#define FLASH_CM0P_START FLASH_START
; Size and start address of the Cortex-M4 application image
#define FLASH_CM4_SIZE (FLASH_SIZE - FLASH_CM0P_SIZE)
#define FLASH_CM4_START (FLASH_CM0P_START + FLASH_CM0P_SIZE)
; Cortex-M0+ application image
LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
; Cortex-M0+ application flash image area
LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
@ -151,8 +148,8 @@ LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
}
}
; Cortex-M4 application image
LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
{
@ -198,7 +195,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required
; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{
* (.cy_app_signature)
}

43
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.50
* \version 2.60
*
* Linker file for the GNU C compiler.
*
@ -40,16 +40,20 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000
#endif
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_ROM_SIZE)
@ -57,11 +61,10 @@ ENTRY(Reset_Handler)
#endif
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
* will be calculate by the system.
*/
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_RAM_START)
@ -76,6 +79,7 @@ ENTRY(Reset_Handler)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
@ -99,6 +103,7 @@ MEMORY
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE
flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
@ -118,13 +123,6 @@ MEMORY
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Size and start address of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x2000;
FLASH_CM0P_START = ORIGIN(flash);
/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE;
FLASH_CM4_START = FLASH_CM0P_START + FLASH_CM0P_SIZE;
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
@ -164,17 +162,17 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
/* Cortex-M0+ application image */
.cy_m0p_image FLASH_CM0P_START :
/* Cortex-M0+ application flash image area */
.cy_m0p_image ORIGIN(cm0p_image) :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
} > cm0p_image
/* Cortex-M4 application image */
.text FLASH_CM4_START :
/* Cortex-M4 application flash area */
.text ORIGIN(flash) :
{
. = ALIGN(4);
__Vectors = . ;
@ -290,7 +288,6 @@ SECTIONS
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
@ -351,7 +348,7 @@ SECTIONS
__HeapLimit = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
@ -404,7 +401,7 @@ SECTIONS
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{

51
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.icf
* \version 2.50
* \version 2.60
*
* Linker file for the IAR compiler.
*
@ -41,16 +41,20 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10000000;
}
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = MBED_ROM_START;
define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
@ -58,11 +62,10 @@ if (!isdefinedsymbol(MBED_ROM_SIZE)) {
}
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
* will be calculate by the system.
*/
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_RAM_START)) {
@ -74,9 +77,16 @@ if (!isdefinedsymbol(MBED_RAM_SIZE)) {
}
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x0400;
} else {
define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE;
}
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
@ -92,6 +102,9 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
/* Flash */
define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START;
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE);
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE);
@ -148,24 +161,16 @@ define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G;
define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__];
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
@ -196,10 +201,12 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block CM0P_RO };
place at start of IROM0_region { block CM0P_RO };
/* Flash - Cortex-M4 application image */
place in IROM1_region { block RO };
/* Flash - Cortex-M4 application */
place at start of IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.50
* \version 2.60
*
* \brief Device system header file.
*
@ -320,6 +320,11 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
* </tr>
* <tr>
* <td>2.50</td>
* <td>Updated assembler files, C files, linker scripts.</td>
* <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.50
* \version 2.60
*
* The device system-source file.
*

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.50
;* \version 2.60
;*
;* Linker file for the ARMCC.
;*
@ -42,16 +42,21 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000
#endif
;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START
;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image.
;*
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_ROM_SIZE)
@ -59,11 +64,10 @@
#endif
;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE
;* will be calculate by the system.
;*
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_RAM_START)
@ -97,9 +101,6 @@
#define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE
; Size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
@ -139,7 +140,7 @@
; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE
LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
@ -148,7 +149,7 @@ LR_IROM FLASH_START FLASH_CM0P_SIZE
}
; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
LR_IROM1 FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
{
@ -194,7 +195,7 @@ LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required
; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{
* (.cy_app_signature)
}

32
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.50
* \version 2.60
*
* Linker file for the GNU C compiler.
*
@ -40,16 +40,20 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000
#endif
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_ROM_SIZE)
@ -57,11 +61,10 @@ ENTRY(Reset_Handler)
#endif
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
* will be calculate by the system.
*/
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_RAM_START)
@ -79,9 +82,6 @@ ENTRY(Reset_Handler)
/* Size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
@ -103,6 +103,7 @@ MEMORY
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE
flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
@ -162,19 +163,16 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
/* Cortex-M0+ application flash image area */
.cy_m0p_image ORIGIN(flash) :
.cy_m0p_image ORIGIN(cm0p_image) :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
/* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
} > cm0p_image
/* Cortex-M4 application flash area */
.text ORIGIN(flash) + FLASH_CM0P_SIZE :
.text ORIGIN(flash) :
{
. = ALIGN(4);
__Vectors = . ;

45
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.icf
* \version 2.50
* \version 2.60
*
* Linker file for the IAR compiler.
*
@ -41,16 +41,20 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10000000;
}
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = MBED_ROM_START;
define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
@ -58,11 +62,10 @@ if (!isdefinedsymbol(MBED_ROM_SIZE)) {
}
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
* will be calculate by the system.
*/
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_RAM_START)) {
@ -74,9 +77,16 @@ if (!isdefinedsymbol(MBED_RAM_SIZE)) {
}
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x0400;
} else {
define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE;
}
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
@ -92,6 +102,9 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
/* Flash */
define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START;
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE);
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE);
@ -148,12 +161,6 @@ define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
@ -162,10 +169,8 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
}
/**** End of ICF editor section. ###ICF###*/
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G;
define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__];
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
@ -196,10 +201,10 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block CM0P_RO };
place at start of IROM0_region { block CM0P_RO };
/* Flash - Cortex-M4 application */
place in IROM1_region { block RO };
place at start of IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.50
* \version 2.60
*
* \brief Device system header file.
*
@ -320,6 +320,11 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
* </tr>
* <tr>
* <td>2.50</td>
* <td>Updated assembler files, C files, linker scripts.</td>
* <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/device/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.50
* \version 2.60
*
* The device system-source file.
*

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.50
;* \version 2.60
;*
;* Linker file for the ARMCC.
;*
@ -42,16 +42,21 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000
#endif
;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START
;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image.
;*
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_ROM_SIZE)
@ -59,11 +64,10 @@
#endif
;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE
;* will be calculate by the system.
;*
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_RAM_START)
@ -97,9 +101,6 @@
#define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE
; Size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
@ -139,7 +140,7 @@
; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE
LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
@ -148,7 +149,7 @@ LR_IROM FLASH_START FLASH_CM0P_SIZE
}
; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
LR_IROM1 FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
{
@ -194,7 +195,7 @@ LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required
; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{
* (.cy_app_signature)
}

32
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.ld
* \version 2.50
* \version 2.60
*
* Linker file for the GNU C compiler.
*
@ -40,16 +40,20 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000
#endif
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_ROM_SIZE)
@ -57,11 +61,10 @@ ENTRY(Reset_Handler)
#endif
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
* will be calculate by the system.
*/
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_RAM_START)
@ -79,9 +82,6 @@ ENTRY(Reset_Handler)
/* Size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
@ -103,6 +103,7 @@ MEMORY
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE
flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
@ -162,19 +163,16 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
/* Cortex-M0+ application flash image area */
.cy_m0p_image ORIGIN(flash) :
.cy_m0p_image ORIGIN(cm0p_image) :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
/* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
} > cm0p_image
/* Cortex-M4 application flash area */
.text ORIGIN(flash) + FLASH_CM0P_SIZE :
.text ORIGIN(flash) :
{
. = ALIGN(4);
__Vectors = . ;

45
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.icf
* \version 2.50
* \version 2.60
*
* Linker file for the IAR compiler.
*
@ -41,16 +41,20 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10000000;
}
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = MBED_ROM_START;
define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
@ -58,11 +62,10 @@ if (!isdefinedsymbol(MBED_ROM_SIZE)) {
}
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
* will be calculate by the system.
*/
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_RAM_START)) {
@ -74,9 +77,16 @@ if (!isdefinedsymbol(MBED_RAM_SIZE)) {
}
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x0400;
} else {
define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE;
}
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
@ -92,6 +102,9 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
/* Flash */
define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START;
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE);
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE);
@ -148,12 +161,6 @@ define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
@ -162,10 +169,8 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
}
/**** End of ICF editor section. ###ICF###*/
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G;
define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__];
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
@ -196,10 +201,10 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block CM0P_RO };
place at start of IROM0_region { block CM0P_RO };
/* Flash - Cortex-M4 application */
place in IROM1_region { block RO };
place at start of IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.50
* \version 2.60
*
* \brief Device system header file.
*
@ -320,6 +320,11 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
* </tr>
* <tr>
* <td>2.50</td>
* <td>Updated assembler files, C files, linker scripts.</td>
* <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.50
* \version 2.60
*
* The device system-source file.
*

37
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xxa_cm4_dual.sct
;* \version 2.50
;* \version 2.60
;*
;* Linker file for the ARMCC.
;*
@ -42,16 +42,21 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000
#endif
;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START
;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image.
;*
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_ROM_SIZE)
@ -59,11 +64,10 @@
#endif
;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE
;* will be calculate by the system.
;*
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_RAM_START)
@ -78,6 +82,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
@ -133,17 +138,9 @@
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
; Size and start address of the Cortex-M0+ application image
#define FLASH_CM0P_SIZE 0x2000
#define FLASH_CM0P_START FLASH_START
; Size and start address of the Cortex-M4 application image
#define FLASH_CM4_SIZE (FLASH_SIZE - FLASH_CM0P_SIZE)
#define FLASH_CM4_START (FLASH_CM0P_START + FLASH_CM0P_SIZE)
; Cortex-M0+ application image
LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
; Cortex-M0+ application flash image area
LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
@ -151,8 +148,8 @@ LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
}
}
; Cortex-M4 application image
LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
{
@ -198,7 +195,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required
; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{
* (.cy_app_signature)
}

43
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.ld
* \version 2.50
* \version 2.60
*
* Linker file for the GNU C compiler.
*
@ -40,16 +40,20 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000
#endif
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_ROM_SIZE)
@ -57,11 +61,10 @@ ENTRY(Reset_Handler)
#endif
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
* will be calculate by the system.
*/
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_RAM_START)
@ -76,6 +79,7 @@ ENTRY(Reset_Handler)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
@ -99,6 +103,7 @@ MEMORY
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE
flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
@ -118,13 +123,6 @@ MEMORY
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Size and start address of the Cortex-M0+ application image */
FLASH_CM0P_SIZE = 0x2000;
FLASH_CM0P_START = ORIGIN(flash);
/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_SIZE = LENGTH(flash) - FLASH_CM0P_SIZE;
FLASH_CM4_START = FLASH_CM0P_START + FLASH_CM0P_SIZE;
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
@ -164,17 +162,17 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
/* Cortex-M0+ application image */
.cy_m0p_image FLASH_CM0P_START :
/* Cortex-M0+ application flash image area */
.cy_m0p_image ORIGIN(cm0p_image) :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
} > cm0p_image
/* Cortex-M4 application image */
.text FLASH_CM4_START :
/* Cortex-M4 application flash area */
.text ORIGIN(flash) :
{
. = ALIGN(4);
__Vectors = . ;
@ -290,7 +288,6 @@ SECTIONS
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
@ -351,7 +348,7 @@ SECTIONS
__HeapLimit = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
@ -404,7 +401,7 @@ SECTIONS
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{

51
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm4_dual.icf
* \version 2.50
* \version 2.60
*
* Linker file for the IAR compiler.
*
@ -41,16 +41,20 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10000000;
}
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = MBED_ROM_START;
define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
@ -58,11 +62,10 @@ if (!isdefinedsymbol(MBED_ROM_SIZE)) {
}
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
* will be calculate by the system.
*/
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_RAM_START)) {
@ -74,9 +77,16 @@ if (!isdefinedsymbol(MBED_RAM_SIZE)) {
}
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x0400;
} else {
define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE;
}
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
@ -92,6 +102,9 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
/* Flash */
define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START;
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE);
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE);
@ -148,24 +161,16 @@ define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G;
define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__];
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
@ -196,10 +201,12 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block CM0P_RO };
place at start of IROM0_region { block CM0P_RO };
/* Flash - Cortex-M4 application image */
place in IROM1_region { block RO };
/* Flash - Cortex-M4 application */
place at start of IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.50
* \version 2.60
*
* \brief Device system header file.
*
@ -320,6 +320,11 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
* </tr>
* <tr>
* <td>2.50</td>
* <td>Updated assembler files, C files, linker scripts.</td>
* <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.50
* \version 2.60
*
* The device system-source file.
*

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_ARM/cy8c6xx7_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cy8c6xx7_cm4_dual.sct
;* \version 2.50
;* \version 2.60
;*
;* Linker file for the ARMCC.
;*
@ -42,16 +42,21 @@
;* limitations under the License.
;******************************************************************************/
; Size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000
#endif
;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START
;* will be calculate by the system. In case if MBED_APP_START address is
;* customized by the bootloader config, the application image should not
;* include CM0p prebuilt image.
;*
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_ROM_SIZE)
@ -59,11 +64,10 @@
#endif
;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE
;* will be calculate by the system.
;*
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_RAM_START)
@ -97,9 +101,6 @@
#define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE
; Size of the Cortex-M0+ application flash image
#define FLASH_CM0P_SIZE 0x2000
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
@ -139,7 +140,7 @@
; Cortex-M0+ application flash image area
LR_IROM FLASH_START FLASH_CM0P_SIZE
LR_IROM MBED_ROM_START FLASH_CM0P_SIZE
{
.cy_m0p_image +0 FLASH_CM0P_SIZE
{
@ -148,7 +149,7 @@ LR_IROM FLASH_START FLASH_CM0P_SIZE
}
; Cortex-M4 application flash area
LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
LR_IROM1 FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
{
@ -194,7 +195,7 @@ LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required
; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
.cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
{
* (.cy_app_signature)
}

32
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.ld
* \version 2.50
* \version 2.60
*
* Linker file for the GNU C compiler.
*
@ -40,16 +40,20 @@ SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
/* Size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000000
#endif
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_ROM_SIZE)
@ -57,11 +61,10 @@ ENTRY(Reset_Handler)
#endif
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
* will be calculate by the system.
*/
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
#endif
#if !defined(MBED_RAM_START)
@ -79,9 +82,6 @@ ENTRY(Reset_Handler)
/* Size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Size of the Cortex-M0+ application image at the start of FLASH */
FLASH_CM0P_SIZE = 0x2000;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
@ -103,6 +103,7 @@ MEMORY
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
cm0p_image (rx) : ORIGIN = MBED_ROM_START, LENGTH = FLASH_CM0P_SIZE
flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
@ -162,19 +163,16 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
/* Cortex-M0+ application flash image area */
.cy_m0p_image ORIGIN(flash) :
.cy_m0p_image ORIGIN(cm0p_image) :
{
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
__cy_m0p_code_end = . ;
} > flash
/* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
} > cm0p_image
/* Cortex-M4 application flash area */
.text ORIGIN(flash) + FLASH_CM0P_SIZE :
.text ORIGIN(flash) :
{
. = ALIGN(4);
__Vectors = . ;

45
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xx7_cm4_dual.icf
* \version 2.50
* \version 2.60
*
* Linker file for the IAR compiler.
*
@ -41,16 +41,20 @@
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10000000;
}
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. In case if MBED_APP_START address is
* customized by the bootloader config, the application image should not
* include CM0p prebuilt image.
*/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = MBED_ROM_START;
define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
@ -58,11 +62,10 @@ if (!isdefinedsymbol(MBED_ROM_SIZE)) {
}
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
* will be calculate by the system.
*/
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE);
}
if (!isdefinedsymbol(MBED_RAM_START)) {
@ -74,9 +77,16 @@ if (!isdefinedsymbol(MBED_RAM_SIZE)) {
}
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x0400;
} else {
define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE;
}
}
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
@ -92,6 +102,9 @@ if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
/* Flash */
define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START;
define symbol __ICFEDIT_region_IROM0_end__ = (MBED_ROM_START + FLASH_CM0P_SIZE);
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE);
@ -148,12 +161,6 @@ define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
@ -162,10 +169,8 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
}
/**** End of ICF editor section. ###ICF###*/
/* Size of the Cortex-M0+ application image */
define symbol FLASH_CM0P_SIZE = 0x2000;
define memory mem with size = 4G;
define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__];
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
@ -196,10 +201,10 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M0+ application image */
place at start of IROM1_region { block CM0P_RO };
place at start of IROM0_region { block CM0P_RO };
/* Flash - Cortex-M4 application */
place in IROM1_region { block RO };
place at start of IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.50
* \version 2.60
*
* \brief Device system header file.
*
@ -320,6 +320,11 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
* </tr>
* <tr>
* <td>2.50</td>
* <td>Updated assembler files, C files, linker scripts.</td>
* <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/device/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.50
* \version 2.60
*
* The device system-source file.
*

4
targets/targets.json
View File

@ -8662,8 +8662,6 @@
"function": "PSOC6Code.complete"
},
"bootloader_supported": true,
"mbed_rom_start": "0x10000000",
"mbed_rom_size": "0x100000",
"sectors": [[268435456, 512]],
"overrides": {
"network-default-interface-type": "WIFI"
@ -8677,8 +8675,6 @@
"function": "PSOC6Code.complete"
},
"bootloader_supported": true,
"mbed_rom_start": "0x10000000",
"mbed_rom_size": "0x200000",
"sectors": [[268435456, 512]]
},
"CY8CKIT_062S2_43012": {