ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #11434 from romanjoe/pr/cy8ckit_064s2_4343w 

Initial addition of files to support CY8CKIT_064S2_4343W target
pull/11714/head
Martin Kojtal 2019-10-18 14:51:59 +02:00 committed by GitHub
parent 734072ffc3 27f9cf85de
commit 9c82706e6f
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
40 changed files with 11742 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c Normal file
View File

@ -0,0 +1,35 @@
/*******************************************************************************
* File Name: cycfg.c
*
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg.h"
void init_cycfg_all(void)
{
init_cycfg_system();
init_cycfg_clocks();
init_cycfg_dmas();
init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();
}

48
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h Normal file
View File

@ -0,0 +1,48 @@
/*******************************************************************************
* File Name: cycfg.h
*
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_H)
#define CYCFG_H
#if defined(__cplusplus)
extern "C" {
#endif
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_clocks.h"
#include "cycfg_dmas.h"
#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
void init_cycfg_all(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_H */

24
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp Normal file
View File

@ -0,0 +1,24 @@
/*******************************************************************************
* File Name: cycfg.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/

105
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c Normal file
View File

@ -0,0 +1,105 @@
/*******************************************************************************
* File Name: cycfg_clocks.c
*
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_USB_CLK_DIV_HW,
.channel_num = CYBSP_USB_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_SDIO_DIV_HW,
.channel_num = CYBSP_SDIO_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t peri_0_div_8_4_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_div_8_4_HW,
.channel_num = peri_0_div_8_4_NUM,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SDIO_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&peri_0_div_8_4_obj);
#endif //defined (CY_USING_HAL)
}

77
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h Normal file
View File

@ -0,0 +1,77 @@
/*******************************************************************************
* File Name: cycfg_clocks.h
*
* Description:
* Clock configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_CLOCKS_H)
#define CYCFG_CLOCKS_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_USB_CLK_DIV_ENABLED 1U
#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_USB_CLK_DIV_NUM 0U
#define CYBSP_SDIO_DIV_ENABLED 1U
#define CYBSP_SDIO_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_SDIO_DIV_NUM 0U
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_CLK_DIV_NUM 3U
#define peri_0_div_8_4_ENABLED 1U
#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_4_NUM 4U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t peri_0_div_8_4_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_CLOCKS_H */

262
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c Normal file
View File

@ -0,0 +1,262 @@
/*******************************************************************************
* File Name: cycfg_dmas.c
*
* Description:
* DMA configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_dmas.h"
const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_IM,
.interruptType = CY_DMA_1ELEMENT,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_DISABLED,
.triggerInType = CY_DMA_1ELEMENT,
.dataSize = CY_DMA_BYTE,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_1D_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 0,
.dstXincrement = 1,
.xCount = 6,
.srcYincrement = 0,
.dstYincrement = 0,
.yCount = 1,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig =
{
.descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0,
.preemptable = true,
.priority = 1,
.enable = false,
.bufferable = false,
};
const cy_stc_dma_crc_config_t cpuss_0_dw0_0_chan_0_crcConfig =
{
.dataReverse = false,
.dataXor = 0,
.reminderReverse = false,
.reminderXor = 0,
.polynomial = 79764919,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 0U,
.channel_num = cpuss_0_dw0_0_chan_0_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_16CYC,
.interruptType = CY_DMA_1ELEMENT,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_DISABLED,
.triggerInType = CY_DMA_1ELEMENT,
.dataSize = CY_DMA_BYTE,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_1D_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 1,
.dstXincrement = 0,
.xCount = 5,
.srcYincrement = 0,
.dstYincrement = 0,
.yCount = 1,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig =
{
.descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0,
.preemptable = true,
.priority = 1,
.enable = false,
.bufferable = false,
};
const cy_stc_dma_crc_config_t cpuss_0_dw0_0_chan_1_crcConfig =
{
.dataReverse = false,
.dataXor = 0,
.reminderReverse = false,
.reminderXor = 0,
.polynomial = 79764919,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 0U,
.channel_num = cpuss_0_dw0_0_chan_1_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_4CYC,
.interruptType = CY_DMA_DESCR,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_DISABLED,
.triggerInType = CY_DMA_X_LOOP,
.dataSize = CY_DMA_HALFWORD,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_2D_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 2,
.dstXincrement = 0,
.xCount = 10,
.srcYincrement = 10,
.dstYincrement = 0,
.yCount = 2,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig =
{
.descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0,
.preemptable = false,
.priority = 0,
.enable = false,
.bufferable = false,
};
const cy_stc_dma_crc_config_t cpuss_0_dw1_0_chan_1_crcConfig =
{
.dataReverse = false,
.dataXor = 0,
.reminderReverse = false,
.reminderXor = 0,
.polynomial = 79764919,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 1U,
.channel_num = cpuss_0_dw1_0_chan_1_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_IM,
.interruptType = CY_DMA_DESCR,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_DISABLED,
.triggerInType = CY_DMA_X_LOOP,
.dataSize = CY_DMA_HALFWORD,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_2D_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 0,
.dstXincrement = 2,
.xCount = 10,
.srcYincrement = 0,
.dstYincrement = 10,
.yCount = 2,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig =
{
.descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0,
.preemptable = false,
.priority = 0,
.enable = false,
.bufferable = false,
};
const cy_stc_dma_crc_config_t cpuss_0_dw1_0_chan_3_crcConfig =
{
.dataReverse = false,
.dataXor = 0,
.reminderReverse = false,
.reminderXor = 0,
.polynomial = 79764919,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 1U,
.channel_num = cpuss_0_dw1_0_chan_3_CHANNEL,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_dmas(void)
{
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj);
#endif //defined (CY_USING_HAL)
}

91
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h Normal file
View File

@ -0,0 +1,91 @@
/*******************************************************************************
* File Name: cycfg_dmas.h
*
* Description:
* DMA configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_DMAS_H)
#define CYCFG_DMAS_H
#include "cycfg_notices.h"
#include "cy_dma.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define cpuss_0_dw0_0_chan_0_ENABLED 1U
#define cpuss_0_dw0_0_chan_0_HW DW0
#define cpuss_0_dw0_0_chan_0_CHANNEL 0U
#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
#define cpuss_0_dw0_0_chan_1_ENABLED 1U
#define cpuss_0_dw0_0_chan_1_HW DW0
#define cpuss_0_dw0_0_chan_1_CHANNEL 1U
#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
#define cpuss_0_dw1_0_chan_1_ENABLED 1U
#define cpuss_0_dw1_0_chan_1_HW DW1
#define cpuss_0_dw1_0_chan_1_CHANNEL 1U
#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
#define cpuss_0_dw1_0_chan_3_ENABLED 1U
#define cpuss_0_dw1_0_chan_3_HW DW1
#define cpuss_0_dw1_0_chan_3_CHANNEL 3U
#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig;
extern const cy_stc_dma_crc_config_t cpuss_0_dw0_0_chan_0_crcConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig;
extern const cy_stc_dma_crc_config_t cpuss_0_dw0_0_chan_1_crcConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig;
extern const cy_stc_dma_crc_config_t cpuss_0_dw1_0_chan_1_crcConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig;
extern const cy_stc_dma_crc_config_t cpuss_0_dw1_0_chan_3_crcConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_dmas(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_DMAS_H */

30
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h Normal file
View File

@ -0,0 +1,30 @@
/*******************************************************************************
* File Name: cycfg_notices.h
*
* Description:
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_NOTICES_H)
#define CYCFG_NOTICES_H
#endif /* CYCFG_NOTICES_H */

210
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c Normal file
View File

@ -0,0 +1,210 @@
/*******************************************************************************
* File Name: cycfg_peripherals.c
*
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_peripherals.h"
#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
};
const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
.smartCardRetryOnNack = false,
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
.oversample = 8,
.enableMsbFirst = false,
.dataWidth = 8UL,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
.breakWidth = 11UL,
.dropOnFrameError = false,
.dropOnParityError = false,
.receiverAddress = 0x0UL,
.receiverAddressMask = 0x0UL,
.acceptAddrInFifo = false,
.enableCts = true,
.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rtsRxFifoLevel = 63,
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rxFifoTriggerLevel = 1UL,
.rxFifoIntEnableMask = 0UL,
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
.slaveAddress1 = 8U,
.slaveAddress2 = 0U,
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_obj =
{
.type = CYHAL_RSC_SMIF,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
.c1Match = 32768U,
.c0Mode = CY_MCWDT_MODE_NONE,
.c1Mode = CY_MCWDT_MODE_NONE,
.c2ToggleBit = 16U,
.c2Mode = CY_MCWDT_MODE_NONE,
.c0ClearOnMatch = false,
.c1ClearOnMatch = false,
.c0c1Cascade = true,
.c1c2Cascade = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_MCWDT0_obj =
{
.type = CYHAL_RSC_LPTIMER,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
.min = 0U,
.hour = 12U,
.amPm = CY_RTC_AM,
.hrFormat = CY_RTC_24_HOURS,
.dayOfWeek = CY_RTC_SUNDAY,
.date = 1U,
.month = CY_RTC_JANUARY,
.year = 0U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_RTC_obj =
{
.type = CYHAL_RSC_RTC,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
{
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
.epBuffer = NULL,
.epBufferSize = 0U,
.dmaConfig[0] = NULL,
.dmaConfig[1] = NULL,
.dmaConfig[2] = NULL,
.dmaConfig[3] = NULL,
.dmaConfig[4] = NULL,
.dmaConfig[5] = NULL,
.dmaConfig[6] = NULL,
.dmaConfig[7] = NULL,
.enableLpm = false,
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USBUART_obj =
{
.type = CYHAL_RSC_USB,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void)
{
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
#endif //defined (CY_USING_HAL)
}

159
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h Normal file
View File

@ -0,0 +1,159 @@
/*******************************************************************************
* File Name: cycfg_peripherals.h
*
* Description:
* Peripheral Hardware Block configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_PERIPHERALS_H)
#define CYCFG_PERIPHERALS_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_csd.h"
#include "cy_scb_uart.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_scb_ezi2c.h"
#include "cy_smif.h"
#include "cycfg_qspi_memslot.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
#include "cy_usbfs_dev_drv.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 100000000u
#define CY_CAPSENSE_PERI_CLK 100000000u
#define CY_CAPSENSE_VDDA_MV 3300u
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
#define CY_CAPSENSE_PERI_DIV_INDEX 3u
#define Cmod_PORT GPIO_PRT7
#define CintA_PORT GPIO_PRT7
#define CintB_PORT GPIO_PRT7
#define Button0_Rx0_PORT GPIO_PRT8
#define Button0_Tx_PORT GPIO_PRT1
#define Button1_Rx0_PORT GPIO_PRT8
#define Button1_Tx_PORT GPIO_PRT1
#define LinearSlider0_Sns0_PORT GPIO_PRT8
#define LinearSlider0_Sns1_PORT GPIO_PRT8
#define LinearSlider0_Sns2_PORT GPIO_PRT8
#define LinearSlider0_Sns3_PORT GPIO_PRT8
#define LinearSlider0_Sns4_PORT GPIO_PRT8
#define Cmod_PIN 7u
#define CintA_PIN 1u
#define CintB_PIN 2u
#define Button0_Rx0_PIN 1u
#define Button0_Tx_PIN 0u
#define Button1_Rx0_PIN 2u
#define Button1_Tx_PIN 0u
#define LinearSlider0_Sns0_PIN 3u
#define LinearSlider0_Sns1_PIN 4u
#define LinearSlider0_Sns2_PIN 5u
#define LinearSlider0_Sns3_PIN 6u
#define LinearSlider0_Sns4_PIN 7u
#define Cmod_PORT_NUM 7u
#define CintA_PORT_NUM 7u
#define CintB_PORT_NUM 7u
#define CYBSP_CSD_HW CSD0
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
#define CYBSP_BT_UART_ENABLED 1U
#define CYBSP_BT_UART_HW SCB2
#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
#define CYBSP_CSD_COMM_ENABLED 1U
#define CYBSP_CSD_COMM_HW SCB3
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
#define CYBSP_QSPI_DATALINES0_1 (1UL)
#define CYBSP_QSPI_DATALINES2_3 (1UL)
#define CYBSP_QSPI_DATALINES4_5 (0UL)
#define CYBSP_QSPI_DATALINES6_7 (0UL)
#define CYBSP_QSPI_SS0 (1UL)
#define CYBSP_QSPI_SS1 (0UL)
#define CYBSP_QSPI_SS2 (0UL)
#define CYBSP_QSPI_SS3 (0UL)
#define CYBSP_QSPI_DESELECT_DELAY 7
#define CYBSP_MCWDT0_ENABLED 1U
#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
#define CYBSP_RTC_ENABLED 1U
#define CYBSP_RTC_10_MONTH_OFFSET (28U)
#define CYBSP_RTC_MONTH_OFFSET (24U)
#define CYBSP_RTC_10_DAY_OFFSET (20U)
#define CYBSP_RTC_DAY_OFFSET (16U)
#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
#define CYBSP_RTC_YEAR_OFFSET (0U)
#define CYBSP_USBUART_ENABLED 1U
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
#define CYBSP_USBUART_HW USBFS0
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
extern cy_stc_csd_context_t cy_csd_0_context;
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_PERIPHERALS_H */

1005
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c Normal file
View File

File diff suppressed because it is too large Load Diff

1000
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h Normal file
View File

File diff suppressed because it is too large Load Diff

265
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c Normal file
View File

@ -0,0 +1,265 @@
/*******************************************************************************
* File Name: cycfg_qspi_memslot.c
*
* Description:
* Provides definitions of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_qspi_memslot.h"
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xECU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_QUAD,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0x01U,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 4U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xDCU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x34U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
.addrWidth = CY_SMIF_WIDTH_SINGLE,
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
.stsRegQuadEnableMask = 0x02U,
/* The max time for the erase type-1 cycle-time in ms. */
.eraseTime = 2600U,
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 460000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
.flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
/* The data-line selection options for a slave device. */
.dataSelect = CY_SMIF_DATA_SEL0,
/* The base address the memory slave is mapped to in the PSoC memory map.
Valid when the memory-mapped mode is enabled. */
.baseAddress = 0x18000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
.memMappedSize = 0x4000000U,
/* If this memory device is one of the devices in the dual quad SPI configuration.
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512S_4byteaddr_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =
{
/* The number of SMIF memories defined. */
.memCount = CY_SMIF_DEVICE_NUM,
/* The pointer to the array of memory config structures of size memCount. */
.memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
/* The version of the SMIF driver. */
.majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
/* The version of the SMIF driver. */
.minorVersion = CY_SMIF_DRV_VERSION_MINOR
};

50
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h Normal file
View File

@ -0,0 +1,50 @@
/*******************************************************************************
* File Name: cycfg_qspi_memslot.h
*
* Description:
* Provides declarations of the SMIF-driver memory configuration.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#ifndef CYCFG_QSPI_MEMSLOT_H
#define CYCFG_QSPI_MEMSLOT_H
#include "cy_smif_memslot.h"
#define CY_SMIF_DEVICE_NUM 1
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;
#endif /*CY_SMIF_MEMCONFIG_H*/

39
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c Normal file
View File

@ -0,0 +1,39 @@
/*******************************************************************************
* File Name: cycfg_routing.c
*
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_routing.h"
#include "cy_device_headers.h"
void init_cycfg_routing(void)
{
HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
}

71
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h Normal file
View File

@ -0,0 +1,71 @@
/*******************************************************************************
* File Name: cycfg_routing.h
*
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_ROUTING_H)
#define CYCFG_ROUTING_H
#if defined(__cplusplus)
extern "C" {
#endif
#include "cycfg_notices.h"
void init_cycfg_routing(void);
#define init_cycfg_connectivity() init_cycfg_routing()
#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
#define ioss_0_port_11_pin_2_HSIOM P11_2_SMIF_SPI_SELECT0
#define ioss_0_port_11_pin_3_HSIOM P11_3_SMIF_SPI_DATA3
#define ioss_0_port_11_pin_4_HSIOM P11_4_SMIF_SPI_DATA2
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_ROUTING_H */

595
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c Normal file
View File

@ -0,0 +1,595 @@
/*******************************************************************************
* File Name: cycfg_system.c
*
* Description:
* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_system.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
#define CY_CFG_SYSCLK_PLL_ERROR 3
#define CY_CFG_SYSCLK_FLL_ERROR 4
#define CY_CFG_SYSCLK_WCO_ERROR 5
#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
#define CY_CFG_SYSCLK_FLL_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 48UL
#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL
#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_ILO_ENABLED 1
#define CY_CFG_SYSCLK_IMO_ENABLED 1
#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
#define CY_CFG_SYSCLK_PLL0_ENABLED 1
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
#define CY_CFG_SYSCLK_WCO_ENABLED 1
#define CY_CFG_PWR_ENABLED 1
#define CY_CFG_PWR_INIT 1
#define CY_CFG_PWR_USING_PMIC 0
#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
{
.fllMult = 500U,
.refDiv = 20U,
.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
.enableOutputDiv = true,
.lockTolerance = 4U,
.igain = 9U,
.pgain = 5U,
.settlingCount = 8U,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
.cco_Freq = 355U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 4U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 30,
.referenceDiv = 1,
.outputDiv = 5,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
(void)error; /* Suppress the compiler warning */
while(1);
}
__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
{
Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
}
__STATIC_INLINE void Cy_SysClk_ClkBakInit()
{
Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
}
__STATIC_INLINE void Cy_SysClk_ClkFastInit()
{
Cy_SysClk_ClkFastSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_FllInit()
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
{
Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
}
__STATIC_INLINE void Cy_SysClk_ClkHf1Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
}
__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
}
__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
}
__STATIC_INLINE void Cy_SysClk_IloInit()
{
/* The WDT is unlocked in the default startup code */
Cy_SysClk_IloEnable();
Cy_SysClk_IloHibernateOn(true);
}
__STATIC_INLINE void Cy_SysClk_ClkLfInit()
{
/* The WDT is unlocked in the default startup code */
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
}
__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
{
Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
{
Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
{
Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath3Init()
{
Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath4Init()
{
Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
Cy_SysClk_ClkPeriSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_Pll0Init()
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
{
Cy_SysClk_ClkSlowSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
{
Cy_SysClk_ClkTimerDisable();
Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
Cy_SysClk_ClkTimerSetDivider(0U);
Cy_SysClk_ClkTimerEnable();
}
__STATIC_INLINE void Cy_SysClk_WcoInit()
{
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
__STATIC_INLINE void init_cycfg_power(void)
{
/* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#else /* Dedicated Supply */
Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
/* Configure core regulator */
#if CY_CFG_PWR_USING_LDO
Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
#else
Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
#endif /* CY_CFG_PWR_USING_LDO */
/* Configure PMIC */
Cy_SysPm_UnlockPmic();
#if CY_CFG_PWR_USING_PMIC
Cy_SysPm_PmicEnableOutput();
#else
Cy_SysPm_PmicDisableOutput();
#endif /* CY_CFG_PWR_USING_PMIC */
}
void init_cycfg_system(void)
{
/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
Cy_SysLib_SetWaitStates(false, 150UL);
#ifdef CY_CFG_PWR_ENABLED
#ifdef CY_CFG_PWR_INIT
init_cycfg_power();
#else
#warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
/* Reset the core clock path to default and disable all the FLLs/PLLs */
Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkFastSetDivider(0U);
Cy_SysClk_ClkPeriSetDivider(1U);
Cy_SysClk_ClkSlowSetDivider(0U);
for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
{
(void)Cy_SysClk_PllDisable(pll);
}
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
(CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
{
Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
}
Cy_SysClk_FllDisable();
Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
#ifdef CY_IP_MXBLESS
(void)Cy_BLE_EcoReset();
#endif
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
Cy_SysClk_PiloInit();
#endif
#ifdef CY_CFG_SYSCLK_WCO_ENABLED
Cy_SysClk_WcoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
Cy_SysClk_ClkLfInit();
#endif
#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
Cy_SysClk_AltHfInit();
#endif
#ifdef CY_CFG_SYSCLK_ECO_ENABLED
Cy_SysClk_EcoInit();
#endif
#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
Cy_SysClk_ExtClkInit();
#endif
/* Configure CPU clock dividers */
#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
Cy_SysClk_ClkFastInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
Cy_SysClk_ClkPeriInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
Cy_SysClk_ClkSlowInit();
#endif
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
/* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
#else
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure Path Clocks */
#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
Cy_SysClk_ClkPath0Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
Cy_SysClk_ClkPath2Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
Cy_SysClk_ClkPath3Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
Cy_SysClk_ClkPath4Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
Cy_SysClk_ClkPath5Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
Cy_SysClk_ClkPath6Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
Cy_SysClk_ClkPath7Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
Cy_SysClk_ClkPath8Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
Cy_SysClk_ClkPath9Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
Cy_SysClk_ClkPath10Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
Cy_SysClk_ClkPath11Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
Cy_SysClk_ClkPath12Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
Cy_SysClk_ClkPath13Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
Cy_SysClk_ClkPath14Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
Cy_SysClk_ClkPath15Init();
#endif
/* Configure and enable FLL */
#ifdef CY_CFG_SYSCLK_FLL_ENABLED
Cy_SysClk_FllInit();
#endif
Cy_SysClk_ClkHf0Init();
#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
/* Apply the ClkPath1 user setting */
Cy_SysClk_ClkPath1Init();
#endif
#endif
/* Configure and enable PLLs */
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
Cy_SysClk_Pll0Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
Cy_SysClk_Pll1Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
Cy_SysClk_Pll2Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
Cy_SysClk_Pll3Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
Cy_SysClk_Pll4Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
Cy_SysClk_Pll5Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
Cy_SysClk_Pll6Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
Cy_SysClk_Pll7Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
Cy_SysClk_Pll8Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
Cy_SysClk_Pll9Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
Cy_SysClk_Pll10Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
Cy_SysClk_Pll11Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
Cy_SysClk_Pll12Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
Cy_SysClk_Pll13Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
Cy_SysClk_Pll14Init();
#endif
/* Configure HF clocks */
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
Cy_SysClk_ClkHf1Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
Cy_SysClk_ClkHf2Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
Cy_SysClk_ClkHf3Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
Cy_SysClk_ClkHf4Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
Cy_SysClk_ClkHf5Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
Cy_SysClk_ClkHf6Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
Cy_SysClk_ClkHf7Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
Cy_SysClk_ClkHf8Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
Cy_SysClk_ClkHf9Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
Cy_SysClk_ClkHf10Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
Cy_SysClk_ClkHf11Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
Cy_SysClk_ClkHf12Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
Cy_SysClk_ClkHf13Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
Cy_SysClk_ClkHf14Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
Cy_SysClk_ClkHf15Init();
#endif
/* Configure miscellaneous clocks */
#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
Cy_SysClk_ClkTimerInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
Cy_SysClk_ClkAltSysTickInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
Cy_SysClk_ClkPumpInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
Cy_SysClk_ClkBakInit();
#endif
/* Configure default enabled clocks */
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
Cy_SysClk_IloInit();
#else
Cy_SysClk_IloDisable();
#endif
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
#error the IMO must be enabled for proper chip operation
#endif
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
Cy_SysClk_MfoInit();
#endif
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
Cy_SysClk_ClkMfInit();
#endif
/* Set accurate flash wait states */
#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
#endif
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
#endif //defined (CY_USING_HAL)
}

111
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h Normal file
View File

@ -0,0 +1,111 @@
/*******************************************************************************
* File Name: cycfg_system.h
*
* Description:
* System configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_SYSTEM_H)
#define CYCFG_SYSTEM_H
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_systick.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_gpio.h"
#include "cy_syspm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define cpuss_0_dap_0_ENABLED 1U
#define srss_0_clock_0_ENABLED 1U
#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
#define srss_0_clock_0_bakclk_0_ENABLED 1U
#define srss_0_clock_0_fastclk_0_ENABLED 1U
#define srss_0_clock_0_fll_0_ENABLED 1U
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define srss_0_clock_0_hfclk_1_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF1 1UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define srss_0_clock_0_hfclk_3_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF3 3UL
#define srss_0_clock_0_hfclk_4_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF4 4UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
#define srss_0_clock_0_pathmux_3_ENABLED 1U
#define srss_0_clock_0_pathmux_4_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_timerclk_0_ENABLED 1U
#define srss_0_clock_0_wco_0_ENABLED 1U
#define srss_0_power_0_ENABLED 1U
#define CY_CFG_PWR_MODE_LP 0x01UL
#define CY_CFG_PWR_MODE_ULP 0x02UL
#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
#define CY_CFG_PWR_MODE_SLEEP 0x08UL
#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
#define CY_CFG_PWR_USING_LDO 1
#define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300
#define CY_CFG_PWR_VDD_NS_MV 3300
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_SYSTEM_H */

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg Normal file
View File

@ -0,0 +1,4 @@
set SMIF_BANKS {
0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
}

26
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
View File

@ -1,28 +1,6 @@
[Device="CYB0644ABZI-D44"]
[Device=CYB0644ABZI-D44]
[Blocks]
# User IO
# CYBSP_USER_LED1
ioss[0].port[1].pin[5]
# CYBSP_USER_LED2
ioss[0].port[13].pin[7]
# CYBSP_USER_LED3
ioss[0].port[0].pin[3]
# CYBSP_USER_LED4
ioss[0].port[1].pin[1]
# CYBSP_USER_LED5
ioss[0].port[11].pin[1]
# CYBSP_USER_BTN1
ioss[0].port[0].pin[4]
# Debug
# CYBSP_DEBUG_UART
scb[5]
# CYBSP_DEBUG_UART_RX
ioss[0].port[5].pin[0]
# CYBSP_DEBUG_UART_TX
ioss[0].port[5].pin[1]
# WIFI
# CYBSP_WIFI_SDIO
sdhc[0]
@ -39,4 +17,4 @@ ioss[0].port[2].pin[4]
# CYBSP_WIFI_SDIO_CLK
ioss[0].port[2].pin[5]
# CYBSP_WIFI_WL_REG_ON
ioss[0].port[2].pin[6]
ioss[0].port[2].pin[6]

409
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense Normal file
View File

@ -0,0 +1,409 @@
<?xml version="1.0"?>
<Configuration major="2" minor="0">
<!--
File Name: cycfg_capsense.cycapsense
Description:
CapSense middleware configuration
This file should not be modified. It was automatically generated by
CapSense Configurator 2.0.0 build 185
-->
<GeneralProperties>
<Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
<Property id="REGULAR_IIR_RC_N" value="128"/>
<Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
<Property id="PROX_IIR_RC_N" value="128"/>
<Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="REGULAR_IIR_BL_N" value="1"/>
<Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="PROX_IIR_BL_N" value="1"/>
<Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="MULTI_FREQ_SCAN_EN" value="false"/>
<Property id="SENSOR_AUTO_RESET_EN" value="false"/>
<Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
<Property id="VREF_SOURCE" value="SRSS"/>
<Property id="IREF_SOURCE" value="SRSS"/>
<Property id="PROX_TOUCH_COEFF" value="300"/>
<Property id="NUM_CENTROIDS" value="1"/>
</GeneralProperties>
<CsdProperties>
<Property id="CSD_AUTOTUNE" value="HWTH"/>
<Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
<Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
<Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
<Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
<Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
<Property id="CSD_IDAC_MIN" value="20"/>
<Property id="CSD_IDAC_COMP_EN" value="true"/>
<Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
<Property id="CSD_VREF_CUSTOM" value="false"/>
<Property id="CSD_VREF" value="1219"/>
<Property id="CSD_SHIELD_EN" value="false"/>
<Property id="CSD_SHIELD_TANK_EN" value="false"/>
<Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
<Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
<Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_FINE_INIT_TIME" value="10"/>
<Property id="CSD_CALIBRATION_ERROR" value="10"/>
<Property id="CSD_R_CONST" value="1000"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsdProperties>
<CsxProperties>
<Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSX_MAX_FINGERS" value="3"/>
<Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
<Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
<Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
<Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
<Property id="CSX_FINE_INIT_TIME" value="10"/>
<Property id="CSX_CALIBRATION_ERROR" value="20"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsxProperties>
<Widgets>
<Widget id="Button0" type="CSX_BUTTON">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Rx0" kind="Column">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Tx" kind="Row">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
<Widget id="Button1" type="CSX_BUTTON">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Rx0" kind="Column">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Tx" kind="Row">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
<Widget id="LinearSlider0" type="LINEAR_SLIDER">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Sns0" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns1" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns2" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns3" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns4" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
</Widgets>
</Configuration>

63
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi Normal file
View File

@ -0,0 +1,63 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
<Configuration app="QSPI" major="2" minor="0">
<DevicePath>PSoC 6.xml</DevicePath>
<SlotConfigs>
<SlotConfig>
<SlaveSlot>0</SlaveSlot>
<PartNumber>S25FL512S-4byteaddr</PartNumber>
<MemoryMapped>true</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18000000</StartAddress>
<Size>0x4000000</Size>
<EndAddress>0x1BFFFFFF</EndAddress>
<WriteEnable>true</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
<MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>1</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18010000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1801FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>2</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18020000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1802FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>3</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18030000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1803FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
</SlotConfigs>
</Configuration>

893
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus Normal file
View File

@ -0,0 +1,893 @@
<?xml version="1.0" encoding="UTF-8"?>
<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
<ToolInfo version="1.0.0"/>
<Devices>
<Device mpn="CYB0644ABZI-S2D44">
<BlockConfig>
<Block location="cpuss[0].dap[0]" alias="" template="mxs40dap" version="1.0">
<Param id="dbgMode" value="SWD"/>
<Param id="traceEnable" value="false"/>
</Block>
<Block location="cpuss[0].dw0[0].chan[0]" alias="" template="mxs40dma" version="1.0">
<Param id="CRC_DATA_REVERSE" value="false"/>
<Param id="CRC_DATA_XOR" value="0"/>
<Param id="CRC_REMINDER_REVERSE" value="false"/>
<Param id="CRC_REMINDER_XOR" value="0"/>
<Param id="CRC_POLYNOMIAL" value="79764919"/>
<Param id="CHANNEL_PRIORITY" value="1"/>
<Param id="NUM_OF_DESCRIPTORS" value="1"/>
<Param id="PREEMPTABLE" value="true"/>
<Param id="BUFFERABLE" value="false"/>
<Param id="DESCR_SELECTION" value="0"/>
<Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
<Param id="ENABLE_CHAINING_0" value="false"/>
<Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
<Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
<Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
<Param id="X_NUM_OF_ELEMENTS_0" value="6"/>
<Param id="X_SRC_INCREMENT_0" value="0"/>
<Param id="X_DST_INCREMENT_0" value="1"/>
<Param id="CRC_0" value="false"/>
<Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
<Param id="Y_SRC_INCREMENT_0" value="0"/>
<Param id="Y_DST_INCREMENT_0" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="cpuss[0].dw0[0].chan[1]" alias="" template="mxs40dma" version="1.0">
<Param id="CRC_DATA_REVERSE" value="false"/>
<Param id="CRC_DATA_XOR" value="0"/>
<Param id="CRC_REMINDER_REVERSE" value="false"/>
<Param id="CRC_REMINDER_XOR" value="0"/>
<Param id="CRC_POLYNOMIAL" value="79764919"/>
<Param id="CHANNEL_PRIORITY" value="1"/>
<Param id="NUM_OF_DESCRIPTORS" value="1"/>
<Param id="PREEMPTABLE" value="true"/>
<Param id="BUFFERABLE" value="false"/>
<Param id="DESCR_SELECTION" value="0"/>
<Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
<Param id="ENABLE_CHAINING_0" value="false"/>
<Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
<Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_16CYC"/>
<Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
<Param id="X_NUM_OF_ELEMENTS_0" value="5"/>
<Param id="X_SRC_INCREMENT_0" value="1"/>
<Param id="X_DST_INCREMENT_0" value="0"/>
<Param id="CRC_0" value="false"/>
<Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
<Param id="Y_SRC_INCREMENT_0" value="0"/>
<Param id="Y_DST_INCREMENT_0" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="cpuss[0].dw1[0].chan[1]" alias="" template="mxs40dma" version="1.0">
<Param id="CRC_DATA_REVERSE" value="false"/>
<Param id="CRC_DATA_XOR" value="0"/>
<Param id="CRC_REMINDER_REVERSE" value="false"/>
<Param id="CRC_REMINDER_XOR" value="0"/>
<Param id="CRC_POLYNOMIAL" value="79764919"/>
<Param id="CHANNEL_PRIORITY" value="0"/>
<Param id="NUM_OF_DESCRIPTORS" value="1"/>
<Param id="PREEMPTABLE" value="false"/>
<Param id="BUFFERABLE" value="false"/>
<Param id="DESCR_SELECTION" value="0"/>
<Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
<Param id="ENABLE_CHAINING_0" value="false"/>
<Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
<Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
<Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_4CYC"/>
<Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
<Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
<Param id="X_SRC_INCREMENT_0" value="2"/>
<Param id="X_DST_INCREMENT_0" value="0"/>
<Param id="CRC_0" value="false"/>
<Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
<Param id="Y_SRC_INCREMENT_0" value="10"/>
<Param id="Y_DST_INCREMENT_0" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="cpuss[0].dw1[0].chan[3]" alias="" template="mxs40dma" version="1.0">
<Param id="CRC_DATA_REVERSE" value="false"/>
<Param id="CRC_DATA_XOR" value="0"/>
<Param id="CRC_REMINDER_REVERSE" value="false"/>
<Param id="CRC_REMINDER_XOR" value="0"/>
<Param id="CRC_POLYNOMIAL" value="79764919"/>
<Param id="CHANNEL_PRIORITY" value="0"/>
<Param id="NUM_OF_DESCRIPTORS" value="1"/>
<Param id="PREEMPTABLE" value="false"/>
<Param id="BUFFERABLE" value="false"/>
<Param id="DESCR_SELECTION" value="0"/>
<Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
<Param id="ENABLE_CHAINING_0" value="false"/>
<Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
<Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
<Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
<Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
<Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
<Param id="X_SRC_INCREMENT_0" value="0"/>
<Param id="X_DST_INCREMENT_0" value="2"/>
<Param id="CRC_0" value="false"/>
<Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
<Param id="Y_SRC_INCREMENT_0" value="0"/>
<Param id="Y_DST_INCREMENT_0" value="10"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
<Param id="CapSenseEnable" value="true"/>
<Param id="CapSenseCore" value="4"/>
<Param id="SensorCount" value="12"/>
<Param id="CapacitorCount" value="3"/>
<Param id="SensorName0" value="Cmod"/>
<Param id="SensorName1" value="CintA"/>
<Param id="SensorName2" value="CintB"/>
<Param id="SensorName3" value="Button0_Rx0"/>
<Param id="SensorName4" value="Button0_Tx"/>
<Param id="SensorName5" value="Button1_Rx0"/>
<Param id="SensorName6" value="Button1_Tx"/>
<Param id="SensorName7" value="LinearSlider0_Sns0"/>
<Param id="SensorName8" value="LinearSlider0_Sns1"/>
<Param id="SensorName9" value="LinearSlider0_Sns2"/>
<Param id="SensorName10" value="LinearSlider0_Sns3"/>
<Param id="SensorName11" value="LinearSlider0_Sns4"/>
<Param id="CapSenseConfigurator" value="0"/>
<Param id="CapSenseTuner" value="0"/>
<Param id="CsdAdcEnable" value="false"/>
<Param id="numChannels" value="1"/>
<Param id="resolution" value="CY_CSDADC_RESOLUTION_10BIT"/>
<Param id="range" value="CY_CSDADC_RANGE_VDDA"/>
<Param id="acqTime" value="10"/>
<Param id="autoCalibrInterval" value="30"/>
<Param id="vref" value="-1"/>
<Param id="operClkDivider" value="1"/>
<Param id="azTime" value="5"/>
<Param id="csdInitTime" value="25"/>
<Param id="inFlash" value="true"/>
<Param id="CsdIdacEnable" value="false"/>
<Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
<Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
<Param id="csdIdacInitTime" value="25"/>
<Param id="idacInFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[0]" alias="CYBSP_WCO_IN" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[1]" alias="CYBSP_WCO_OUT" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[3]" alias="CYBSP_QSPI_D3" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[4]" alias="CYBSP_QSPI_D2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[5]" alias="CYBSP_QSPI_D1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[6]" alias="CYBSP_QSPI_D0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[7]" alias="CYBSP_QSPI_SCK" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[14].pin[0]" alias="CYBSP_USB_DP" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[14].pin[1]" alias="CYBSP_USB_DM" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[7]" alias="CYBSP_WIFI_HOST_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="0"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[0]" alias="CYBSP_BT_UART_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[1]" alias="CYBSP_BT_UART_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[2]" alias="CYBSP_BT_UART_RTS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[3]" alias="CYBSP_BT_UART_CTS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[4]" alias="CYBSP_BT_POWER" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[5]" alias="CYBSP_BT_HOST_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="0"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[4].pin[0]" alias="CYBSP_BT_DEVICE_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="0"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[1]" alias="CYBSP_EZI2C_SDA" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[4]" alias="CYBSP_SWO" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[6]" alias="CYBSP_SWDIO" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[7]" alias="CYBSP_SWDCK" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[7].pin[1]" alias="CYBSP_CINA" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[7].pin[2]" alias="CYBSP_CINB" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[7].pin[7]" alias="CYBSP_CMOD" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[1]" alias="CYBSP_CSD_BTN0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[2]" alias="CYBSP_CSD_BTN1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[3]" alias="CYBSP_CSD_SLD0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[4]" alias="CYBSP_CSD_SLD1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[5]" alias="CYBSP_CSD_SLD2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[6]" alias="CYBSP_CSD_SLD3" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[8].pin[7]" alias="CYBSP_CSD_SLD4" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="peri[0].div_16[0]" alias="CYBSP_USB_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="1000"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[0]" alias="CYBSP_SDIO_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="8"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[3]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="256"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[4]" alias="" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="109"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="scb[2]" alias="CYBSP_BT_UART" template="mxs40uart" version="1.0">
<Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
<Param id="IrdaLowPower" value="false"/>
<Param id="BaudRate" value="115200"/>
<Param id="Oversample" value="8"/>
<Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
<Param id="DataWidth" value="8"/>
<Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
<Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
<Param id="EnableInputFilter" value="false"/>
<Param id="EnableTxEn" value="false"/>
<Param id="FlowControl" value="true"/>
<Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsTriggerLevel" value="63"/>
<Param id="RxTriggerLevel" value="1"/>
<Param id="TxTriggerLevel" value="63"/>
<Param id="MultiProc" value="false"/>
<Param id="MpRxAddress" value="0"/>
<Param id="MpRxAddressMask" value="255"/>
<Param id="MpRxAcceptAddress" value="false"/>
<Param id="DropOnFrameErr" value="false"/>
<Param id="DropOnParityErr" value="false"/>
<Param id="BreakSignalBits" value="11"/>
<Param id="SmCardRetryOnNack" value="false"/>
<Param id="IrdaPolarity" value="NON_INVERTING"/>
<Param id="inFlash" value="true"/>
<Param id="ApiMode" value="HIGH_LEVEL"/>
<Param id="IntrRxNotEmpty" value="false"/>
<Param id="IntrRxFull" value="false"/>
<Param id="IntrRxOverflow" value="false"/>
<Param id="IntrRxUnderflow" value="false"/>
<Param id="IntrRxFrameErr" value="false"/>
<Param id="IntrRxParityErr" value="false"/>
<Param id="IntrRxBreakDetected" value="false"/>
<Param id="IntrRxTrigger" value="false"/>
<Param id="IntrTxUartDone" value="false"/>
<Param id="IntrTxUartLostArb" value="false"/>
<Param id="IntrTxUartNack" value="false"/>
<Param id="IntrTxEmpty" value="false"/>
<Param id="IntrTxNotFull" value="false"/>
<Param id="IntrTxOverflow" value="false"/>
<Param id="IntrTxUnderflow" value="false"/>
<Param id="IntrTxTrigger" value="false"/>
</Block>
<Block location="scb[3]" alias="CYBSP_CSD_COMM" template="mxs40ezi2c" version="1.0">
<Param id="DataRate" value="100"/>
<Param id="NumOfAddr" value="CY_SCB_EZI2C_ONE_ADDRESS"/>
<Param id="SlaveAddress1" value="8"/>
<Param id="SlaveAddress2" value="9"/>
<Param id="SubAddrSize" value="CY_SCB_EZI2C_SUB_ADDR16_BITS"/>
<Param id="EnableWakeup" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
<Param id="configurator" value="0"/>
<Param id="isrAlignment" value="false"/>
<Param id="isrUnderflow" value="false"/>
<Param id="isrCmdOverflow" value="false"/>
<Param id="isrDataOverflow" value="false"/>
<Param id="rxTriggerLevel" value="0"/>
<Param id="txTriggerLevel" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="srss[0].clock[0]" alias="" template="mxs40sysclocks" version="1.2"/>
<Block location="srss[0].clock[0].altsystickclk[0]" alias="" template="mxs40altsystick" version="1.0">
<Param id="sourceClock" value="lfclk"/>
</Block>
<Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
<Param id="sourceClock" value="wco"/>
</Block>
<Block location="srss[0].clock[0].fastclk[0]" alias="" template="mxs40fastclk" version="1.0">
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].fll[0]" alias="" template="mxs40fll" version="1.0">
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="100.000"/>
</Block>
<Block location="srss[0].clock[0].hfclk[0]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].hfclk[1]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="1"/>
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].hfclk[2]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="2"/>
</Block>
<Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="1"/>
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].hfclk[4]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].ilo[0]" alias="" template="mxs40ilo" version="1.0">
<Param id="hibernate" value="true"/>
</Block>
<Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
<Param id="trim" value="0.25"/>
</Block>
<Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
<Param id="sourceClock" value="wco"/>
</Block>
<Block location="srss[0].clock[0].pathmux[0]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[1]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[2]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[3]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[4]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].pll[0]" alias="" template="mxs40pll" version="1.0">
<Param id="lowFrequencyMode" value="false"/>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="48.000"/>
<Param id="optimization" value="MinPower"/>
</Block>
<Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].timerclk[0]" alias="" template="mxs40timerclk" version="1.0">
<Param id="sourceClock" value="imo"/>
<Param id="timerDivider" value="1"/>
</Block>
<Block location="srss[0].clock[0].wco[0]" alias="" template="mxs40wco" version="1.0">
<Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
<Param id="clockLostDetection" value="false"/>
<Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
<Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
<Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
<Param id="accuracyPpm" value="150"/>
</Block>
<Block location="srss[0].mcwdt[0]" alias="CYBSP_MCWDT0" template="mxs40mcwdt" version="1.0">
<Param id="C0ClearOnMatch" value="FREE_RUNNING"/>
<Param id="C0Match" value="32768"/>
<Param id="C0Mode" value="CY_MCWDT_MODE_NONE"/>
<Param id="C1ClearOnMatch" value="FREE_RUNNING"/>
<Param id="C1Match" value="32768"/>
<Param id="C1Mode" value="CY_MCWDT_MODE_NONE"/>
<Param id="C2Mode" value="CY_MCWDT_MODE_NONE"/>
<Param id="C2Period" value="16"/>
<Param id="CascadeC0C1" value="true"/>
<Param id="CascadeC1C2" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
<Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
<Param id="pmicEnable" value="false"/>
<Param id="backupSrc" value="VDDD"/>
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
<Param id="deepsleepLatency" value="0"/>
<Param id="vddaMv" value="3300"/>
<Param id="vdddMv" value="3300"/>
<Param id="vBackupMv" value="3300"/>
<Param id="vddNsMv" value="3300"/>
<Param id="vddio0Mv" value="3300"/>
<Param id="vddio1Mv" value="3300"/>
</Block>
<Block location="srss[0].rtc[0]" alias="CYBSP_RTC" template="mxs40rtc" version="1.1">
<Param id="format" value="0"/>
<Param id="dst" value="false"/>
<Param id="dstFormat" value="CY_RTC_DST_RELATIVE"/>
<Param id="sec" value="0"/>
<Param id="min" value="0"/>
<Param id="hrFormat" value="CY_RTC_24_HOURS"/>
<Param id="hr" value="12"/>
<Param id="amPmPeriodOfDay" value="CY_RTC_AM"/>
<Param id="dayOfTheWeek" value="CY_RTC_SUNDAY"/>
<Param id="dayOfTheMonth" value="1"/>
<Param id="month" value="CY_RTC_JANUARY"/>
<Param id="year" value="0"/>
<Param id="dstStartMonth" value="CY_RTC_MARCH"/>
<Param id="dstStartDay" value="22"/>
<Param id="dstStartWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
<Param id="dstStartDayOfWeek" value="CY_RTC_SUNDAY"/>
<Param id="dstStartHour" value="0"/>
<Param id="dstStopMonth" value="CY_RTC_OCTOBER"/>
<Param id="dstStopDay" value="22"/>
<Param id="dstStopWeek" value="CY_RTC_LAST_WEEK_OF_MONTH"/>
<Param id="dstStopDayOfWeek" value="CY_RTC_SUNDAY"/>
<Param id="dstStopHour" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.1">
<Param id="epMask" value="0"/>
<Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
<Param id="bufSize" value="512"/>
<Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
<Param id="enableLpm" value="false"/>
<Param id="lpmIntr" value="0x0U"/>
<Param id="ArbIntr" value="0x0U"/>
<Param id="ep0CntrIntr" value="0x2U"/>
<Param id="busResetIntr" value="0x2U"/>
<Param id="sofIntr" value="0x1U"/>
<Param id="ep0Intr" value="0x1U"/>
<Param id="ep1Intr" value="0x1U"/>
<Param id="ep2Intr" value="0x1U"/>
<Param id="ep3Intr" value="0x1U"/>
<Param id="ep4Intr" value="0x1U"/>
<Param id="ep5Intr" value="0x1U"/>
<Param id="ep6Intr" value="0x1U"/>
<Param id="ep7Intr" value="0x1U"/>
<Param id="inFlash" value="true"/>
</Block>
</BlockConfig>
<Netlist>
<Net>
<Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
<Port name="ioss[0].port[6].pin[7].digital_in[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
<Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
<Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
</Net>
<Net>
<Port name="csd[0].csd[0].clock[0]"/>
<Port name="peri[0].div_8[3].clk[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[0].pin[0].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_in[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[0].pin[1].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
<Port name="scb[2].uart_rx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[3].pin[1].digital_inout[0]"/>
<Port name="scb[2].uart_tx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[3].pin[2].digital_out[0]"/>
<Port name="scb[2].uart_rts[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[3].pin[3].digital_in[0]"/>
<Port name="scb[2].uart_cts[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
<Port name="scb[3].i2c_scl[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[6].pin[1].digital_inout[0]"/>
<Port name="scb[3].i2c_sda[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[2].digital_out[0]"/>
<Port name="smif[0].spi_select0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[3].digital_out[0]"/>
<Port name="smif[0].spi_data3[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[4].digital_out[0]"/>
<Port name="smif[0].spi_data2[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[5].digital_out[0]"/>
<Port name="smif[0].spi_data1[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[6].digital_out[0]"/>
<Port name="smif[0].spi_data0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
<Port name="smif[0].spi_clk[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[14].pin[0].aux[0]"/>
<Port name="usb[0].usb_dp_pad[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[14].pin[1].aux[0]"/>
<Port name="usb[0].usb_dm_pad[0]"/>
</Net>
<Net>
<Port name="peri[0].div_16[0].clk[0]"/>
<Port name="usb[0].clock_dev_brs[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[1].clk[0]"/>
<Port name="scb[3].clock[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[4].clk[0]"/>
<Port name="scb[2].clock[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_hf[0]"/>
<Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_if[0]"/>
<Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
</Net>
<Net>
<Port name="srss[0].clock[0].hfclk[3].root_clk[0]"/>
<Port name="usb[0].clk_usb_dev[0]"/>
</Net>
<Mux name="sense" location="csd[0].csd[0]">
<Arm>
<Port name="ioss[0].port[7].pin[7].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[7].pin[1].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[7].pin[2].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[1].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[1].pin[0].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[2].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[1].pin[0].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[3].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[4].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[5].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[6].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[7].analog[0]"/>
</Arm>
</Mux>
</Netlist>
</Device>
<Device mpn="CYW4343WKUBG">
<BlockConfig/>
<Netlist/>
</Device>
</Devices>
<Libraries/>
<ConfiguratorData/>
</Design>

114
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/PeripheralNames.h Normal file
View File

@ -0,0 +1,114 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
* Copyright (c) 2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)SCB0_BASE,
UART_1 = (int)SCB1_BASE,
UART_2 = (int)SCB2_BASE,
UART_3 = (int)SCB3_BASE,
UART_4 = (int)SCB4_BASE,
UART_5 = (int)SCB5_BASE,
UART_6 = (int)SCB6_BASE,
UART_7 = (int)SCB7_BASE,
} UARTName;
#define DEVICE_SPI_COUNT CY_IP_MXSCB_INSTANCES
typedef enum {
SPI_0 = (int)SCB0_BASE,
SPI_1 = (int)SCB1_BASE,
SPI_2 = (int)SCB2_BASE,
SPI_3 = (int)SCB3_BASE,
SPI_4 = (int)SCB4_BASE,
SPI_5 = (int)SCB5_BASE,
SPI_6 = (int)SCB6_BASE,
SPI_7 = (int)SCB7_BASE,
SPI_8 = (int)SCB8_BASE,
} SPIName;
typedef enum {
I2C_0 = (int)SCB0_BASE,
I2C_1 = (int)SCB1_BASE,
I2C_2 = (int)SCB2_BASE,
I2C_3 = (int)SCB3_BASE,
I2C_4 = (int)SCB4_BASE,
I2C_5 = (int)SCB5_BASE,
I2C_6 = (int)SCB6_BASE,
I2C_7 = (int)SCB7_BASE,
I2C_8 = (int)SCB8_BASE,
} I2CName;
typedef enum {
PWM_32b_0 = TCPWM0_BASE,
PWM_32b_1,
PWM_32b_2,
PWM_32b_3,
PWM_32b_4,
PWM_32b_5,
PWM_32b_6,
PWM_32b_7,
PWM_16b_0 = TCPWM1_BASE,
PWM_16b_1,
PWM_16b_2,
PWM_16b_3,
PWM_16b_4,
PWM_16b_5,
PWM_16b_6,
PWM_16b_7,
PWM_16b_8,
PWM_16b_9,
PWM_16b_10,
PWM_16b_11,
PWM_16b_12,
PWM_16b_13,
PWM_16b_14,
PWM_16b_15,
PWM_16b_16,
PWM_16b_17,
PWM_16b_18,
PWM_16b_19,
PWM_16b_20,
PWM_16b_21,
PWM_16b_22,
PWM_16b_23,
} PWMName;
typedef enum {
ADC_0 = (int)SAR_BASE,
} ADCName;
typedef enum {
QSPI_0,
} QSPIName;
#ifdef __cplusplus
}
#endif
#endif

467
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/PeripheralPins.c Normal file
View File

@ -0,0 +1,467 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
* Copyright (c) 2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralNames.h"
#include "PeripheralPins.h"
#include "pinmap.h"
#if DEVICE_SERIAL
//*** SERIAL ***
const PinMap PinMap_UART_RX[] = {
{P0_2, UART_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
{P1_0, UART_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)},
{P2_0, UART_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)},
{P3_0, UART_2, CYHAL_PIN_IN_FUNCTION(P3_0_SCB2_UART_RX)},
{P4_0, UART_7, CYHAL_PIN_IN_FUNCTION(P4_0_SCB7_UART_RX)},
{P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
{P6_0, UART_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
{P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
{P7_0, UART_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
{P8_0, UART_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
{P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
{P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
{P11_0, UART_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
{P12_0, UART_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)},
{P13_0, UART_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)},
{NC, NC, 0}
};
const PinMap PinMap_UART_TX[] = {
{P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
{P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)},
{P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)},
{P3_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_1_SCB2_UART_TX)},
{P4_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P4_1_SCB7_UART_TX)},
{P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
{P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
{P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
{P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
{P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
{P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
{P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
{P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
{P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)},
{P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)},
{NC, NC, 0}
};
const PinMap PinMap_UART_RTS[] = {
{P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
{P1_2, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_UART_RTS)},
{P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)},
{P3_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_UART_RTS)},
{P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
{P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
{P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
{P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
{P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
{P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
{P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)},
{P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
{P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)},
{NC, NC, 0}
};
const PinMap PinMap_UART_CTS[] = {
{P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
{P1_3, UART_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_UART_CTS)},
{P2_3, UART_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)},
{P3_3, UART_2, CYHAL_PIN_IN_FUNCTION(P3_3_SCB2_UART_CTS)},
{P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
{P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
{P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
{P7_3, UART_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
{P8_3, UART_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)},
{P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
{P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)},
{P11_3, UART_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
{P12_3, UART_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)},
{NC, NC, 0}
};
#endif // DEVICE_SERIAL
#if DEVICE_I2C
//*** I2C ***
const PinMap PinMap_I2C_SCL[] = {
{P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
{P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
{P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)},
{P3_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_0_SCB2_I2C_SCL)},
{P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_0_SCB7_I2C_SCL)},
{P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
{P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
{P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
{P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)},
{P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)},
{NC, NC, 0}
};
const PinMap PinMap_I2C_SDA[] = {
{P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
{P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
{P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)},
{P3_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_1_SCB2_I2C_SDA)},
{P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_1_SCB7_I2C_SDA)},
{P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
{P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
{P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
{P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)},
{P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)},
{NC, NC, 0}
};
#endif // DEVICE_I2C
#if DEVICE_SPI
//*** SPI ***
const PinMap PinMap_SPI_MOSI[] = {
{P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)},
{P3_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_0_SCB2_SPI_MOSI)},
{P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)},
{P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)},
{NC, NC, 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)},
{P3_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P3_1_SCB2_SPI_MISO)},
{P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)},
{P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SCLK[] = {
{P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)},
{P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)},
{P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)},
{P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)},
{NC, NC, 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
{P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)},
{P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
{P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
{NC, NC, 0}
};
#endif // DEVICE_SPI
#if DEVICE_PWMOUT
//*** PWM ***
const PinMap PinMap_PWM_OUT[] = {
// 16-bit PWM outputs
{P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
{P0_2, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)},
{P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
{P1_0, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)},
{P1_2, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12)},
{P1_4, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)},
{P2_0, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15)},
{P2_2, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16)},
{P2_4, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17)},
{P2_6, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18)},
{P3_0, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM1_LINE19)},
{P3_2, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM1_LINE20)},
{P3_4, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM1_LINE21)},
{P4_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM1_LINE22)},
{P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)},
{P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)},
{P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)},
{P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)},
{P6_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)},
{P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
{P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
{P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
{P7_0, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)},
{P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
{P7_4, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)},
{P7_6, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)},
{P8_0, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)},
{P8_2, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)},
{P8_4, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)},
{P8_6, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19)},
{P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
{P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
{P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)},
{P9_6, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)},
{P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
{P10_2, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)},
{P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)},
{P10_6, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)},
{P11_0, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)},
{P11_2, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)},
{P11_4, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)},
{P12_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)},
{P12_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)},
{P12_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)},
{P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)},
{P13_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)},
{P13_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)},
{P13_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)},
{P13_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)},
// 16-bit PWM inverted outputs
{P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
{P0_3, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)},
{P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
{P1_1, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)},
{P1_3, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12)},
{P1_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)},
{P2_1, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15)},
{P2_3, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16)},
{P2_5, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17)},
{P2_7, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18)},
{P3_1, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM1_LINE_COMPL19)},
{P3_3, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM1_LINE_COMPL20)},
{P3_5, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM1_LINE_COMPL21)},
{P4_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM1_LINE_COMPL22)},
{P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)},
{P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)},
{P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)},
{P5_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)},
{P6_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)},
{P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
{P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
{P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
{P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
{P7_3, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)},
{P7_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)},
{P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
{P8_1, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)},
{P8_3, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)},
{P8_5, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18)},
{P8_7, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19)},
{P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
{P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
{P9_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)},
{P9_7, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)},
{P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
{P10_3, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)},
{P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)},
{P10_7, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)},
{P11_1, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)},
{P11_3, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)},
{P11_5, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)},
{P12_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)},
{P12_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)},
{P12_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)},
{P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)},
{P13_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)},
{P13_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)},
{P13_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)},
{P13_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)},
// 32-bit PWM outputs
{P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
{P0_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)},
{P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
{P1_0, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)},
{P1_2, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4)},
{P1_4, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)},
{P2_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6)},
{P2_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7)},
{P2_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0)},
{P2_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1)},
{P3_0, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM0_LINE2)},
{P3_2, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM0_LINE3)},
{P3_4, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM0_LINE4)},
{P4_0, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM0_LINE5)},
{P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)},
{P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)},
{P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)},
{P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)},
{P6_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)},
{P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
{P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
{P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
{P7_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)},
{P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
{P7_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)},
{P7_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)},
{P8_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)},
{P8_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)},
{P8_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)},
{P8_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3)},
{P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
{P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
{P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)},
{P9_6, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)},
{P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
{P10_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)},
{P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)},
{P10_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)},
{P11_0, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)},
{P11_2, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)},
{P11_4, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)},
{P12_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)},
{P12_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)},
{P12_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)},
{P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)},
{P13_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)},
{P13_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)},
{P13_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)},
{P13_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)},
// 32-bit PWM inverted outputs
{P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
{P0_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)},
{P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
{P1_1, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)},
{P1_3, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4)},
{P1_5, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)},
{P2_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6)},
{P2_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7)},
{P2_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0)},
{P2_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1)},
{P3_1, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM0_LINE_COMPL2)},
{P3_3, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM0_LINE_COMPL3)},
{P3_5, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM0_LINE_COMPL4)},
{P4_1, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM0_LINE_COMPL5)},
{P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)},
{P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)},
{P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)},
{P5_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)},
{P6_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)},
{P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
{P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
{P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
{P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
{P7_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)},
{P7_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)},
{P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
{P8_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)},
{P8_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)},
{P8_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2)},
{P8_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3)},
{P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
{P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
{P9_5, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)},
{P9_7, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)},
{P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
{P10_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)},
{P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)},
{P10_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)},
{P11_1, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)},
{P11_3, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)},
{P11_5, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)},
{P12_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)},
{P12_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)},
{P12_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)},
{P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)},
{P13_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)},
{P13_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)},
{P13_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)},
{P13_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)},
{NC, NC, 0}
};
#endif // DEVICE_PWMOUT
#if DEVICE_ANALOGIN
const PinMap PinMap_ADC[] = {
{P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
{NC, NC, 0}
};
#endif // DEVICE_ANALOGIN
#if DEVICE_QSPI
const PinMap PinMap_QSPI_SCLK[] = {
{P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
{NC, NC, 0},
};
const PinMap PinMap_QSPI_SSEL[] = {
{P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
{NC, NC, 0},
};
const PinMap PinMap_QSPI_DATA0[] = {
{P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
{NC, NC, 0},
};
const PinMap PinMap_QSPI_DATA1[] = {
{P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
{NC, NC, 0},
};
const PinMap PinMap_QSPI_DATA2[] = {
{P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
{NC, NC, 0},
};
const PinMap PinMap_QSPI_DATA3[] = {
{P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
{NC, NC, 0},
};
#endif // DEVICE_QSPI

80
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/PinNames.h Normal file
View File

@ -0,0 +1,80 @@
/*
* mbed Microcontroller Library
* Copyright (c) 2017-2018 Future Electronics
* Copyright (c) 2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "PinNamesTypes.h"
#include "cyhal_pin_package.h"
// Generic signal names
#define I2C_SCL P6_0
#define I2C_SDA P6_1
#define SPI_MOSI P12_0
#define SPI_MISO P12_1
#define SPI_CLK P12_2
#define SPI_CS P12_4
#define UART_RX P5_0
#define UART_TX P5_1
#define UART_RTS P5_2
#define UART_CTS P5_3
#define LED1 P0_3
#define LED2 P11_1
#define LED3 P1_1
#define LED4 P1_5
#define LED5 P13_7
#define LED_RED LED1
#define LED_BLUE LED2
#define LED_GREEN LED3
// Reset pin unavailable
#define SWITCH2 P0_4
#define USER_BUTTON SWITCH2
#define BUTTON1 USER_BUTTON
#define QSPI_CLK P11_7
#define QSPI_IO_0 P11_6
#define QSPI_IO_1 P11_5
#define QSPI_IO_2 P11_4
#define QSPI_IO_3 P11_3
#define QSPI_SEL P11_2
#define QSPI_FLASH1_IO0 QSPI_IO_0
#define QSPI_FLASH1_IO1 QSPI_IO_1
#define QSPI_FLASH1_IO2 QSPI_IO_2
#define QSPI_FLASH1_IO3 QSPI_IO_3
#define QSPI_FLASH1_SCK QSPI_CLK
#define QSPI_FLASH1_CSN QSPI_SEL
// Standardized interfaces names
#define STDIO_UART_TX UART_TX
#define STDIO_UART_RX UART_RX
#define STDIO_UART_CTS UART_CTS
#define STDIO_UART_RTS UART_RTS
#define USBTX UART_TX
#define USBRX UART_RX
#define AOUT P9_6
#endif

124
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.c Normal file
View File

@ -0,0 +1,124 @@
/***************************************************************************//**
* \file cybsp.c
*
* Description:
* Provides initialization code for starting up the hardware contained on the
* Cypress board.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <stdlib.h>
#include "cybsp.h"
#if defined(CY_USING_HAL)
#include "cyhal_utils.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#endif
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
static cyhal_sdio_t sdio_obj;
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
{
return &sdio_obj;
}
#endif
/**
* Registers a power management callback that prepares the clock system
* for entering deep sleep mode and restore the clocks upon wakeup from deep sleep.
* NOTE: This is called automatically as part of \ref cybsp_init
*/
static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL};
static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = {
.callback = &Cy_SysClk_DeepSleepCallback,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &cybsp_sysclk_pm_callback_param,
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
{
result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
}
return result;
}
cy_rslt_t cybsp_init(void)
{
/* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
#if defined(CY_USING_HAL)
cy_rslt_t result = cyhal_hwmgr_init();
#else
cy_rslt_t result = CY_RSLT_SUCCESS;
#endif
init_cycfg_system();
if (CY_RSLT_SUCCESS == result)
{
result = cybsp_register_sysclk_pm_callback();
}
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
/* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
* specific peripheral instances.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
*/
if (CY_RSLT_SUCCESS == result)
{
/* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
* CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
*/
result = cyhal_sdio_init(
&sdio_obj,
CYBSP_WIFI_SDIO_CMD,
CYBSP_WIFI_SDIO_CLK,
CYBSP_WIFI_SDIO_D0,
CYBSP_WIFI_SDIO_D1,
CYBSP_WIFI_SDIO_D2,
CYBSP_WIFI_SDIO_D3);
}
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both.
*/
return result;
}
#if defined(__cplusplus)
}
#endif

74
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp.h Normal file
View File

@ -0,0 +1,74 @@
/***************************************************************************//**
* \file cybsp.h
*
* \brief
* Basic API for setting up boards containing a Cypress MCU.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include "cy_result.h"
#include "cybsp_types.h"
#include "cycfg.h"
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
#include "cyhal_sdio.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_macros Macros
* \{
*/
/** Failed to configure sysclk power management callback */
#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
/** \} group_bsp_macros */
/**
* \addtogroup group_bsp_functions Functions
* \{
*/
/**
* \brief Initialize all hardware on the board
* \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is
* a problem initializing any hardware it returns an error code specific
* to the hardware module that had a problem.
*/
cy_rslt_t cybsp_init(void);
#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
/**
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \note This function should only be called after cybsp_init();
* \returns The initialized sdio object.
*/
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/** \} group_bsp_functions */
#ifdef __cplusplus
}
#endif /* __cplusplus */

243
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/cybsp_types.h Normal file
View File

@ -0,0 +1,243 @@
/***************************************************************************//**
* \file CY8CKIT-064S2-4343W/cybsp_types.h
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CY8CKIT-064S2-4343W pioneer kit.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#if defined(CY_USING_HAL)
#include "cyhal_pin_package.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_pin_state Pin States
* \{
*/
/** Pin state for the LED on. */
#define CYBSP_LED_STATE_ON (0U)
/** Pin state for the LED off. */
#define CYBSP_LED_STATE_OFF (1U)
/** Pin state for when a button is pressed. */
#define CYBSP_BTN_PRESSED (0U)
/** Pin state for when a button is released. */
#define CYBSP_BTN_OFF (1U)
/** \} group_bsp_pin_state */
#if defined(CY_USING_HAL)
/**
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
/**
* \addtogroup group_bsp_pins_led LED Pins
* \{
*/
/** LED 8; User LED1 */
#define CYBSP_LED8 (P1_5)
/** LED 9; User LED2 */
#define CYBSP_LED9 (P13_7)
/** LED 5: RGB LED - Red; User LED3 */
#define CYBSP_LED_RGB_RED (P0_3)
/** LED 5: RGB LED - Green; User LED4 */
#define CYBSP_LED_RGB_GREEN (P1_1)
/** LED 5: RGB LED - Blue; User LED5 */
#define CYBSP_LED_RGB_BLUE (P11_1)
/** LED 8; User LED1 */
#define CYBSP_USER_LED1 (CYBSP_LED8)
/** LED 9; User LED2 */
#define CYBSP_USER_LED2 (CYBSP_LED9)
/** LED 5: RGB LED - Red; User LED3 */
#define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED)
/** LED 5: RGB LED - Green; User LED4 */
#define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN)
/** LED 5: RGB LED - Blue; User LED5 */
#define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE)
/** LED 8; User LED1 */
#define CYBSP_USER_LED (CYBSP_USER_LED1)
/** \} group_bsp_pins_led */
/**
* \addtogroup group_bsp_pins_btn Button Pins
* \{
*/
/** Switch 2; User Button 1 */
#define CYBSP_SW2 (P0_4)
/** Switch 2; User Button 1 */
#define CYBSP_USER_BTN1 (CYBSP_SW2)
/** Switch 2; User Button 1 */
#define CYBSP_USER_BTN (CYBSP_USER_BTN1)
/** \} group_bsp_pins_btn */
/**
* \addtogroup group_bsp_pins_comm Communication Pins
* \{
*/
/** Pin: WIFI SDIO D0 */
#define CYBSP_WIFI_SDIO_D0 (P2_0)
/** Pin: WIFI SDIO D1 */
#define CYBSP_WIFI_SDIO_D1 (P2_1)
/** Pin: WIFI SDIO D2 */
#define CYBSP_WIFI_SDIO_D2 (P2_2)
/** Pin: WIFI SDIO D3 */
#define CYBSP_WIFI_SDIO_D3 (P2_3)
/** Pin: WIFI SDIO CMD */
#define CYBSP_WIFI_SDIO_CMD (P2_4)
/** Pin: WIFI SDIO CLK */
#define CYBSP_WIFI_SDIO_CLK (P2_5)
/** Pin: WIFI ON */
#define CYBSP_WIFI_WL_REG_ON (P2_6)
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE (P2_7)
/** Pin: BT UART RX */
#define CYBSP_BT_UART_RX (P3_0)
/** Pin: BT UART TX */
#define CYBSP_BT_UART_TX (P3_1)
/** Pin: BT UART RTS */
#define CYBSP_BT_UART_RTS (P3_2)
/** Pin: BT UART CTS */
#define CYBSP_BT_UART_CTS (P3_3)
/** Pin: BT Power */
#define CYBSP_BT_POWER (P3_4)
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE (P3_5)
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE (P4_0)
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RX (P5_0)
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_TX (P5_1)
/** Pin: I2C SCL */
#define CYBSP_I2C_SCL (P6_0)
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA (P6_1)
/** Pin: SWO */
#define CYBSP_SWO (P6_4)
/** Pin: SWDIO */
#define CYBSP_SWDIO (P6_6)
/** Pin: SWDCK */
#define CYBSP_SWDCK (P6_7)
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS (P11_2)
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 (P11_3)
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 (P11_4)
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 (P11_5)
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 (P11_6)
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK (P11_7)
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
/** \} group_bsp_pins_comm */
/**
* \addtogroup group_bsp_pins_arduino Arduino Header Pins
* \{
*/
/** Arduino A0 */
#define CYBSP_A0 P10_0
/** Arduino A1 */
#define CYBSP_A1 P10_1
/** Arduino A2 */
#define CYBSP_A2 P10_2
/** Arduino A3 */
#define CYBSP_A3 P10_3
/** Arduino A4 */
#define CYBSP_A4 P10_4
/** Arduino A5 */
#define CYBSP_A5 P10_5
/** Arduino D0 */
#define CYBSP_D0 (P5_0)
/** Arduino D1 */
#define CYBSP_D1 (P5_1)
/** Arduino D2 */
#define CYBSP_D2 (P5_2)
/** Arduino D3 */
#define CYBSP_D3 (P5_3)
/** Arduino D4 */
#define CYBSP_D4 (P5_4)
/** Arduino D5 */
#define CYBSP_D5 (P5_5)
/** Arduino D6 */
#define CYBSP_D6 (P5_6)
/** Arduino D7 */
#define CYBSP_D7 (P0_2)
/** Arduino D8 */
#define CYBSP_D8 (P13_0)
/** Arduino D9 */
#define CYBSP_D9 (P13_1)
/** Arduino D10 */
#define CYBSP_D10 (P12_3)
/** Arduino D11 */
#define CYBSP_D11 (P12_0)
/** Arduino D12 */
#define CYBSP_D12 (P12_1)
/** Arduino D13 */
#define CYBSP_D13 (P12_2)
/** Arduino D14 */
#define CYBSP_D14 (P6_1)
/** Arduino D15 */
#define CYBSP_D15 (P6_0)
/** \} group_bsp_pins_arduino */
/** \} group_bsp_pins */
#endif /* defined(CY_USING_HAL) */
#if defined(__cplusplus)
}
#endif

300
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct Normal file
View File

@ -0,0 +1,300 @@
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;*******************************************************************************
;* \file cyb06xxa_cm4_dual.sct
;* \version 2.60
;*
;* Linker file for the ARMCC.
;*
;* The main purpose of the linker script is to describe how the sections in the
;* input files should be mapped into the output file, and to control the memory
;* layout of the output file.
;*
;* \note The entry point location is fixed and starts at 0x10000000. The valid
;* application image should be placed there.
;*
;* \note The linker files included with the PDL template projects must be
;* generic and handle all common use cases. Your project may not use every
;* section defined in the linker files. In that case you may see the warnings
;* during the build process: L6314W (no section matches pattern) and/or L6329W
;* (pattern only matches removed unused sections). In your project, you can
;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
;* the linker, simply comment out or remove the relevant code in the linker
;* file.
;*
;*******************************************************************************
;* \copyright
;* Copyright 2016-2019 Cypress Semiconductor Corporation
;* SPDX-License-Identifier: Apache-2.0
;*
;* Licensed under the Apache License, Version 2.0 (the "License");
;* you may not use this file except in compliance with the License.
;* You may obtain a copy of the License at
;*
;* http://www.apache.org/licenses/LICENSE-2.0
;*
;* Unless required by applicable law or agreed to in writing, software
;* distributed under the License is distributed on an "AS IS" BASIS,
;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
;* See the License for the specific language governing permissions and
;* limitations under the License.
;******************************************************************************/
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000400
#endif
;* MBED_APP_START is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_START
;* is equal to MBED_ROM_START
;*
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x001CFC00
#endif
;* MBED_APP_SIZE is being used by the bootloader build script and
;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
;* is equal to MBED_ROM_SIZE
;*
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x000D8000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
; Use these defines to specify the memory regions available for allocation.
; The following defines control RAM and flash memory allocation for the CM4 core.
; You can change the memory allocation by editing RAM and Flash defines.
; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
; Using this memory region for other purposes will lead to unexpected behavior.
; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
; RAM
#define RAM_START MBED_RAM_START
#define RAM_SIZE MBED_RAM_SIZE
; Flash
#define FLASH_START MBED_APP_START
#define FLASH_SIZE MBED_APP_SIZE
; The following defines describe a 32K flash region used for EEPROM emulation.
; This region can also be used as the general purpose flash.
; You can assign sections to this memory region for only one of the cores.
; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
; Therefore, repurposing this memory region will prevent such middleware from operation.
#define EM_EEPROM_START 0x14000000
#define EM_EEPROM_SIZE 0x8000
; The following defines describe device specific memory regions and must not be changed.
; Supervisory flash: User data
#define SFLASH_USER_DATA_START 0x16000800
#define SFLASH_USER_DATA_SIZE 0x00000800
; Supervisory flash: Normal Access Restrictions (NAR)
#define SFLASH_NAR_START 0x16001A00
#define SFLASH_NAR_SIZE 0x00000200
; Supervisory flash: Public Key
#define SFLASH_PUBLIC_KEY_START 0x16005A00
#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
; Supervisory flash: Table of Content # 2
#define SFLASH_TOC_2_START 0x16007C00
#define SFLASH_TOC_2_SIZE 0x00000200
; Supervisory flash: Table of Content # 2 Copy
#define SFLASH_RTOC_2_START 0x16007E00
#define SFLASH_RTOC_2_SIZE 0x00000200
; External memory
#define XIP_START 0x18000000
#define XIP_SIZE 0x08000000
; eFuse
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
{
* (RESET, +FIRST)
}
ER_FLASH_CODE +0 FIXED
{
* (InRoot$$Sections)
* (+RO)
}
ER_RAM_VECTORS RAM_START UNINIT
{
* (RESET_RAM, +FIRST)
}
RW_RAM_DATA +0
{
* (.cy_ramfunc)
* (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
; device startup.
RW_IRAM1 +0 UNINIT
{
* (.noinit)
}
; Application heap area (HEAP)
ARM_LIB_HEAP +0
{
* (HEAP)
}
; Stack region growing down
ARM_LIB_STACK RAM_START+RAM_SIZE -STACK_SIZE
{
* (STACK)
}
; Used for the digital signature of the secure application and the
; Bootloader SDK application. The size of the section depends on the required
; data size.
.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
{
* (.cy_app_signature)
}
}
; Emulated EEPROM Flash area
LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
{
.cy_em_eeprom +0
{
* (.cy_em_eeprom)
}
}
; Supervisory flash: User data
LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
{
.cy_sflash_user_data +0
{
* (.cy_sflash_user_data)
}
}
; Supervisory flash: Normal Access Restrictions (NAR)
LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
{
.cy_sflash_nar +0
{
* (.cy_sflash_nar)
}
}
; Supervisory flash: Public Key
LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
{
.cy_sflash_public_key +0
{
* (.cy_sflash_public_key)
}
}
; Supervisory flash: Table of Content # 2
LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
{
.cy_toc_part2 +0
{
* (.cy_toc_part2)
}
}
; Supervisory flash: Table of Content # 2 Copy
LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
{
.cy_rtoc_part2 +0
{
* (.cy_rtoc_part2)
}
}
; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
LR_EROM XIP_START XIP_SIZE
{
.cy_xip +0
{
* (.cy_xip)
}
}
; eFuse
LR_EFUSE EFUSE_START EFUSE_SIZE
{
.cy_efuse +0
{
* (.cy_efuse)
}
}
; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
#define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x001D0000
#define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */
#define __cy_memory_1_start 0x14000000
#define __cy_memory_1_length 0x8000
#define __cy_memory_1_row_size 0x200
/* Supervisory Flash */
#define __cy_memory_2_start 0x16000000
#define __cy_memory_2_length 0x8000
#define __cy_memory_2_row_size 0x200
/* XIP */
#define __cy_memory_3_start 0x18000000
#define __cy_memory_3_length 0x08000000
#define __cy_memory_3_row_size 0x200
/* eFuse */
#define __cy_memory_4_start 0x90700000
#define __cy_memory_4_length 0x100000
#define __cy_memory_4_row_size 1
/* [] END OF FILE */

747
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S Normal file
View File

@ -0,0 +1,747 @@
;/**************************************************************************//**
; * @file startup_psoc6_02_cm4.S
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device Series
; * @version V5.00
; * @date 02. March 2016
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
Stack_Size EQU 0x00000400
ENDIF
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
IF :DEF:__HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
Heap_Size EQU 0x00000400
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD 0x0000000D ; NMI Handler located at ROM code
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External interrupts Description
DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0
DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1
DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2
DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3
DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4
DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5
DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6
DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7
DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8
DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9
DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10
DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11
DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12
DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13
DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14
DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports
DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt
DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt
DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable)
DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0
DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1
DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2
DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3
DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4
DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5
DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6
DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7
DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8
DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9
DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10
DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11
DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12
DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13
DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14
DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15
DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0
DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1
DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2
DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3
DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4
DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5
DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6
DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7
DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9
DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10
DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11
DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12
DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0
DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1
DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2
DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3
DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0
DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1
DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2
DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3
DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4
DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5
DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6
DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7
DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8
DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9
DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10
DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11
DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12
DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13
DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14
DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15
DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16
DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17
DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18
DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19
DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20
DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21
DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22
DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23
DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24
DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25
DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26
DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27
DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28
DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0
DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1
DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2
DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3
DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4
DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5
DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6
DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7
DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8
DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9
DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10
DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11
DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12
DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13
DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14
DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15
DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16
DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17
DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18
DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19
DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20
DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21
DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22
DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23
DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24
DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25
DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26
DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27
DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28
DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0
DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1
DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt
DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt
DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault
DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0
DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1
DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0
DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1
DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0
DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1
DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2
DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3
DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4
DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5
DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6
DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7
DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0
DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1
DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2
DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3
DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4
DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5
DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6
DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7
DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8
DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9
DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10
DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11
DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12
DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13
DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14
DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15
DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16
DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17
DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18
DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19
DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20
DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21
DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22
DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23
DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt
DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt
DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt
DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
DCD usb_interrupt_hi_IRQHandler ; USB Interrupt
DCD usb_interrupt_med_IRQHandler ; USB Interrupt
DCD usb_interrupt_lo_IRQHandler ; USB Interrupt
DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc
DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else
DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used
DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
EXPORT __ramVectors
AREA RESET_RAM, READWRITE, NOINIT
__ramVectors SPACE __Vectors_Size
AREA |.text|, CODE, READONLY
; Weak function for startup customization
;
; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
; because this function is executed as the first instruction in the ResetHandler.
; The PDL is also not initialized to use the proper register offsets.
; The user of this function is responsible for initializing the PDL and resources before using them.
;
Cy_OnResetUser PROC
EXPORT Cy_OnResetUser [WEAK]
BX LR
ENDP
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT Cy_SystemInitFpuEnable
IMPORT __main
; Define strong function for startup customization
BL Cy_OnResetUser
; Disable global interrupts
CPSID I
; Copy vectors from ROM to RAM
LDR r1, =__Vectors
LDR r0, =__ramVectors
LDR r2, =__Vectors_Size
Vectors_Copy
LDR r3, [r1]
STR r3, [r0]
ADDS r0, r0, #4
ADDS r1, r1, #4
SUBS r2, r2, #1
CMP r2, #0
BNE Vectors_Copy
; Update Vector Table Offset Register. */
LDR r0, =__ramVectors
LDR r1, =0xE000ED08
STR r0, [r1]
dsb 0xF
; Enable the FPU if used
LDR R0, =Cy_SystemInitFpuEnable
BLX R0
LDR R0, =__main
BLX R0
; Should never get here
B .
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
Cy_SysLib_FaultHandler PROC
EXPORT Cy_SysLib_FaultHandler [WEAK]
B .
ENDP
HardFault_Wrapper\
PROC
EXPORT HardFault_Wrapper [WEAK]
movs r0, #4
mov r1, LR
tst r0, r1
beq L_MSP
mrs r0, PSP
bl L_API_call
L_MSP
mrs r0, MSP
L_API_call
bl Cy_SysLib_FaultHandler
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B HardFault_Wrapper
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B HardFault_Wrapper
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B HardFault_Wrapper
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B HardFault_Wrapper
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT Default_Handler [WEAK]
EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK]
EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK]
EXPORT ioss_interrupt_gpio_IRQHandler [WEAK]
EXPORT ioss_interrupt_vdd_IRQHandler [WEAK]
EXPORT lpcomp_interrupt_IRQHandler [WEAK]
EXPORT scb_8_interrupt_IRQHandler [WEAK]
EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK]
EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK]
EXPORT srss_interrupt_backup_IRQHandler [WEAK]
EXPORT srss_interrupt_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK]
EXPORT scb_0_interrupt_IRQHandler [WEAK]
EXPORT scb_1_interrupt_IRQHandler [WEAK]
EXPORT scb_2_interrupt_IRQHandler [WEAK]
EXPORT scb_3_interrupt_IRQHandler [WEAK]
EXPORT scb_4_interrupt_IRQHandler [WEAK]
EXPORT scb_5_interrupt_IRQHandler [WEAK]
EXPORT scb_6_interrupt_IRQHandler [WEAK]
EXPORT scb_7_interrupt_IRQHandler [WEAK]
EXPORT scb_9_interrupt_IRQHandler [WEAK]
EXPORT scb_10_interrupt_IRQHandler [WEAK]
EXPORT scb_11_interrupt_IRQHandler [WEAK]
EXPORT scb_12_interrupt_IRQHandler [WEAK]
EXPORT csd_interrupt_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK]
EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK]
EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK]
EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK]
EXPORT cpuss_interrupt_fm_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK]
EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK]
EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK]
EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK]
EXPORT pass_interrupt_sar_IRQHandler [WEAK]
EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK]
EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK]
EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK]
EXPORT profile_interrupt_IRQHandler [WEAK]
EXPORT smif_interrupt_IRQHandler [WEAK]
EXPORT usb_interrupt_hi_IRQHandler [WEAK]
EXPORT usb_interrupt_med_IRQHandler [WEAK]
EXPORT usb_interrupt_lo_IRQHandler [WEAK]
EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK]
EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK]
EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK]
EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK]
ioss_interrupts_gpio_0_IRQHandler
ioss_interrupts_gpio_1_IRQHandler
ioss_interrupts_gpio_2_IRQHandler
ioss_interrupts_gpio_3_IRQHandler
ioss_interrupts_gpio_4_IRQHandler
ioss_interrupts_gpio_5_IRQHandler
ioss_interrupts_gpio_6_IRQHandler
ioss_interrupts_gpio_7_IRQHandler
ioss_interrupts_gpio_8_IRQHandler
ioss_interrupts_gpio_9_IRQHandler
ioss_interrupts_gpio_10_IRQHandler
ioss_interrupts_gpio_11_IRQHandler
ioss_interrupts_gpio_12_IRQHandler
ioss_interrupts_gpio_13_IRQHandler
ioss_interrupts_gpio_14_IRQHandler
ioss_interrupt_gpio_IRQHandler
ioss_interrupt_vdd_IRQHandler
lpcomp_interrupt_IRQHandler
scb_8_interrupt_IRQHandler
srss_interrupt_mcwdt_0_IRQHandler
srss_interrupt_mcwdt_1_IRQHandler
srss_interrupt_backup_IRQHandler
srss_interrupt_IRQHandler
cpuss_interrupts_ipc_0_IRQHandler
cpuss_interrupts_ipc_1_IRQHandler
cpuss_interrupts_ipc_2_IRQHandler
cpuss_interrupts_ipc_3_IRQHandler
cpuss_interrupts_ipc_4_IRQHandler
cpuss_interrupts_ipc_5_IRQHandler
cpuss_interrupts_ipc_6_IRQHandler
cpuss_interrupts_ipc_7_IRQHandler
cpuss_interrupts_ipc_8_IRQHandler
cpuss_interrupts_ipc_9_IRQHandler
cpuss_interrupts_ipc_10_IRQHandler
cpuss_interrupts_ipc_11_IRQHandler
cpuss_interrupts_ipc_12_IRQHandler
cpuss_interrupts_ipc_13_IRQHandler
cpuss_interrupts_ipc_14_IRQHandler
cpuss_interrupts_ipc_15_IRQHandler
scb_0_interrupt_IRQHandler
scb_1_interrupt_IRQHandler
scb_2_interrupt_IRQHandler
scb_3_interrupt_IRQHandler
scb_4_interrupt_IRQHandler
scb_5_interrupt_IRQHandler
scb_6_interrupt_IRQHandler
scb_7_interrupt_IRQHandler
scb_9_interrupt_IRQHandler
scb_10_interrupt_IRQHandler
scb_11_interrupt_IRQHandler
scb_12_interrupt_IRQHandler
csd_interrupt_IRQHandler
cpuss_interrupts_dmac_0_IRQHandler
cpuss_interrupts_dmac_1_IRQHandler
cpuss_interrupts_dmac_2_IRQHandler
cpuss_interrupts_dmac_3_IRQHandler
cpuss_interrupts_dw0_0_IRQHandler
cpuss_interrupts_dw0_1_IRQHandler
cpuss_interrupts_dw0_2_IRQHandler
cpuss_interrupts_dw0_3_IRQHandler
cpuss_interrupts_dw0_4_IRQHandler
cpuss_interrupts_dw0_5_IRQHandler
cpuss_interrupts_dw0_6_IRQHandler
cpuss_interrupts_dw0_7_IRQHandler
cpuss_interrupts_dw0_8_IRQHandler
cpuss_interrupts_dw0_9_IRQHandler
cpuss_interrupts_dw0_10_IRQHandler
cpuss_interrupts_dw0_11_IRQHandler
cpuss_interrupts_dw0_12_IRQHandler
cpuss_interrupts_dw0_13_IRQHandler
cpuss_interrupts_dw0_14_IRQHandler
cpuss_interrupts_dw0_15_IRQHandler
cpuss_interrupts_dw0_16_IRQHandler
cpuss_interrupts_dw0_17_IRQHandler
cpuss_interrupts_dw0_18_IRQHandler
cpuss_interrupts_dw0_19_IRQHandler
cpuss_interrupts_dw0_20_IRQHandler
cpuss_interrupts_dw0_21_IRQHandler
cpuss_interrupts_dw0_22_IRQHandler
cpuss_interrupts_dw0_23_IRQHandler
cpuss_interrupts_dw0_24_IRQHandler
cpuss_interrupts_dw0_25_IRQHandler
cpuss_interrupts_dw0_26_IRQHandler
cpuss_interrupts_dw0_27_IRQHandler
cpuss_interrupts_dw0_28_IRQHandler
cpuss_interrupts_dw1_0_IRQHandler
cpuss_interrupts_dw1_1_IRQHandler
cpuss_interrupts_dw1_2_IRQHandler
cpuss_interrupts_dw1_3_IRQHandler
cpuss_interrupts_dw1_4_IRQHandler
cpuss_interrupts_dw1_5_IRQHandler
cpuss_interrupts_dw1_6_IRQHandler
cpuss_interrupts_dw1_7_IRQHandler
cpuss_interrupts_dw1_8_IRQHandler
cpuss_interrupts_dw1_9_IRQHandler
cpuss_interrupts_dw1_10_IRQHandler
cpuss_interrupts_dw1_11_IRQHandler
cpuss_interrupts_dw1_12_IRQHandler
cpuss_interrupts_dw1_13_IRQHandler
cpuss_interrupts_dw1_14_IRQHandler
cpuss_interrupts_dw1_15_IRQHandler
cpuss_interrupts_dw1_16_IRQHandler
cpuss_interrupts_dw1_17_IRQHandler
cpuss_interrupts_dw1_18_IRQHandler
cpuss_interrupts_dw1_19_IRQHandler
cpuss_interrupts_dw1_20_IRQHandler
cpuss_interrupts_dw1_21_IRQHandler
cpuss_interrupts_dw1_22_IRQHandler
cpuss_interrupts_dw1_23_IRQHandler
cpuss_interrupts_dw1_24_IRQHandler
cpuss_interrupts_dw1_25_IRQHandler
cpuss_interrupts_dw1_26_IRQHandler
cpuss_interrupts_dw1_27_IRQHandler
cpuss_interrupts_dw1_28_IRQHandler
cpuss_interrupts_fault_0_IRQHandler
cpuss_interrupts_fault_1_IRQHandler
cpuss_interrupt_crypto_IRQHandler
cpuss_interrupt_fm_IRQHandler
cpuss_interrupts_cm4_fp_IRQHandler
cpuss_interrupts_cm0_cti_0_IRQHandler
cpuss_interrupts_cm0_cti_1_IRQHandler
cpuss_interrupts_cm4_cti_0_IRQHandler
cpuss_interrupts_cm4_cti_1_IRQHandler
tcpwm_0_interrupts_0_IRQHandler
tcpwm_0_interrupts_1_IRQHandler
tcpwm_0_interrupts_2_IRQHandler
tcpwm_0_interrupts_3_IRQHandler
tcpwm_0_interrupts_4_IRQHandler
tcpwm_0_interrupts_5_IRQHandler
tcpwm_0_interrupts_6_IRQHandler
tcpwm_0_interrupts_7_IRQHandler
tcpwm_1_interrupts_0_IRQHandler
tcpwm_1_interrupts_1_IRQHandler
tcpwm_1_interrupts_2_IRQHandler
tcpwm_1_interrupts_3_IRQHandler
tcpwm_1_interrupts_4_IRQHandler
tcpwm_1_interrupts_5_IRQHandler
tcpwm_1_interrupts_6_IRQHandler
tcpwm_1_interrupts_7_IRQHandler
tcpwm_1_interrupts_8_IRQHandler
tcpwm_1_interrupts_9_IRQHandler
tcpwm_1_interrupts_10_IRQHandler
tcpwm_1_interrupts_11_IRQHandler
tcpwm_1_interrupts_12_IRQHandler
tcpwm_1_interrupts_13_IRQHandler
tcpwm_1_interrupts_14_IRQHandler
tcpwm_1_interrupts_15_IRQHandler
tcpwm_1_interrupts_16_IRQHandler
tcpwm_1_interrupts_17_IRQHandler
tcpwm_1_interrupts_18_IRQHandler
tcpwm_1_interrupts_19_IRQHandler
tcpwm_1_interrupts_20_IRQHandler
tcpwm_1_interrupts_21_IRQHandler
tcpwm_1_interrupts_22_IRQHandler
tcpwm_1_interrupts_23_IRQHandler
pass_interrupt_sar_IRQHandler
audioss_0_interrupt_i2s_IRQHandler
audioss_0_interrupt_pdm_IRQHandler
audioss_1_interrupt_i2s_IRQHandler
profile_interrupt_IRQHandler
smif_interrupt_IRQHandler
usb_interrupt_hi_IRQHandler
usb_interrupt_med_IRQHandler
usb_interrupt_lo_IRQHandler
sdhc_0_interrupt_wakeup_IRQHandler
sdhc_0_interrupt_general_IRQHandler
sdhc_1_interrupt_wakeup_IRQHandler
sdhc_1_interrupt_general_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
ALIGN
ENDIF
END
; [] END OF FILE

448
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld Normal file
View File

@ -0,0 +1,448 @@
/***************************************************************************//**
* \file cyb06xxa_cm4_dual.ld
* \version 2.60
*
* Linker file for the GNU C compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point location is fixed and starts at 0x10000000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
SEARCH_DIR(.)
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
#if !defined(MBED_ROM_START)
#define MBED_ROM_START 0x10000400
#endif
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
*/
#if !defined(MBED_APP_START)
#define MBED_APP_START MBED_ROM_START
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE 0x001CFC00
#endif
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
*/
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE MBED_ROM_SIZE
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x08000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x000D8000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
* this may, for example, trigger linking of additional modules from standard
* libraries. You may list several symbols for each EXTERN, and you may use
* EXTERN multiple times. This command has the same effect as the -u command-line
* option.
*/
EXTERN(Reset_Handler)
/* The MEMORY section below describes the location and size of blocks of memory in the target.
* Use this section to specify the memory regions available for allocation.
*/
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing the 'ram' and 'flash' regions.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
SECTIONS
{
/* Cortex-M4 application flash area */
.text ORIGIN(flash) :
{
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
. = ALIGN(4);
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
. = ALIGN(4);
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
/* Read-only code (constants). */
*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.eh_frame*))
} > flash
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > flash
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* uncomment .copy.table section and,
* define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
/* Copy interrupt vectors from flash to RAM */
LONG (__Vectors) /* From */
LONG (__ram_vectors_start__) /* To */
LONG (__Vectors_End - __Vectors) /* Size */
/* Copy data section to RAM */
LONG (__etext) /* From */
LONG (__data_start__) /* To */
LONG (__data_end__ - __data_start__) /* Size */
__copy_table_end__ = .;
} > flash
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
__zero_table_end__ = .;
} > flash
__etext = . ;
.ramVectors (NOLOAD) : ALIGN(8)
{
__ram_vectors_start__ = .;
KEEP(*(.ram_vectors))
__ram_vectors_end__ = .;
} > ram
.data __ram_vectors_end__ : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
__data_end__ = .;
} > ram
/* Place variables in the section that should not be initialized during the
* device startup.
*/
.noinit (NOLOAD) : ALIGN(8)
{
KEEP(*(.noinit))
} > ram
/* The uninitialized global or static variables are placed in this section.
*
* The NOLOAD attribute tells linker that .bss section does not consume
* any space in the image. The NOLOAD attribute changes the .bss type to
* NOBITS, and that makes linker to A) not allocate section in memory, and
* A) put information to clear the section with all zeros during application
* loading.
*
* Without the NOLOAD attribute, the .bss section might get PROGBITS type.
* This makes linker to A) allocate zeroed section in memory, and B) copy
* this section to RAM during application loading.
*/
.bss (NOLOAD):
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* Used for the digital signature of the secure application and the Bootloader SDK application.
* The size of the section depends on the required data size. */
.cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
{
KEEP(*(.cy_app_signature))
} > flash
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
KEEP(*(.cy_em_eeprom))
} > em_eeprom
/* Supervisory Flash: User data */
.cy_sflash_user_data :
{
KEEP(*(.cy_sflash_user_data))
} > sflash_user_data
/* Supervisory Flash: Normal Access Restrictions (NAR) */
.cy_sflash_nar :
{
KEEP(*(.cy_sflash_nar))
} > sflash_nar
/* Supervisory Flash: Public Key */
.cy_sflash_public_key :
{
KEEP(*(.cy_sflash_public_key))
} > sflash_public_key
/* Supervisory Flash: Table of Content # 2 */
.cy_toc_part2 :
{
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
KEEP(*(.cy_rtoc_part2))
} > sflash_rtoc_2
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
.cy_xip :
{
KEEP(*(.cy_xip))
} > xip
/* eFuse */
.cy_efuse :
{
KEEP(*(.cy_efuse))
} > efuse
/* These sections are used for additional metadata (silicon revision,
* Silicon/JTAG ID, etc.) storage.
*/
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x001D0000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
__cy_memory_1_start = 0x14000000;
__cy_memory_1_length = 0x8000;
__cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
__cy_memory_2_start = 0x16000000;
__cy_memory_2_length = 0x8000;
__cy_memory_2_row_size = 0x200;
/* XIP */
__cy_memory_3_start = 0x18000000;
__cy_memory_3_length = 0x08000000;
__cy_memory_3_row_size = 0x200;
/* eFuse */
__cy_memory_4_start = 0x90700000;
__cy_memory_4_length = 0x100000;
__cy_memory_4_row_size = 1;
/* EOF */

673
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S Normal file
View File

@ -0,0 +1,673 @@
/**************************************************************************//**
* @file startup_psoc6_02_cm4.S
* @brief CMSIS Core Device Startup File for
* ARMCM4 Device Series
* @version V5.00
* @date 02. March 2016
******************************************************************************/
/*
* Copyright (c) 2009-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Address of the NMI handler */
#define CY_NMI_HANLDER_ADDR 0x0000000D
/* The CPU VTOR register */
#define CY_CPU_VTOR_ADDR 0xE000ED08
/* Copy flash vectors and data section to RAM */
#define __STARTUP_COPY_MULTIPLE
/* Clear single BSS section */
#define __STARTUP_CLEAR_BSS
.syntax unified
.arch armv7-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00001000
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x00000400
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long CY_NMI_HANLDER_ADDR /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts Description */
.long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
.long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
.long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
.long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
.long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
.long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
.long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
.long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
.long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
.long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
.long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
.long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
.long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
.long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
.long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
.long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
.long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
.long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
.long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
.long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
.long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
.long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
.long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
.long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
.long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
.long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
.long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
.long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
.long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
.long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
.long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
.long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
.long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
.long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
.long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
.long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
.long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
.long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
.long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
.long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
.long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
.long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
.long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
.long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
.long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
.long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
.long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
.long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
.long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
.long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
.long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
.long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
.long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
.long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
.long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
.long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
.long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
.long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
.long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
.long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
.long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
.long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
.long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
.long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
.long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
.long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
.long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
.long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
.long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
.long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
.long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
.long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
.long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
.long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
.long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
.long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
.long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
.long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
.long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
.long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
.long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
.long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
.long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
.long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
.long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
.long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
.long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
.long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
.long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
.long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
.long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
.long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
.long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
.long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
.long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
.long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
.long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
.long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
.long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
.long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
.long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
.long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
.long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
.long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
.long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
.long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
.long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
.long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
.long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
.long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
.long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
.long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
.long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
.long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
.long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
.long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
.long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
.long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
.long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
.long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
.long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
.long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
.long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
.long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
.long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
.long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
.long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
.long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
.long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
.long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
.long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
.long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
.long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
.long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
.long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
.long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
.long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
.long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
.long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
.long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
.long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
.long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
.long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
.long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
.long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
.long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
.long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
.long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
.long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
.long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
.long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
.long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
.long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
.long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
.long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
.long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
.long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
.long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
.long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
.long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
.long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
.long usb_interrupt_hi_IRQHandler /* USB Interrupt */
.long usb_interrupt_med_IRQHandler /* USB Interrupt */
.long usb_interrupt_lo_IRQHandler /* USB Interrupt */
.long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
.long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
.long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.size __Vectors, . - __Vectors
.equ __VectorsSize, . - __Vectors
.section .ram_vectors
.align 2
.globl __ramVectors
__ramVectors:
.space __VectorsSize
.size __ramVectors, . - __ramVectors
.text
.thumb
.thumb_func
.align 2
/*
* Device startup customization
*
* Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
* because this function is executed as the first instruction in the ResetHandler.
* The PDL is also not initialized to use the proper register offsets.
* The user of this function is responsible for initializing the PDL and resources before using them.
*/
.weak Cy_OnResetUser
.func Cy_OnResetUser, Cy_OnResetUser
.type Cy_OnResetUser, %function
Cy_OnResetUser:
bx lr
.size Cy_OnResetUser, . - Cy_OnResetUser
.endfunc
/* Reset handler */
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
bl Cy_OnResetUser
cpsid i
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
/* Update Vector Table Offset Register. */
ldr r0, =__ramVectors
ldr r1, =CY_CPU_VTOR_ADDR
str r0, [r1]
dsb 0xF
/* Enable the FPU if used */
bl Cy_SystemInitFpuEnable
bl _start
/* Should never get here */
b .
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
.weak Cy_SysLib_FaultHandler
.type Cy_SysLib_FaultHandler, %function
Cy_SysLib_FaultHandler:
b .
.size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
.type Fault_Handler, %function
Fault_Handler:
/* Storing LR content for Creator call stack trace */
push {LR}
movs r0, #4
mov r1, LR
tst r0, r1
beq .L_MSP
mrs r0, PSP
b .L_API_call
.L_MSP:
mrs r0, MSP
.L_API_call:
/* Compensation of stack pointer address due to pushing 4 bytes of LR */
adds r0, r0, #4
bl Cy_SysLib_FaultHandler
b .
.size Fault_Handler, . - Fault_Handler
.macro def_fault_Handler fault_handler_name
.weak \fault_handler_name
.set \fault_handler_name, Fault_Handler
.endm
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_fault_Handler HardFault_Handler
def_fault_Handler MemManage_Handler
def_fault_Handler BusFault_Handler
def_fault_Handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
.end
/* [] END OF FILE */

273
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf Normal file
View File

@ -0,0 +1,273 @@
/***************************************************************************//**
* \file cyb06xxa_cm4_dual.icf
* \version 2.60
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = 0x10000400;
}
/* MBED_APP_START is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_START
* is equal to MBED_ROM_START
*/
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = MBED_ROM_START;
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = 0x001CFC00;
}
/* MBED_APP_SIZE is being used by the bootloader build script and
* will be calculate by the system. Without bootloader the MBED_APP_SIZE
* is equal to MBED_ROM_SIZE
*/
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
}
if (!isdefinedsymbol(MBED_RAM_START)) {
define symbol MBED_RAM_START = 0x08000000;
}
if (!isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = 0x000D8000;
}
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
/* The symbols below define the location and size of blocks of memory in the target.
* Use these symbols to specify the memory regions available for allocation.
*/
/* The following symbols control RAM and flash memory allocation for the CM4 core.
* You can change the memory allocation by editing RAM and Flash symbols.
* Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
* Using this memory region for other purposes will lead to unexpected behavior.
* Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
*/
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE);
/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE);
/* The following symbols define a 32K flash region used for EEPROM emulation.
* This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
* Therefore, repurposing this memory region will prevent such middleware from operation.
*/
define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF;
/* The following symbols define device specific memory regions and must not be changed. */
/* Supervisory FLASH - User Data */
define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF;
/* Supervisory FLASH - Normal Access Restrictions (NAR) */
define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF;
/* Supervisory FLASH - Public Key */
define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF;
/* Supervisory FLASH - Table of Content # 2 */
define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF;
/* Supervisory FLASH - Table of Content # 2 Copy */
define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF;
/* eFuse */
define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF;
/* XIP */
define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
/*-Sizes-*/
if (!isdefinedsymbol(__STACK_SIZE)) {
define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
} else {
define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
}
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
define block RAM_DATA {readwrite section .data};
define block RAM_OTHER {readwrite section * };
define block RAM_NOINIT {readwrite section .noinit};
define block RAM_BSS {readwrite section .bss};
define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
define block RO {first section .intvec, readonly};
/*-Initializations-*/
initialize by copy { readwrite };
do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M4 application */
place at start of IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */
".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom };
/* Supervisory Flash - User Data */
".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data };
/* Supervisory Flash - NAR */
".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar };
/* Supervisory Flash - Public Key */
".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key };
/* Supervisory Flash - TOC2 */
".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 };
/* Supervisory Flash - RTOC2 */
".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 };
/* eFuse */
".cy_efuse" : place at start of IROM8_region { section .cy_efuse };
/* Execute in Place (XIP). See the smif driver documentation for details. */
".cy_xip" : place at start of EROM1_region { section .cy_xip };
/* RAM */
place at start of IRAM1_region { readwrite section .intvec_ram};
place in IRAM1_region { block RAM};
place in IRAM1_region { block HEAP};
place at end of IRAM1_region { block CSTACK };
/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
keep { section .cy_app_signature,
section .cy_em_eeprom,
section .cy_sflash_user_data,
section .cy_sflash_nar,
section .cy_sflash_public_key,
section .cy_toc_part2,
section .cy_rtoc_part2,
section .cy_efuse,
section .cy_xip,
section .cymeta,
};
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x001D0000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */
define exported symbol __cy_memory_1_start = 0x14000000;
define exported symbol __cy_memory_1_length = 0x8000;
define exported symbol __cy_memory_1_row_size = 0x200;
/* Supervisory Flash */
define exported symbol __cy_memory_2_start = 0x16000000;
define exported symbol __cy_memory_2_length = 0x8000;
define exported symbol __cy_memory_2_row_size = 0x200;
/* XIP */
define exported symbol __cy_memory_3_start = 0x18000000;
define exported symbol __cy_memory_3_length = 0x08000000;
define exported symbol __cy_memory_3_row_size = 0x200;
/* eFuse */
define exported symbol __cy_memory_4_start = 0x90700000;
define exported symbol __cy_memory_4_length = 0x100000;
define exported symbol __cy_memory_4_row_size = 1;
/* EOF */

1263
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S Normal file
View File

File diff suppressed because it is too large Load Diff

680
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h Normal file
View File

@ -0,0 +1,680 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.60
*
* \brief Device system header file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _SYSTEM_PSOC6_H_
#define _SYSTEM_PSOC6_H_
/**
* \addtogroup group_system_config
* \{
* Provides device startup, system configuration, and linker script files.
* The system startup provides the followings features:
* - See \ref group_system_config_device_initialization for the:
* * \ref group_system_config_dual_core_device_initialization
* * \ref group_system_config_single_core_device_initialization
* - \ref group_system_config_device_memory_definition
* - \ref group_system_config_heap_stack_config
* - \ref group_system_config_merge_apps
* - \ref group_system_config_default_handlers
* - \ref group_system_config_device_vector_table
* - \ref group_system_config_cm4_functions
*
* \section group_system_config_configuration Configuration Considerations
*
* \subsection group_system_config_device_memory_definition Device Memory Definition
* The flash and RAM allocation for each CPU is defined by the linker scripts.
* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
* 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
* For Single-Core devices the system reserves additional 80 bytes of RAM.
* Using the reserved memory area for other purposes will lead to unexpected behavior.
*
* \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
* In that case you may see warnings during the build process. To eliminate build
* warnings in your project, you can simply comment out or remove the relevant
* code in the linker file.
*
* <b>ARM GCC</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
* Cy_SysEnableCM4() function call.
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.ld', where 'xx' is the device group:
* \code
* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
* \endcode
* - 'xx_cm4_dual.ld', where 'xx' is the device group:
* \code
* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
* by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
*
* <b>ARM MDK</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call.
*
* \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
* In that case you may see the warnings during the build process:
* L6314W (no section matches pattern) and/or L6329W
* (pattern only matches removed unused sections). In your project, you can
* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
* the linker. You can also comment out or remove the relevant code in the linker
* file.
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.scat', where 'xx' is the device group:
* \code
* #define FLASH_START 0x10000000
* #define FLASH_SIZE 0x00080000
* #define RAM_START 0x08000000
* #define RAM_SIZE 0x00024000
* \endcode
* - 'xx_cm4_dual.scat', where 'xx' is the device group:
* \code
* #define FLASH_START 0x10080000
* #define FLASH_SIZE 0x00080000
* #define RAM_START 0x08024000
* #define RAM_SIZE 0x00023800
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
* value in the 'xx_cm4_dual.scat' file,
* where 'xx' is the device group. Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
*
* <b>IAR</b>\n
* The flash and RAM sections for the CPU are defined in the linker files:
* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
* \note If the start of the Cortex-M4 application image is changed, the value
* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
* Cy_SysEnableCM4() function call.
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
* - 'xx_cm0plus.icf', where 'xx' is the device group:
* \code
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
* \endcode
* - 'xx_cm4_dual.icf', where 'xx' is the device group:
* \code
* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
* \endcode
*
* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
* is the device group. Do this by either:
* - Passing the following commands to the compiler:\n
* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
* 'xx' is device family:\n
* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
*
* \subsection group_system_config_device_initialization Device Initialization
* After a power-on-reset (POR), the boot process is handled by the boot code
* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot
* code passes the control to the Cortex-M0+ startup code located in flash.
*
* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices
* The Cortex-M0+ startup code performs the device initialization by a call to
* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
* by default. Enable the core using the \ref Cy_SysEnableCM4() function.
* See \ref group_system_config_cm4_functions for more details.
* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
* The function has a separate implementation on each core.
* Both function implementations unlock and disable the WDT.
* Therefore enable the WDT after both cores have been initialized.
*
* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
* The Cortex-M0+ core is not user-accessible on these devices. In this case the
* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
*
* \subsection group_system_config_heap_stack_config Heap and Stack Configuration
* There are two ways to adjust heap and stack configurations:
* -# Editing source code files
* -# Specifying via command line
*
* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
*
* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the assembler startup files
* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
* Change the heap and stack sizes by modifying the following lines:\n
* \code .equ Stack_Size, 0x00001000 \endcode
* \code .equ Heap_Size, 0x00000400 \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the compiler:\n
* \code -D __STACK_SIZE=0x000000400 \endcode
* \code -D __HEAP_SIZE=0x000000100 \endcode
*
* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the assembler startup files
* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* Change the heap and stack sizes by modifying the following lines:\n
* \code Stack_Size EQU 0x00001000 \endcode
* \code Heap_Size EQU 0x00000400 \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the assembler:\n
* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
*
* \subsubsection group_system_config_heap_stack_config_iar IAR
* - <b>Editing source code files</b>\n
* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
* where 'xx' is the device family, and 'yy' is the target CPU; for example,
* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
* Change the heap and stack sizes by modifying the following lines:\n
* \code Stack_Size EQU 0x00001000 \endcode
* \code Heap_Size EQU 0x00000400 \endcode
*
* - <b>Specifying via command line</b>\n
* Change the heap and stack sizes passing the following commands to the
* linker (including quotation marks):\n
* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
*
* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
* The CM0+ project and linker script build the CM0+ application image. Similarly,
* the CM4 linker script builds the CM4 application image. Each specifies
* locations, sizes, and contents of sections in memory. See
* \ref group_system_config_device_memory_definition for the symbols and default
* values.
*
* The cymcuelftool is invoked by a post-build command. The precise project
* setting is IDE-specific.
*
* The cymcuelftool combines the two executables. The tool examines the
* executables to ensure that memory regions either do not overlap, or contain
* identical bytes (shared). If there are no problems, it creates a new ELF file
* with the merged image, without changing any of the addresses or data.
*
* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
* The default interrupt handler functions are defined as weak functions to a dummy
* handler in the startup file. The naming convention for the interrupt handler names
* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
* user code by defining the handler function using the same name. For example:
* \code
* void scb_0_interrupt_IRQHandler(void)
*{
* ...
*}
* \endcode
*
* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM
* This process uses memory sections defined in the linker script. The startup
* code actually defines the contents of the vector table and performs the copy.
* \subsubsection group_system_config_device_vector_table_gcc ARM GCC
* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
* It defines sections and locations in memory.\n
* Copy interrupt vectors from flash to RAM: \n
* From: \code LONG (__Vectors) \endcode
* To: \code LONG (__ram_vectors_start__) \endcode
* Size: \code LONG (__Vectors_End - __Vectors) \endcode
* The vector table address (and the vector table itself) are defined in the
* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
* The code in these files copies the vector table from Flash to RAM.
* \subsubsection group_system_config_device_vector_table_mdk ARM MDK
* The linker script file is 'xx_yy.scat', where 'xx' is the device family,
* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
* (RESET_RAM) shall be first in the RAM section.\n
* RESET_RAM represents the vector table. It is defined in the assembler startup
* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* The code in these files copies the vector table from Flash to RAM.
*
* \subsubsection group_system_config_device_vector_table_iar IAR
* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
* This file defines the .intvec_ram section and its location.
* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode
* The vector table address (and the vector table itself) are defined in the
* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
* The code in these files copies the vector table from Flash to RAM.
*
* \section group_system_config_more_information More Information
* Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
* more details.
*
* \section group_system_config_MISRA MISRA Compliance
*
* <table class="doxtable">
* <tr>
* <th>MISRA Rule</th>
* <th>Rule Class (Required/Advisory)</th>
* <th>Rule Description</th>
* <th>Description of Deviation(s)</th>
* </tr>
* <tr>
* <td>2.3</td>
* <td>R</td>
* <td>The character sequence // shall not be used within a comment.</td>
* <td>The comments provide a useful WEB link to the documentation.</td>
* </tr>
* </table>
*
* \section group_system_config_changelog Changelog
* <table class="doxtable">
* <tr>
* <th>Version</th>
* <th>Changes</th>
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
* </tr>
* <tr>
* <td>2.50</td>
* <td>Updated assembler files, C files, linker scripts.</td>
* <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>
* </tr>
* <tr>
* <td>2.40</td>
* <td>Updated assembler files, C files, linker scripts.</td>
* <td>Added Arm Compiler 6 support.</td>
* </tr>
* <tr>
* <td rowspan="2">2.30</td>
* <td>Added assembler files, linker scripts for Mbed OS.</td>
* <td>Added Arm Mbed OS embedded operating system support.</td>
* </tr>
* <tr>
* <td>Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.</td>
* <td>Enhanced PDL usability.</td>
* </tr>
* <tr>
* <td>2.20</td>
* <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.</td>
* <td>Changed the IPC driver configuration method from compile time to run time.</td>
* </tr>
* <tr>
* <td rowspan="2"> 2.10</td>
* <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
* Removed $Sub$$main symbol for ARM MDK compiler.
* </td>
* <td>uVision Debugger support.</td>
* </tr>
* <tr>
* <td>Updated description of the Startup behavior for Single-Core Devices. \n
* Added note about WDT disabling by SystemInit() function.
* </td>
* <td>Documentation improvement.</td>
* </tr>
* <tr>
* <td rowspan="4"> 2.0</td>
* <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
* Single core device support.
* </td>
* <td></td>
* </tr>
* <tr>
* <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
* Renamed 'wflash' memory region to 'em_eeprom'.
* </td>
* <td>Linker scripts usability improvement.</td>
* </tr>
* <tr>
* <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
* <td>Reserved system resources for internal operations.</td>
* </tr>
* <tr>
* <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
* <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
* </tr>
* <tr>
* <td>1.0</td>
* <td>Initial version</td>
* <td></td>
* </tr>
* </table>
*
*
* \defgroup group_system_config_macro Macro
* \{
* \defgroup group_system_config_system_macro System
* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status
* \defgroup group_system_config_user_settings_macro User Settings
* \}
* \defgroup group_system_config_functions Functions
* \{
* \defgroup group_system_config_system_functions System
* \defgroup group_system_config_cm4_functions Cortex-M4 Control
* \}
* \defgroup group_system_config_globals Global Variables
*
* \}
*/
/**
* \addtogroup group_system_config_system_functions
* \{
* \details
* The following system functions implement CMSIS Core functions.
* Refer to the [CMSIS documentation]
* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
* for more details.
* \}
*/
#ifdef __cplusplus
extern "C" {
#endif
/*******************************************************************************
* Include files
*******************************************************************************/
#include <stdint.h>
/*******************************************************************************
* Global preprocessor symbols/macros ('define')
*******************************************************************************/
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
(defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)))
#define CY_SYSTEM_CPU_CM0P 1UL
#else
#define CY_SYSTEM_CPU_CM0P 0UL
#endif
#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U)
#include "cyfitter.h"
#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */
/*******************************************************************************
*
* START OF USER SETTINGS HERE
* ===========================
*
* All lines with '<<<' can be set by user.
*
*******************************************************************************/
/**
* \addtogroup group_system_config_user_settings_macro
* \{
*/
#if defined (CYDEV_CLK_EXTCLK__HZ)
#define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ)
#else
/***************************************************************************//**
* External Clock Frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_EXTCLK__HZ) */
#if defined (CYDEV_CLK_ECO__HZ)
#define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ)
#else
/***************************************************************************//**
* \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled
* within PSoC Creator and the clock is enabled in the DWR, the value from DWR
* used.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */
#endif /* (CYDEV_CLK_ECO__HZ) */
#if defined (CYDEV_CLK_ALTHF__HZ)
#define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ)
#else
/***************************************************************************//**
* \brief Alternate high frequency (in Hz, [value]UL). If compiled within
* PSoC Creator and the clock is enabled in the DWR, the value from DWR used.
* Otherwise, edit the value below.
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */
#endif /* (CYDEV_CLK_ALTHF__HZ) */
/***************************************************************************//**
* \brief Start address of the Cortex-M4 application ([address]UL)
* <i>(USER SETTING)</i>
*******************************************************************************/
#if !defined (CY_CORTEX_M4_APPL_ADDR)
#define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */
#endif /* (CY_CORTEX_M4_APPL_ADDR) */
/***************************************************************************//**
* \brief IPC Semaphores allocation ([value]UL).
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */
/***************************************************************************//**
* \brief IPC Pipe definitions ([value]UL).
* <i>(USER SETTING)</i>
*******************************************************************************/
#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */
/*******************************************************************************
*
* END OF USER SETTINGS HERE
* =========================
*
*******************************************************************************/
/** \} group_system_config_user_settings_macro */
/**
* \addtogroup group_system_config_system_macro
* \{
*/
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
/** The Cortex-M0+ startup driver identifier */
#define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
/** The Cortex-M4 startup driver identifier */
#define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U))
#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
/** \} group_system_config_system_macro */
/**
* \addtogroup group_system_config_system_functions
* \{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/** \} group_system_config_system_functions */
/**
* \addtogroup group_system_config_cm4_functions
* \{
*/
extern uint32_t Cy_SysGetCM4Status(void);
extern void Cy_SysEnableCM4(uint32_t vectorTableOffset);
extern void Cy_SysDisableCM4(void);
extern void Cy_SysRetainCM4(void);
extern void Cy_SysResetCM4(void);
/** \} group_system_config_cm4_functions */
/** \cond */
extern void Default_Handler (void);
void Cy_SysIpcPipeIsrCm0(void);
void Cy_SysIpcPipeIsrCm4(void);
extern void Cy_SystemInit(void);
extern void Cy_SystemInitFpuEnable(void);
extern uint32_t cy_delayFreqHz;
extern uint32_t cy_delayFreqKhz;
extern uint8_t cy_delayFreqMhz;
extern uint32_t cy_delay32kMs;
/** \endcond */
#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
/**
* \addtogroup group_system_config_cm4_status_macro
* \{
*/
#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */
#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */
#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */
#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
/** \} group_system_config_cm4_status_macro */
#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
/*******************************************************************************
* IPC Configuration
* =========================
*******************************************************************************/
/* IPC CY_PIPE default configuration */
#define CY_SYS_CYPIPE_CLIENT_CNT (8UL)
#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */
#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */
#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */
#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
/*
* The System pipe configuration defines the IPC channel number, interrupt
* number, and the pipe interrupt mask for the endpoint.
*
* The format of the endPoint configuration
* Bits[31:16] Interrupt Mask
* Bits[15:8 ] IPC interrupt
* Bits[ 7:0 ] IPC channel
*/
/* System Pipe addresses */
/* CyPipe defines */
#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP0)
#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
| (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
| CY_IPC_CHAN_CYPIPE_EP1)
/******************************************************************************/
/** \addtogroup group_system_config_globals
* \{
*/
extern uint32_t SystemCoreClock;
extern uint32_t cy_BleEcoClockFreqHz;
extern uint32_t cy_Hfclk0FreqHz;
extern uint32_t cy_PeriClkFreqHz;
/** \} group_system_config_globals */
/** \cond INTERNAL */
/*******************************************************************************
* Backward compatibility macro. The following code is DEPRECATED and must
* not be used in new projects
*******************************************************************************/
/* BWC defines for functions related to enter/exit critical section */
#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection
#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
/** \endcond */
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_PSOC6_H_ */
/* [] END OF FILE */

552
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6_cm4.c Normal file
View File

@ -0,0 +1,552 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.60
*
* The device system-source file.
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <stdbool.h>
#include "system_psoc6.h"
#include "cy_device.h"
#include "cy_device_headers.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
#include "cy_ipc_pipe.h"
#include "cy_ipc_drv.h"
#if defined(CY_DEVICE_PSOC6ABLE2)
#include "cy_flash.h"
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
/*******************************************************************************
* SystemCoreClockUpdate()
*******************************************************************************/
/** Default HFClk frequency in Hz */
#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
/** Default PeriClk frequency in Hz */
#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
/** Default SlowClk system core frequency in Hz */
#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
/** IMO frequency in Hz */
#define CY_CLK_IMO_FREQ_HZ (8000000UL)
/** HVILO frequency in Hz */
#define CY_CLK_HVILO_FREQ_HZ (32000UL)
/** PILO frequency in Hz */
#define CY_CLK_PILO_FREQ_HZ (32768UL)
/** WCO frequency in Hz */
#define CY_CLK_WCO_FREQ_HZ (32768UL)
/** ALTLF frequency in Hz */
#define CY_CLK_ALTLF_FREQ_HZ (32768UL)
/**
* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
* which is the system clock frequency supplied to the SysTick timer and the
* processor core clock.
* This variable implements CMSIS Core global variable.
* Refer to the [CMSIS documentation]
* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
* for more details.
* This variable can be used by debuggers to query the frequency
* of the debug timer or to configure the trace clock speed.
*
* \attention Compilers must be configured to avoid removing this variable in case
* the application program is not using it. Debugging systems require the variable
* to be physically present in memory so that it can be examined to configure the debugger. */
uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */
#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN)
uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ;
#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */
/* SCB->CPACR */
#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
/*******************************************************************************
* SystemInit()
*******************************************************************************/
/* CLK_FLL_CONFIG default values */
#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
/*******************************************************************************
* SystemCoreClockUpdate (void)
*******************************************************************************/
/* Do not use these definitions directly in your application */
#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
#define CY_DELAY_1K_THRESHOLD (1000u)
#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
#define CY_DELAY_1M_THRESHOLD (1000000u)
#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
CY_DELAY_1K_THRESHOLD;
uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
CY_DELAY_1M_THRESHOLD);
uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD *
((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD);
#define CY_ROOT_PATH_SRC_IMO (0UL)
#define CY_ROOT_PATH_SRC_EXT (1UL)
#if (SRSS_ECO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ECO (2UL)
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if (SRSS_ALTHF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_ALTHF (3UL)
#endif /* (SRSS_ALTHF_PRESENT == 1U) */
#define CY_ROOT_PATH_SRC_DSI_MUX (4UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL)
#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL)
#if (SRSS_ALTLF_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL)
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
#define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL)
#endif /* (SRSS_PILO_PRESENT == 1U) */
/*******************************************************************************
* Function Name: SystemInit
****************************************************************************//**
* \cond
* Initializes the system:
* - Restores FLL registers to the default state for single core devices.
* - Unlocks and disables WDT.
* - Calls Cy_PDL_Init() function to define the driver library.
* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
* - Calls \ref SystemCoreClockUpdate().
* \endcond
*******************************************************************************/
void SystemInit(void)
{
Cy_PDL_Init(CY_DEVICE_CFG);
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Restore FLL registers to the default state as they are not restored by the ROM code */
uint32_t copy = SRSS->CLK_FLL_CONFIG;
copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
SRSS->CLK_FLL_CONFIG = copy;
copy = SRSS->CLK_ROOT_SELECT[0u];
copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
SRSS->CLK_ROOT_SELECT[0u] = copy;
SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
/* Unlock and disable WDT */
Cy_WDT_Unlock();
Cy_WDT_Disable();
#endif /* (__CM0P_PRESENT == 0) */
#endif /* __CM0P_PRESENT */
Cy_SystemInit();
SystemCoreClockUpdate();
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#ifdef __CM0P_PRESENT
#if (__CM0P_PRESENT == 0)
/* Allocate and initialize semaphores for the system operations. */
static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
#else
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
#endif /* (__CM0P_PRESENT) */
#else
(void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
#endif /* __CM0P_PRESENT */
/********************************************************************************
*
* Initializes the system pipes. The system pipes are used by BLE and Flash.
*
* If the default startup file is not used, or SystemInit() is not called in your
* project, call the following three functions prior to executing any flash or
* EmEEPROM write or erase operation:
* -# Cy_IPC_Sema_Init()
* -# Cy_IPC_Pipe_Config()
* -# Cy_IPC_Pipe_Init()
* -# Cy_Flash_Init()
*
*******************************************************************************/
/* Create an array of endpoint structures */
static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
{
/* .ep0ConfigData */
{
/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
/* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
/* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
},
/* .ep1ConfigData */
{
/* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
/* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
/* .ipcNotifierMuxNumber */ 0u,
/* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
/* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
},
/* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
/* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
/* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
};
if (cy_device->flashPipeRequired != 0u)
{
Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
}
#if defined(CY_DEVICE_PSOC6ABLE2)
Cy_Flash_Init();
#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
}
/*******************************************************************************
* Function Name: Cy_SystemInit
****************************************************************************//**
*
* The function is called during device startup. Once project compiled as part of
* the PSoC Creator project, the Cy_SystemInit() function is generated by the
* PSoC Creator.
*
* The function generated by PSoC Creator performs all of the necessary device
* configuration based on the design settings. This includes settings from the
* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
* configuration that is necessary.
*
*******************************************************************************/
__WEAK void Cy_SystemInit(void)
{
/* Empty weak function. The actual implementation to be in the PSoC Creator
* generated strong function.
*/
}
/*******************************************************************************
* Function Name: SystemCoreClockUpdate
****************************************************************************//**
*
* Gets core clock frequency and updates \ref SystemCoreClock, \ref
* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
*
* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
*
*******************************************************************************/
void SystemCoreClockUpdate (void)
{
uint32_t srcFreqHz;
uint32_t pathFreqHz;
uint32_t fastClkDiv;
uint32_t periClkDiv;
uint32_t rootPath;
uint32_t srcClk;
/* Get root path clock for the high-frequency clock # 0 */
rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]);
/* Get source of the root path clock */
srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]);
/* Get frequency of the source */
switch (srcClk)
{
case CY_ROOT_PATH_SRC_IMO:
srcFreqHz = CY_CLK_IMO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_EXT:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
#if (SRSS_ECO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ECO:
srcFreqHz = CY_CLK_ECO_FREQ_HZ;
break;
#endif /* (SRSS_ECO_PRESENT == 1U) */
#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_ALTHF:
srcFreqHz = cy_BleEcoClockFreqHz;
break;
#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */
case CY_ROOT_PATH_SRC_DSI_MUX:
{
uint32_t dsi_src;
dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]);
switch (dsi_src)
{
case CY_ROOT_PATH_SRC_DSI_MUX_HVILO:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
case CY_ROOT_PATH_SRC_DSI_MUX_WCO:
srcFreqHz = CY_CLK_WCO_FREQ_HZ;
break;
#if (SRSS_ALTLF_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF:
srcFreqHz = CY_CLK_ALTLF_FREQ_HZ;
break;
#endif /* (SRSS_ALTLF_PRESENT == 1U) */
#if (SRSS_PILO_PRESENT == 1U)
case CY_ROOT_PATH_SRC_DSI_MUX_PILO:
srcFreqHz = CY_CLK_PILO_FREQ_HZ;
break;
#endif /* (SRSS_PILO_PRESENT == 1U) */
default:
srcFreqHz = CY_CLK_HVILO_FREQ_HZ;
break;
}
}
break;
default:
srcFreqHz = CY_CLK_EXT_FREQ_HZ;
break;
}
if (rootPath == 0UL)
{
/* FLL */
bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS));
bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3));
bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) ||
(1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)));
if ((fllOutputAuto && fllLocked) || fllOutputOutput)
{
uint32_t fllMult;
uint32_t refDiv;
uint32_t outputDiv;
fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG);
refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2);
outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL;
pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else if ((rootPath == 1UL) || (rootPath == 2UL))
{
/* PLL */
bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL]));
bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]));
bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) ||
(1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])));
if ((pllOutputAuto && pllLocked) || pllOutputOutput)
{
uint32_t feedbackDiv;
uint32_t referenceDiv;
uint32_t outputDiv;
feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]);
pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv;
}
else
{
pathFreqHz = srcFreqHz;
}
}
else
{
/* Direct */
pathFreqHz = srcFreqHz;
}
/* Get frequency after hf_clk pre-divider */
pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]);
cy_Hfclk0FreqHz = pathFreqHz;
/* Fast Clock Divider */
fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL);
/* Peripheral Clock Divider */
periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL);
cy_PeriClkFreqHz = pathFreqHz / periClkDiv;
pathFreqHz = pathFreqHz / fastClkDiv;
SystemCoreClock = pathFreqHz;
/* Sets clock frequency for Delay API */
cy_delayFreqHz = SystemCoreClock;
cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
}
/*******************************************************************************
* Function Name: Cy_SystemInitFpuEnable
****************************************************************************//**
*
* Enables the FPU if it is used. The function is called from the startup file.
*
*******************************************************************************/
void Cy_SystemInitFpuEnable(void)
{
#if defined (__FPU_USED) && (__FPU_USED == 1U)
uint32_t interruptState;
interruptState = Cy_SysLib_EnterCriticalSection();
SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
__DSB();
__ISB();
Cy_SysLib_ExitCriticalSection(interruptState);
#endif /* (__FPU_USED) && (__FPU_USED == 1U) */
}
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
/*******************************************************************************
* Function Name: Cy_SysIpcPipeIsrCm4
****************************************************************************//**
*
* This is the interrupt service routine for the system pipe.
*
*******************************************************************************/
void Cy_SysIpcPipeIsrCm4(void)
{
Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
}
#endif
/*******************************************************************************
* Function Name: Cy_MemorySymbols
****************************************************************************//**
*
* The intention of the function is to declare boundaries of the memories for the
* MDK compilers. For the rest of the supported compilers, this is done using
* linker configuration files. The following symbols used by the cymcuelftool.
*
*******************************************************************************/
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
__asm void Cy_MemorySymbols(void)
{
/* Flash */
EXPORT __cy_memory_0_start
EXPORT __cy_memory_0_length
EXPORT __cy_memory_0_row_size
/* Working Flash */
EXPORT __cy_memory_1_start
EXPORT __cy_memory_1_length
EXPORT __cy_memory_1_row_size
/* Supervisory Flash */
EXPORT __cy_memory_2_start
EXPORT __cy_memory_2_length
EXPORT __cy_memory_2_row_size
/* XIP */
EXPORT __cy_memory_3_start
EXPORT __cy_memory_3_length
EXPORT __cy_memory_3_row_size
/* eFuse */
EXPORT __cy_memory_4_start
EXPORT __cy_memory_4_length
EXPORT __cy_memory_4_row_size
/* Flash */
__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
__cy_memory_0_row_size EQU 0x200
/* Flash region for EEPROM emulation */
__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
__cy_memory_1_row_size EQU 0x200
/* Supervisory Flash */
__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
__cy_memory_2_row_size EQU 0x200
/* XIP */
__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
__cy_memory_3_row_size EQU 0x200
/* eFuse */
__cy_memory_4_start EQU __cpp(0x90700000)
__cy_memory_4_length EQU __cpp(0x100000)
__cy_memory_4_row_size EQU __cpp(1)
}
#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
/* [] END OF FILE */

17
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/secure_image_parameters.json Normal file
View File

@ -0,0 +1,17 @@
{
"boot0" : {
"VERSION" : "0.1",
"ROLLBACK_COUNTER" : "0"
},
"boot1" : {
"VERSION" : "0.1",
"ROLLBACK_COUNTER" : "0"
},
"sdk_path" : "targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/",
"priv_key_file": "keys/USERAPP_CM4_KEY_PRIV.pem",
"aes_key_file": "keys/image-aes-128.key",
"dev_pub_key_file": "keys/dev_pub_key.pem",
"policy_file": "policy/policy_single_stage_CM4_2m.json"
}

113
targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/policy/policy_single_stage_CM4_2m.json Normal file
View File

@ -0,0 +1,113 @@
{
"debug" :
{
"m0p" : {
"permission" : "disabled",
"control" : "firmware",
"key" : 5
},
"m4" : {
"permission" : "allowed",
"control" : "firmware",
"key" : 5
},
"system" : {
"permission" : "enabled",
"control" : "firmware",
"key" : 5,
"syscall": true,
"mmio": true,
"flash": true,
"workflash": true,
"sflash": true,
"sram": true
},
"rma" : {
"permission" : "allowed",
"destroy_fuses" : [
{
"start" : 888,
"size" : 136
},
{
"start" : 648,
"size" : 104
}
],
"destroy_flash" : [
{
"start" : 268435456,
"size" : 851968
},
{
"start" : 269483520,
"size" : 16
}
],
"key" : 5
}
},
"wounding" :
{
},
"boot_upgrade" :
{
"title": "upgrade_policy",
"firmware": [
{
"boot_auth": [
3
],
"id": 0,
"launch": 4,
"smif_id": 0,
"upgrade": false,
"upgrade_auth": [
3
],
"resources": [
{
"type": "FLASH_PC1_SPM",
"address": 269287424,
"size": 65536
},
{
"type": "SRAM_SPM_PRIV",
"address": 134348800,
"size": 65536
},
{
"type": "SRAM_DAP",
"address": 134397952,
"size": 16384
}
]
},
{
"boot_auth": [
8
],
"id": 4,
"monotonic": 0,
"smif_id": 0,
"upgrade": true,
"upgrade_auth": [
8
],
"resources": [
{
"type": "BOOT",
"address": 268435456,
"size": 655360
},
{
"type": "UPGRADE",
"address": 269090816,
"size": 655360
}
]
}
]
}
}

26
targets/targets.json
View File

@ -9106,6 +9106,32 @@
"network-default-interface-type": "WIFI"
}
},
"CY8CKIT_064S2_4343W": {
"inherits": ["MCU_PSOC6_M4"],
"features": ["BLE"],
"components_remove": ["QSPIF"],
"supported_form_factors": ["ARDUINO"],
"device_has_remove": ["ANALOGOUT", "QSPI"],
"extra_labels_add": [
"PSOC6_02",
"MXCRYPTO_02",
"CM0P_SLEEP",
"WHD",
"4343W",
"CYW43XXX",
"CORDIO"
],
"macros_add": ["CYB0644ABZI_S2D44", "CYBSP_WIFI_CAPABLE"],
"detect_code": ["190A"],
"post_binary_hook": {
"function": "PSOC6Code.sign_image"
},
"forced_reset_timeout": 5,
"overrides": {
"network-default-interface-type": "WIFI"
},
"program_cycle_s": 10
},
"CY8CKIT_062_WIFI_BT": {
"inherits": ["MCU_PSOC6_M4"],
"features": ["BLE"],