Without free-up of peripheral pins, peripheral pins of the same peripheral may
share by multiple ports after port iteration, and this peripheral may fail with
pin interference.
In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes.
Targets not supporting this feature are listed below:
- NUMAKER_PFM_NANO130
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M453
Fix logic error on replying NACK at the end of transfer.
This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/
i2c - test single byte read i2c API.
Better IP initialization sequence:
1. Configure IP pins
2. Select IP clock source and then enable it
3. Reset the IP (SYS_ResetModule)
NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if
IP clock enable is before IP reset.
NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then
IP reset.
NOTE3: IP reset at the end of IP initialization sequence can cover unexpected
situation.
On Nuvoton targets, lp_ticker_set_interrupt(...) needs around 3 lp-ticker
ticks to take effect. It may miss when current tick and match tick are very
close (see hal/LowPowerTickerWrapper.cpp). Enlarge LPTICKER_DELAY_TICKS to
4 from 3 to address this boundary case.
Without this override, mpu hal will require 5 mpu regions which exceed 4 mpu
regions supported by M252 (see hal/mpu/mbed_mpu_v8m.c). In this scenario,
we will hit assert error but we actually meet stack overrun first due to just
0x400 bytes for emitting error message. The issue doesn’t occur on other
targets such as M487 because it has 8 mpu regions.
static_memory_defines controls the macro MBED_RAM_START AND MBED_RAM_SIZE
when nrf52840 to use softdevice, it need MBED_RAM_START to set the true application ram start
default static_memory_defines is true, so just remove NRF52840 and NRF52832's set
Remove some (Cypress-proprietary) BSP interfaces and hardware initialization
from the BSPs which is better implemented by a library or application firmware.
Move some remaining functionality from common to the individual targets.
Don't malloc during wifi initialization, as that could cause double allocation in some cases.
The thread stack will be allocated by cy_rtos_thread_start if necessary.
- Add const and static qualifiers in places where they are
applicable but missing
- Remove headers for drivers that aren't implemented yet
- Misc minor bugfixes
Keep vector table and crash data ram in 0x20000000 for
tests-mbed_platform-crash_reporting test.
Move the rest in RAM (0x24000000). This is needed for ethernet and allows
user to use more RAM (512k).
Signed-off-by: Vincent Veron <vincent.veron@st.com>
NOTE1: USB UART is partitioned for non-secure world. Secure world still can share
it with limit that its interrupt cannot use in secure world.
NOTE2: In secure world, USB UART is only for Greentea and STDIO. Developers shouldn't
use it for other purposes.
Support secure/non-secure combined build for non-PSA target:
1. In secure post-build, deliver built secure image to TARGET_NU_PREBUILD_SECURE
directory which is to combine later.
2. In non-secure post-build, merge non-secure image with secure image saved in
TARGET_NU_PREBUILD_SECURE directory.
3. In non-secure post-build, user can also drop pre-built secure image saved in
TARGET_NU_PREBUILD_SECURE directory and provide its own by adding the line below
in mbed_app.json:
"target.extra_labels_remove": ["NU_PREBUILD_SECURE"]
1. Create a private target name NU_PFM_M2351_CM which stands for the
NuMaker-PFM-M2351 board and is to be extended.
2. NU_PFM_M2351_NPSA_S/NS target names for non-PSA secure/non-secure targets
respectively.
3. The original target name NUMAKER_PFM_M2351 is recycled and cannot be used.
Use NU_PFM_M2351_S/NS for non-PSA secure/non-secure targets instead.
NOTE: Target name doesn't follow the rule below because online database has
limit of max 20 chars:
NUMAKER_PFM_M2351_PSA/NOPSA_S/NS
Instead, it has the rule:
NU_PFM_M2351_[NPSA_]S/NS
NU_PFM_M2351_S/NS for PSA targets. This is to be consistent with current
PSA target naming. So the resolved target names are:
NU_PFM_M2351_S : PSA secure target
NU_PFM_M2351_NS : PSA non-secure target
NU_PFM_M2351_NPSA_S : Non-PSA secure target
NU_PFM_M2351_NPSA_NS : Non-PSA non-secure target
We should not block in case the UART is busy transmitting. The
API has been updated to check the status of all UART's and return
1 in case any of them is busy transmitting.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The code checks if any of the UART's is still transmitting.
If so then prevent from entering deepsleep
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
We should not block in case the UART is busy transmitting. The
API has been updated to check the status of all UART's and return
1 in case any of them is busy transmitting.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The code checks if any of the UART's is still transmitting.
If so then prevent from entering deepsleep
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Fixed HAL API implementation for InterruptIn:
- Interrupt was not enabled by default after configuration as it should be.
- Interrupt-to-object linking was not handled properly.
Removed private TODO file.
Fixed cmsis.h so that renaming of CS and DIR_H is not necessary any more.
Leave pinmap.h unchanged although it should include stdint.h
Moved stdint.h to PinNames.h instead, where it is also used.
Reworked system startup (clock configuration) to be more flexible
(different clock sources for MCLK and SMCLK, configurable clock dividers).
Fixed Copyright headers
Changed default clock settings for MSP432 Launchpad to
MCLK 48 MHz (HFXT) and SMCLK 24 MHz (HFXT)
Remove mbed_rtx.h
Added common mbed_rtx.h file (merge with lastest master)
Added support for IAR toolchain
Fixed some astyle problems.
Added support for ARM C5/C6 toolchains
Small changes to us_ticker implementation after port testing.
Changed default clock configuration to DCO (MCLK 48MHz, SMCLK 24MHz).
De-configured the LFXT crysal, because this made the system_reset() test to time out.
Removed MPU from device_has list. Changed clock source to HFXT.
Reworked startup_msp432p401r.c -> now only one startup file for all compilers.
Changed all linker scripts to delete VECTORS stuff (not needed).
Moved position of MSP432 in targets.json so TI stuff is in one block.
Without free-up of peripheral pins, peripheral pins of the same peripheral may
share by multiple ports after port iteration, and this peripheral may fail with
pin interference.
In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes.
Targets not supporting this feature are listed below:
- NUMAKER_PFM_NANO130
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M453
Fix logic error on replying NACK at the end of transfer.
This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/
i2c - test single byte read i2c API.
Better IP initialization sequence:
1. Configure IP pins
2. Select IP clock source and then enable it
3. Reset the IP (SYS_ResetModule)
NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if
IP clock enable is before IP reset.
NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then
IP reset.
NOTE3: IP reset at the end of IP initialization sequence can cover unexpected
situation.
This test requires total latency (tot = h/w + s/w) (wakeup from deepsleep) be
under 1ms. To check the issue, measure total latency on Nuvoton targets:
TARGET EXP(us) EXP+TOL(us) ACT(us)
NANO130 42000 43000 42939
NUC472 42000 43000 42236
M453 42000 43000 43274
M487 42000 43000 42877
M2351 42000 43000 43213
Checking h/w spec, h/w latency (wakeup time from normal power-down mode) on
M487/M2351 is just 1us (n/a on other targets). S/W latency plays the major
part here.
S/W latency relies on system performance. On Nuvoton targets, 'LPTICKER_DELAY_TICKS'
possibly complicates the test. Anyway, to pass the test, add extra 1ms latency
(deep-sleep-latency) in targets.json for Nuvoton targets.
On Nuvoton targets, lp_ticker_set_interrupt(...) needs around 3 lp-ticker
ticks to take effect. It may miss when current tick and match tick are very
close (see hal/LowPowerTickerWrapper.cpp). Enlarge LPTICKER_DELAY_TICKS to
4 from 3 to address this boundary case.
For kit targets that inherit from a module, move the kit a top-level
target folder rather than nesting underneath the module folder, to
avoid too-long-path issues on Windows.
Note this only changes the folder layout, not the inheritance.
Enables code examples/end user applications to override if necessary
Add BSP_DESIGN_MODUS component by default to all PSOC6 boards. Applications can remove this if necessary.
This avoids a stack overflow if sleep is called for the first time from
the idle thread (which by default has a fairly small stack, and which is
already fairly deep by the time it calls into the usticker adapter)
These provide information to allow Cypress graphical configuration tools
to avoid conflicting usage of hardware resources which are managed by
firware included with the BSP.
static_memory_defines controls the macro MBED_RAM_START AND MBED_RAM_SIZE
when nrf52832 to use softdevice, it need MBED_RAM_START to set the true application ram start
[Warning] tcm_heap.c@70,18: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'MemChunk * {aka struct _MemChunk *}' [-Wformat=]
[Warning] tcm_heap.c@70,28: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'MemChunk * {aka struct _MemChunk *}' [-Wformat=]
Signed-off-by: Tony Wu <tonywu@realtek.com>
Keep former behaviour for I2C V1.
For I2C V2:
Use only I2C_FIRST_FRAME, I2C_FIRST_AND_LAST_FRAME and I2C_LAST_FRAME,
thus we avoid using reload bit.
Reload suppose the next frame would be in the same direction,
but we have no guarranty about this. So we cannot use reload bit.
Note: in case of 2 consecutive I2C_FIRST_FRAME,
a restart is automatically generated only if there is direction change in the direction.
For STM32 platforms that embed an OSPI IP, we're offering
a QSPI fallback support with this commit.
When OSPI is supported in mbed, we can consider adding full
OSPI support
1. FPGA test shield requires at least half sclk period delay between
CS assertion and first sclk edge
2. Update Kinetis SPI drivers to match what is already done for K64F
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
- Added dummy data setup API to allow users to configure
the dummy data to be transferred.
- Added new APIs for half-duplex transfer function. Users
can send and receive data by one API in the polling/interrupt/EDMA way,
and they can choose either to transmit first or to receive first.
Additionally, the PCS pin can be configured as assert status in
transmission (between transmit and receive) by setting the
isPcsAssertInTransfer to true.
- Fix for MISRA issues
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Chun-Chieh Li
jeromecoutant
Martin Kojtal
Chris Trowbridge
Kyle Kearney
Volodymyr Medvid
James Wang
George Psimenos
Vincent Veron
int_szyk
mahanthgouda
Kostiantyn Tkachov
Michal Paszta
Mahesh Mahadevan
Lin Gao
Leszek Rusinowicz
Andreas Terstegge
dolphin\gena
Jaeden Amero
Ryan Morse
Roman Okhrimenko
Hennadiy Kytsun
Laurent Meunier
aqib-ublox
Orest Akymyshyn
Leon Lindenfelser
Marcelo Salazar
Malavika Sajikumar
Shuopeng Deng
Tony Wu
Alexandre Bourdiol
cyliangtw
Anna Bridge