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Fix LPA pin configuration for two Cypress Targets 

Fixes are for CY8CKIT_062S2_43012 and CY8CPROTO_062_4343W
pull/11367/head
Ryan Morse 2019-08-27 12:52:41 -07:00 committed by Kyle Kearney
parent 0ee6dfd4a8
commit 13f216d23d
8 changed files with 221 additions and 154 deletions
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58
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -360,30 +360,6 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
.channel_num = CYBSP_BT_POWER_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
{
.outVal = 0,
@ -408,6 +384,30 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
{
.outVal = 1,
@ -841,16 +841,16 @@ void init_cycfg_pins(void)
cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);

76
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -372,44 +372,20 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_ENABLED 1U
#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
#define CYBSP_BT_HOST_WAKE_PORT_NUM 3U
#define CYBSP_BT_HOST_WAKE_PIN 5U
#define CYBSP_BT_HOST_WAKE_NUM 5U
#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT3
#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 3U
#define CYBSP_BT_DEVICE_WAKE_PIN 5U
#define CYBSP_BT_DEVICE_WAKE_NUM 5U
#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_3_pin_5_HSIOM
#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P3_5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 4U
#define CYBSP_BT_DEVICE_WAKE_PIN 0U
#define CYBSP_BT_DEVICE_WAKE_NUM 0U
#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_4_pin_0_HSIOM
#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P4_0
#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P3_5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
@ -420,6 +396,30 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_ENABLED 1U
#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT4
#define CYBSP_BT_HOST_WAKE_PORT_NUM 4U
#define CYBSP_BT_HOST_WAKE_PIN 0U
#define CYBSP_BT_HOST_WAKE_NUM 0U
#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_4_pin_0_HSIOM
#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P4_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_ENABLED 1U
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
#define CYBSP_EZI2C_SCL_PORT_NUM 6U
@ -837,14 +837,14 @@ extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -40,7 +40,7 @@ void init_cycfg_routing(void);
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
@ -53,9 +53,9 @@ void init_cycfg_routing(void);
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB

10
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
<Design version="11" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v2">
<ToolInfo version="1.0.0"/>
<Devices>
<Device mpn="CY8C624ABZI-D44">
@ -184,8 +184,8 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[5]" alias="CYBSP_BT_HOST_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Block location="ioss[0].port[3].pin[5]" alias="CYBSP_BT_DEVICE_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="0"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@ -194,8 +194,8 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[4].pin[0]" alias="CYBSP_BT_DEVICE_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Block location="ioss[0].port[4].pin[0]" alias="CYBSP_BT_HOST_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="0"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>

87
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -72,6 +72,30 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM,
.channel_num = CYBSP_WIFI_HOST_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
{
.outVal = 1,
@ -360,30 +384,6 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
.channel_num = CYBSP_BT_POWER_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
{
.outVal = 0,
@ -408,6 +408,30 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_BT_HOST_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
{
.outVal = 1,
@ -782,6 +806,11 @@ void init_cycfg_pins(void)
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
@ -841,16 +870,16 @@ void init_cycfg_pins(void)
cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);

104
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -84,6 +84,30 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT0
#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 0U
#define CYBSP_WIFI_HOST_WAKE_PIN 4U
#define CYBSP_WIFI_HOST_WAKE_NUM 4U
#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_0_pin_4_HSIOM
#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_0_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P0_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_ENABLED 1U
#define CYBSP_QSPI_SS_PORT GPIO_PRT11
#define CYBSP_QSPI_SS_PORT_NUM 11U
@ -372,44 +396,20 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_ENABLED 1U
#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
#define CYBSP_BT_HOST_WAKE_PORT_NUM 3U
#define CYBSP_BT_HOST_WAKE_PIN 5U
#define CYBSP_BT_HOST_WAKE_NUM 5U
#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT3
#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 3U
#define CYBSP_BT_DEVICE_WAKE_PIN 5U
#define CYBSP_BT_DEVICE_WAKE_NUM 5U
#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_3_pin_5_HSIOM
#define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P3_5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 4U
#define CYBSP_BT_DEVICE_WAKE_PIN 0U
#define CYBSP_BT_DEVICE_WAKE_NUM 0U
#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_BT_DEVICE_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_4_pin_0_HSIOM
#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P4_0
#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P3_5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
@ -420,6 +420,30 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_ENABLED 1U
#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT4
#define CYBSP_BT_HOST_WAKE_PORT_NUM 4U
#define CYBSP_BT_HOST_WAKE_PIN 0U
#define CYBSP_BT_HOST_WAKE_NUM 0U
#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_BT_HOST_WAKE_INIT_DRIVESTATE 0
#ifndef ioss_0_port_4_pin_0_HSIOM
#define ioss_0_port_4_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P4_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_ENABLED 1U
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
#define CYBSP_EZI2C_SCL_PORT_NUM 6U
@ -789,6 +813,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
@ -837,14 +865,14 @@ extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -40,7 +40,7 @@ void init_cycfg_routing(void);
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
@ -50,16 +50,16 @@ void init_cycfg_routing(void);
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#if defined(__cplusplus)
}

20
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
<Design version="11" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v2">
<ToolInfo version="1.0.0"/>
<Devices>
<Device mpn="CY8C624ABZI-D44">
@ -64,6 +64,16 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[4]" alias="CYBSP_WIFI_HOST_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="0"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
@ -184,8 +194,8 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[5]" alias="CYBSP_BT_HOST_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Block location="ioss[0].port[3].pin[5]" alias="CYBSP_BT_DEVICE_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="0"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
@ -194,8 +204,8 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[4].pin[0]" alias="CYBSP_BT_DEVICE_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Block location="ioss[0].port[4].pin[0]" alias="CYBSP_BT_HOST_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="0"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>