ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #11309 from NXPmicro/Fix_Kinetis_Spi 

MCUXpresso Kinetis SPI drive: Add a delay between CS assertion and first sclk edge
pull/11235/head
Martin Kojtal 2019-08-29 08:49:49 +02:00 committed by GitHub
parent 56a8227c54 5af80db8b6
commit 27571bc2d7
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
7 changed files with 15 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/spi_api.c
View File

@ -80,7 +80,6 @@ void spi_free(spi_t *obj)
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
dspi_master_config_t master_config;
dspi_slave_config_t slave_config;
@ -100,7 +99,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
master_config.ctarConfig.direction = kDSPI_MsbFirst;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
}

5
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/spi_api.c
View File

@ -61,7 +61,6 @@ void spi_free(spi_t *obj)
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
dspi_master_config_t master_config;
dspi_slave_config_t slave_config;
@ -81,7 +80,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
master_config.ctarConfig.direction = kDSPI_MsbFirst;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
}
@ -95,7 +94,7 @@ void spi_frequency(spi_t *obj, int hz)
DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
}
static inline int spi_readable(spi_t * obj)
static inline int spi_readable(spi_t *obj)
{
return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
}

4
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/spi_api.c
View File

@ -80,7 +80,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
master_config.ctarConfig.direction = kDSPI_MsbFirst;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
}
@ -94,7 +94,7 @@ void spi_frequency(spi_t *obj, int hz)
DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
}
static inline int spi_readable(spi_t * obj)
static inline int spi_readable(spi_t *obj)
{
return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
}

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/spi_api.c
View File

@ -99,7 +99,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
master_config.ctarConfig.direction = kDSPI_MsbFirst;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
}

2
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/spi_api.c
View File

@ -99,7 +99,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
master_config.ctarConfig.direction = kDSPI_MsbFirst;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
}

4
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/spi_api.c
View File

@ -80,7 +80,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
master_config.ctarConfig.direction = kDSPI_MsbFirst;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
DSPI_MasterInit(spi_address[obj->instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->instance]));
}
@ -94,7 +94,7 @@ void spi_frequency(spi_t *obj, int hz)
DSPI_MasterSetDelayTimes(spi_address[obj->instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
}
static inline int spi_readable(spi_t * obj)
static inline int spi_readable(spi_t *obj)
{
return (DSPI_GetStatusFlags(spi_address[obj->instance]) & kDSPI_RxFifoDrainRequestFlag);
}

12
targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/spi_api.c
View File

@ -90,7 +90,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave)
master_config.ctarConfig.cpol = (mode & 0x2) ? kDSPI_ClockPolarityActiveLow : kDSPI_ClockPolarityActiveHigh;
master_config.ctarConfig.cpha = (mode & 0x1) ? kDSPI_ClockPhaseSecondEdge : kDSPI_ClockPhaseFirstEdge;
master_config.ctarConfig.direction = kDSPI_MsbFirst;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 0;
master_config.ctarConfig.pcsToSckDelayInNanoSec = 100;
DSPI_MasterInit(spi_address[obj->spi.instance], &master_config, CLOCK_GetFreq(spi_clocks[obj->spi.instance]));
}
@ -104,7 +104,7 @@ void spi_frequency(spi_t *obj, int hz)
DSPI_MasterSetDelayTimes(spi_address[obj->spi.instance], kDSPI_Ctar0, kDSPI_LastSckToPcs, busClock, 500000000 / hz);
}
static inline int spi_readable(spi_t * obj)
static inline int spi_readable(spi_t *obj)
{
return (DSPI_GetStatusFlags(spi_address[obj->spi.instance]) & kDSPI_RxFifoDrainRequestFlag);
}
@ -314,14 +314,14 @@ static void spi_buffer_set(spi_t *obj, const void *tx, uint32_t tx_length, void
void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint)
{
if(spi_active(obj)) {
if (spi_active(obj)) {
return;
}
/* check corner case */
if(tx_length == 0) {
if (tx_length == 0) {
tx_length = rx_length;
tx = (void*) 0;
tx = (void *) 0;
}
/* First, set the buffer */
@ -422,7 +422,7 @@ uint32_t spi_irq_handler_asynch(spi_t *obj)
void spi_abort_asynch(spi_t *obj)
{
// If we're not currently transferring, then there's nothing to do here
if(spi_active(obj) == 0) {
if (spi_active(obj) == 0) {
return;
}