Add reserved resources lists to Cypress BSPs

These provide information to allow Cypress graphical configuration tools
to avoid conflicting usage of hardware resources which are managed by
firware included with the BSP.

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,48 @@
+[Device="CY8C624ABZI-D44"]
+ 
+[Blocks]
+# User IO
+# CYBSP_USER_LED1
+ioss[0].port[11].pin[1]
+# CYBSP_USER_LED2
+ioss[0].port[1].pin[5]
+# CYBSP_USER_LED3
+ioss[0].port[1].pin[1]
+# CYBSP_USER_LED4
+ioss[0].port[0].pin[5]
+# CYBSP_USER_LED5
+ioss[0].port[7].pin[3]
+# CYBSP_USER_BTN1
+ioss[0].port[0].pin[4]
+# CYBSP_USER_BTN2
+ioss[0].port[1].pin[4] 
+
+# Debug
+# CYBSP_DEBUG_UART
+scb[5]
+# CYBSP_DEBUG_UART_RX
+ioss[0].port[5].pin[0]
+# CYBSP_DEBUG_UART_TX
+ioss[0].port[5].pin[1]
+# CYBSP_DEBUG_UART_RTS
+ioss[0].port[5].pin[2]
+# CYBSP_DEBUG_UART_CTS 
+ioss[0].port[5].pin[3]
+
+# WIFI
+# CYBSP_WIFI_SDIO
+sdhc[0]
+# CYBSP_WIFI_SDIO_D0
+ioss[0].port[2].pin[0]
+# CYBSP_WIFI_SDIO_D1
+ioss[0].port[2].pin[1]
+# CYBSP_WIFI_SDIO_D2
+ioss[0].port[2].pin[2]
+# CYBSP_WIFI_SDIO_D3
+ioss[0].port[2].pin[3]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[2].pin[4]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[2].pin[5]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[2].pin[6]

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,42 @@
+[Device="CY8C624ABZI-D44"]
+ 
+[Blocks]
+# User IO
+# CYBSP_USER_LED1
+ioss[0].port[1].pin[5]
+# CYBSP_USER_LED2
+ioss[0].port[13].pin[7]
+# CYBSP_USER_LED3
+ioss[0].port[0].pin[3]
+# CYBSP_USER_LED4
+ioss[0].port[1].pin[1]
+# CYBSP_USER_LED5
+ioss[0].port[11].pin[1]
+# CYBSP_USER_BTN1
+ioss[0].port[0].pin[4]
+
+# Debug
+# CYBSP_DEBUG_UART
+scb[5]
+# CYBSP_DEBUG_UART_RX
+ioss[0].port[5].pin[0]
+# CYBSP_DEBUG_UART_TX
+ioss[0].port[5].pin[1]
+
+# WIFI
+# CYBSP_WIFI_SDIO
+sdhc[0]
+# CYBSP_WIFI_SDIO_D0
+ioss[0].port[2].pin[0]
+# CYBSP_WIFI_SDIO_D1
+ioss[0].port[2].pin[1]
+# CYBSP_WIFI_SDIO_D2
+ioss[0].port[2].pin[2]
+# CYBSP_WIFI_SDIO_D3
+ioss[0].port[2].pin[3]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[2].pin[4]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[2].pin[5]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[2].pin[6]

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,24 @@
+[Device="CY8C6347BZI-BLD53"]
+ 
+[Blocks]
+# User IO
+# CYBSP_USER_LED1
+ioss[0].port[1].pin[5]
+# CYBSP_USER_LED2
+ioss[0].port[13].pin[7]
+# CYBSP_USER_LED3
+ioss[0].port[0].pin[3]
+# CYBSP_USER_LED4
+ioss[0].port[1].pin[1]
+# CYBSP_USER_LED5
+ioss[0].port[11].pin[1]
+# CYBSP_USER_BTN1
+ioss[0].port[0].pin[4]
+
+# Debug
+# CYBSP_DEBUG_UART
+scb[5]
+# CYBSP_DEBUG_UART_RX
+ioss[0].port[5].pin[0]
+# CYBSP_DEBUG_UART_TX
+ioss[0].port[5].pin[1]

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,42 @@
+[Device="CY8C6247BZI-D54"]
+ 
+[Blocks]
+# User IO
+# CYBSP_USER_LED1
+ioss[0].port[1].pin[5]
+# CYBSP_USER_LED2
+ioss[0].port[13].pin[7]
+# CYBSP_USER_LED3
+ioss[0].port[0].pin[3]
+# CYBSP_USER_LED4
+ioss[0].port[1].pin[1]
+# CYBSP_USER_LED5
+ioss[0].port[11].pin[1]
+# CYBSP_USER_BTN1
+ioss[0].port[0].pin[4]
+
+# Debug
+# CYBSP_DEBUG_UART
+scb[5]
+# CYBSP_DEBUG_UART_RX
+ioss[0].port[5].pin[0]
+# CYBSP_DEBUG_UART_TX
+ioss[0].port[5].pin[1]
+
+# WIFI
+# CYBSP_WIFI_SDIO
+udb[0]
+# CYBSP_WIFI_SDIO_D0
+ioss[0].port[2].pin[0]
+# CYBSP_WIFI_SDIO_D1
+ioss[0].port[2].pin[1]
+# CYBSP_WIFI_SDIO_D2
+ioss[0].port[2].pin[2]
+# CYBSP_WIFI_SDIO_D3
+ioss[0].port[2].pin[3]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[2].pin[4]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[2].pin[5]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[2].pin[6]

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,42 @@
+[Device="CYB0644ABZI-D44"]
+ 
+[Blocks]
+# User IO
+# CYBSP_USER_LED1
+ioss[0].port[1].pin[5]
+# CYBSP_USER_LED2
+ioss[0].port[13].pin[7]
+# CYBSP_USER_LED3
+ioss[0].port[0].pin[3]
+# CYBSP_USER_LED4
+ioss[0].port[1].pin[1]
+# CYBSP_USER_LED5
+ioss[0].port[11].pin[1]
+# CYBSP_USER_BTN1
+ioss[0].port[0].pin[4]
+
+# Debug
+# CYBSP_DEBUG_UART
+scb[5]
+# CYBSP_DEBUG_UART_RX
+ioss[0].port[5].pin[0]
+# CYBSP_DEBUG_UART_TX
+ioss[0].port[5].pin[1]
+
+# WIFI
+# CYBSP_WIFI_SDIO
+sdhc[0]
+# CYBSP_WIFI_SDIO_D0
+ioss[0].port[2].pin[0]
+# CYBSP_WIFI_SDIO_D1
+ioss[0].port[2].pin[1]
+# CYBSP_WIFI_SDIO_D2
+ioss[0].port[2].pin[2]
+# CYBSP_WIFI_SDIO_D3
+ioss[0].port[2].pin[3]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[2].pin[4]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[2].pin[5]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[2].pin[6]

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,34 @@
+[Device="CY8C6245LQI-S3D72"]
+ 
+[Blocks]
+# User IO
+# CYBSP_USER_LED1
+ioss[0].port[11].pin[1]
+# CYBSP_USER_BTN1
+ioss[0].port[0].pin[4]
+
+# Debug
+# CYBSP_DEBUG_UART
+scb[1]
+# CYBSP_DEBUG_UART_RX
+ioss[0].port[10].pin[0]
+# CYBSP_DEBUG_UART_TX
+ioss[0].port[10].pin[1]
+
+# WIFI
+# CYBSP_WIFI_SDIO
+sdhc[0]
+# CYBSP_WIFI_SDIO_D0
+ioss[0].port[2].pin[0]
+# CYBSP_WIFI_SDIO_D1
+ioss[0].port[2].pin[1]
+# CYBSP_WIFI_SDIO_D2
+ioss[0].port[2].pin[2]
+# CYBSP_WIFI_SDIO_D3
+ioss[0].port[2].pin[3]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[2].pin[4]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[2].pin[5]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[2].pin[6]

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,34 @@
+[Device="CY8C624ABZI-D44"]
+ 
+[Blocks]
+# User IO
+# CYBSP_USER_LED1
+ioss[0].port[13].pin[7]
+# CYBSP_USER_BTN1
+ioss[0].port[0].pin[4]
+
+# Debug
+# CYBSP_DEBUG_UART
+scb[5]
+# CYBSP_DEBUG_UART_RX
+ioss[0].port[5].pin[0]
+# CYBSP_DEBUG_UART_TX
+ioss[0].port[5].pin[1]
+
+# WIFI
+# CYBSP_WIFI_SDIO
+sdhc[0]
+# CYBSP_WIFI_SDIO_D0
+ioss[0].port[2].pin[0]
+# CYBSP_WIFI_SDIO_D1
+ioss[0].port[2].pin[1]
+# CYBSP_WIFI_SDIO_D2
+ioss[0].port[2].pin[2]
+# CYBSP_WIFI_SDIO_D3
+ioss[0].port[2].pin[3]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[2].pin[4]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[2].pin[5]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[2].pin[6]

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_063_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,18 @@
+[Device="CYBLE-416045-02"]
+ 
+[Blocks]
+# User IO
+# CYBSP_USER_LED1
+ioss[0].port[6].pin[3]
+# CYBSP_USER_LED2
+ioss[0].port[7].pin[1]
+# CYBSP_USER_BTN1
+ioss[0].port[0].pin[4]
+
+# Debug
+# CYBSP_DEBUG_UART
+scb[5]
+# CYBSP_DEBUG_UART_RX
+ioss[0].port[5].pin[0]
+# CYBSP_DEBUG_UART_TX
+ioss[0].port[5].pin[1]

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,18 @@
+[Device="CYB06447BZI-D54"]
+ 
+[Blocks]
+# User IO
+# CYBSP_USER_LED1
+ioss[0].port[13].pin[7]
+# CYBSP_USER_LED2
+ioss[0].port[1].pin[5]
+# CYBSP_USER_BTN1
+ioss[0].port[0].pin[4]
+
+# Debug
+# CYBSP_DEBUG_UART
+scb[5]
+# CYBSP_DEBUG_UART_RX
+ioss[0].port[5].pin[0]
+# CYBSP_DEBUG_UART_TX
+ioss[0].port[5].pin[1]

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,38 @@
+[Device="CY8C6247BZI-D54"]
+ 
+[Blocks]
+# User IO
+# CYBSP_USER_LED1
+ioss[0].port[0].pin[3]
+# CYBSP_USER_LED2
+ioss[0].port[1].pin[1]
+# CYBSP_USER_LED3
+ioss[0].port[10].pin[6]
+# CYBSP_USER_BTN1
+ioss[0].port[0].pin[4]
+
+# Debug
+# CYBSP_DEBUG_UART
+scb[6]
+# CYBSP_DEBUG_UART_RX
+ioss[0].port[13].pin[0]
+# CYBSP_DEBUG_UART_TX
+ioss[0].port[13].pin[1]
+
+# WIFI
+# CYBSP_WIFI_SDIO
+udb[0]
+# CYBSP_WIFI_SDIO_D0
+ioss[0].port[2].pin[0]
+# CYBSP_WIFI_SDIO_D1
+ioss[0].port[2].pin[1]
+# CYBSP_WIFI_SDIO_D2
+ioss[0].port[2].pin[2]
+# CYBSP_WIFI_SDIO_D3
+ioss[0].port[2].pin[3]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[2].pin[4]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[2].pin[5]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[2].pin[6]

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,40 @@
+[Device="CY8C6247FDI-D32"]
+ 
+[Blocks]
+# User IO
+# CYBSP_USER_LED1
+ioss[0].port[1].pin[5]
+# CYBSP_USER_LED2
+ioss[0].port[11].pin[1]
+# CYBSP_USER_BTN1
+ioss[0].port[1].pin[4]
+
+# Debug
+# CYBSP_DEBUG_UART
+scb[5]
+# CYBSP_DEBUG_UART_RX
+ioss[0].port[5].pin[0]
+# CYBSP_DEBUG_UART_TX
+ioss[0].port[5].pin[1]
+# CYBSP_DEBUG_UART_RTS
+ioss[0].port[5].pin[2]
+# CYBSP_DEBUG_UART_CTS
+ioss[0].port[5].pin[3]
+
+# WIFI
+# CYBSP_WIFI_SDIO
+udb[0]
+# CYBSP_WIFI_SDIO_D0
+ioss[0].port[12].pin[1]
+# CYBSP_WIFI_SDIO_D1
+ioss[0].port[12].pin[2]
+# CYBSP_WIFI_SDIO_D2
+ioss[0].port[12].pin[3]
+# CYBSP_WIFI_SDIO_D3
+ioss[0].port[12].pin[4]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[12].pin[5]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[12].pin[0]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[6].pin[2]

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,48 @@
+[Device="CY8C6247BZI-D54"]
+ 
+[Blocks]
+# User IO
+# CYBSP_USER_LED1
+ioss[0].port[11].pin[1]
+# CYBSP_USER_LED2
+ioss[0].port[1].pin[5]
+# CYBSP_USER_LED3
+ioss[0].port[1].pin[1]
+# CYBSP_USER_LED4
+ioss[0].port[0].pin[5]
+# CYBSP_USER_LED5
+ioss[0].port[7].pin[3]
+# CYBSP_USER_BTN1
+ioss[0].port[0].pin[4]
+# CYBSP_USER_BTN2
+ioss[0].port[1].pin[4]
+
+# Debug
+# CYBSP_DEBUG_UART
+scb[5]
+# CYBSP_DEBUG_UART_RX
+ioss[0].port[5].pin[0]
+# CYBSP_DEBUG_UART_TX
+ioss[0].port[5].pin[1]
+# CYBSP_DEBUG_UART_RTS
+ioss[0].port[5].pin[2]
+# CYBSP_DEBUG_UART_CTS
+ioss[0].port[5].pin[3]
+
+# WIFI
+# CYBSP_WIFI_SDIO
+udb[0]
+# CYBSP_WIFI_SDIO_DAT0
+ioss[0].port[2].pin[0]
+# CYBSP_WIFI_SDIO_DAT1
+ioss[0].port[2].pin[1]
+# CYBSP_WIFI_SDIO_DAT2
+ioss[0].port[2].pin[2]
+# CYBSP_WIFI_SDIO_DAT3
+ioss[0].port[2].pin[3]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[2].pin[4]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[2].pin[5]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[2].pin[6]