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Update board hardware configuration 

Include all configurator design files with each BSP
pull/11367/head
Kyle Kearney 2019-08-23 15:52:30 -07:00
parent 166325ac37
commit 8c2dec1233
89 changed files with 8813 additions and 3713 deletions
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8
features/FEATURE_BLE/targets/TARGET_Cypress/TARGET_CYW43XXX/HCIDriver.cpp
View File

@ -422,13 +422,13 @@ private:
ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver() {
static ble::vendor::cypress_ble::CyH4TransportDriver transport_driver(
/* TX */ CY_BT_UART_TX, /* RX */ CY_BT_UART_RX,
/* cts */ CY_BT_UART_CTS, /* rts */ CY_BT_UART_RTS, 115200,
CY_BT_PIN_HOST_WAKE, CY_BT_PIN_DEVICE_WAKE
/* TX */ CYBSP_BT_UART_TX, /* RX */ CYBSP_BT_UART_RX,
/* cts */ CYBSP_BT_UART_CTS, /* rts */ CYBSP_BT_UART_RTS, 115200,
CYBSP_BT_HOST_WAKE, CYBSP_BT_DEVICE_WAKE
);
static ble::vendor::cypress::HCIDriver hci_driver(
transport_driver,
/* bt_power */ CY_BT_PIN_POWER
/* bt_power */ CYBSP_BT_POWER
);
return hci_driver;
}

24
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp Normal file
View File

@ -0,0 +1,24 @@
/*******************************************************************************
* File Name: cycfg.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/

38
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -24,22 +24,52 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_BT_UART_CLK_DIV_HW,
.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 51U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 5U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
}

16
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -27,14 +27,14 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U
#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_BT_UART_CLK_DIV_NUM 1U
@ -45,6 +45,16 @@ extern "C" {
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void);
#if defined(__cplusplus)

103
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -56,6 +56,14 @@ const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@ -64,51 +72,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
.smartCardRetryOnNack = false,
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
.oversample = 12,
.enableMsbFirst = false,
.dataWidth = 9UL,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
.breakWidth = 11UL,
.dropOnFrameError = false,
.dropOnParityError = false,
.receiverAddress = 0x0UL,
.receiverAddressMask = 0x0UL,
.acceptAddrInFifo = false,
.enableCts = true,
.ctsPolarity = CY_SCB_UART_ACTIVE_HIGH,
.rtsRxFifoLevel = 63,
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rxFifoTriggerLevel = 63UL,
.rxFifoIntEnableMask = 0UL,
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC;
cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC;
uint32_t CYBSP_RADIO_rca = 0u;
const cy_stc_sd_host_init_config_t CYBSP_RADIO_config =
{
.emmc = false,
.dmaType = CY_SD_HOST_DMA_SDMA,
.enableLedControl = false,
};
cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg =
{
.lowVoltageSignaling = false,
.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
.cardType = &CYBSP_RADIO_cardType,
.rca = &CYBSP_RADIO_rca,
.cardCapacity = &CYBSP_RADIO_cardCapacity,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
@ -116,6 +87,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_obj =
{
.type = CYHAL_RSC_SMIF,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_mcwdt_config_t CYBSP_MCWDT_config =
{
.c0Match = 32768U,
@ -129,6 +108,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_MCWDT_obj =
{
.type = CYHAL_RSC_LPTIMER,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
@ -141,6 +128,14 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
.month = CY_RTC_JANUARY,
.year = 0U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_RTC_obj =
{
.type = CYHAL_RSC_RTC,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void)
@ -148,8 +143,24 @@ void init_cycfg_peripherals(void)
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_16_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_MCWDT_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
#endif //defined (CY_USING_HAL)
}

54
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -29,9 +29,12 @@
#include "cy_sysclk.h"
#include "cy_csd.h"
#include "cy_scb_uart.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_scb_ezi2c.h"
#include "cy_sd_host.h"
#include "cy_smif.h"
#include "cycfg_qspi_memslot.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
@ -39,7 +42,7 @@
extern "C" {
#endif
#define CYBSP_CAPSENSE_ENABLED 1U
#define CYBSP_CSD_ENABLED 1U
#define CY_CAPSENSE_CORE 4u
#define CY_CAPSENSE_CPU_CLK 144000000u
#define CY_CAPSENSE_PERI_CLK 72000000u
@ -49,10 +52,10 @@ extern "C" {
#define Cmod_PORT GPIO_PRT7
#define CintA_PORT GPIO_PRT7
#define CintB_PORT GPIO_PRT7
#define Button0_Rx0_PORT GPIO_PRT8
#define Button0_Tx_PORT GPIO_PRT1
#define Button1_Rx0_PORT GPIO_PRT8
#define Button1_Tx_PORT GPIO_PRT1
#define Button0_Rx0_PORT GPIO_PRT1
#define Button0_Tx_PORT GPIO_PRT8
#define Button1_Rx0_PORT GPIO_PRT1
#define Button1_Tx_PORT GPIO_PRT8
#define LinearSlider0_Sns0_PORT GPIO_PRT8
#define LinearSlider0_Sns1_PORT GPIO_PRT8
#define LinearSlider0_Sns2_PORT GPIO_PRT8
@ -61,10 +64,10 @@ extern "C" {
#define Cmod_PIN 7u
#define CintA_PIN 1u
#define CintB_PIN 2u
#define Button0_Rx0_PIN 1u
#define Button0_Tx_PIN 0u
#define Button1_Rx0_PIN 2u
#define Button1_Tx_PIN 0u
#define Button0_Rx0_PIN 0u
#define Button0_Tx_PIN 1u
#define Button1_Rx0_PIN 0u
#define Button1_Tx_PIN 2u
#define LinearSlider0_Sns0_PIN 3u
#define LinearSlider0_Sns1_PIN 4u
#define LinearSlider0_Sns2_PIN 5u
@ -73,20 +76,14 @@ extern "C" {
#define Cmod_PORT_NUM 7u
#define CintA_PORT_NUM 7u
#define CintB_PORT_NUM 7u
#define CYBSP_CAPSENSE_HW CSD0
#define CYBSP_CAPSENSE_IRQ csd_interrupt_IRQn
#define CYBSP_CSD_HW CSD0
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
#define CYBSP_BT_UART_ENABLED 1U
#define CYBSP_BT_UART_HW SCB2
#define CYBSP_BT_UART_IRQ scb_2_interrupt_IRQn
#define CYBSP_CSD_COMM_ENABLED 1U
#define CYBSP_CSD_COMM_HW SCB3
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
#define CYBSP_DEBUG_UART_ENABLED 1U
#define CYBSP_DEBUG_UART_HW SCB5
#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
#define CYBSP_RADIO_ENABLED 1U
#define CYBSP_RADIO_HW SDHC0
#define CYBSP_RADIO_IRQ sdhc_0_interrupt_general_IRQn
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@ -119,16 +116,25 @@ extern "C" {
extern cy_stc_csd_context_t cy_csd_0_context;
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
extern cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity;
extern cy_en_sd_host_card_type_t CYBSP_RADIO_cardType;
extern uint32_t CYBSP_RADIO_rca;
extern const cy_stc_sd_host_init_config_t CYBSP_RADIO_config;
extern cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_MCWDT_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);

651
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_IN_PORT_NUM,
.channel_num = CYBSP_WCO_IN_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
@ -56,54 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_SW2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = CYBSP_SW2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_G_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED5_RGB_G_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED9_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED9_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_OUT_PORT_NUM,
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config =
{
.outVal = 1,
@ -120,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_SS0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SS0_PORT_NUM,
.channel_num = CYBSP_QSPI_SS0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config =
{
.outVal = 1,
@ -136,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA3_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config =
{
.outVal = 1,
@ -152,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA2_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config =
{
.outVal = 1,
@ -168,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA1_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config =
{
.outVal = 1,
@ -184,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA0_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config =
{
.outVal = 1,
@ -200,155 +208,19 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SPI_CLOCK_PORT_NUM,
.channel_num = CYBSP_QSPI_SPI_CLOCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_CSD_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_R_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED5_RGB_R_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_SW4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_SW4_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED8_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED8_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_SDHC0_DAT0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_SDHC0_DAT1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_SDHC0_DAT2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_SDHC0_DAT3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_SDHC0_DAT3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CMD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_SDHC0_CMD_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CLK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_SDHC0_CLK_HSIOM,
.hsiom = CYBSP_CSD_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
@ -360,6 +232,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SDHC0_CLK_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_RX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_RX_PORT_NUM,
.channel_num = CYBSP_CSD_RX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
{
.outVal = 1,
@ -376,6 +256,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_UART_RX_PORT_NUM,
.channel_num = CYBSP_BT_UART_RX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
{
.outVal = 1,
@ -392,6 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_UART_TX_PORT_NUM,
.channel_num = CYBSP_BT_UART_TX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
{
.outVal = 1,
@ -408,6 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
.channel_num = CYBSP_BT_UART_RTS_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
{
.outVal = 1,
@ -424,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
.channel_num = CYBSP_BT_UART_CTS_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
{
.outVal = 1,
@ -440,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_POWER_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_POWER_PORT_NUM,
.channel_num = CYBSP_BT_POWER_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
{
.outVal = 0,
@ -456,6 +376,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
{
.outVal = 0,
@ -472,70 +400,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RTS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_DEBUG_UART_RTS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_CTS_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = CYBSP_DEBUG_UART_CTS_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
{
.outVal = 1,
@ -552,6 +424,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
.channel_num = CYBSP_EZI2C_SCL_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
{
.outVal = 1,
@ -568,6 +448,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
.channel_num = CYBSP_EZI2C_SDA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
@ -584,6 +472,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
@ -600,6 +496,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
@ -616,6 +520,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
@ -632,6 +544,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINA_PORT_NUM,
.channel_num = CYBSP_CINA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
@ -648,22 +568,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED5_RGB_B_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED5_RGB_B_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINB_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINB_PORT_NUM,
.channel_num = CYBSP_CINB_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
@ -680,6 +592,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CMOD_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CMOD_PORT_NUM,
.channel_num = CYBSP_CMOD_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
@ -696,6 +616,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN0_PORT_NUM,
.channel_num = CYBSP_CSD_BTN0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
@ -712,6 +640,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN1_PORT_NUM,
.channel_num = CYBSP_CSD_BTN1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
@ -728,6 +664,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD0_PORT_NUM,
.channel_num = CYBSP_CSD_SLD0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
@ -744,6 +688,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD1_PORT_NUM,
.channel_num = CYBSP_CSD_SLD1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
@ -760,6 +712,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD2_PORT_NUM,
.channel_num = CYBSP_CSD_SLD2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
@ -776,6 +736,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD3_PORT_NUM,
.channel_num = CYBSP_CSD_SLD3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
@ -792,92 +760,159 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD4_PORT_NUM,
.channel_num = CYBSP_CSD_SLD4_PIN,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void)
{
Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
Cy_GPIO_Pin_Init(CYBSP_SW2_PORT, CYBSP_SW2_PIN, &CYBSP_SW2_config);
Cy_GPIO_Pin_Init(CYBSP_LED5_RGB_G_PORT, CYBSP_LED5_RGB_G_PIN, &CYBSP_LED5_RGB_G_config);
Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS0_PORT, CYBSP_QSPI_SS0_PIN, &CYBSP_QSPI_SS0_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS0_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA3_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA2_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA0_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SPI_CLOCK_PORT, CYBSP_QSPI_SPI_CLOCK_PIN, &CYBSP_QSPI_SPI_CLOCK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SPI_CLOCK_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_LED5_RGB_R_PORT, CYBSP_LED5_RGB_R_PIN, &CYBSP_LED5_RGB_R_config);
Cy_GPIO_Pin_Init(CYBSP_SW4_PORT, CYBSP_SW4_PIN, &CYBSP_SW4_config);
Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config);
Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT0_PORT, CYBSP_SDHC0_DAT0_PIN, &CYBSP_SDHC0_DAT0_config);
Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT1_PORT, CYBSP_SDHC0_DAT1_PIN, &CYBSP_SDHC0_DAT1_config);
Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT2_PORT, CYBSP_SDHC0_DAT2_PIN, &CYBSP_SDHC0_DAT2_config);
Cy_GPIO_Pin_Init(CYBSP_SDHC0_DAT3_PORT, CYBSP_SDHC0_DAT3_PIN, &CYBSP_SDHC0_DAT3_config);
Cy_GPIO_Pin_Init(CYBSP_SDHC0_CMD_PORT, CYBSP_SDHC0_CMD_PIN, &CYBSP_SDHC0_CMD_config);
Cy_GPIO_Pin_Init(CYBSP_SDHC0_CLK_PORT, CYBSP_SDHC0_CLK_PIN, &CYBSP_SDHC0_CLK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RTS_PORT, CYBSP_DEBUG_UART_RTS_PIN, &CYBSP_DEBUG_UART_RTS_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_CTS_PORT, CYBSP_DEBUG_UART_CTS_PIN, &CYBSP_DEBUG_UART_CTS_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_LED5_RGB_B_PORT, CYBSP_LED5_RGB_B_PIN, &CYBSP_LED5_RGB_B_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
#endif //defined (CY_USING_HAL)
}

721
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

File diff suppressed because it is too large Load Diff

62
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -24,10 +24,10 @@
#include "cycfg_qspi_memslot.h"
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xEBU,
.command = 0xECU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
@ -78,10 +78,10 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xD8U,
.command = 0xDCU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
@ -114,10 +114,10 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x38U,
.command = 0x34U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
@ -186,52 +186,52 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x03U,
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd,
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd,
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd,
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd,
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd,
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd,
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd,
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd,
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
.stsRegQuadEnableMask = 0x02U,
/* The max time for the erase type-1 cycle-time in ms. */
.eraseTime = 520U,
.eraseTime = 2600U,
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 134000U,
.chipEraseTime = 460000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 340U
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
.flags = CY_SMIF_FLAG_WR_EN,
.flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
/* The data-line selection options for a slave device. */
.dataSelect = CY_SMIF_DATA_SEL0,
/* The base address the memory slave is mapped to in the PSoC memory map.
@ -239,16 +239,16 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
.baseAddress = 0x18000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
.memMappedSize = 0x10000U,
.memMappedSize = 0x4000000U,
/* If this memory device is one of the devices in the dual quad SPI configuration.
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512S_SlaveSlot_0
&S25FL512SX4byteaddr_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -28,19 +28,19 @@
#define CY_SMIF_DEVICE_NUM 1
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;

16
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -41,20 +41,10 @@ void init_cycfg_routing(void);
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_2_pin_0_HSIOM P2_0_SDHC0_CARD_DAT_3TO00
#define ioss_0_port_2_pin_1_HSIOM P2_1_SDHC0_CARD_DAT_3TO01
#define ioss_0_port_2_pin_2_HSIOM P2_2_SDHC0_CARD_DAT_3TO02
#define ioss_0_port_2_pin_3_HSIOM P2_3_SDHC0_CARD_DAT_3TO03
#define ioss_0_port_2_pin_4_HSIOM P2_4_SDHC0_CARD_CMD
#define ioss_0_port_2_pin_5_HSIOM P2_5_SDHC0_CLK_CARD
#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
#define ioss_0_port_5_pin_2_HSIOM P5_2_SCB5_UART_RTS
#define ioss_0_port_5_pin_3_HSIOM P5_3_SCB5_UART_CTS
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
@ -62,10 +52,10 @@ void init_cycfg_routing(void);
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB

106
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -39,6 +39,9 @@
#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL
#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2
#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
@ -49,11 +52,20 @@
#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
#define CY_CFG_SYSCLK_PLL0_ENABLED 1
#define CY_CFG_SYSCLK_PLL1_ENABLED 1
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
#define CY_CFG_SYSCLK_WCO_ENABLED 1
#define CY_CFG_PWR_ENABLED 1
#define CY_CFG_PWR_INIT 1
#define CY_CFG_PWR_USING_PMIC 0
#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
#define CY_CFG_PWR_USING_ULP 0
static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
{
@ -68,6 +80,30 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
.cco_Freq = 355U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 36,
@ -76,6 +112,14 @@ static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
{
.feedbackDiv = 30,
.referenceDiv = 1,
.outputDiv = 5,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
@ -116,6 +160,12 @@ __STATIC_INLINE void Cy_SysClk_ClkHf2Init()
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
}
__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
@ -141,6 +191,10 @@ __STATIC_INLINE void Cy_SysClk_ClkPath1Init()
{
Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
{
Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
Cy_SysClk_ClkPeriSetDivider(1U);
@ -156,6 +210,17 @@ __STATIC_INLINE void Cy_SysClk_Pll0Init()
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_Pll1Init()
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
{
Cy_SysClk_ClkSlowSetDivider(0U);
@ -176,6 +241,35 @@ __STATIC_INLINE void Cy_SysClk_WcoInit()
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
__STATIC_INLINE void init_cycfg_power(void)
{
/* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
#if (CY_CFG_PWR_VBACKUP_USING_VDDD)
if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
{
Cy_SysLib_ResetBackupDomain();
Cy_SysClk_IloDisable();
Cy_SysClk_IloInit();
}
#else /* Dedicated Supply */
Cy_SysPm_BackupSetSupply(CY_SYSPM_VDDBACKUP_VBACKUP);
#endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
/* Configure core regulator */
#if CY_CFG_PWR_USING_LDO
Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
#else
Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
#endif /* CY_CFG_PWR_USING_LDO */
/* Configure PMIC */
Cy_SysPm_UnlockPmic();
#if CY_CFG_PWR_USING_PMIC
Cy_SysPm_PmicEnableOutput();
#else
Cy_SysPm_PmicDisableOutput();
#endif /* CY_CFG_PWR_USING_PMIC */
}
void init_cycfg_system(void)
@ -461,4 +555,16 @@ void init_cycfg_system(void)
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
#endif //defined (CY_USING_HAL)
}

34
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -28,7 +28,11 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_systick.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_gpio.h"
#include "cy_syspm.h"
#if defined(__cplusplus)
extern "C" {
@ -44,6 +48,8 @@ extern "C" {
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define srss_0_clock_0_hfclk_3_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF3 3UL
#define srss_0_clock_0_hfclk_4_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF4 4UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
@ -52,11 +58,39 @@ extern "C" {
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32000
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_0_ENABLED 1U
#define srss_0_clock_0_pll_1_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_timerclk_0_ENABLED 1U
#define srss_0_clock_0_wco_0_ENABLED 1U
#define srss_0_power_0_ENABLED 1U
#define CY_CFG_PWR_MODE_LP 0x01UL
#define CY_CFG_PWR_MODE_ULP 0x02UL
#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
#define CY_CFG_PWR_MODE_SLEEP 0x08UL
#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
#define CY_CFG_PWR_USING_LDO 1
#define CY_CFG_PWR_VDDA_MV 3300
#define CY_CFG_PWR_VDDD_MV 3300
#define CY_CFG_PWR_VBACKUP_MV 3300
#define CY_CFG_PWR_VDD_NS_MV 3300
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
View File

@ -1,2 +1,4 @@
set SMIF_BANKS {
0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
}

402
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense Normal file
View File

@ -0,0 +1,402 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by CapSense Configurator 2.0.0 build 531-->
<Configuration app="Capsense" major="2" minor="0">
<GeneralProperties>
<Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
<Property id="REGULAR_IIR_RC_N" value="128"/>
<Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
<Property id="PROX_IIR_RC_N" value="128"/>
<Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="REGULAR_IIR_BL_N" value="1"/>
<Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="PROX_IIR_BL_N" value="1"/>
<Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="MULTI_FREQ_SCAN_EN" value="false"/>
<Property id="SENSOR_AUTO_RESET_EN" value="false"/>
<Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
<Property id="VREF_SOURCE" value="SRSS"/>
<Property id="IREF_SOURCE" value="SRSS"/>
<Property id="PROX_TOUCH_COEFF" value="300"/>
<Property id="NUM_CENTROIDS" value="1"/>
</GeneralProperties>
<CsdProperties>
<Property id="CSD_AUTOTUNE" value="HWTH"/>
<Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
<Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
<Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
<Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
<Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
<Property id="CSD_IDAC_MIN" value="20"/>
<Property id="CSD_IDAC_COMP_EN" value="true"/>
<Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
<Property id="CSD_VREF_CUSTOM" value="false"/>
<Property id="CSD_VREF" value="1219"/>
<Property id="CSD_SHIELD_EN" value="false"/>
<Property id="CSD_SHIELD_TANK_EN" value="false"/>
<Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
<Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
<Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_FINE_INIT_TIME" value="10"/>
<Property id="CSD_CALIBRATION_ERROR" value="10"/>
<Property id="CSD_R_CONST" value="1000"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsdProperties>
<CsxProperties>
<Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSX_MAX_FINGERS" value="3"/>
<Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
<Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
<Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
<Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
<Property id="CSX_FINE_INIT_TIME" value="10"/>
<Property id="CSX_CALIBRATION_ERROR" value="20"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsxProperties>
<Widgets>
<Widget id="Button0" type="CSX_BUTTON">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Rx0" kind="Column">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Tx" kind="Row">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
<Widget id="Button1" type="CSX_BUTTON">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Rx0" kind="Column">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Tx" kind="Row">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
<Widget id="LinearSlider0" type="LINEAR_SLIDER">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Sns0" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns1" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns2" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns3" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns4" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
</Widgets>
</Configuration>

63
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi Normal file
View File

@ -0,0 +1,63 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
<Configuration app="QSPI" major="2" minor="0">
<DevicePath>PSoC 6.xml</DevicePath>
<SlotConfigs>
<SlotConfig>
<SlaveSlot>0</SlaveSlot>
<PartNumber>S25FL512S-4byteaddr</PartNumber>
<MemoryMapped>true</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18000000</StartAddress>
<Size>0x4000000</Size>
<EndAddress>0x1BFFFFFF</EndAddress>
<WriteEnable>true</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
<MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>1</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18010000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1801FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>2</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18020000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1802FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>3</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18030000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1803FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
</SlotConfigs>
</Configuration>

319
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -8,7 +8,7 @@
<Param id="dbgMode" value="SWD"/>
<Param id="traceEnable" value="false"/>
</Block>
<Block location="csd[0].csd[0]" alias="CYBSP_CAPSENSE" template="mxs40csd" version="2.0">
<Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
<Param id="CapSenseEnable" value="true"/>
<Param id="CapSenseCore" value="4"/>
<Param id="SensorCount" value="12"/>
@ -64,36 +64,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[4]" alias="CYBSP_SW2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[5]" alias="CYBSP_LED5_RGB_G" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[1]" alias="CYBSP_LED9" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
@ -154,7 +124,7 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
<Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@ -164,96 +134,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[1]" alias="CYBSP_LED5_RGB_R" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[4]" alias="CYBSP_SW4" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[5]" alias="CYBSP_LED8" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[0]" alias="CYBSP_SDHC0_DAT0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[1]" alias="CYBSP_SDHC0_DAT1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[2]" alias="CYBSP_SDHC0_DAT2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[3]" alias="CYBSP_SDHC0_DAT3" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[4]" alias="CYBSP_SDHC0_CMD" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[5]" alias="CYBSP_SDHC0_CLK" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[0]" alias="CYBSP_BT_UART_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
@ -324,46 +204,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[2]" alias="CYBSP_DEBUG_UART_RTS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[3]" alias="CYBSP_DEBUG_UART_CTS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
<Param id="initialState" value="1"/>
@ -434,16 +274,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[7].pin[3]" alias="CYBSP_LED5_RGB_B" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[7].pin[7]" alias="CYBSP_CMOD" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -524,11 +354,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="peri[0].div_16[0]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="52"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_16[1]" alias="CYBSP_BT_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="78"/>
<Param id="fracDivider" value="0"/>
@ -598,59 +423,6 @@
<Param id="EnableWakeup" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
<Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
<Param id="IrdaLowPower" value="false"/>
<Param id="BaudRate" value="115200"/>
<Param id="Oversample" value="12"/>
<Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
<Param id="DataWidth" value="9"/>
<Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
<Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
<Param id="EnableInputFilter" value="false"/>
<Param id="EnableTxEn" value="false"/>
<Param id="FlowControl" value="true"/>
<Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_HIGH"/>
<Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsTriggerLevel" value="63"/>
<Param id="RxTriggerLevel" value="63"/>
<Param id="TxTriggerLevel" value="63"/>
<Param id="MultiProc" value="false"/>
<Param id="MpRxAddress" value="0"/>
<Param id="MpRxAddressMask" value="255"/>
<Param id="MpRxAcceptAddress" value="false"/>
<Param id="DropOnFrameErr" value="false"/>
<Param id="DropOnParityErr" value="false"/>
<Param id="BreakSignalBits" value="11"/>
<Param id="SmCardRetryOnNack" value="false"/>
<Param id="IrdaPolarity" value="NON_INVERTING"/>
<Param id="inFlash" value="true"/>
<Param id="ApiMode" value="HIGH_LEVEL"/>
<Param id="IntrRxNotEmpty" value="false"/>
<Param id="IntrRxFull" value="false"/>
<Param id="IntrRxOverflow" value="false"/>
<Param id="IntrRxUnderflow" value="false"/>
<Param id="IntrRxFrameErr" value="false"/>
<Param id="IntrRxParityErr" value="false"/>
<Param id="IntrRxBreakDetected" value="false"/>
<Param id="IntrRxTrigger" value="false"/>
<Param id="IntrTxUartDone" value="false"/>
<Param id="IntrTxUartLostArb" value="false"/>
<Param id="IntrTxUartNack" value="false"/>
<Param id="IntrTxEmpty" value="false"/>
<Param id="IntrTxNotFull" value="false"/>
<Param id="IntrTxOverflow" value="false"/>
<Param id="IntrTxUnderflow" value="false"/>
<Param id="IntrTxTrigger" value="false"/>
</Block>
<Block location="sdhc[0]" alias="CYBSP_RADIO" template="mxs40sdhost" version="1.0">
<Param id="cardType" value="nonEmmc"/>
<Param id="dmaType" value="CY_SD_HOST_DMA_SDMA"/>
<Param id="enableLedControl" value="false"/>
<Param id="busWidth" value="CY_SD_HOST_BUS_WIDTH_4_BIT"/>
<Param id="lowVoltageSignaling" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
<Param id="configurator" value="0"/>
<Param id="isrAlignment" value="false"/>
@ -683,6 +455,10 @@
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="2"/>
</Block>
<Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="2"/>
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].hfclk[4]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
@ -702,6 +478,9 @@
<Block location="srss[0].clock[0].pathmux[1]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].pathmux[2]" alias="" template="mxs40pathmux" version="1.0">
<Param id="sourceClock" value="imo"/>
</Block>
<Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
<Param id="divider" value="2"/>
</Block>
@ -711,6 +490,12 @@
<Param id="desiredFrequency" value="144.000"/>
<Param id="optimization" value="MinPower"/>
</Block>
<Block location="srss[0].clock[0].pll[1]" alias="" template="mxs40pll" version="1.0">
<Param id="lowFrequencyMode" value="false"/>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="48.000"/>
<Param id="optimization" value="MinPower"/>
</Block>
<Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
<Param id="divider" value="1"/>
</Block>
@ -739,6 +524,22 @@
<Param id="CascadeC1C2" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
<Param id="pwrEstimator" value="0"/>
<Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
<Param id="pmicEnable" value="false"/>
<Param id="backupSrc" value="VDDD"/>
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
<Param id="deepsleepLatency" value="0"/>
<Param id="vddaMv" value="3300"/>
<Param id="vdddMv" value="3300"/>
<Param id="vBackupMv" value="3300"/>
<Param id="vddNsMv" value="3300"/>
<Param id="vddio0Mv" value="3300"/>
<Param id="vddio1Mv" value="3300"/>
</Block>
<Block location="srss[0].rtc[0]" alias="CYBSP_RTC" template="mxs40rtc" version="1.1">
<Param id="format" value="0"/>
<Param id="dst" value="false"/>
@ -790,30 +591,6 @@
<Port name="ioss[0].port[0].pin[1].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[0].digital_inout[0]"/>
<Port name="sdhc[0].card_dat_3to0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[1].digital_inout[0]"/>
<Port name="sdhc[0].card_dat_3to0[1]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[2].digital_inout[0]"/>
<Port name="sdhc[0].card_dat_3to0[2]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[3].digital_inout[0]"/>
<Port name="sdhc[0].card_dat_3to0[3]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[4].digital_inout[0]"/>
<Port name="sdhc[0].card_cmd[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[5].digital_out[0]"/>
<Port name="sdhc[0].clk_card[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
<Port name="scb[2].uart_rx[0]"/>
@ -830,22 +607,6 @@
<Port name="ioss[0].port[3].pin[3].digital_in[0]"/>
<Port name="scb[2].uart_cts[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
<Port name="scb[5].uart_rx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
<Port name="scb[5].uart_tx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[2].digital_out[0]"/>
<Port name="scb[5].uart_rts[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[3].digital_in[0]"/>
<Port name="scb[5].uart_cts[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
<Port name="scb[3].i2c_scl[0]"/>
@ -878,10 +639,6 @@
<Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
<Port name="smif[0].spi_clk[0]"/>
</Net>
<Net>
<Port name="peri[0].div_16[0].clk[0]"/>
<Port name="scb[5].clock[0]"/>
</Net>
<Net>
<Port name="peri[0].div_16[1].clk[0]"/>
<Port name="scb[2].clock[0]"/>
@ -890,10 +647,6 @@
<Port name="peri[0].div_8[1].clk[0]"/>
<Port name="scb[3].clock[0]"/>
</Net>
<Net>
<Port name="sdhc[0].clk_hf[0]"/>
<Port name="srss[0].clock[0].hfclk[4].root_clk[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_hf[0]"/>
<Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
@ -912,6 +665,9 @@
<Arm>
<Port name="ioss[0].port[7].pin[2].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[1].pin[0].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[1].analog[0]"/>
</Arm>
@ -921,9 +677,6 @@
<Arm>
<Port name="ioss[0].port[8].pin[2].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[1].pin[0].analog[0]"/>
</Arm>
<Arm>
<Port name="ioss[0].port[8].pin[3].analog[0]"/>
</Arm>
@ -942,6 +695,10 @@
</Mux>
</Netlist>
</Device>
<Device mpn="CYW43012WKWBG">
<BlockConfig/>
<Netlist/>
</Device>
</Devices>
<Libraries>
<Library name="bt_sdk" version="1.1"/>

24
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp Normal file
View File

@ -0,0 +1,24 @@
/*******************************************************************************
* File Name: cycfg.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -24,18 +24,37 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
}

13
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -27,6 +27,9 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
@ -38,9 +41,13 @@ extern "C" {
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void);

87
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -24,6 +24,14 @@
#include "cycfg_peripherals.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BLE_obj =
{
.type = CYHAL_RSC_BLESS,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
@ -36,34 +44,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
.smartCardRetryOnNack = false,
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
.oversample = 8,
.enableMsbFirst = false,
.dataWidth = 8UL,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
.breakWidth = 11UL,
.dropOnFrameError = false,
.dropOnParityError = false,
.receiverAddress = 0x0UL,
.receiverAddressMask = 0x0UL,
.acceptAddrInFifo = false,
.enableCts = false,
.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rtsRxFifoLevel = 0UL,
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rxFifoTriggerLevel = 63UL,
.rxFifoIntEnableMask = 0UL,
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
@ -71,6 +59,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_obj =
{
.type = CYHAL_RSC_SMIF,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
@ -84,6 +80,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_MCWDT0_obj =
{
.type = CYHAL_RSC_LPTIMER,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
@ -96,13 +100,38 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
.month = CY_RTC_JANUARY,
.year = 0U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_RTC_obj =
{
.type = CYHAL_RSC_RTC,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void)
{
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BLE_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
#endif //defined (CY_USING_HAL)
}

24
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -26,11 +26,14 @@
#define CYCFG_PERIPHERALS_H
#include "cycfg_notices.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_sysclk.h"
#include "cy_csd.h"
#include "cy_scb_ezi2c.h"
#include "cy_scb_uart.h"
#include "cy_smif.h"
#include "cycfg_qspi_memslot.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
@ -85,9 +88,6 @@ extern "C" {
#define CYBSP_CSD_COMM_ENABLED 1U
#define CYBSP_CSD_COMM_HW SCB3
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
#define CYBSP_DEBUG_UART_ENABLED 1U
#define CYBSP_DEBUG_UART_HW SCB5
#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@ -118,12 +118,26 @@ extern "C" {
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
#define CYBSP_RTC_YEAR_OFFSET (0U)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BLE_obj;
#endif //defined (CY_USING_HAL)
extern cy_stc_csd_context_t cy_csd_0_context;
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);

408
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_IN_PORT_NUM,
.channel_num = CYBSP_WCO_IN_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
@ -56,54 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED_RED_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_BTN2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = CYBSP_BTN2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED_BLUE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_OUT_PORT_NUM,
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
{
.outVal = 1,
@ -120,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_SS_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SS_PORT_NUM,
.channel_num = CYBSP_QSPI_SS_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
{
.outVal = 1,
@ -136,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_D3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_D3_PORT_NUM,
.channel_num = CYBSP_QSPI_D3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
{
.outVal = 1,
@ -152,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_D2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_D2_PORT_NUM,
.channel_num = CYBSP_QSPI_D2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
{
.outVal = 1,
@ -168,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_D1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_D1_PORT_NUM,
.channel_num = CYBSP_QSPI_D1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
{
.outVal = 1,
@ -184,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_D0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_D0_PORT_NUM,
.channel_num = CYBSP_QSPI_D0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
{
.outVal = 1,
@ -200,22 +208,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED9_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED9_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SCK_PORT_NUM,
.channel_num = CYBSP_QSPI_SCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
@ -232,70 +232,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED_GREEN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED8_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED8_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_TX_PORT_NUM,
.channel_num = CYBSP_CSD_TX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
{
.outVal = 1,
@ -312,6 +256,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
.channel_num = CYBSP_EZI2C_SCL_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
{
.outVal = 1,
@ -328,6 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
.channel_num = CYBSP_EZI2C_SDA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
@ -344,6 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
@ -360,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
@ -376,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
@ -392,6 +376,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINA_PORT_NUM,
.channel_num = CYBSP_CINA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
@ -408,6 +400,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINB_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINB_PORT_NUM,
.channel_num = CYBSP_CINB_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
@ -424,6 +424,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CMOD_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CMOD_PORT_NUM,
.channel_num = CYBSP_CMOD_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
@ -440,6 +448,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN0_PORT_NUM,
.channel_num = CYBSP_CSD_BTN0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
@ -456,6 +472,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN1_PORT_NUM,
.channel_num = CYBSP_CSD_BTN1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
@ -472,6 +496,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD0_PORT_NUM,
.channel_num = CYBSP_CSD_SLD0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
@ -488,6 +520,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD1_PORT_NUM,
.channel_num = CYBSP_CSD_SLD1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
@ -504,6 +544,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD2_PORT_NUM,
.channel_num = CYBSP_CSD_SLD2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
@ -520,6 +568,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD3_PORT_NUM,
.channel_num = CYBSP_CSD_SLD3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
@ -536,60 +592,124 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD4_PORT_NUM,
.channel_num = CYBSP_CSD_SLD4_PIN,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void)
{
Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
Cy_GPIO_Pin_Init(CYBSP_LED_BLUE_PORT, CYBSP_LED_BLUE_PIN, &CYBSP_LED_BLUE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config);
Cy_GPIO_Pin_Init(CYBSP_LED_GREEN_PORT, CYBSP_LED_GREEN_PIN, &CYBSP_LED_GREEN_config);
Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
#endif //defined (CY_USING_HAL)
}

483
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -27,6 +27,9 @@
#include "cycfg_notices.h"
#include "cy_gpio.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cycfg_routing.h"
#if defined(__cplusplus)
@ -35,6 +38,7 @@ extern "C" {
#define CYBSP_WCO_IN_ENABLED 1U
#define CYBSP_WCO_IN_PORT GPIO_PRT0
#define CYBSP_WCO_IN_PORT_NUM 0U
#define CYBSP_WCO_IN_PIN 0U
#define CYBSP_WCO_IN_NUM 0U
#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
@ -44,8 +48,21 @@ extern "C" {
#endif
#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_ENABLED 1U
#define CYBSP_WCO_OUT_PORT GPIO_PRT0
#define CYBSP_WCO_OUT_PORT_NUM 0U
#define CYBSP_WCO_OUT_PIN 1U
#define CYBSP_WCO_OUT_NUM 1U
#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
@ -55,41 +72,21 @@ extern "C" {
#endif
#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_LED_RED_ENABLED 1U
#define CYBSP_LED_RED_PORT GPIO_PRT0
#define CYBSP_LED_RED_PIN 3U
#define CYBSP_LED_RED_NUM 3U
#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED_RED_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_3_HSIOM
#define ioss_0_port_0_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED_RED_HSIOM ioss_0_port_0_pin_3_HSIOM
#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_BTN2_ENABLED 1U
#define CYBSP_BTN2_PORT GPIO_PRT0
#define CYBSP_BTN2_PIN 4U
#define CYBSP_BTN2_NUM 4U
#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_BTN2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_LED_BLUE_ENABLED 1U
#define CYBSP_LED_BLUE_PORT GPIO_PRT11
#define CYBSP_LED_BLUE_PIN 1U
#define CYBSP_LED_BLUE_NUM 1U
#define CYBSP_LED_BLUE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED_BLUE_INIT_DRIVESTATE 1
#ifndef ioss_0_port_11_pin_1_HSIOM
#define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED_BLUE_HSIOM ioss_0_port_11_pin_1_HSIOM
#define CYBSP_LED_BLUE_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_ENABLED 1U
#define CYBSP_QSPI_SS_PORT GPIO_PRT11
#define CYBSP_QSPI_SS_PORT_NUM 11U
#define CYBSP_QSPI_SS_PIN 2U
#define CYBSP_QSPI_SS_NUM 2U
#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
@ -99,8 +96,21 @@ extern "C" {
#endif
#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_D3_ENABLED 1U
#define CYBSP_QSPI_D3_PORT GPIO_PRT11
#define CYBSP_QSPI_D3_PORT_NUM 11U
#define CYBSP_QSPI_D3_PIN 3U
#define CYBSP_QSPI_D3_NUM 3U
#define CYBSP_QSPI_D3_DRIVEMODE CY_GPIO_DM_STRONG
@ -110,8 +120,21 @@ extern "C" {
#endif
#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_D2_ENABLED 1U
#define CYBSP_QSPI_D2_PORT GPIO_PRT11
#define CYBSP_QSPI_D2_PORT_NUM 11U
#define CYBSP_QSPI_D2_PIN 4U
#define CYBSP_QSPI_D2_NUM 4U
#define CYBSP_QSPI_D2_DRIVEMODE CY_GPIO_DM_STRONG
@ -121,8 +144,21 @@ extern "C" {
#endif
#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_D1_ENABLED 1U
#define CYBSP_QSPI_D1_PORT GPIO_PRT11
#define CYBSP_QSPI_D1_PORT_NUM 11U
#define CYBSP_QSPI_D1_PIN 5U
#define CYBSP_QSPI_D1_NUM 5U
#define CYBSP_QSPI_D1_DRIVEMODE CY_GPIO_DM_STRONG
@ -132,8 +168,21 @@ extern "C" {
#endif
#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_D0_ENABLED 1U
#define CYBSP_QSPI_D0_PORT GPIO_PRT11
#define CYBSP_QSPI_D0_PORT_NUM 11U
#define CYBSP_QSPI_D0_PIN 6U
#define CYBSP_QSPI_D0_NUM 6U
#define CYBSP_QSPI_D0_DRIVEMODE CY_GPIO_DM_STRONG
@ -143,8 +192,21 @@ extern "C" {
#endif
#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_ENABLED 1U
#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
#define CYBSP_QSPI_SCK_PORT_NUM 11U
#define CYBSP_QSPI_SCK_PIN 7U
#define CYBSP_QSPI_SCK_NUM 7U
#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
@ -154,19 +216,21 @@ extern "C" {
#endif
#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_LED9_ENABLED 1U
#define CYBSP_LED9_PORT GPIO_PRT13
#define CYBSP_LED9_PIN 7U
#define CYBSP_LED9_NUM 7U
#define CYBSP_LED9_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED9_INIT_DRIVESTATE 1
#ifndef ioss_0_port_13_pin_7_HSIOM
#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED9_HSIOM ioss_0_port_13_pin_7_HSIOM
#define CYBSP_LED9_IRQ ioss_interrupts_gpio_13_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_TX_ENABLED 1U
#define CYBSP_CSD_TX_PORT GPIO_PRT1
#define CYBSP_CSD_TX_PORT_NUM 1U
#define CYBSP_CSD_TX_PIN 0U
#define CYBSP_CSD_TX_NUM 0U
#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
@ -176,52 +240,21 @@ extern "C" {
#endif
#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_LED_GREEN_ENABLED 1U
#define CYBSP_LED_GREEN_PORT GPIO_PRT1
#define CYBSP_LED_GREEN_PIN 1U
#define CYBSP_LED_GREEN_NUM 1U
#define CYBSP_LED_GREEN_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED_GREEN_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_1_HSIOM
#define ioss_0_port_1_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED_GREEN_HSIOM ioss_0_port_1_pin_1_HSIOM
#define CYBSP_LED_GREEN_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_LED8_ENABLED 1U
#define CYBSP_LED8_PORT GPIO_PRT1
#define CYBSP_LED8_PIN 5U
#define CYBSP_LED8_NUM 5U
#define CYBSP_LED8_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED8_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_5_HSIOM
#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED8_HSIOM ioss_0_port_1_pin_5_HSIOM
#define CYBSP_LED8_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_DEBUG_UART_RX_ENABLED 1U
#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
#define CYBSP_DEBUG_UART_RX_PIN 0U
#define CYBSP_DEBUG_UART_RX_NUM 0U
#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_0_HSIOM
#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
#define CYBSP_DEBUG_UART_TX_ENABLED 1U
#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
#define CYBSP_DEBUG_UART_TX_PIN 1U
#define CYBSP_DEBUG_UART_TX_NUM 1U
#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_1_HSIOM
#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_PORT_PIN P1_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_ENABLED 1U
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
#define CYBSP_EZI2C_SCL_PORT_NUM 6U
#define CYBSP_EZI2C_SCL_PIN 0U
#define CYBSP_EZI2C_SCL_NUM 0U
#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
@ -231,8 +264,21 @@ extern "C" {
#endif
#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
#endif //defined (CY_USING_HAL)
#define CYBSP_EZI2C_SDA_ENABLED 1U
#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
#define CYBSP_EZI2C_SDA_PORT_NUM 6U
#define CYBSP_EZI2C_SDA_PIN 1U
#define CYBSP_EZI2C_SDA_NUM 1U
#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
@ -242,8 +288,21 @@ extern "C" {
#endif
#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
#endif //defined (CY_USING_HAL)
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT6
#define CYBSP_SWO_PORT_NUM 6U
#define CYBSP_SWO_PIN 4U
#define CYBSP_SWO_NUM 4U
#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
@ -253,8 +312,21 @@ extern "C" {
#endif
#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_PORT_PIN P6_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_SWDIO_ENABLED 1U
#define CYBSP_SWDIO_PORT GPIO_PRT6
#define CYBSP_SWDIO_PORT_NUM 6U
#define CYBSP_SWDIO_PIN 6U
#define CYBSP_SWDIO_NUM 6U
#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
@ -264,8 +336,21 @@ extern "C" {
#endif
#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
#endif //defined (CY_USING_HAL)
#define CYBSP_SWDCK_ENABLED 1U
#define CYBSP_SWDCK_PORT GPIO_PRT6
#define CYBSP_SWDCK_PORT_NUM 6U
#define CYBSP_SWDCK_PIN 7U
#define CYBSP_SWDCK_NUM 7U
#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
@ -275,8 +360,21 @@ extern "C" {
#endif
#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
#endif //defined (CY_USING_HAL)
#define CYBSP_CINA_ENABLED 1U
#define CYBSP_CINA_PORT GPIO_PRT7
#define CYBSP_CINA_PORT_NUM 7U
#define CYBSP_CINA_PIN 1U
#define CYBSP_CINA_NUM 1U
#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
@ -286,8 +384,21 @@ extern "C" {
#endif
#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_PORT_PIN P7_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CINB_ENABLED 1U
#define CYBSP_CINB_PORT GPIO_PRT7
#define CYBSP_CINB_PORT_NUM 7U
#define CYBSP_CINB_PIN 2U
#define CYBSP_CINB_NUM 2U
#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
@ -297,8 +408,21 @@ extern "C" {
#endif
#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_PORT_PIN P7_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CMOD_ENABLED 1U
#define CYBSP_CMOD_PORT GPIO_PRT7
#define CYBSP_CMOD_PORT_NUM 7U
#define CYBSP_CMOD_PIN 7U
#define CYBSP_CMOD_NUM 7U
#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
@ -308,8 +432,21 @@ extern "C" {
#endif
#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_PORT_PIN P7_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_ENABLED 1U
#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
#define CYBSP_CSD_BTN0_PORT_NUM 8U
#define CYBSP_CSD_BTN0_PIN 1U
#define CYBSP_CSD_BTN0_NUM 1U
#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
@ -319,8 +456,21 @@ extern "C" {
#endif
#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_ENABLED 1U
#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
#define CYBSP_CSD_BTN1_PORT_NUM 8U
#define CYBSP_CSD_BTN1_PIN 2U
#define CYBSP_CSD_BTN1_NUM 2U
#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
@ -330,8 +480,21 @@ extern "C" {
#endif
#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_ENABLED 1U
#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
#define CYBSP_CSD_SLD0_PORT_NUM 8U
#define CYBSP_CSD_SLD0_PIN 3U
#define CYBSP_CSD_SLD0_NUM 3U
#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
@ -341,8 +504,21 @@ extern "C" {
#endif
#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_ENABLED 1U
#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
#define CYBSP_CSD_SLD1_PORT_NUM 8U
#define CYBSP_CSD_SLD1_PIN 4U
#define CYBSP_CSD_SLD1_NUM 4U
#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
@ -352,8 +528,21 @@ extern "C" {
#endif
#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_ENABLED 1U
#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
#define CYBSP_CSD_SLD2_PORT_NUM 8U
#define CYBSP_CSD_SLD2_PIN 5U
#define CYBSP_CSD_SLD2_NUM 5U
#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
@ -363,8 +552,21 @@ extern "C" {
#endif
#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_ENABLED 1U
#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
#define CYBSP_CSD_SLD3_PORT_NUM 8U
#define CYBSP_CSD_SLD3_PIN 6U
#define CYBSP_CSD_SLD3_NUM 6U
#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
@ -374,8 +576,21 @@ extern "C" {
#endif
#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_ENABLED 1U
#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
#define CYBSP_CSD_SLD4_PORT_NUM 8U
#define CYBSP_CSD_SLD4_PIN 7U
#define CYBSP_CSD_SLD4_NUM 7U
#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
@ -385,39 +600,115 @@ extern "C" {
#endif
#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED9_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED8_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CINA_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CINB_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void);

65
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -24,10 +24,10 @@
#include "cycfg_qspi_memslot.h"
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xEBU,
.command = 0xECU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -42,7 +42,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
@ -60,7 +60,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
@ -78,10 +78,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xD8U,
.command = 0xDCU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -96,7 +96,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
@ -114,10 +114,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x38U,
.command = 0x34U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -132,7 +132,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
@ -150,7 +150,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
@ -168,7 +168,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
@ -186,52 +186,52 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x03U,
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = &S25FL512S_SlaveSlot_0_readCmd,
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = &S25FL512S_SlaveSlot_0_programCmd,
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
.stsRegQuadEnableMask = 0x02U,
/* The max time for the erase type-1 cycle-time in ms. */
.eraseTime = 520U,
.eraseTime = 2600U,
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 134000U,
.chipEraseTime = 460000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 340U
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
.flags = CY_SMIF_FLAG_WR_EN,
.flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
/* The data-line selection options for a slave device. */
.dataSelect = CY_SMIF_DATA_SEL0,
/* The base address the memory slave is mapped to in the PSoC memory map.
@ -239,16 +239,16 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
.baseAddress = 0x18000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
.memMappedSize = 0x10000U,
.memMappedSize = 0x4000000U,
/* If this memory device is one of the devices in the dual quad SPI configuration.
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
&S25FL512S_SlaveSlot_0
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512SX4byteaddr_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =
@ -262,3 +262,4 @@ const cy_stc_smif_block_config_t smifBlockConfig =
/* The version of the SMIF driver. */
.minorVersion = CY_SMIF_DRV_VERSION_MINOR
};

25
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -28,22 +28,23 @@
#define CY_SMIF_DEVICE_NUM 1
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;
#endif /*CY_SMIF_MEMCONFIG_H*/

10
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -40,9 +40,7 @@ void init_cycfg_routing(void);
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
@ -50,11 +48,11 @@ void init_cycfg_routing(void);
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA

60
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -83,6 +83,46 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
.cco_Freq = 355U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 4U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 30,
@ -523,4 +563,24 @@ void init_cycfg_system(void)
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
#endif //defined (CY_USING_HAL)
}

19
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -29,6 +29,9 @@
#include "cy_sysclk.h"
#include "cy_ble_clk.h"
#include "cy_systick.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_gpio.h"
#include "cy_syspm.h"
@ -81,6 +84,22 @@ extern "C" {
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);
#if defined(__cplusplus)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
View File

@ -1,2 +1,4 @@
set SMIF_BANKS {
0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
}

409
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense Normal file
View File

@ -0,0 +1,409 @@
<?xml version="1.0"?>
<Configuration major="2" minor="0">
<!--
File Name: cycfg_capsense.cycapsense
Description:
CapSense middleware configuration
This file should not be modified. It was automatically generated by
CapSense Configurator 2.0.0 build 351
-->
<GeneralProperties>
<Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
<Property id="REGULAR_IIR_RC_N" value="128"/>
<Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
<Property id="PROX_IIR_RC_N" value="128"/>
<Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="REGULAR_IIR_BL_N" value="1"/>
<Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="PROX_IIR_BL_N" value="1"/>
<Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="MULTI_FREQ_SCAN_EN" value="false"/>
<Property id="SENSOR_AUTO_RESET_EN" value="false"/>
<Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
<Property id="VREF_SOURCE" value="SRSS"/>
<Property id="IREF_SOURCE" value="SRSS"/>
<Property id="PROX_TOUCH_COEFF" value="300"/>
<Property id="NUM_CENTROIDS" value="1"/>
</GeneralProperties>
<CsdProperties>
<Property id="CSD_AUTOTUNE" value="HWTH"/>
<Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
<Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
<Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
<Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
<Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
<Property id="CSD_IDAC_MIN" value="20"/>
<Property id="CSD_IDAC_COMP_EN" value="true"/>
<Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
<Property id="CSD_VREF_CUSTOM" value="false"/>
<Property id="CSD_VREF" value="1219"/>
<Property id="CSD_SHIELD_EN" value="false"/>
<Property id="CSD_SHIELD_TANK_EN" value="false"/>
<Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
<Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
<Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_FINE_INIT_TIME" value="10"/>
<Property id="CSD_CALIBRATION_ERROR" value="10"/>
<Property id="CSD_R_CONST" value="1000"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsdProperties>
<CsxProperties>
<Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSX_MAX_FINGERS" value="3"/>
<Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
<Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
<Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
<Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
<Property id="CSX_FINE_INIT_TIME" value="10"/>
<Property id="CSX_CALIBRATION_ERROR" value="20"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsxProperties>
<Widgets>
<Widget id="Button0" type="CSX_BUTTON">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Rx0" kind="Column">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Tx" kind="Row">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
<Widget id="Button1" type="CSX_BUTTON">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Rx0" kind="Column">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Tx" kind="Row">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
<Widget id="LinearSlider0" type="LINEAR_SLIDER">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Sns0" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns1" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns2" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns3" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns4" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
</Widgets>
</Configuration>

63
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi Normal file
View File

@ -0,0 +1,63 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
<Configuration app="QSPI" major="2" minor="0">
<DevicePath>PSoC 6.xml</DevicePath>
<SlotConfigs>
<SlotConfig>
<SlaveSlot>0</SlaveSlot>
<PartNumber>S25FL512S-4byteaddr</PartNumber>
<MemoryMapped>true</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18000000</StartAddress>
<Size>0x4000000</Size>
<EndAddress>0x1BFFFFFF</EndAddress>
<WriteEnable>true</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
<MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>1</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18010000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1801FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>2</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18020000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1802FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>3</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18030000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1803FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
</SlotConfigs>
</Configuration>

143
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus Normal file → Executable file
View File

@ -5,7 +5,6 @@
<Device mpn="CY8C6347BZI-BLD53">
<BlockConfig>
<Block location="bless[0]" alias="CYBSP_BLE" template="mxs40ble" version="1.1">
<Param id="BleConfigurator" value="0"/>
<Param id="BleSharing" value="0"/>
<Param id="ExtPaLnaEnable" value="false"/>
</Block>
@ -69,36 +68,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[3]" alias="CYBSP_LED_RED" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[4]" alias="CYBSP_BTN2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[1]" alias="CYBSP_LED_BLUE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
@ -159,16 +128,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[13].pin[7]" alias="CYBSP_LED9" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -179,46 +138,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[1]" alias="CYBSP_LED_GREEN" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[5]" alias="CYBSP_LED8" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
<Param id="initialState" value="1"/>
@ -379,11 +298,6 @@
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[2]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="109"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="scb[3]" alias="CYBSP_CSD_COMM" template="mxs40ezi2c" version="1.0">
<Param id="DataRate" value="100"/>
<Param id="NumOfAddr" value="CY_SCB_EZI2C_ONE_ADDRESS"/>
@ -393,51 +307,6 @@
<Param id="EnableWakeup" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
<Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
<Param id="IrdaLowPower" value="false"/>
<Param id="BaudRate" value="115200"/>
<Param id="Oversample" value="8"/>
<Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
<Param id="DataWidth" value="8"/>
<Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
<Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
<Param id="EnableInputFilter" value="false"/>
<Param id="EnableTxEn" value="false"/>
<Param id="FlowControl" value="false"/>
<Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsTriggerLevel" value="63"/>
<Param id="RxTriggerLevel" value="63"/>
<Param id="TxTriggerLevel" value="63"/>
<Param id="MultiProc" value="false"/>
<Param id="MpRxAddress" value="0"/>
<Param id="MpRxAddressMask" value="255"/>
<Param id="MpRxAcceptAddress" value="false"/>
<Param id="DropOnFrameErr" value="false"/>
<Param id="DropOnParityErr" value="false"/>
<Param id="BreakSignalBits" value="11"/>
<Param id="SmCardRetryOnNack" value="false"/>
<Param id="IrdaPolarity" value="NON_INVERTING"/>
<Param id="inFlash" value="true"/>
<Param id="ApiMode" value="HIGH_LEVEL"/>
<Param id="IntrRxNotEmpty" value="false"/>
<Param id="IntrRxFull" value="false"/>
<Param id="IntrRxOverflow" value="false"/>
<Param id="IntrRxUnderflow" value="false"/>
<Param id="IntrRxFrameErr" value="false"/>
<Param id="IntrRxParityErr" value="false"/>
<Param id="IntrRxBreakDetected" value="false"/>
<Param id="IntrRxTrigger" value="false"/>
<Param id="IntrTxUartDone" value="false"/>
<Param id="IntrTxUartLostArb" value="false"/>
<Param id="IntrTxUartNack" value="false"/>
<Param id="IntrTxEmpty" value="false"/>
<Param id="IntrTxNotFull" value="false"/>
<Param id="IntrTxOverflow" value="false"/>
<Param id="IntrTxUnderflow" value="false"/>
<Param id="IntrTxTrigger" value="false"/>
</Block>
<Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
<Param id="configurator" value="0"/>
<Param id="isrAlignment" value="false"/>
@ -606,14 +475,6 @@
<Port name="ioss[0].port[0].pin[1].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
<Port name="scb[5].uart_rx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
<Port name="scb[5].uart_tx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
<Port name="scb[3].i2c_scl[0]"/>
@ -650,10 +511,6 @@
<Port name="peri[0].div_8[1].clk[0]"/>
<Port name="scb[3].clock[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[2].clk[0]"/>
<Port name="scb[5].clock[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_hf[0]"/>
<Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
View File

@ -28,6 +28,7 @@ void init_cycfg_all(void)
{
init_cycfg_system();
init_cycfg_clocks();
init_cycfg_dmas();
init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();

24
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp Normal file
View File

@ -0,0 +1,24 @@
/*******************************************************************************
* File Name: cycfg.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/

64
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -24,26 +24,82 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_USB_CLK_DIV_HW,
.channel_num = CYBSP_USB_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_SDIO_DIV_HW,
.channel_num = CYBSP_SDIO_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t peri_0_div_8_4_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_div_8_4_HW,
.channel_num = peri_0_div_8_4_NUM,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SDIO_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&peri_0_div_8_4_obj);
#endif //defined (CY_USING_HAL)
}

25
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -27,6 +27,9 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
@ -41,12 +44,28 @@ extern "C" {
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_CLK_DIV_NUM 3U
#define peri_0_div_8_4_ENABLED 1U
#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_4_NUM 4U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t peri_0_div_8_4_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void);

51
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
View File

@ -62,6 +62,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig =
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 0U,
.channel_num = cpuss_0_dw0_0_chan_0_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_16CYC,
@ -100,6 +108,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig =
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 0U,
.channel_num = cpuss_0_dw0_0_chan_1_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_4CYC,
@ -138,6 +154,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig =
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 1U,
.channel_num = cpuss_0_dw1_0_chan_1_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_IM,
@ -176,4 +200,31 @@ const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig =
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 1U,
.channel_num = cpuss_0_dw1_0_chan_3_CHANNEL,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_dmas(void)
{
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj);
#endif //defined (CY_USING_HAL)
}

24
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
View File

@ -27,6 +27,9 @@
#include "cycfg_notices.h"
#include "cy_dma.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
@ -34,34 +37,47 @@ extern "C" {
#define cpuss_0_dw0_0_chan_0_ENABLED 1U
#define cpuss_0_dw0_0_chan_0_HW DW0
#define cpuss_0_dw0_0_chan_0_CHANNEL 0
#define cpuss_0_dw0_0_chan_0_CHANNEL 0U
#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
#define cpuss_0_dw0_0_chan_1_ENABLED 1U
#define cpuss_0_dw0_0_chan_1_HW DW0
#define cpuss_0_dw0_0_chan_1_CHANNEL 1
#define cpuss_0_dw0_0_chan_1_CHANNEL 1U
#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
#define cpuss_0_dw1_0_chan_1_ENABLED 1U
#define cpuss_0_dw1_0_chan_1_HW DW1
#define cpuss_0_dw1_0_chan_1_CHANNEL 1
#define cpuss_0_dw1_0_chan_1_CHANNEL 1U
#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
#define cpuss_0_dw1_0_chan_3_ENABLED 1U
#define cpuss_0_dw1_0_chan_3_HW DW1
#define cpuss_0_dw1_0_chan_3_CHANNEL 3
#define cpuss_0_dw1_0_chan_3_CHANNEL 3U
#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_dmas(void);
#if defined(__cplusplus)
}

99
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -70,6 +70,14 @@ const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@ -78,34 +86,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
.smartCardRetryOnNack = false,
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
.oversample = 8,
.enableMsbFirst = false,
.dataWidth = 8UL,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
.breakWidth = 11UL,
.dropOnFrameError = false,
.dropOnParityError = false,
.receiverAddress = 0x0UL,
.receiverAddressMask = 0x0UL,
.acceptAddrInFifo = false,
.enableCts = false,
.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rtsRxFifoLevel = 0UL,
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rxFifoTriggerLevel = 63UL,
.rxFifoIntEnableMask = 0UL,
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
@ -113,6 +101,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_obj =
{
.type = CYHAL_RSC_SMIF,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
@ -126,6 +122,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_MCWDT0_obj =
{
.type = CYHAL_RSC_LPTIMER,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
@ -138,6 +142,14 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
.month = CY_RTC_JANUARY,
.year = 0U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_RTC_obj =
{
.type = CYHAL_RSC_RTC,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
{
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
@ -155,19 +167,44 @@ const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
.enableLpm = false,
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USBUART_obj =
{
.type = CYHAL_RSC_USB,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void)
{
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
#endif //defined (CY_USING_HAL)
}

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -29,8 +29,12 @@
#include "cy_sysclk.h"
#include "cy_csd.h"
#include "cy_scb_uart.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_scb_ezi2c.h"
#include "cy_smif.h"
#include "cycfg_qspi_memslot.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
#include "cy_usbfs_dev_drv.h"
@ -81,9 +85,6 @@ extern "C" {
#define CYBSP_CSD_COMM_ENABLED 1U
#define CYBSP_CSD_COMM_HW SCB3
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
#define CYBSP_DEBUG_UART_ENABLED 1U
#define CYBSP_DEBUG_UART_HW SCB5
#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@ -113,7 +114,6 @@ extern "C" {
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
#define CYBSP_RTC_YEAR_OFFSET (0U)
#define CYBSP_SDIO_ENABLED 1U
#define CYBSP_USBUART_ENABLED 1U
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
@ -126,12 +126,29 @@ extern "C" {
extern cy_stc_csd_context_t cy_csd_0_context;
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);

644
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_IN_PORT_NUM,
.channel_num = CYBSP_WCO_IN_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
@ -56,54 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED_RED_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_BTN2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = CYBSP_BTN2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED_BLUE_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED_BLUE_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_OUT_PORT_NUM,
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
{
.outVal = 1,
@ -120,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_SS_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SS_PORT_NUM,
.channel_num = CYBSP_QSPI_SS_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
{
.outVal = 1,
@ -136,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_D3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_D3_PORT_NUM,
.channel_num = CYBSP_QSPI_D3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
{
.outVal = 1,
@ -152,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_D2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_D2_PORT_NUM,
.channel_num = CYBSP_QSPI_D2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
{
.outVal = 1,
@ -168,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_D1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_D1_PORT_NUM,
.channel_num = CYBSP_QSPI_D1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
{
.outVal = 1,
@ -184,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_D0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_D0_PORT_NUM,
.channel_num = CYBSP_QSPI_D0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
{
.outVal = 1,
@ -200,22 +208,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED9_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED9_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SCK_PORT_NUM,
.channel_num = CYBSP_QSPI_SCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config =
{
.outVal = 1,
@ -232,6 +232,14 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t ioss_0_port_14_pin_0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = ioss_0_port_14_pin_0_PORT_NUM,
.channel_num = ioss_0_port_14_pin_0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config =
{
.outVal = 1,
@ -248,6 +256,14 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t ioss_0_port_14_pin_1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = ioss_0_port_14_pin_1_PORT_NUM,
.channel_num = ioss_0_port_14_pin_1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
@ -264,150 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED_GREEN_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED_GREEN_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED8_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED8_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_WIFI_SDIO_D0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_WIFI_SDIO_D1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_WIFI_SDIO_D2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_D3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_WIFI_SDIO_D3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_WIFI_SDIO_CMD_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_WIFI_SDIO_CLK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_WL_REG_ON_config =
{
.outVal = 0,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_WIFI_WL_REG_ON_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_TX_PORT_NUM,
.channel_num = CYBSP_CSD_TX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
{
.outVal = 0,
@ -424,6 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM,
.channel_num = CYBSP_WIFI_HOST_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
{
.outVal = 1,
@ -440,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_UART_RX_PORT_NUM,
.channel_num = CYBSP_BT_UART_RX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
{
.outVal = 1,
@ -456,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_UART_TX_PORT_NUM,
.channel_num = CYBSP_BT_UART_TX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
{
.outVal = 1,
@ -472,6 +376,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
.channel_num = CYBSP_BT_UART_RTS_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
{
.outVal = 1,
@ -488,6 +400,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
.channel_num = CYBSP_BT_UART_CTS_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
{
.outVal = 1,
@ -504,6 +424,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_POWER_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_POWER_PORT_NUM,
.channel_num = CYBSP_BT_POWER_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
{
.outVal = 0,
@ -520,6 +448,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
{
.outVal = 0,
@ -536,38 +472,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
{
.outVal = 1,
@ -584,6 +496,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
.channel_num = CYBSP_EZI2C_SCL_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
{
.outVal = 1,
@ -600,6 +520,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
.channel_num = CYBSP_EZI2C_SDA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
@ -616,6 +544,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
@ -632,6 +568,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
@ -648,6 +592,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
@ -664,6 +616,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINA_PORT_NUM,
.channel_num = CYBSP_CINA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
@ -680,6 +640,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINB_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINB_PORT_NUM,
.channel_num = CYBSP_CINB_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
@ -696,6 +664,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CMOD_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CMOD_PORT_NUM,
.channel_num = CYBSP_CMOD_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
@ -712,6 +688,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN0_PORT_NUM,
.channel_num = CYBSP_CSD_BTN0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
@ -728,6 +712,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN1_PORT_NUM,
.channel_num = CYBSP_CSD_BTN1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
@ -744,6 +736,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD0_PORT_NUM,
.channel_num = CYBSP_CSD_SLD0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
@ -760,6 +760,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD1_PORT_NUM,
.channel_num = CYBSP_CSD_SLD1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
@ -776,6 +784,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD2_PORT_NUM,
.channel_num = CYBSP_CSD_SLD2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
@ -792,6 +808,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD3_PORT_NUM,
.channel_num = CYBSP_CSD_SLD3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
@ -808,94 +832,174 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD4_PORT_NUM,
.channel_num = CYBSP_CSD_SLD4_PIN,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void)
{
Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
Cy_GPIO_Pin_Init(CYBSP_LED_BLUE_PORT, CYBSP_LED_BLUE_PIN, &CYBSP_LED_BLUE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
Cy_GPIO_Pin_Init(CYBSP_LED9_PORT, CYBSP_LED9_PIN, &CYBSP_LED9_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(ioss_0_port_14_pin_0_PORT, ioss_0_port_14_pin_0_PIN, &ioss_0_port_14_pin_0_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&ioss_0_port_14_pin_0_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(ioss_0_port_14_pin_1_PORT, ioss_0_port_14_pin_1_PIN, &ioss_0_port_14_pin_1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&ioss_0_port_14_pin_1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_LED_GREEN_PORT, CYBSP_LED_GREEN_PIN, &CYBSP_LED_GREEN_config);
Cy_GPIO_Pin_Init(CYBSP_LED8_PORT, CYBSP_LED8_PIN, &CYBSP_LED8_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D0_PORT, CYBSP_WIFI_SDIO_D0_PIN, &CYBSP_WIFI_SDIO_D0_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D1_PORT, CYBSP_WIFI_SDIO_D1_PIN, &CYBSP_WIFI_SDIO_D1_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D2_PORT, CYBSP_WIFI_SDIO_D2_PIN, &CYBSP_WIFI_SDIO_D2_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_D3_PORT, CYBSP_WIFI_SDIO_D3_PIN, &CYBSP_WIFI_SDIO_D3_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CMD_PORT, CYBSP_WIFI_SDIO_CMD_PIN, &CYBSP_WIFI_SDIO_CMD_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CLK_PORT, CYBSP_WIFI_SDIO_CLK_PIN, &CYBSP_WIFI_SDIO_CLK_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_WL_REG_ON_PORT, CYBSP_WIFI_WL_REG_ON_PIN, &CYBSP_WIFI_WL_REG_ON_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
#endif //defined (CY_USING_HAL)
}

727
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

File diff suppressed because it is too large Load Diff

65
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -24,10 +24,10 @@
#include "cycfg_qspi_memslot.h"
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xEBU,
.command = 0xECU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -42,7 +42,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
@ -60,7 +60,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
@ -78,10 +78,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xD8U,
.command = 0xDCU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -96,7 +96,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
@ -114,10 +114,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x38U,
.command = 0x34U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -132,7 +132,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
@ -150,7 +150,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
@ -168,7 +168,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
@ -186,52 +186,52 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x03U,
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = &S25FL512S_SlaveSlot_0_readCmd,
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = &S25FL512S_SlaveSlot_0_programCmd,
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
.stsRegQuadEnableMask = 0x02U,
/* The max time for the erase type-1 cycle-time in ms. */
.eraseTime = 520U,
.eraseTime = 2600U,
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 134000U,
.chipEraseTime = 460000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 340U
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
.flags = CY_SMIF_FLAG_WR_EN,
.flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
/* The data-line selection options for a slave device. */
.dataSelect = CY_SMIF_DATA_SEL0,
/* The base address the memory slave is mapped to in the PSoC memory map.
@ -239,16 +239,16 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
.baseAddress = 0x18000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
.memMappedSize = 0x10000U,
.memMappedSize = 0x4000000U,
/* If this memory device is one of the devices in the dual quad SPI configuration.
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
&S25FL512S_SlaveSlot_0
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512SX4byteaddr_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =
@ -262,3 +262,4 @@ const cy_stc_smif_block_config_t smifBlockConfig =
/* The version of the SMIF driver. */
.minorVersion = CY_SMIF_DRV_VERSION_MINOR
};

25
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -28,22 +28,23 @@
#define CY_SMIF_DEVICE_NUM 1
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;
#endif /*CY_SMIF_MEMCONFIG_H*/

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
View File

@ -24,22 +24,10 @@
#include "cycfg_routing.h"
#include "cy_trigmux.h"
#include "stdbool.h"
#include "cy_device_headers.h"
void init_cycfg_routing(void)
{
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT44, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT1, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |

31
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -42,19 +42,11 @@ void init_cycfg_routing(void);
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_2_pin_0_HSIOM P2_0_DSI_DSI
#define ioss_0_port_2_pin_1_HSIOM P2_1_DSI_DSI
#define ioss_0_port_2_pin_2_HSIOM P2_2_DSI_DSI
#define ioss_0_port_2_pin_3_HSIOM P2_3_DSI_DSI
#define ioss_0_port_2_pin_4_HSIOM P2_4_DSI_DSI
#define ioss_0_port_2_pin_5_HSIOM P2_5_DSI_GPIO
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
@ -63,27 +55,14 @@ void init_cycfg_routing(void);
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#define CYBSP_SDIO_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
#define CYBSP_SDIO_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
#define CYBSP_SDIO_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT4
#define CYBSP_SDIO_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
#define CYBSP_SDIO_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
#define CYBSP_SDIO_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
#define CYBSP_SDIO_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
#define CYBSP_SDIO_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT1
#define cpuss_0_dw0_0_chan_0_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN0
#define cpuss_0_dw0_0_chan_1_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN1
#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1
#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3
#if defined(__cplusplus)
}
#endif

60
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -83,6 +83,46 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
.cco_Freq = 355U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 4U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 30,
@ -523,4 +563,24 @@ void init_cycfg_system(void)
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
#endif //defined (CY_USING_HAL)
}

19
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -28,6 +28,9 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#include "cy_systick.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_gpio.h"
#include "cy_syspm.h"
@ -80,6 +83,22 @@ extern "C" {
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);
#if defined(__cplusplus)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
View File

@ -1,2 +1,4 @@
set SMIF_BANKS {
0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
}

409
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense Normal file
View File

@ -0,0 +1,409 @@
<?xml version="1.0"?>
<Configuration major="2" minor="0">
<!--
File Name: cycfg_capsense.cycapsense
Description:
CapSense middleware configuration
This file should not be modified. It was automatically generated by
CapSense Configurator 2.0.0 build 185
-->
<GeneralProperties>
<Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
<Property id="REGULAR_IIR_RC_N" value="128"/>
<Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
<Property id="PROX_IIR_RC_N" value="128"/>
<Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="REGULAR_IIR_BL_N" value="1"/>
<Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="PROX_IIR_BL_N" value="1"/>
<Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="MULTI_FREQ_SCAN_EN" value="false"/>
<Property id="SENSOR_AUTO_RESET_EN" value="false"/>
<Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
<Property id="VREF_SOURCE" value="SRSS"/>
<Property id="IREF_SOURCE" value="SRSS"/>
<Property id="PROX_TOUCH_COEFF" value="300"/>
<Property id="NUM_CENTROIDS" value="1"/>
</GeneralProperties>
<CsdProperties>
<Property id="CSD_AUTOTUNE" value="HWTH"/>
<Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
<Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
<Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
<Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
<Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
<Property id="CSD_IDAC_MIN" value="20"/>
<Property id="CSD_IDAC_COMP_EN" value="true"/>
<Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
<Property id="CSD_VREF_CUSTOM" value="false"/>
<Property id="CSD_VREF" value="1219"/>
<Property id="CSD_SHIELD_EN" value="false"/>
<Property id="CSD_SHIELD_TANK_EN" value="false"/>
<Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
<Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
<Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_FINE_INIT_TIME" value="10"/>
<Property id="CSD_CALIBRATION_ERROR" value="10"/>
<Property id="CSD_R_CONST" value="1000"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsdProperties>
<CsxProperties>
<Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSX_MAX_FINGERS" value="3"/>
<Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
<Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
<Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
<Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
<Property id="CSX_FINE_INIT_TIME" value="10"/>
<Property id="CSX_CALIBRATION_ERROR" value="20"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsxProperties>
<Widgets>
<Widget id="Button0" type="CSX_BUTTON">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Rx0" kind="Column">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Tx" kind="Row">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
<Widget id="Button1" type="CSX_BUTTON">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Rx0" kind="Column">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Tx" kind="Row">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
<Widget id="LinearSlider0" type="LINEAR_SLIDER">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Sns0" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns1" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns2" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns3" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns4" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
</Widgets>
</Configuration>

63
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi Normal file
View File

@ -0,0 +1,63 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
<Configuration app="QSPI" major="2" minor="0">
<DevicePath>PSoC 6.xml</DevicePath>
<SlotConfigs>
<SlotConfig>
<SlaveSlot>0</SlaveSlot>
<PartNumber>S25FL512S-4byteaddr</PartNumber>
<MemoryMapped>true</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18000000</StartAddress>
<Size>0x4000000</Size>
<EndAddress>0x1BFFFFFF</EndAddress>
<WriteEnable>true</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
<MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>1</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18010000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1801FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>2</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18020000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1802FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>3</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18030000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1803FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
</SlotConfigs>
</Configuration>

299
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -172,36 +172,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[3]" alias="CYBSP_LED_RED" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[4]" alias="CYBSP_BTN2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[1]" alias="CYBSP_LED_BLUE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
@ -262,16 +232,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[13].pin[7]" alias="CYBSP_LED9" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[14].pin[0]" alias="" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -302,96 +262,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[1]" alias="CYBSP_LED_GREEN" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[5]" alias="CYBSP_LED8" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[0]" alias="CYBSP_WIFI_SDIO_D0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[1]" alias="CYBSP_WIFI_SDIO_D1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[2]" alias="CYBSP_WIFI_SDIO_D2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[3]" alias="CYBSP_WIFI_SDIO_D3" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[4]" alias="CYBSP_WIFI_SDIO_CMD" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[5]" alias="CYBSP_WIFI_SDIO_CLK" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[6]" alias="CYBSP_WIFI_WL_REG_ON" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="0"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[7]" alias="CYBSP_WIFI_HOST_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="0"/>
@ -472,26 +342,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
<Param id="initialState" value="1"/>
@ -657,13 +507,13 @@
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[2]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="109"/>
<Block location="peri[0].div_8[3]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="256"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[3]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="256"/>
<Block location="peri[0].div_8[4]" alias="" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="109"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
@ -721,51 +571,6 @@
<Param id="EnableWakeup" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
<Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
<Param id="IrdaLowPower" value="false"/>
<Param id="BaudRate" value="115200"/>
<Param id="Oversample" value="8"/>
<Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
<Param id="DataWidth" value="8"/>
<Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
<Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
<Param id="EnableInputFilter" value="false"/>
<Param id="EnableTxEn" value="false"/>
<Param id="FlowControl" value="false"/>
<Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsTriggerLevel" value="63"/>
<Param id="RxTriggerLevel" value="63"/>
<Param id="TxTriggerLevel" value="63"/>
<Param id="MultiProc" value="false"/>
<Param id="MpRxAddress" value="0"/>
<Param id="MpRxAddressMask" value="255"/>
<Param id="MpRxAcceptAddress" value="false"/>
<Param id="DropOnFrameErr" value="false"/>
<Param id="DropOnParityErr" value="false"/>
<Param id="BreakSignalBits" value="11"/>
<Param id="SmCardRetryOnNack" value="false"/>
<Param id="IrdaPolarity" value="NON_INVERTING"/>
<Param id="inFlash" value="true"/>
<Param id="ApiMode" value="HIGH_LEVEL"/>
<Param id="IntrRxNotEmpty" value="false"/>
<Param id="IntrRxFull" value="false"/>
<Param id="IntrRxOverflow" value="false"/>
<Param id="IntrRxUnderflow" value="false"/>
<Param id="IntrRxFrameErr" value="false"/>
<Param id="IntrRxParityErr" value="false"/>
<Param id="IntrRxBreakDetected" value="false"/>
<Param id="IntrRxTrigger" value="false"/>
<Param id="IntrTxUartDone" value="false"/>
<Param id="IntrTxUartLostArb" value="false"/>
<Param id="IntrTxUartNack" value="false"/>
<Param id="IntrTxEmpty" value="false"/>
<Param id="IntrTxNotFull" value="false"/>
<Param id="IntrTxOverflow" value="false"/>
<Param id="IntrTxUnderflow" value="false"/>
<Param id="IntrTxTrigger" value="false"/>
</Block>
<Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
<Param id="configurator" value="0"/>
<Param id="isrAlignment" value="false"/>
@ -908,7 +713,6 @@
<Param id="dstStopHour" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="udb[0]" alias="CYBSP_SDIO" template="mxs40udbsdio" version="1.0"/>
<Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.0">
<Param id="configurator" value="0"/>
<Param id="UsbCore" value="4"/>
@ -946,22 +750,6 @@
<Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
<Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dw0[0].chan[0].tr_in[0]"/>
<Port name="udb[0].out_p[119]"/>
</Net>
<Net>
<Port name="cpuss[0].dw0[0].chan[1].tr_in[0]"/>
<Port name="udb[0].out_p[117]"/>
</Net>
<Net>
<Port name="cpuss[0].dw1[0].chan[1].tr_in[0]"/>
<Port name="udb[0].out_p[116]"/>
</Net>
<Net>
<Port name="cpuss[0].dw1[0].chan[3].tr_in[0]"/>
<Port name="udb[0].out_p[123]"/>
</Net>
<Net>
<Port name="csd[0].csd[0].clock[0]"/>
<Port name="peri[0].div_8[3].clk[0]"/>
@ -974,70 +762,6 @@
<Port name="ioss[0].port[0].pin[1].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[0].digital_in[0]"/>
<Port name="udb[0].in_p[48]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[0].digital_out[0]"/>
<Port name="udb[0].port_if[16]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[0].oe[0]"/>
<Port name="udb[0].port_oe[16]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[1].digital_in[0]"/>
<Port name="udb[0].in_p[49]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[1].digital_out[0]"/>
<Port name="udb[0].port_if[17]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[1].oe[0]"/>
<Port name="udb[0].port_oe[17]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[2].digital_in[0]"/>
<Port name="udb[0].in_p[50]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[2].digital_out[0]"/>
<Port name="udb[0].port_if[18]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[2].oe[0]"/>
<Port name="udb[0].port_oe[18]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[3].digital_in[0]"/>
<Port name="udb[0].in_p[51]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[3].digital_out[0]"/>
<Port name="udb[0].port_if[19]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[3].oe[0]"/>
<Port name="udb[0].port_oe[19]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[4].digital_in[0]"/>
<Port name="udb[0].in_p[52]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[4].digital_out[0]"/>
<Port name="udb[0].port_if[20]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[4].oe[0]"/>
<Port name="udb[0].port_oe[20]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[5].digital_out[0]"/>
<Port name="udb[0].port_if[21]"/>
</Net>
<Net>
<Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
<Port name="scb[2].uart_rx[0]"/>
@ -1054,14 +778,6 @@
<Port name="ioss[0].port[3].pin[3].digital_in[0]"/>
<Port name="scb[2].uart_cts[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
<Port name="scb[5].uart_rx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
<Port name="scb[5].uart_tx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
<Port name="scb[3].i2c_scl[0]"/>
@ -1106,18 +822,13 @@
<Port name="peri[0].div_16[0].clk[0]"/>
<Port name="usb[0].clock_dev_brs[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[0].clk[0]"/>
<Port name="udb[0].clocks[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[1].clk[0]"/>
<Port name="scb[3].clock[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[2].clk[0]"/>
<Port name="peri[0].div_8[4].clk[0]"/>
<Port name="scb[2].clock[0]"/>
<Port name="scb[5].clock[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_hf[0]"/>

24
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp Normal file
View File

@ -0,0 +1,24 @@
/*******************************************************************************
* File Name: cycfg.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/

40
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -24,18 +24,52 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_BT_UART_CLK_DIV_HW,
.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 35U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 35U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
}

19
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -27,6 +27,9 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
@ -38,9 +41,19 @@ extern "C" {
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_BT_UART_CLK_DIV_NUM 3U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void);

105
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -56,6 +56,14 @@ const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@ -64,51 +72,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
.smartCardRetryOnNack = false,
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
.oversample = 12,
.enableMsbFirst = false,
.dataWidth = 9UL,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
.breakWidth = 11UL,
.dropOnFrameError = false,
.dropOnParityError = false,
.receiverAddress = 0x0UL,
.receiverAddressMask = 0x0UL,
.acceptAddrInFifo = false,
.enableCts = false,
.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rtsRxFifoLevel = 0UL,
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rxFifoTriggerLevel = 63UL,
.rxFifoIntEnableMask = 0UL,
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity = CY_SD_HOST_SDSC;
cy_en_sd_host_card_type_t CYBSP_RADIO_cardType = CY_SD_HOST_NOT_EMMC;
uint32_t CYBSP_RADIO_rca = 0u;
const cy_stc_sd_host_init_config_t CYBSP_RADIO_config =
{
.emmc = false,
.dmaType = CY_SD_HOST_DMA_SDMA,
.enableLedControl = false,
};
cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg =
{
.lowVoltageSignaling = false,
.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
.cardType = &CYBSP_RADIO_cardType,
.rca = &CYBSP_RADIO_rca,
.cardCapacity = &CYBSP_RADIO_cardCapacity,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
@ -116,6 +87,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_obj =
{
.type = CYHAL_RSC_SMIF,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
@ -129,6 +108,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_MCWDT0_obj =
{
.type = CYHAL_RSC_LPTIMER,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
@ -141,15 +128,39 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
.month = CY_RTC_JANUARY,
.year = 0U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_RTC_obj =
{
.type = CYHAL_RSC_RTC,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void)
{
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
#endif //defined (CY_USING_HAL)
}

32
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -29,9 +29,12 @@
#include "cy_sysclk.h"
#include "cy_csd.h"
#include "cy_scb_uart.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_scb_ezi2c.h"
#include "cy_sd_host.h"
#include "cy_smif.h"
#include "cycfg_qspi_memslot.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
@ -81,12 +84,6 @@ extern "C" {
#define CYBSP_CSD_COMM_ENABLED 1U
#define CYBSP_CSD_COMM_HW SCB3
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
#define CYBSP_DEBUG_UART_ENABLED 1U
#define CYBSP_DEBUG_UART_HW SCB5
#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
#define CYBSP_RADIO_ENABLED 1U
#define CYBSP_RADIO_HW SDHC0
#define CYBSP_RADIO_IRQ sdhc_0_interrupt_general_IRQn
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@ -119,16 +116,25 @@ extern "C" {
extern cy_stc_csd_context_t cy_csd_0_context;
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
extern cy_en_sd_host_card_capacity_t CYBSP_RADIO_cardCapacity;
extern cy_en_sd_host_card_type_t CYBSP_RADIO_cardType;
extern uint32_t CYBSP_RADIO_rca;
extern const cy_stc_sd_host_init_config_t CYBSP_RADIO_config;
extern cy_stc_sd_host_sd_card_config_t CYBSP_RADIO_card_cfg;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);

521
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_IN_PORT_NUM,
.channel_num = CYBSP_WCO_IN_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
@ -56,22 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_BTN2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = CYBSP_BTN2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_OUT_PORT_NUM,
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
{
.outVal = 1,
@ -88,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_SS_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SS_PORT_NUM,
.channel_num = CYBSP_QSPI_SS_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config =
{
.outVal = 1,
@ -104,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA3_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config =
{
.outVal = 1,
@ -120,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA2_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config =
{
.outVal = 1,
@ -136,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA1_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config =
{
.outVal = 1,
@ -152,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_DATA0_PORT_NUM,
.channel_num = CYBSP_QSPI_DATA0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
{
.outVal = 1,
@ -168,22 +208,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED_RED_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SCK_PORT_NUM,
.channel_num = CYBSP_QSPI_SCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
@ -200,102 +232,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_WIFI_SDIO_DAT0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_WIFI_SDIO_DAT1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_WIFI_SDIO_DAT2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_WIFI_SDIO_DAT3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_WIFI_SDIO_CMD_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = CYBSP_WIFI_SDIO_CLK_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_TX_PORT_NUM,
.channel_num = CYBSP_CSD_TX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
{
.outVal = 1,
@ -312,6 +256,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_UART_RX_PORT_NUM,
.channel_num = CYBSP_BT_UART_RX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
{
.outVal = 1,
@ -328,6 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_UART_TX_PORT_NUM,
.channel_num = CYBSP_BT_UART_TX_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
{
.outVal = 1,
@ -344,6 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_UART_RTS_PORT_NUM,
.channel_num = CYBSP_BT_UART_RTS_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
{
.outVal = 1,
@ -360,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_UART_CTS_PORT_NUM,
.channel_num = CYBSP_BT_UART_CTS_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
{
.outVal = 1,
@ -376,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_POWER_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_POWER_PORT_NUM,
.channel_num = CYBSP_BT_POWER_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
{
.outVal = 0,
@ -392,6 +376,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_HOST_WAKE_PORT_NUM,
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
{
.outVal = 0,
@ -408,38 +400,14 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = CYBSP_DEBUG_UART_RX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_DEBUG_UART_TX_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_BT_DEVICE_WAKE_PORT_NUM,
.channel_num = CYBSP_BT_DEVICE_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
{
.outVal = 1,
@ -456,6 +424,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_EZI2C_SCL_PORT_NUM,
.channel_num = CYBSP_EZI2C_SCL_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
{
.outVal = 1,
@ -472,6 +448,14 @@ const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_EZI2C_SDA_PORT_NUM,
.channel_num = CYBSP_EZI2C_SDA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
@ -488,6 +472,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
@ -504,6 +496,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
{
.outVal = 1,
@ -520,6 +520,14 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDCK_PORT_NUM,
.channel_num = CYBSP_SWDCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
{
.outVal = 1,
@ -536,6 +544,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINA_PORT_NUM,
.channel_num = CYBSP_CINA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
{
.outVal = 1,
@ -552,6 +568,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CINB_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CINB_PORT_NUM,
.channel_num = CYBSP_CINB_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
{
.outVal = 1,
@ -568,6 +592,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CMOD_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CMOD_PORT_NUM,
.channel_num = CYBSP_CMOD_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
{
.outVal = 1,
@ -584,6 +616,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN0_PORT_NUM,
.channel_num = CYBSP_CSD_BTN0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
{
.outVal = 1,
@ -600,6 +640,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_BTN1_PORT_NUM,
.channel_num = CYBSP_CSD_BTN1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
{
.outVal = 1,
@ -616,6 +664,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD0_PORT_NUM,
.channel_num = CYBSP_CSD_SLD0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
{
.outVal = 1,
@ -632,6 +688,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD1_PORT_NUM,
.channel_num = CYBSP_CSD_SLD1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
{
.outVal = 1,
@ -648,6 +712,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD2_PORT_NUM,
.channel_num = CYBSP_CSD_SLD2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
{
.outVal = 1,
@ -664,6 +736,14 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD3_PORT_NUM,
.channel_num = CYBSP_CSD_SLD3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
{
.outVal = 1,
@ -680,78 +760,159 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_CSD_SLD4_PORT_NUM,
.channel_num = CYBSP_CSD_SLD4_PIN,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void)
{
Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
Cy_GPIO_Pin_Init(CYBSP_BTN2_PORT, CYBSP_BTN2_PIN, &CYBSP_BTN2_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA3_PORT, CYBSP_QSPI_DATA3_PIN, &CYBSP_QSPI_DATA3_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA3_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA2_PORT, CYBSP_QSPI_DATA2_PIN, &CYBSP_QSPI_DATA2_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA2_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA1_PORT, CYBSP_QSPI_DATA1_PIN, &CYBSP_QSPI_DATA1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_DATA0_PORT, CYBSP_QSPI_DATA0_PIN, &CYBSP_QSPI_DATA0_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_DATA0_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_LED_RED_PORT, CYBSP_LED_RED_PIN, &CYBSP_LED_RED_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT0_PORT, CYBSP_WIFI_SDIO_DAT0_PIN, &CYBSP_WIFI_SDIO_DAT0_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT1_PORT, CYBSP_WIFI_SDIO_DAT1_PIN, &CYBSP_WIFI_SDIO_DAT1_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT2_PORT, CYBSP_WIFI_SDIO_DAT2_PIN, &CYBSP_WIFI_SDIO_DAT2_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_DAT3_PORT, CYBSP_WIFI_SDIO_DAT3_PIN, &CYBSP_WIFI_SDIO_DAT3_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CMD_PORT, CYBSP_WIFI_SDIO_CMD_PIN, &CYBSP_WIFI_SDIO_CMD_config);
Cy_GPIO_Pin_Init(CYBSP_WIFI_SDIO_CLK_PORT, CYBSP_WIFI_SDIO_CLK_PIN, &CYBSP_WIFI_SDIO_CLK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RX_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_TX_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_UART_RTS_PORT, CYBSP_BT_UART_RTS_PIN, &CYBSP_BT_UART_RTS_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_RTS_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_POWER_PORT, CYBSP_BT_POWER_PIN, &CYBSP_BT_POWER_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_POWER_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_HOST_WAKE_PORT, CYBSP_BT_HOST_WAKE_PIN, &CYBSP_BT_HOST_WAKE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_BT_DEVICE_WAKE_PORT, CYBSP_BT_DEVICE_WAKE_PIN, &CYBSP_BT_DEVICE_WAKE_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_RX_PORT, CYBSP_DEBUG_UART_RX_PIN, &CYBSP_DEBUG_UART_RX_config);
Cy_GPIO_Pin_Init(CYBSP_DEBUG_UART_TX_PORT, CYBSP_DEBUG_UART_TX_PIN, &CYBSP_DEBUG_UART_TX_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_DEVICE_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SDA_PORT, CYBSP_EZI2C_SDA_PIN, &CYBSP_EZI2C_SDA_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SDA_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
#endif //defined (CY_USING_HAL)
}

619
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -27,6 +27,9 @@
#include "cycfg_notices.h"
#include "cy_gpio.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cycfg_routing.h"
#if defined(__cplusplus)
@ -35,6 +38,7 @@ extern "C" {
#define CYBSP_WCO_IN_ENABLED 1U
#define CYBSP_WCO_IN_PORT GPIO_PRT0
#define CYBSP_WCO_IN_PORT_NUM 0U
#define CYBSP_WCO_IN_PIN 0U
#define CYBSP_WCO_IN_NUM 0U
#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
@ -44,8 +48,21 @@ extern "C" {
#endif
#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_ENABLED 1U
#define CYBSP_WCO_OUT_PORT GPIO_PRT0
#define CYBSP_WCO_OUT_PORT_NUM 0U
#define CYBSP_WCO_OUT_PIN 1U
#define CYBSP_WCO_OUT_NUM 1U
#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
@ -55,19 +72,21 @@ extern "C" {
#endif
#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_BTN2_ENABLED 1U
#define CYBSP_BTN2_PORT GPIO_PRT0
#define CYBSP_BTN2_PIN 4U
#define CYBSP_BTN2_NUM 4U
#define CYBSP_BTN2_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_BTN2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_BTN2_HSIOM ioss_0_port_0_pin_4_HSIOM
#define CYBSP_BTN2_IRQ ioss_interrupts_gpio_0_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_ENABLED 1U
#define CYBSP_QSPI_SS_PORT GPIO_PRT11
#define CYBSP_QSPI_SS_PORT_NUM 11U
#define CYBSP_QSPI_SS_PIN 2U
#define CYBSP_QSPI_SS_NUM 2U
#define CYBSP_QSPI_SS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
@ -77,8 +96,21 @@ extern "C" {
#endif
#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_ENABLED 1U
#define CYBSP_QSPI_DATA3_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA3_PORT_NUM 11U
#define CYBSP_QSPI_DATA3_PIN 3U
#define CYBSP_QSPI_DATA3_NUM 3U
#define CYBSP_QSPI_DATA3_DRIVEMODE CY_GPIO_DM_STRONG
@ -88,8 +120,21 @@ extern "C" {
#endif
#define CYBSP_QSPI_DATA3_HSIOM ioss_0_port_11_pin_3_HSIOM
#define CYBSP_QSPI_DATA3_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_HAL_PORT_PIN P11_3
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_ENABLED 1U
#define CYBSP_QSPI_DATA2_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA2_PORT_NUM 11U
#define CYBSP_QSPI_DATA2_PIN 4U
#define CYBSP_QSPI_DATA2_NUM 4U
#define CYBSP_QSPI_DATA2_DRIVEMODE CY_GPIO_DM_STRONG
@ -99,8 +144,21 @@ extern "C" {
#endif
#define CYBSP_QSPI_DATA2_HSIOM ioss_0_port_11_pin_4_HSIOM
#define CYBSP_QSPI_DATA2_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_HAL_PORT_PIN P11_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_ENABLED 1U
#define CYBSP_QSPI_DATA1_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA1_PORT_NUM 11U
#define CYBSP_QSPI_DATA1_PIN 5U
#define CYBSP_QSPI_DATA1_NUM 5U
#define CYBSP_QSPI_DATA1_DRIVEMODE CY_GPIO_DM_STRONG
@ -110,8 +168,21 @@ extern "C" {
#endif
#define CYBSP_QSPI_DATA1_HSIOM ioss_0_port_11_pin_5_HSIOM
#define CYBSP_QSPI_DATA1_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_HAL_PORT_PIN P11_5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_ENABLED 1U
#define CYBSP_QSPI_DATA0_PORT GPIO_PRT11
#define CYBSP_QSPI_DATA0_PORT_NUM 11U
#define CYBSP_QSPI_DATA0_PIN 6U
#define CYBSP_QSPI_DATA0_NUM 6U
#define CYBSP_QSPI_DATA0_DRIVEMODE CY_GPIO_DM_STRONG
@ -121,8 +192,21 @@ extern "C" {
#endif
#define CYBSP_QSPI_DATA0_HSIOM ioss_0_port_11_pin_6_HSIOM
#define CYBSP_QSPI_DATA0_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_HAL_PORT_PIN P11_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_DATA0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_ENABLED 1U
#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
#define CYBSP_QSPI_SCK_PORT_NUM 11U
#define CYBSP_QSPI_SCK_PIN 7U
#define CYBSP_QSPI_SCK_NUM 7U
#define CYBSP_QSPI_SCK_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
@ -132,19 +216,21 @@ extern "C" {
#endif
#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
#define CYBSP_LED_RED_ENABLED 1U
#define CYBSP_LED_RED_PORT GPIO_PRT13
#define CYBSP_LED_RED_PIN 7U
#define CYBSP_LED_RED_NUM 7U
#define CYBSP_LED_RED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED_RED_INIT_DRIVESTATE 1
#ifndef ioss_0_port_13_pin_7_HSIOM
#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED_RED_HSIOM ioss_0_port_13_pin_7_HSIOM
#define CYBSP_LED_RED_IRQ ioss_interrupts_gpio_13_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_TX_ENABLED 1U
#define CYBSP_CSD_TX_PORT GPIO_PRT1
#define CYBSP_CSD_TX_PORT_NUM 1U
#define CYBSP_CSD_TX_PIN 0U
#define CYBSP_CSD_TX_NUM 0U
#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
@ -154,74 +240,21 @@ extern "C" {
#endif
#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
#define CYBSP_WIFI_SDIO_DAT0_ENABLED 1U
#define CYBSP_WIFI_SDIO_DAT0_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_DAT0_PIN 0U
#define CYBSP_WIFI_SDIO_DAT0_NUM 0U
#define CYBSP_WIFI_SDIO_DAT0_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_DAT0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_0_HSIOM
#define ioss_0_port_2_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_SDIO_DAT0_HSIOM ioss_0_port_2_pin_0_HSIOM
#define CYBSP_WIFI_SDIO_DAT0_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_DAT1_ENABLED 1U
#define CYBSP_WIFI_SDIO_DAT1_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_DAT1_PIN 1U
#define CYBSP_WIFI_SDIO_DAT1_NUM 1U
#define CYBSP_WIFI_SDIO_DAT1_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_DAT1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_1_HSIOM
#define ioss_0_port_2_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_SDIO_DAT1_HSIOM ioss_0_port_2_pin_1_HSIOM
#define CYBSP_WIFI_SDIO_DAT1_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_DAT2_ENABLED 1U
#define CYBSP_WIFI_SDIO_DAT2_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_DAT2_PIN 2U
#define CYBSP_WIFI_SDIO_DAT2_NUM 2U
#define CYBSP_WIFI_SDIO_DAT2_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_DAT2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_2_HSIOM
#define ioss_0_port_2_pin_2_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_SDIO_DAT2_HSIOM ioss_0_port_2_pin_2_HSIOM
#define CYBSP_WIFI_SDIO_DAT2_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_DAT3_ENABLED 1U
#define CYBSP_WIFI_SDIO_DAT3_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_DAT3_PIN 3U
#define CYBSP_WIFI_SDIO_DAT3_NUM 3U
#define CYBSP_WIFI_SDIO_DAT3_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_DAT3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_3_HSIOM
#define ioss_0_port_2_pin_3_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_SDIO_DAT3_HSIOM ioss_0_port_2_pin_3_HSIOM
#define CYBSP_WIFI_SDIO_DAT3_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_CMD_ENABLED 1U
#define CYBSP_WIFI_SDIO_CMD_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_CMD_PIN 4U
#define CYBSP_WIFI_SDIO_CMD_NUM 4U
#define CYBSP_WIFI_SDIO_CMD_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_CMD_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_4_HSIOM
#define ioss_0_port_2_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_SDIO_CMD_HSIOM ioss_0_port_2_pin_4_HSIOM
#define CYBSP_WIFI_SDIO_CMD_IRQ ioss_interrupts_gpio_2_IRQn
#define CYBSP_WIFI_SDIO_CLK_ENABLED 1U
#define CYBSP_WIFI_SDIO_CLK_PORT GPIO_PRT2
#define CYBSP_WIFI_SDIO_CLK_PIN 5U
#define CYBSP_WIFI_SDIO_CLK_NUM 5U
#define CYBSP_WIFI_SDIO_CLK_DRIVEMODE CY_GPIO_DM_STRONG
#define CYBSP_WIFI_SDIO_CLK_INIT_DRIVESTATE 1
#ifndef ioss_0_port_2_pin_5_HSIOM
#define ioss_0_port_2_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_SDIO_CLK_HSIOM ioss_0_port_2_pin_5_HSIOM
#define CYBSP_WIFI_SDIO_CLK_IRQ ioss_interrupts_gpio_2_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_PORT_PIN P1_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_UART_RX_ENABLED 1U
#define CYBSP_BT_UART_RX_PORT GPIO_PRT3
#define CYBSP_BT_UART_RX_PORT_NUM 3U
#define CYBSP_BT_UART_RX_PIN 0U
#define CYBSP_BT_UART_RX_NUM 0U
#define CYBSP_BT_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
@ -231,8 +264,21 @@ extern "C" {
#endif
#define CYBSP_BT_UART_RX_HSIOM ioss_0_port_3_pin_0_HSIOM
#define CYBSP_BT_UART_RX_IRQ ioss_interrupts_gpio_3_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_RX_HAL_PORT_PIN P3_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_UART_TX_ENABLED 1U
#define CYBSP_BT_UART_TX_PORT GPIO_PRT3
#define CYBSP_BT_UART_TX_PORT_NUM 3U
#define CYBSP_BT_UART_TX_PIN 1U
#define CYBSP_BT_UART_TX_NUM 1U
#define CYBSP_BT_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
@ -242,8 +288,21 @@ extern "C" {
#endif
#define CYBSP_BT_UART_TX_HSIOM ioss_0_port_3_pin_1_HSIOM
#define CYBSP_BT_UART_TX_IRQ ioss_interrupts_gpio_3_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_TX_HAL_PORT_PIN P3_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_UART_RTS_ENABLED 1U
#define CYBSP_BT_UART_RTS_PORT GPIO_PRT3
#define CYBSP_BT_UART_RTS_PORT_NUM 3U
#define CYBSP_BT_UART_RTS_PIN 2U
#define CYBSP_BT_UART_RTS_NUM 2U
#define CYBSP_BT_UART_RTS_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
@ -253,8 +312,21 @@ extern "C" {
#endif
#define CYBSP_BT_UART_RTS_HSIOM ioss_0_port_3_pin_2_HSIOM
#define CYBSP_BT_UART_RTS_IRQ ioss_interrupts_gpio_3_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_RTS_HAL_PORT_PIN P3_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_RTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_RTS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_RTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_UART_CTS_ENABLED 1U
#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
#define CYBSP_BT_UART_CTS_PORT_NUM 3U
#define CYBSP_BT_UART_CTS_PIN 3U
#define CYBSP_BT_UART_CTS_NUM 3U
#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_HIGHZ
@ -264,8 +336,21 @@ extern "C" {
#endif
#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_3_HSIOM
#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_3
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_POWER_ENABLED 1U
#define CYBSP_BT_POWER_PORT GPIO_PRT3
#define CYBSP_BT_POWER_PORT_NUM 3U
#define CYBSP_BT_POWER_PIN 4U
#define CYBSP_BT_POWER_NUM 4U
#define CYBSP_BT_POWER_DRIVEMODE CY_GPIO_DM_OD_DRIVESHIGH_IN_OFF
@ -275,8 +360,21 @@ extern "C" {
#endif
#define CYBSP_BT_POWER_HSIOM ioss_0_port_3_pin_4_HSIOM
#define CYBSP_BT_POWER_IRQ ioss_interrupts_gpio_3_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_POWER_HAL_PORT_PIN P3_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_POWER_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_POWER_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_POWER_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_ENABLED 1U
#define CYBSP_BT_HOST_WAKE_PORT GPIO_PRT3
#define CYBSP_BT_HOST_WAKE_PORT_NUM 3U
#define CYBSP_BT_HOST_WAKE_PIN 5U
#define CYBSP_BT_HOST_WAKE_NUM 5U
#define CYBSP_BT_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
@ -286,8 +384,21 @@ extern "C" {
#endif
#define CYBSP_BT_HOST_WAKE_HSIOM ioss_0_port_3_pin_5_HSIOM
#define CYBSP_BT_HOST_WAKE_IRQ ioss_interrupts_gpio_3_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_PORT_PIN P3_5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_ENABLED 1U
#define CYBSP_BT_DEVICE_WAKE_PORT GPIO_PRT4
#define CYBSP_BT_DEVICE_WAKE_PORT_NUM 4U
#define CYBSP_BT_DEVICE_WAKE_PIN 0U
#define CYBSP_BT_DEVICE_WAKE_NUM 0U
#define CYBSP_BT_DEVICE_WAKE_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
@ -297,30 +408,21 @@ extern "C" {
#endif
#define CYBSP_BT_DEVICE_WAKE_HSIOM ioss_0_port_4_pin_0_HSIOM
#define CYBSP_BT_DEVICE_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
#define CYBSP_DEBUG_UART_RX_ENABLED 1U
#define CYBSP_DEBUG_UART_RX_PORT GPIO_PRT5
#define CYBSP_DEBUG_UART_RX_PIN 0U
#define CYBSP_DEBUG_UART_RX_NUM 0U
#define CYBSP_DEBUG_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
#define CYBSP_DEBUG_UART_RX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_0_HSIOM
#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DEBUG_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
#define CYBSP_DEBUG_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
#define CYBSP_DEBUG_UART_TX_ENABLED 1U
#define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
#define CYBSP_DEBUG_UART_TX_PIN 1U
#define CYBSP_DEBUG_UART_TX_NUM 1U
#define CYBSP_DEBUG_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_DEBUG_UART_TX_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_1_HSIOM
#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_DEBUG_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
#define CYBSP_DEBUG_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_HAL_PORT_PIN P4_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_BT_DEVICE_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_ENABLED 1U
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
#define CYBSP_EZI2C_SCL_PORT_NUM 6U
#define CYBSP_EZI2C_SCL_PIN 0U
#define CYBSP_EZI2C_SCL_NUM 0U
#define CYBSP_EZI2C_SCL_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
@ -330,8 +432,21 @@ extern "C" {
#endif
#define CYBSP_EZI2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
#define CYBSP_EZI2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_HAL_PORT_PIN P6_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
#endif //defined (CY_USING_HAL)
#define CYBSP_EZI2C_SDA_ENABLED 1U
#define CYBSP_EZI2C_SDA_PORT GPIO_PRT6
#define CYBSP_EZI2C_SDA_PORT_NUM 6U
#define CYBSP_EZI2C_SDA_PIN 1U
#define CYBSP_EZI2C_SDA_NUM 1U
#define CYBSP_EZI2C_SDA_DRIVEMODE CY_GPIO_DM_OD_DRIVESLOW
@ -341,8 +456,21 @@ extern "C" {
#endif
#define CYBSP_EZI2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
#define CYBSP_EZI2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SDA_HAL_PORT_PIN P6_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_EZI2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
#endif //defined (CY_USING_HAL)
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT6
#define CYBSP_SWO_PORT_NUM 6U
#define CYBSP_SWO_PIN 4U
#define CYBSP_SWO_NUM 4U
#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
@ -352,8 +480,21 @@ extern "C" {
#endif
#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_PORT_PIN P6_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_SWDIO_ENABLED 1U
#define CYBSP_SWDIO_PORT GPIO_PRT6
#define CYBSP_SWDIO_PORT_NUM 6U
#define CYBSP_SWDIO_PIN 6U
#define CYBSP_SWDIO_NUM 6U
#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
@ -363,8 +504,21 @@ extern "C" {
#endif
#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
#endif //defined (CY_USING_HAL)
#define CYBSP_SWDCK_ENABLED 1U
#define CYBSP_SWDCK_PORT GPIO_PRT6
#define CYBSP_SWDCK_PORT_NUM 6U
#define CYBSP_SWDCK_PIN 7U
#define CYBSP_SWDCK_NUM 7U
#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
@ -374,8 +528,21 @@ extern "C" {
#endif
#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
#endif //defined (CY_USING_HAL)
#define CYBSP_CINA_ENABLED 1U
#define CYBSP_CINA_PORT GPIO_PRT7
#define CYBSP_CINA_PORT_NUM 7U
#define CYBSP_CINA_PIN 1U
#define CYBSP_CINA_NUM 1U
#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
@ -385,8 +552,21 @@ extern "C" {
#endif
#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_PORT_PIN P7_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CINB_ENABLED 1U
#define CYBSP_CINB_PORT GPIO_PRT7
#define CYBSP_CINB_PORT_NUM 7U
#define CYBSP_CINB_PIN 2U
#define CYBSP_CINB_NUM 2U
#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
@ -396,8 +576,21 @@ extern "C" {
#endif
#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_PORT_PIN P7_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CMOD_ENABLED 1U
#define CYBSP_CMOD_PORT GPIO_PRT7
#define CYBSP_CMOD_PORT_NUM 7U
#define CYBSP_CMOD_PIN 7U
#define CYBSP_CMOD_NUM 7U
#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
@ -407,8 +600,21 @@ extern "C" {
#endif
#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_PORT_PIN P7_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_ENABLED 1U
#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
#define CYBSP_CSD_BTN0_PORT_NUM 8U
#define CYBSP_CSD_BTN0_PIN 1U
#define CYBSP_CSD_BTN0_NUM 1U
#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
@ -418,8 +624,21 @@ extern "C" {
#endif
#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_ENABLED 1U
#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
#define CYBSP_CSD_BTN1_PORT_NUM 8U
#define CYBSP_CSD_BTN1_PIN 2U
#define CYBSP_CSD_BTN1_NUM 2U
#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
@ -429,8 +648,21 @@ extern "C" {
#endif
#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_ENABLED 1U
#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
#define CYBSP_CSD_SLD0_PORT_NUM 8U
#define CYBSP_CSD_SLD0_PIN 3U
#define CYBSP_CSD_SLD0_NUM 3U
#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
@ -440,8 +672,21 @@ extern "C" {
#endif
#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_ENABLED 1U
#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
#define CYBSP_CSD_SLD1_PORT_NUM 8U
#define CYBSP_CSD_SLD1_PIN 4U
#define CYBSP_CSD_SLD1_NUM 4U
#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
@ -451,8 +696,21 @@ extern "C" {
#endif
#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_ENABLED 1U
#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
#define CYBSP_CSD_SLD2_PORT_NUM 8U
#define CYBSP_CSD_SLD2_PIN 5U
#define CYBSP_CSD_SLD2_NUM 5U
#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
@ -462,8 +720,21 @@ extern "C" {
#endif
#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_ENABLED 1U
#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
#define CYBSP_CSD_SLD3_PORT_NUM 8U
#define CYBSP_CSD_SLD3_PIN 6U
#define CYBSP_CSD_SLD3_NUM 6U
#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
@ -473,8 +744,21 @@ extern "C" {
#endif
#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_ENABLED 1U
#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
#define CYBSP_CSD_SLD4_PORT_NUM 8U
#define CYBSP_CSD_SLD4_PIN 7U
#define CYBSP_CSD_SLD4_NUM 7U
#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
@ -484,48 +768,143 @@ extern "C" {
#endif
#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
extern const cy_stc_gpio_pin_config_t CYBSP_BTN2_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA3_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA3_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA2_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA2_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_DATA0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_DATA0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED_RED_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT2_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_DAT3_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CMD_config;
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_SDIO_CLK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_RX_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_TX_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_TX_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RTS_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_RTS_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_POWER_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_POWER_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_BT_DEVICE_WAKE_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_RX_config;
extern const cy_stc_gpio_pin_config_t CYBSP_DEBUG_UART_TX_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_DEVICE_WAKE_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SDA_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_EZI2C_SDA_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CINA_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CINB_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void);

71
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -24,7 +24,7 @@
#include "cycfg_qspi_memslot.h"
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xECU,
@ -37,12 +37,12 @@ cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readCmd =
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 8U,
.dummyCycles = 4U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeEnCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
@ -60,7 +60,7 @@ cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeDisCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
@ -78,10 +78,10 @@ cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_eraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x21U,
.command = 0xDCU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -96,7 +96,7 @@ cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_chipEraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
@ -114,10 +114,10 @@ cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_programCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x12U,
.command = 0x34U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -125,14 +125,14 @@ cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_programCmd =
/* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
.mode = 0xFFFFFFFFU,
/* The width of the mode command transfer. */
.modeWidth = CY_SMIF_WIDTH_SINGLE,
.modeWidth = CY_SMIF_WIDTH_QUAD,
/* The number of dummy cycles. A zero value suggests no dummy cycles. */
.dummyCycles = 0U,
/* The width of the data transfer. */
.dataWidth = CY_SMIF_WIDTH_SINGLE
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
@ -150,7 +150,7 @@ cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegWipCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
@ -168,7 +168,7 @@ cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
@ -186,52 +186,52 @@ cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_0 =
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = &S25HL512T_SlaveSlot_0_readCmd,
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = &S25HL512T_SlaveSlot_0_writeEnCmd,
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = &S25HL512T_SlaveSlot_0_writeDisCmd,
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = &S25HL512T_SlaveSlot_0_eraseCmd,
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x0001000U,
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = &S25HL512T_SlaveSlot_0_chipEraseCmd,
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = &S25HL512T_SlaveSlot_0_programCmd,
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x0000100U,
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = &S25HL512T_SlaveSlot_0_readStsRegQeCmd,
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = &S25HL512T_SlaveSlot_0_readStsRegWipCmd,
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = &S25HL512T_SlaveSlot_0_writeStsRegQeCmd,
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
.stsRegQuadEnableMask = 0x02U,
/* The max time for the erase type-1 cycle-time in ms. */
.eraseTime = 42U,
.eraseTime = 2600U,
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 201000U,
.chipEraseTime = 460000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 418U
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_0 =
const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
.flags = CY_SMIF_FLAG_WR_EN,
.flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
/* The data-line selection options for a slave device. */
.dataSelect = CY_SMIF_DATA_SEL0,
/* The base address the memory slave is mapped to in the PSoC memory map.
@ -239,16 +239,16 @@ const cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_0 =
.baseAddress = 0x18000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
.memMappedSize = 0x10000U,
.memMappedSize = 0x4000000U,
/* If this memory device is one of the devices in the dual quad SPI configuration.
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = &deviceCfg_S25HL512T_SlaveSlot_0
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
&S25HL512T_SlaveSlot_0
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512SX4byteaddr_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =
@ -262,3 +262,4 @@ const cy_stc_smif_block_config_t smifBlockConfig =
/* The version of the SMIF driver. */
.minorVersion = CY_SMIF_DRV_VERSION_MINOR
};

25
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -28,22 +28,23 @@
#define CY_SMIF_DEVICE_NUM 1
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeEnCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeDisCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_eraseCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_chipEraseCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_programCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegQeCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_readStsRegWipCmd;
extern cy_stc_smif_mem_cmd_t S25HL512T_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25HL512T_SlaveSlot_0;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25HL512T_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;
#endif /*CY_SMIF_MEMCONFIG_H*/

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -40,34 +40,26 @@ void init_cycfg_routing(void);
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_2_pin_0_HSIOM P2_0_SDHC0_CARD_DAT_3TO00
#define ioss_0_port_2_pin_1_HSIOM P2_1_SDHC0_CARD_DAT_3TO01
#define ioss_0_port_2_pin_2_HSIOM P2_2_SDHC0_CARD_DAT_3TO02
#define ioss_0_port_2_pin_3_HSIOM P2_3_SDHC0_CARD_DAT_3TO03
#define ioss_0_port_2_pin_4_HSIOM P2_4_SDHC0_CARD_CMD
#define ioss_0_port_2_pin_5_HSIOM P2_5_SDHC0_CLK_CARD
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
#define ioss_0_port_3_pin_3_HSIOM P3_3_SCB2_UART_CTS
#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#if defined(__cplusplus)
}

101
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -38,6 +38,9 @@
#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL
#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2
#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
@ -57,6 +60,7 @@
#define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
#define CY_CFG_SYSCLK_PLL1_ENABLED 1
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
#define CY_CFG_SYSCLK_WCO_ENABLED 1
#define CY_CFG_PWR_ENABLED 1
@ -79,6 +83,62 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
.cco_Freq = 355U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 4U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 5U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
{
.feedbackDiv = 30,
.referenceDiv = 1,
.outputDiv = 5,
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
@ -115,6 +175,12 @@ __STATIC_INLINE void Cy_SysClk_ClkHf2Init()
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
}
__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
}
__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
{
Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
@ -160,6 +226,17 @@ __STATIC_INLINE void Cy_SysClk_ClkPeriInit()
{
Cy_SysClk_ClkPeriSetDivider(1U);
}
__STATIC_INLINE void Cy_SysClk_Pll1Init()
{
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
{
Cy_SysClk_ClkSlowSetDivider(0U);
@ -487,4 +564,28 @@ void init_cycfg_system(void)
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj);
#endif //defined (CY_USING_HAL)
}

25
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -27,6 +27,9 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_gpio.h"
#include "cy_syspm.h"
@ -43,6 +46,8 @@ extern "C" {
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define srss_0_clock_0_hfclk_2_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF2 2UL
#define srss_0_clock_0_hfclk_3_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF3 3UL
#define srss_0_clock_0_hfclk_4_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF4 4UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
@ -56,6 +61,7 @@ extern "C" {
#define srss_0_clock_0_pathmux_4_ENABLED 1U
#define srss_0_clock_0_pathmux_5_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
#define srss_0_clock_0_pll_1_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
#define srss_0_clock_0_wco_0_ENABLED 1U
#define srss_0_power_0_ENABLED 1U
@ -75,6 +81,25 @@ extern "C" {
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);
#if defined(__cplusplus)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
View File

@ -1,2 +1,4 @@
set SMIF_BANKS {
0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
}

78
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense Normal file
View File

@ -0,0 +1,78 @@
<?xml version="1.0"?>
<Configuration major="2" minor="0">
<!--
File Name: cycfg_capsense.cycapsense
Description:
CapSense middleware configuration
This file should not be modified. It was automatically generated by
CapSense Configurator 2.0.0 build 351
-->
<GeneralProperties>
<Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
<Property id="REGULAR_IIR_RC_N" value="128"/>
<Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
<Property id="PROX_IIR_RC_N" value="128"/>
<Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="REGULAR_IIR_BL_N" value="1"/>
<Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="PROX_IIR_BL_N" value="1"/>
<Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="MULTI_FREQ_SCAN_EN" value="false"/>
<Property id="SENSOR_AUTO_RESET_EN" value="false"/>
<Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
<Property id="VREF_SOURCE" value="SRSS"/>
<Property id="IREF_SOURCE" value="SRSS"/>
<Property id="PROX_TOUCH_COEFF" value="300"/>
<Property id="NUM_CENTROIDS" value="1"/>
</GeneralProperties>
<CsdProperties>
<Property id="CSD_AUTOTUNE" value="HWTH"/>
<Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
<Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
<Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
<Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
<Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
<Property id="CSD_IDAC_MIN" value="20"/>
<Property id="CSD_IDAC_COMP_EN" value="true"/>
<Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
<Property id="CSD_VREF_CUSTOM" value="false"/>
<Property id="CSD_VREF" value="1219"/>
<Property id="CSD_SHIELD_EN" value="false"/>
<Property id="CSD_SHIELD_TANK_EN" value="false"/>
<Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
<Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
<Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_FINE_INIT_TIME" value="10"/>
<Property id="CSD_CALIBRATION_ERROR" value="10"/>
<Property id="CSD_R_CONST" value="1000"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsdProperties>
<CsxProperties>
<Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSX_MAX_FINGERS" value="3"/>
<Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
<Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
<Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
<Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
<Property id="CSX_FINE_INIT_TIME" value="10"/>
<Property id="CSX_CALIBRATION_ERROR" value="20"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsxProperties>
<Widgets/>
</Configuration>

63
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi Normal file
View File

@ -0,0 +1,63 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
<Configuration app="QSPI" major="2" minor="0">
<DevicePath>PSoC 6.xml</DevicePath>
<SlotConfigs>
<SlotConfig>
<SlaveSlot>0</SlaveSlot>
<PartNumber>S25FL512S-4byteaddr</PartNumber>
<MemoryMapped>true</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18000000</StartAddress>
<Size>0x4000000</Size>
<EndAddress>0x1BFFFFFF</EndAddress>
<WriteEnable>true</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
<MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>1</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18010000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1801FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>2</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18020000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1802FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>3</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18030000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1803FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
</SlotConfigs>
</Configuration>

212
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -8,7 +8,7 @@
<Param id="dbgMode" value="SWD"/>
<Param id="traceEnable" value="false"/>
</Block>
<Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="1.1">
<Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
<Param id="CapSenseEnable" value="true"/>
<Param id="CapSenseCore" value="4"/>
<Param id="SensorCount" value="12"/>
@ -39,10 +39,8 @@
<Param id="csdInitTime" value="25"/>
<Param id="inFlash" value="true"/>
<Param id="CsdIdacEnable" value="false"/>
<Param id="CsdIdacAEnable" value="false"/>
<Param id="IdacAbusOnly" value="false"/>
<Param id="CsdIdacBEnable" value="false"/>
<Param id="IdacBbusOnly" value="false"/>
<Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
<Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
<Param id="csdIdacInitTime" value="25"/>
<Param id="idacInFlash" value="true"/>
</Block>
@ -66,16 +64,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[4]" alias="CYBSP_BTN2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
@ -136,16 +124,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[13].pin[7]" alias="CYBSP_LED_RED" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -156,66 +134,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[0]" alias="CYBSP_WIFI_SDIO_DAT0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[1]" alias="CYBSP_WIFI_SDIO_DAT1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[2]" alias="CYBSP_WIFI_SDIO_DAT2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[3]" alias="CYBSP_WIFI_SDIO_DAT3" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[4]" alias="CYBSP_WIFI_SDIO_CMD" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[5]" alias="CYBSP_WIFI_SDIO_CLK" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[3].pin[0]" alias="CYBSP_BT_UART_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
@ -286,26 +204,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
<Param id="initialState" value="1"/>
@ -466,7 +364,7 @@
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[2]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Block location="peri[0].div_8[3]" alias="CYBSP_BT_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="36"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
@ -525,59 +423,6 @@
<Param id="EnableWakeup" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
<Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
<Param id="IrdaLowPower" value="false"/>
<Param id="BaudRate" value="115200"/>
<Param id="Oversample" value="12"/>
<Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
<Param id="DataWidth" value="9"/>
<Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
<Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
<Param id="EnableInputFilter" value="false"/>
<Param id="EnableTxEn" value="false"/>
<Param id="FlowControl" value="false"/>
<Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_HIGH"/>
<Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsTriggerLevel" value="63"/>
<Param id="RxTriggerLevel" value="63"/>
<Param id="TxTriggerLevel" value="63"/>
<Param id="MultiProc" value="false"/>
<Param id="MpRxAddress" value="0"/>
<Param id="MpRxAddressMask" value="255"/>
<Param id="MpRxAcceptAddress" value="false"/>
<Param id="DropOnFrameErr" value="false"/>
<Param id="DropOnParityErr" value="false"/>
<Param id="BreakSignalBits" value="11"/>
<Param id="SmCardRetryOnNack" value="false"/>
<Param id="IrdaPolarity" value="NON_INVERTING"/>
<Param id="inFlash" value="true"/>
<Param id="ApiMode" value="HIGH_LEVEL"/>
<Param id="IntrRxNotEmpty" value="false"/>
<Param id="IntrRxFull" value="false"/>
<Param id="IntrRxOverflow" value="false"/>
<Param id="IntrRxUnderflow" value="false"/>
<Param id="IntrRxFrameErr" value="false"/>
<Param id="IntrRxParityErr" value="false"/>
<Param id="IntrRxBreakDetected" value="false"/>
<Param id="IntrRxTrigger" value="false"/>
<Param id="IntrTxUartDone" value="false"/>
<Param id="IntrTxUartLostArb" value="false"/>
<Param id="IntrTxUartNack" value="false"/>
<Param id="IntrTxEmpty" value="false"/>
<Param id="IntrTxNotFull" value="false"/>
<Param id="IntrTxOverflow" value="false"/>
<Param id="IntrTxUnderflow" value="false"/>
<Param id="IntrTxTrigger" value="false"/>
</Block>
<Block location="sdhc[0]" alias="CYBSP_RADIO" template="mxs40sdhost" version="1.0">
<Param id="cardType" value="nonEmmc"/>
<Param id="dmaType" value="CY_SD_HOST_DMA_SDMA"/>
<Param id="enableLedControl" value="false"/>
<Param id="busWidth" value="CY_SD_HOST_BUS_WIDTH_4_BIT"/>
<Param id="lowVoltageSignaling" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
<Param id="configurator" value=""/>
<Param id="isrAlignment" value="false"/>
@ -607,6 +452,10 @@
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="2"/>
</Block>
<Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="2"/>
<Param id="divider" value="1"/>
</Block>
<Block location="srss[0].clock[0].hfclk[4]" alias="" template="mxs40hfclk" version="1.1">
<Param id="sourceClockNumber" value="0"/>
<Param id="divider" value="1"/>
@ -641,6 +490,12 @@
<Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
<Param id="divider" value="2"/>
</Block>
<Block location="srss[0].clock[0].pll[1]" alias="" template="mxs40pll" version="1.0">
<Param id="lowFrequencyMode" value="false"/>
<Param id="configuration" value="auto"/>
<Param id="desiredFrequency" value="48.000"/>
<Param id="optimization" value="MinPower"/>
</Block>
<Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
<Param id="divider" value="1"/>
</Block>
@ -732,30 +587,6 @@
<Port name="ioss[0].port[0].pin[1].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[0].digital_inout[0]"/>
<Port name="sdhc[0].card_dat_3to0[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[1].digital_inout[0]"/>
<Port name="sdhc[0].card_dat_3to0[1]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[2].digital_inout[0]"/>
<Port name="sdhc[0].card_dat_3to0[2]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[3].digital_inout[0]"/>
<Port name="sdhc[0].card_dat_3to0[3]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[4].digital_inout[0]"/>
<Port name="sdhc[0].card_cmd[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[5].digital_out[0]"/>
<Port name="sdhc[0].clk_card[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
<Port name="scb[2].uart_rx[0]"/>
@ -772,14 +603,6 @@
<Port name="ioss[0].port[3].pin[3].digital_in[0]"/>
<Port name="scb[2].uart_cts[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
<Port name="scb[5].uart_rx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
<Port name="scb[5].uart_tx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
<Port name="scb[3].i2c_scl[0]"/>
@ -817,13 +640,8 @@
<Port name="scb[3].clock[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[2].clk[0]"/>
<Port name="peri[0].div_8[3].clk[0]"/>
<Port name="scb[2].clock[0]"/>
<Port name="scb[5].clock[0]"/>
</Net>
<Net>
<Port name="sdhc[0].clk_hf[0]"/>
<Port name="srss[0].clock[0].hfclk[4].root_clk[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_hf[0]"/>

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
View File

@ -28,6 +28,7 @@ void init_cycfg_all(void)
{
init_cycfg_system();
init_cycfg_clocks();
init_cycfg_dmas();
init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();

24
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp Normal file
View File

@ -0,0 +1,24 @@
/*******************************************************************************
* File Name: cycfg.timestamp
*
* Description:
* Sentinel file for determining if generated source is up to date.
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/

84
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -24,34 +24,112 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USB_UART_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_USB_UART_CLK_DIV_HW,
.channel_num = CYBSP_USB_UART_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SDIO_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_SDIO_CLK_DIV_HW,
.channel_num = CYBSP_SDIO_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t peri_0_div_8_3_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_div_8_3_HW,
.channel_num = peri_0_div_8_3_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_CSD_CLK_DIV_HW,
.channel_num = CYBSP_CSD_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SPI_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_SPI_CLK_DIV_HW,
.channel_num = CYBSP_SPI_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WL_UART_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_WL_UART_CLK_DIV_HW,
.channel_num = CYBSP_WL_UART_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USB_UART_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SDIO_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&peri_0_div_8_3_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 5U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 5U, 6U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 5U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SPI_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 6U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 6U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 6U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WL_UART_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
}

31
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -27,6 +27,9 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
@ -41,9 +44,9 @@ extern "C" {
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
#define peri_0_div_8_3_ENABLED 1U
#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_3_NUM 3U
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_CLK_DIV_NUM 4U
@ -54,6 +57,28 @@ extern "C" {
#define CYBSP_WL_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_WL_UART_CLK_DIV_NUM 6U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_UART_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SDIO_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t peri_0_div_8_3_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SPI_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WL_UART_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void);
#if defined(__cplusplus)

51
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
View File

@ -62,6 +62,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig =
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 0U,
.channel_num = cpuss_0_dw0_0_chan_0_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_16CYC,
@ -100,6 +108,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig =
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 0U,
.channel_num = cpuss_0_dw0_0_chan_1_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_4CYC,
@ -138,6 +154,14 @@ const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig =
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 1U,
.channel_num = cpuss_0_dw1_0_chan_1_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_IM,
@ -176,4 +200,31 @@ const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig =
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 1U,
.channel_num = cpuss_0_dw1_0_chan_3_CHANNEL,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_dmas(void)
{
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj);
#endif //defined (CY_USING_HAL)
}

24
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
View File

@ -27,6 +27,9 @@
#include "cycfg_notices.h"
#include "cy_dma.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
@ -34,34 +37,47 @@ extern "C" {
#define cpuss_0_dw0_0_chan_0_ENABLED 1U
#define cpuss_0_dw0_0_chan_0_HW DW0
#define cpuss_0_dw0_0_chan_0_CHANNEL 0
#define cpuss_0_dw0_0_chan_0_CHANNEL 0U
#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
#define cpuss_0_dw0_0_chan_1_ENABLED 1U
#define cpuss_0_dw0_0_chan_1_HW DW0
#define cpuss_0_dw0_0_chan_1_CHANNEL 1
#define cpuss_0_dw0_0_chan_1_CHANNEL 1U
#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
#define cpuss_0_dw1_0_chan_1_ENABLED 1U
#define cpuss_0_dw1_0_chan_1_HW DW1
#define cpuss_0_dw1_0_chan_1_CHANNEL 1
#define cpuss_0_dw1_0_chan_1_CHANNEL 1U
#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
#define cpuss_0_dw1_0_chan_3_ENABLED 1U
#define cpuss_0_dw1_0_chan_3_HW DW1
#define cpuss_0_dw1_0_chan_3_CHANNEL 3
#define cpuss_0_dw1_0_chan_3_CHANNEL 3U
#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_dmas(void);
#if defined(__cplusplus)
}

121
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -66,6 +66,14 @@ const cy_stc_scb_spi_config_t CYBSP_SPI_config =
.txFifoIntEnableMask = 0UL,
.masterSlaveIntEnableMask = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SPI_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 1U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
@ -94,6 +102,14 @@ const cy_stc_scb_uart_config_t CYBSP_BT_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@ -102,6 +118,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
.enableWakeFromSleep = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_scb_uart_config_t CYBSP_WL_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
@ -130,34 +154,14 @@ const cy_stc_scb_uart_config_t CYBSP_WL_UART_config =
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
.smartCardRetryOnNack = false,
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
.oversample = 8,
.enableMsbFirst = false,
.dataWidth = 8UL,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
.breakWidth = 11UL,
.dropOnFrameError = false,
.dropOnParityError = false,
.receiverAddress = 0x0UL,
.receiverAddressMask = 0x0UL,
.acceptAddrInFifo = false,
.enableCts = false,
.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rtsRxFifoLevel = 0UL,
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rxFifoTriggerLevel = 63UL,
.rxFifoIntEnableMask = 0UL,
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WL_UART_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 5U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
@ -165,6 +169,14 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_obj =
{
.type = CYHAL_RSC_SMIF,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
{
.c0Match = 32768U,
@ -178,6 +190,14 @@ const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
.c0c1Cascade = true,
.c1c2Cascade = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_MCWDT0_obj =
{
.type = CYHAL_RSC_LPTIMER,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_rtc_config_t CYBSP_RTC_config =
{
.sec = 0U,
@ -190,6 +210,14 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
.month = CY_RTC_JANUARY,
.year = 0U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_RTC_obj =
{
.type = CYHAL_RSC_RTC,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
{
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
@ -207,6 +235,14 @@ const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
.enableLpm = false,
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USBUART_obj =
{
.type = CYHAL_RSC_USB,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void)
@ -214,16 +250,39 @@ void init_cycfg_peripherals(void)
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 4U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, CY_SYSCLK_DIV_8_BIT, 5U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SPI_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_BT_UART_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 6U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WL_UART_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB6_CLOCK, CY_SYSCLK_DIV_8_BIT, 2U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0u);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_MCWDT0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
#endif //defined (CY_USING_HAL)
}

33
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -29,9 +29,13 @@
#include "cy_sysclk.h"
#include "cy_csd.h"
#include "cy_scb_spi.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_scb_uart.h"
#include "cy_scb_ezi2c.h"
#include "cy_smif.h"
#include "cycfg_qspi_memslot.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
#include "cy_usbfs_dev_drv.h"
@ -88,9 +92,6 @@ extern "C" {
#define CYBSP_WL_UART_ENABLED 1U
#define CYBSP_WL_UART_HW SCB5
#define CYBSP_WL_UART_IRQ scb_5_interrupt_IRQn
#define CYBSP_DEBUG_UART_ENABLED 1U
#define CYBSP_DEBUG_UART_HW SCB6
#define CYBSP_DEBUG_UART_IRQ scb_6_interrupt_IRQn
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@ -120,7 +121,6 @@ extern "C" {
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
#define CYBSP_RTC_YEAR_OFFSET (0U)
#define CYBSP_SDIO_ENABLED 1U
#define CYBSP_USBUART_ENABLED 1U
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 7U
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 140U
@ -133,14 +133,37 @@ extern "C" {
extern cy_stc_csd_context_t cy_csd_0_context;
extern const cy_stc_scb_spi_config_t CYBSP_SPI_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SPI_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_scb_uart_config_t CYBSP_WL_UART_config;
extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WL_UART_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_MCWDT0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);

905
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
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File diff suppressed because it is too large Load Diff

1135
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
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File diff suppressed because it is too large Load Diff

65
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -24,10 +24,10 @@
#include "cycfg_qspi_memslot.h"
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xEBU,
.command = 0xECU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -42,7 +42,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
@ -60,7 +60,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
@ -78,10 +78,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xD8U,
.command = 0xDCU,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -96,7 +96,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
@ -114,10 +114,10 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x38U,
.command = 0x34U,
/* The width of the command transfer. */
.cmdWidth = CY_SMIF_WIDTH_SINGLE,
/* The width of the address transfer. */
@ -132,7 +132,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
@ -150,7 +150,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
@ -168,7 +168,7 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
@ -186,52 +186,52 @@ cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x03U,
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = &S25FL512S_SlaveSlot_0_readCmd,
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = &S25FL512S_SlaveSlot_0_programCmd,
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
.stsRegQuadEnableMask = 0x02U,
/* The max time for the erase type-1 cycle-time in ms. */
.eraseTime = 520U,
.eraseTime = 2600U,
/* The max time for the chip-erase cycle-time in ms. */
.chipEraseTime = 134000U,
.chipEraseTime = 460000U,
/* The max time for the page-program cycle-time in us. */
.programTime = 340U
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
/* Flags. */
.flags = CY_SMIF_FLAG_WR_EN,
.flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
/* The data-line selection options for a slave device. */
.dataSelect = CY_SMIF_DATA_SEL0,
/* The base address the memory slave is mapped to in the PSoC memory map.
@ -239,16 +239,16 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
.baseAddress = 0x18000000U,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
.memMappedSize = 0x10000U,
.memMappedSize = 0x4000000U,
/* If this memory device is one of the devices in the dual quad SPI configuration.
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* smifMemConfigs[] = {
&S25FL512S_SlaveSlot_0
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512SX4byteaddr_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =
@ -262,3 +262,4 @@ const cy_stc_smif_block_config_t smifBlockConfig =
/* The version of the SMIF driver. */
.minorVersion = CY_SMIF_DRV_VERSION_MINOR
};

25
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -28,22 +28,23 @@
#define CY_SMIF_DEVICE_NUM 1
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;
#endif /*CY_SMIF_MEMCONFIG_H*/

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
View File

@ -24,22 +24,10 @@
#include "cycfg_routing.h"
#include "cy_trigmux.h"
#include "stdbool.h"
#include "cy_device_headers.h"
void init_cycfg_routing(void)
{
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT3, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT46, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT45, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT2, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -47,17 +47,9 @@ void init_cycfg_routing(void);
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_12_pin_6_ANALOG P12_6_SRSS_ECO_IN
#define ioss_0_port_12_pin_7_ANALOG P12_7_SRSS_ECO_OUT
#define ioss_0_port_13_pin_0_HSIOM P13_0_SCB6_UART_RX
#define ioss_0_port_13_pin_1_HSIOM P13_1_SCB6_UART_TX
#define ioss_0_port_14_pin_0_AUX USBDP_USB_USB_DP_PAD
#define ioss_0_port_14_pin_1_AUX USBDM_USB_USB_DM_PAD
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_2_pin_0_HSIOM P2_0_DSI_DSI
#define ioss_0_port_2_pin_1_HSIOM P2_1_DSI_DSI
#define ioss_0_port_2_pin_2_HSIOM P2_2_DSI_DSI
#define ioss_0_port_2_pin_3_HSIOM P2_3_DSI_DSI
#define ioss_0_port_2_pin_4_HSIOM P2_4_DSI_DSI
#define ioss_0_port_2_pin_5_HSIOM P2_5_DSI_GPIO
#define ioss_0_port_3_pin_0_HSIOM P3_0_SCB2_UART_RX
#define ioss_0_port_3_pin_1_HSIOM P3_1_SCB2_UART_TX
#define ioss_0_port_3_pin_2_HSIOM P3_2_SCB2_UART_RTS
@ -74,28 +66,15 @@ void init_cycfg_routing(void);
#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
#define ioss_0_port_9_pin_0_HSIOM P9_0_CPUSS_TRACE_DATA3
#define ioss_0_port_9_pin_1_HSIOM P9_1_CPUSS_TRACE_DATA2
#define ioss_0_port_9_pin_2_HSIOM P9_2_CPUSS_TRACE_DATA1
#define ioss_0_port_9_pin_3_HSIOM P9_3_CPUSS_TRACE_DATA0
#define CYBSP_SDIO_out_p_116_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB0
#define CYBSP_SDIO_out_p_116_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT0
#define CYBSP_SDIO_out_p_117_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT3
#define CYBSP_SDIO_out_p_117_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB1
#define CYBSP_SDIO_out_p_119_TRIGGER_IN_0 TRIG0_IN_TR_GROUP14_OUTPUT1
#define CYBSP_SDIO_out_p_119_TRIGGER_IN_1 TRIG14_IN_UDB_TR_UDB3
#define CYBSP_SDIO_out_p_123_TRIGGER_IN_0 TRIG14_IN_UDB_TR_UDB7
#define CYBSP_SDIO_out_p_123_TRIGGER_IN_1 TRIG1_IN_TR_GROUP14_OUTPUT2
#define cpuss_0_dw0_0_chan_0_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN0
#define cpuss_0_dw0_0_chan_1_tr_in_0_TRIGGER_OUT TRIG0_OUT_CPUSS_DW0_TR_IN1
#define cpuss_0_dw1_0_chan_1_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN1
#define cpuss_0_dw1_0_chan_3_tr_in_0_TRIGGER_OUT TRIG1_OUT_CPUSS_DW1_TR_IN3
#if defined(__cplusplus)
}
#endif

69
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -32,6 +32,7 @@
#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
#define CY_CFG_SYSCLK_ECO_ENABLED 1
#define CY_CFG_SYSCLK_ECO_FREQ 24000000UL
#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
#define CY_CFG_SYSCLK_FLL_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
@ -84,6 +85,46 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
.cco_Freq = 355U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 4U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 30,
@ -108,13 +149,13 @@ __STATIC_INLINE void Cy_SysClk_ClkBakInit()
}
__STATIC_INLINE void Cy_SysClk_EcoInit()
{
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT12, 6, 0x00u, 0x00u, HSIOM_SEL_GPIO);
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT12, 7, 0x00u, 0x00u, HSIOM_SEL_GPIO);
if (CY_SYSCLK_BAD_PARAM == Cy_SysClk_EcoConfigure(24000000U, 18U, 50U, 100U))
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT12, 6, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO);
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT12, 7, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO);
if (CY_SYSCLK_BAD_PARAM == Cy_SysClk_EcoConfigure(CY_CFG_SYSCLK_ECO_FREQ, 18UL, 50UL, 100UL))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_ECO_ERROR);
}
if (CY_SYSCLK_TIMEOUT == Cy_SysClk_EcoEnable(3000u))
if (CY_SYSCLK_TIMEOUT == Cy_SysClk_EcoEnable(3000UL))
{
cycfg_ClockStartupError(CY_CFG_SYSCLK_ECO_ERROR);
}
@ -537,4 +578,24 @@ void init_cycfg_system(void)
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
#endif //defined (CY_USING_HAL)
}

21
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -29,6 +29,9 @@
#include "cy_sysclk.h"
#include "cy_systick.h"
#include "cy_gpio.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_syspm.h"
#if defined(__cplusplus)
@ -70,7 +73,7 @@ extern "C" {
#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
#define CY_CFG_PWR_MODE_SLEEP 0x08UL
#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_SLEEP
#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
#define CY_CFG_PWR_USING_LDO 1
@ -81,6 +84,22 @@ extern "C" {
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);
#if defined(__cplusplus)

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg
View File

@ -1,2 +1,4 @@
set SMIF_BANKS {
0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
}

409
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense Normal file
View File

@ -0,0 +1,409 @@
<?xml version="1.0"?>
<Configuration major="2" minor="0">
<!--
File Name: cycfg_capsense.cycapsense
Description:
CapSense middleware configuration
This file should not be modified. It was automatically generated by
CapSense Configurator 2.0.0 build 185
-->
<GeneralProperties>
<Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
<Property id="REGULAR_IIR_RC_N" value="128"/>
<Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
<Property id="PROX_IIR_RC_N" value="128"/>
<Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
<Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
<Property id="REGULAR_IIR_BL_N" value="1"/>
<Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="PROX_IIR_BL_N" value="1"/>
<Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
<Property id="MULTI_FREQ_SCAN_EN" value="false"/>
<Property id="SENSOR_AUTO_RESET_EN" value="false"/>
<Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
<Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
<Property id="VREF_SOURCE" value="SRSS"/>
<Property id="IREF_SOURCE" value="SRSS"/>
<Property id="PROX_TOUCH_COEFF" value="300"/>
<Property id="NUM_CENTROIDS" value="1"/>
</GeneralProperties>
<CsdProperties>
<Property id="CSD_AUTOTUNE" value="HWTH"/>
<Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
<Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
<Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
<Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
<Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
<Property id="CSD_IDAC_MIN" value="20"/>
<Property id="CSD_IDAC_COMP_EN" value="true"/>
<Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
<Property id="CSD_VREF_CUSTOM" value="false"/>
<Property id="CSD_VREF" value="1219"/>
<Property id="CSD_SHIELD_EN" value="false"/>
<Property id="CSD_SHIELD_TANK_EN" value="false"/>
<Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
<Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
<Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSD_FINE_INIT_TIME" value="10"/>
<Property id="CSD_CALIBRATION_ERROR" value="10"/>
<Property id="CSD_R_CONST" value="1000"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsdProperties>
<CsxProperties>
<Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
<Property id="CSX_MAX_FINGERS" value="3"/>
<Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
<Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
<Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
<Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
<Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
<Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
<Property id="CSX_FINE_INIT_TIME" value="10"/>
<Property id="CSX_CALIBRATION_ERROR" value="20"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsxProperties>
<Widgets>
<Widget id="Button0" type="CSX_BUTTON">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Rx0" kind="Column">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Tx" kind="Row">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
<Widget id="Button1" type="CSX_BUTTON">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Rx0" kind="Column">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Tx" kind="Row">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
<Widget id="LinearSlider0" type="LINEAR_SLIDER">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Sns0" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns1" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns2" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns3" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns4" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
</Widgets>
</Configuration>

63
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi Normal file
View File

@ -0,0 +1,63 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
<Configuration app="QSPI" major="2" minor="0">
<DevicePath>PSoC 6.xml</DevicePath>
<SlotConfigs>
<SlotConfig>
<SlaveSlot>0</SlaveSlot>
<PartNumber>S25FL512S-4byteaddr</PartNumber>
<MemoryMapped>true</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18000000</StartAddress>
<Size>0x4000000</Size>
<EndAddress>0x1BFFFFFF</EndAddress>
<WriteEnable>true</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
<MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>1</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18010000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1801FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>2</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18020000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1802FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>3</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18030000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1803FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
</SlotConfigs>
</Configuration>

291
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -172,26 +172,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[3]" alias="CYBSP_LED_RED" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[4]" alias="CYBSP_SW6" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[10].pin[0]" alias="CYBSP_ROW6_SPI_MOSI" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
@ -242,16 +222,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[10].pin[6]" alias="CYBSP_LED_BLUE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[10].pin[7]" alias="CYBSP_WL_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
@ -402,26 +372,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[13].pin[0]" alias="CYBSP_DEBUG_UART_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[13].pin[1]" alias="CYBSP_DEBUG_UART_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[13].pin[4]" alias="CYBSP_USB_DEV_VBUS_DET" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
@ -482,16 +432,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[1]" alias="CYBSP_LED_GREEN" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[2]" alias="CYBSP_WL_SECI_IN" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
@ -532,76 +472,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[0]" alias="CYBSP_WIFI_SDIO_D0" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[1]" alias="CYBSP_WIFI_SDIO_D1" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[2]" alias="CYBSP_WIFI_SDIO_D2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[3]" alias="CYBSP_WIFI_SDIO_D3" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[4]" alias="CYBSP_WIFI_SDIO_CMD" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[5]" alias="CYBSP_WIFI_SDIO_CLK" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[6]" alias="CYBSP_WIFI_WL_REG_ON" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="0"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[2].pin[7]" alias="CYBSP_WIFI_HOST_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
@ -907,7 +777,7 @@
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[2]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Block location="peri[0].div_8[3]" alias="" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="109"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
@ -1062,51 +932,6 @@
<Param id="IntrTxUnderflow" value="false"/>
<Param id="IntrTxTrigger" value="false"/>
</Block>
<Block location="scb[6]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
<Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
<Param id="IrdaLowPower" value="false"/>
<Param id="BaudRate" value="115200"/>
<Param id="Oversample" value="8"/>
<Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
<Param id="DataWidth" value="8"/>
<Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
<Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
<Param id="EnableInputFilter" value="false"/>
<Param id="EnableTxEn" value="false"/>
<Param id="FlowControl" value="false"/>
<Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsTriggerLevel" value="63"/>
<Param id="RxTriggerLevel" value="63"/>
<Param id="TxTriggerLevel" value="63"/>
<Param id="MultiProc" value="false"/>
<Param id="MpRxAddress" value="0"/>
<Param id="MpRxAddressMask" value="255"/>
<Param id="MpRxAcceptAddress" value="false"/>
<Param id="DropOnFrameErr" value="false"/>
<Param id="DropOnParityErr" value="false"/>
<Param id="BreakSignalBits" value="11"/>
<Param id="SmCardRetryOnNack" value="false"/>
<Param id="IrdaPolarity" value="NON_INVERTING"/>
<Param id="inFlash" value="true"/>
<Param id="ApiMode" value="HIGH_LEVEL"/>
<Param id="IntrRxNotEmpty" value="false"/>
<Param id="IntrRxFull" value="false"/>
<Param id="IntrRxOverflow" value="false"/>
<Param id="IntrRxUnderflow" value="false"/>
<Param id="IntrRxFrameErr" value="false"/>
<Param id="IntrRxParityErr" value="false"/>
<Param id="IntrRxBreakDetected" value="false"/>
<Param id="IntrRxTrigger" value="false"/>
<Param id="IntrTxUartDone" value="false"/>
<Param id="IntrTxUartLostArb" value="false"/>
<Param id="IntrTxUartNack" value="false"/>
<Param id="IntrTxEmpty" value="false"/>
<Param id="IntrTxNotFull" value="false"/>
<Param id="IntrTxOverflow" value="false"/>
<Param id="IntrTxUnderflow" value="false"/>
<Param id="IntrTxTrigger" value="false"/>
</Block>
<Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
<Param id="configurator" value=""/>
<Param id="isrAlignment" value="false"/>
@ -1124,8 +949,8 @@
<Block location="srss[0].clock[0].bakclk[0]" alias="" template="mxs40bakclk" version="1.0">
<Param id="sourceClock" value="wco"/>
</Block>
<Block location="srss[0].clock[0].eco[0]" alias="" template="mxs40eco" version="1.1">
<Param id="ecoFrequency" value="24.00"/>
<Block location="srss[0].clock[0].eco[0]" alias="" template="mxs40eco" version="1.2">
<Param id="ecoFrequency" value="24.0000"/>
<Param id="accuracyPpm" value="0"/>
<Param id="driveLevel" value="100"/>
<Param id="esr" value="50"/>
@ -1222,7 +1047,7 @@
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
<Param id="pmicEnable" value="false"/>
<Param id="backupSrc" value="VDDD"/>
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_SLEEP"/>
<Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
<Param id="deepsleepLatency" value="0"/>
<Param id="vddaMv" value="3300"/>
<Param id="vdddMv" value="3300"/>
@ -1256,7 +1081,6 @@
<Param id="dstStopHour" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="udb[0]" alias="CYBSP_SDIO" template="mxs40udbsdio" version="1.0"/>
<Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.0">
<Param id="configurator" value=""/>
<Param id="UsbCore" value="4"/>
@ -1314,22 +1138,6 @@
<Port name="cpuss[0].dap[0].trace_data[3]"/>
<Port name="ioss[0].port[9].pin[0].digital_out[0]"/>
</Net>
<Net>
<Port name="cpuss[0].dw0[0].chan[0].tr_in[0]"/>
<Port name="udb[0].out_p[119]"/>
</Net>
<Net>
<Port name="cpuss[0].dw0[0].chan[1].tr_in[0]"/>
<Port name="udb[0].out_p[117]"/>
</Net>
<Net>
<Port name="cpuss[0].dw1[0].chan[1].tr_in[0]"/>
<Port name="udb[0].out_p[116]"/>
</Net>
<Net>
<Port name="cpuss[0].dw1[0].chan[3].tr_in[0]"/>
<Port name="udb[0].out_p[123]"/>
</Net>
<Net>
<Port name="csd[0].csd[0].clock[0]"/>
<Port name="peri[0].div_8[4].clk[0]"/>
@ -1342,70 +1150,6 @@
<Port name="ioss[0].port[0].pin[1].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[0].digital_in[0]"/>
<Port name="udb[0].in_p[48]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[0].digital_out[0]"/>
<Port name="udb[0].port_if[16]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[0].oe[0]"/>
<Port name="udb[0].port_oe[16]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[1].digital_in[0]"/>
<Port name="udb[0].in_p[49]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[1].digital_out[0]"/>
<Port name="udb[0].port_if[17]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[1].oe[0]"/>
<Port name="udb[0].port_oe[17]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[2].digital_in[0]"/>
<Port name="udb[0].in_p[50]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[2].digital_out[0]"/>
<Port name="udb[0].port_if[18]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[2].oe[0]"/>
<Port name="udb[0].port_oe[18]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[3].digital_in[0]"/>
<Port name="udb[0].in_p[51]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[3].digital_out[0]"/>
<Port name="udb[0].port_if[19]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[3].oe[0]"/>
<Port name="udb[0].port_oe[19]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[4].digital_in[0]"/>
<Port name="udb[0].in_p[52]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[4].digital_out[0]"/>
<Port name="udb[0].port_if[20]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[4].oe[0]"/>
<Port name="udb[0].port_oe[20]"/>
</Net>
<Net>
<Port name="ioss[0].port[2].pin[5].digital_out[0]"/>
<Port name="udb[0].port_if[21]"/>
</Net>
<Net>
<Port name="ioss[0].port[3].pin[0].digital_inout[0]"/>
<Port name="scb[2].uart_rx[0]"/>
@ -1482,14 +1226,6 @@
<Port name="ioss[0].port[12].pin[7].analog[0]"/>
<Port name="srss[0].clock[0].eco[0].eco_out[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[13].pin[0].digital_inout[0]"/>
<Port name="scb[6].uart_rx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[13].pin[1].digital_inout[0]"/>
<Port name="scb[6].uart_tx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[14].pin[0].aux[0]"/>
<Port name="usb[0].usb_dp_pad[0]"/>
@ -1502,26 +1238,13 @@
<Port name="peri[0].div_16[0].clk[0]"/>
<Port name="usb[0].clock_dev_brs[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[0].clk[0]"/>
<Port name="udb[0].clocks[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[1].clk[0]"/>
<Port name="scb[3].clock[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[2].clk[0]"/>
<Port name="peri[0].div_8[3].clk[0]"/>
<Port name="scb[2].clock[0]"/>
<Port name="scb[6].clock[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[5].clk[0]"/>
<Port name="scb[1].clock[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[6].clk[0]"/>
<Port name="scb[5].clock[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_hf[0]"/>
@ -1575,6 +1298,10 @@
</Mux>
</Netlist>
</Device>
<Device mpn="CYW43012WKWBG">
<BlockConfig/>
<Netlist/>
</Device>
</Devices>
<Libraries>
<Library name="psoc6sw" version="1.2"/>