mirror of https://github.com/ARMmbed/mbed-os.git
Updated target files structure to align with the following BSP PR.
Roman Okhrimenko
parent
bfe1d04ba2
commit
c249bf97c2
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@ -0,0 +1,24 @@
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/*******************************************************************************
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* File Name: cycfg.timestamp
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*
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* Description:
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* Sentinel file for determining if generated source is up to date.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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@ -24,7 +24,7 @@
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#include "cycfg_qspi_memslot.h"
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cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd =
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const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0xEBU,
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@ -42,7 +42,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd =
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.dataWidth = CY_SMIF_WIDTH_QUAD
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};
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cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd =
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const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x06U,
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@ -60,7 +60,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd =
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd =
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const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x04U,
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@ -78,7 +78,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd =
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd =
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const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x20U,
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@ -96,7 +96,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd =
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd =
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const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x60U,
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@ -114,7 +114,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd =
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd =
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const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x38U,
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@ -132,7 +132,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd =
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.dataWidth = CY_SMIF_WIDTH_QUAD
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};
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cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd =
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const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x35U,
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@ -150,7 +150,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd =
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd =
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const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x05U,
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@ -168,7 +168,7 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd =
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd =
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const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd =
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{
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/* The 8-bit command. 1 x I/O read command. */
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.command = 0x01U,
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@ -186,52 +186,52 @@ cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd =
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.dataWidth = CY_SMIF_WIDTH_SINGLE
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};
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cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0 =
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const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0 =
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{
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/* Specifies the number of address bytes used by the memory slave device. */
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.numOfAddrBytes = 0x03U,
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/* The size of the memory. */
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.memSize = 0x1000000U,
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/* Specifies the Read command. */
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.readCmd = &S25FL128S_SlaveSlot_0_readCmd,
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.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_readCmd,
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/* Specifies the Write Enable command. */
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.writeEnCmd = &S25FL128S_SlaveSlot_0_writeEnCmd,
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.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_writeEnCmd,
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/* Specifies the Write Disable command. */
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.writeDisCmd = &S25FL128S_SlaveSlot_0_writeDisCmd,
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.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_writeDisCmd,
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/* Specifies the Erase command. */
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.eraseCmd = &S25FL128S_SlaveSlot_0_eraseCmd,
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.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_eraseCmd,
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/* Specifies the sector size of each erase. */
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.eraseSize = 0x0001000U,
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/* Specifies the Chip Erase command. */
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.chipEraseCmd = &S25FL128S_SlaveSlot_0_chipEraseCmd,
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.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_chipEraseCmd,
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/* Specifies the Program command. */
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.programCmd = &S25FL128S_SlaveSlot_0_programCmd,
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.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_programCmd,
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/* Specifies the page size for programming. */
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.programSize = 0x0000200U,
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/* Specifies the command to read the QE-containing status register. */
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.readStsRegQeCmd = &S25FL128S_SlaveSlot_0_readStsRegQeCmd,
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.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_readStsRegQeCmd,
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/* Specifies the command to read the WIP-containing status register. */
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.readStsRegWipCmd = &S25FL128S_SlaveSlot_0_readStsRegWipCmd,
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.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_readStsRegWipCmd,
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/* Specifies the command to write into the QE-containing status register. */
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.writeStsRegQeCmd = &S25FL128S_SlaveSlot_0_writeStsRegQeCmd,
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.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_writeStsRegQeCmd,
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/* The mask for the status register. */
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.stsRegBusyMask = 0x01U,
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/* The mask for the status register. */
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.stsRegQuadEnableMask = 0x02U,
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/* The max time for the erase type-1 cycle-time in ms. */
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.eraseTime = 140U,
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.eraseTime = 650U,
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/* The max time for the chip-erase cycle-time in ms. */
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.chipEraseTime = 40000U,
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.chipEraseTime = 165000U,
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/* The max time for the page-program cycle-time in us. */
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.programTime = 250U
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.programTime = 750U
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};
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cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0 =
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const cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0 =
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{
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/* Determines the slot number where the memory device is placed. */
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.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
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/* Flags. */
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.flags = CY_SMIF_FLAG_WR_EN,
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.flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
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/* The data-line selection options for a slave device. */
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.dataSelect = CY_SMIF_DATA_SEL0,
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/* The base address the memory slave is mapped to in the PSoC memory map.
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@ -239,19 +239,19 @@ cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0 =
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.baseAddress = 0x18000000U,
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/* The size allocated in the PSoC memory map, for the memory slave device.
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The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
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.memMappedSize = 0x10000U,
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.memMappedSize = 0x1000000U,
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/* If this memory device is one of the devices in the dual quad SPI configuration.
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Valid when the memory mapped mode is enabled. */
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.dualQuadSlots = 0,
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/* The configuration of the device. */
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.deviceCfg = &deviceCfg_S25FL128S_SlaveSlot_0
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.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL128S_SlaveSlot_0
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};
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cy_stc_smif_mem_config_t* smifMemConfigs[] = {
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const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
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&S25FL128S_SlaveSlot_0
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};
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cy_stc_smif_block_config_t smifBlockConfig =
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const cy_stc_smif_block_config_t smifBlockConfig =
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{
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/* The number of SMIF memories defined. */
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.memCount = CY_SMIF_DEVICE_NUM,
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@ -28,22 +28,22 @@
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#define CY_SMIF_DEVICE_NUM 1
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extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd;
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extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd;
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extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd;
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extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd;
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extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd;
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extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd;
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extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd;
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extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd;
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extern cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd;
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extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd;
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extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0;
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extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0;
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extern cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0;
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extern cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
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extern const cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0;
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extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
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extern cy_stc_smif_block_config_t smifBlockConfig;
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extern const cy_stc_smif_block_config_t smifBlockConfig;
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#endif /*CY_SMIF_MEMCONFIG_H*/
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@ -38,6 +38,9 @@
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#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
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#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
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#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
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#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
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#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL
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#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
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#define CY_CFG_SYSCLK_ILO_ENABLED 1
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#define CY_CFG_SYSCLK_IMO_ENABLED 1
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#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
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@ -52,6 +55,7 @@
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#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
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#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
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#define CY_CFG_SYSCLK_PLL0_ENABLED 1
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#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
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#define CY_CFG_SYSCLK_WCO_ENABLED 1
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#define CY_CFG_PWR_ENABLED 1
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@ -74,6 +78,14 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
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.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
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.cco_Freq = 355U,
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};
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static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
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{
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.feedbackDiv = 30,
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.referenceDiv = 1,
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.outputDiv = 5,
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.lfMode = false,
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.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
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};
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__WEAK void cycfg_ClockStartupError(uint32_t error)
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{
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@ -110,6 +122,12 @@ __STATIC_INLINE void Cy_SysClk_ClkHf2Init()
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Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
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Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
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}
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__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
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{
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Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
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Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
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Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
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}
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__STATIC_INLINE void Cy_SysClk_IloInit()
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{
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/* The WDT is unlocked in the default startup code */
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@ -145,6 +163,17 @@ __STATIC_INLINE void Cy_SysClk_ClkPeriInit()
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{
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Cy_SysClk_ClkPeriSetDivider(1U);
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}
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__STATIC_INLINE void Cy_SysClk_Pll0Init()
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{
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if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
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{
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cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
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}
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if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
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{
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cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
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}
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}
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__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
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{
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Cy_SysClk_ClkSlowSetDivider(0U);
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@ -43,6 +43,8 @@ extern "C" {
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#define CY_CFG_SYSCLK_CLKHF0 0UL
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#define srss_0_clock_0_hfclk_2_ENABLED 1U
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#define CY_CFG_SYSCLK_CLKHF2 2UL
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#define srss_0_clock_0_hfclk_3_ENABLED 1U
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#define CY_CFG_SYSCLK_CLKHF3 3UL
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#define srss_0_clock_0_ilo_0_ENABLED 1U
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#define srss_0_clock_0_imo_0_ENABLED 1U
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#define srss_0_clock_0_lfclk_0_ENABLED 1U
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@ -53,6 +55,7 @@ extern "C" {
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#define srss_0_clock_0_pathmux_3_ENABLED 1U
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#define srss_0_clock_0_pathmux_4_ENABLED 1U
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#define srss_0_clock_0_periclk_0_ENABLED 1U
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#define srss_0_clock_0_pll_0_ENABLED 1U
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#define srss_0_clock_0_slowclk_0_ENABLED 1U
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#define srss_0_clock_0_wco_0_ENABLED 1U
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#define srss_0_power_0_ENABLED 1U
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@ -0,0 +1,4 @@
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set SMIF_BANKS {
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0 {addr 0x18000000 size 0x1000000 psize 0x0000200 esize 0x0001000}
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}
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@ -198,33 +198,33 @@
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<Param id="sioOutputBuffer" value="true"/>
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<Param id="inFlash" value="true"/>
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</Block>
|
||||
<Block location="ioss[0].port[6].pin[4]" alias="CYBSP_SWO" template="mxs40pin" version="1.0">
|
||||
<Block location="ioss[0].port[6].pin[4]" alias="CYBSP_SWO" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_FULL"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[6]" alias="CYBSP_SWDIO" template="mxs40pin" version="1.0">
|
||||
<Block location="ioss[0].port[6].pin[6]" alias="CYBSP_SWDIO" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_FULL"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Block>
|
||||
<Block location="ioss[0].port[6].pin[7]" alias="CYBSP_SWCLK" template="mxs40pin" version="1.0">
|
||||
<Block location="ioss[0].port[6].pin[7]" alias="CYBSP_SWCLK" template="mxs40pin" version="1.1">
|
||||
<Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
|
||||
<Param id="initialState" value="1"/>
|
||||
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
|
||||
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
|
||||
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_FULL"/>
|
||||
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
|
||||
<Param id="sioOutputBuffer" value="true"/>
|
||||
<Param id="inFlash" value="true"/>
|
||||
</Block>
|
||||
|
|
@ -326,6 +326,10 @@
|
|||
<Param id="sourceClockNumber" value="0"/>
|
||||
<Param id="divider" value="2"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].hfclk[3]" alias="" template="mxs40hfclk" version="1.1">
|
||||
<Param id="sourceClockNumber" value="1"/>
|
||||
<Param id="divider" value="1"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].ilo[0]" alias="" template="mxs40ilo" version="1.0">
|
||||
<Param id="hibernate" value="true"/>
|
||||
</Block>
|
||||
|
|
@ -353,6 +357,12 @@
|
|||
<Block location="srss[0].clock[0].periclk[0]" alias="" template="mxs40periclk" version="1.0">
|
||||
<Param id="divider" value="2"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].pll[0]" alias="" template="mxs40pll" version="1.0">
|
||||
<Param id="lowFrequencyMode" value="false"/>
|
||||
<Param id="configuration" value="auto"/>
|
||||
<Param id="desiredFrequency" value="48.000"/>
|
||||
<Param id="optimization" value="MinPower"/>
|
||||
</Block>
|
||||
<Block location="srss[0].clock[0].slowclk[0]" alias="" template="mxs40slowclk" version="1.0">
|
||||
<Param id="divider" value="1"/>
|
||||
</Block>
|
||||
|
|
@ -38,6 +38,7 @@ typedef enum {
|
|||
UART_7 = (int)SCB7_BASE,
|
||||
} UARTName;
|
||||
|
||||
#define DEVICE_SPI_COUNT CY_IP_MXSCB_INSTANCES
|
||||
|
||||
typedef enum {
|
||||
SPI_0 = (int)SCB0_BASE,
|
||||
|
|
@ -107,7 +108,7 @@ typedef enum {
|
|||
} DACName;
|
||||
|
||||
typedef enum {
|
||||
SMIF_0 = (int)SMIF0_BASE,
|
||||
QSPI_0 = (int)SMIF0_BASE,
|
||||
} SMIFName;
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
|
|
@ -24,71 +24,71 @@
|
|||
#if DEVICE_SERIAL
|
||||
//*** SERIAL ***
|
||||
const PinMap PinMap_UART_RX[] = {
|
||||
{P0_2, UART_0, CYHAL_PIN_IN_FUNCTION( P0_2_SCB0_UART_RX)},
|
||||
{P1_0, UART_7, CYHAL_PIN_IN_FUNCTION( P1_0_SCB7_UART_RX)},
|
||||
{P2_0, UART_1, CYHAL_PIN_IN_FUNCTION( P2_0_SCB1_UART_RX)},
|
||||
{P3_0, UART_2, CYHAL_PIN_IN_FUNCTION( P3_0_SCB2_UART_RX)},
|
||||
{P4_0, UART_7, CYHAL_PIN_IN_FUNCTION( P4_0_SCB7_UART_RX)},
|
||||
{P5_0, UART_5, CYHAL_PIN_IN_FUNCTION( P5_0_SCB5_UART_RX)},
|
||||
{P6_0, UART_3, CYHAL_PIN_IN_FUNCTION( P6_0_SCB3_UART_RX)},
|
||||
{P6_4, UART_6, CYHAL_PIN_IN_FUNCTION( P6_4_SCB6_UART_RX)},
|
||||
{P7_0, UART_4, CYHAL_PIN_IN_FUNCTION( P7_0_SCB4_UART_RX)},
|
||||
{P8_0, UART_4, CYHAL_PIN_IN_FUNCTION( P8_0_SCB4_UART_RX)},
|
||||
{P9_0, UART_2, CYHAL_PIN_IN_FUNCTION( P9_0_SCB2_UART_RX)},
|
||||
{P10_0, UART_1, CYHAL_PIN_IN_FUNCTION( P10_0_SCB1_UART_RX)},
|
||||
{P11_0, UART_5, CYHAL_PIN_IN_FUNCTION( P11_0_SCB5_UART_RX)},
|
||||
{P12_0, UART_6, CYHAL_PIN_IN_FUNCTION( P12_0_SCB6_UART_RX)},
|
||||
{P13_0, UART_6, CYHAL_PIN_IN_FUNCTION( P13_0_SCB6_UART_RX)},
|
||||
{P0_2, UART_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
|
||||
{P1_0, UART_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)},
|
||||
{P2_0, UART_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)},
|
||||
{P3_0, UART_2, CYHAL_PIN_IN_FUNCTION(P3_0_SCB2_UART_RX)},
|
||||
{P4_0, UART_7, CYHAL_PIN_IN_FUNCTION(P4_0_SCB7_UART_RX)},
|
||||
{P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
|
||||
{P6_0, UART_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
|
||||
{P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
|
||||
{P7_0, UART_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
|
||||
{P8_0, UART_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
|
||||
{P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
|
||||
{P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
|
||||
{P11_0, UART_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
|
||||
{P12_0, UART_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)},
|
||||
{P13_0, UART_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_UART_TX[] = {
|
||||
{P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION( P0_3_SCB0_UART_TX)},
|
||||
{P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION( P1_1_SCB7_UART_TX)},
|
||||
{P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION( P2_1_SCB1_UART_TX)},
|
||||
{P3_1, UART_2, CYHAL_PIN_OUT_FUNCTION( P3_1_SCB2_UART_TX)},
|
||||
{P4_1, UART_7, CYHAL_PIN_OUT_FUNCTION( P4_1_SCB7_UART_TX)},
|
||||
{P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION( P5_1_SCB5_UART_TX)},
|
||||
{P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION( P6_1_SCB3_UART_TX)},
|
||||
{P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION( P6_5_SCB6_UART_TX)},
|
||||
{P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION( P7_1_SCB4_UART_TX)},
|
||||
{P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION( P8_1_SCB4_UART_TX)},
|
||||
{P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION( P9_1_SCB2_UART_TX)},
|
||||
{P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION( P10_1_SCB1_UART_TX)},
|
||||
{P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION( P11_1_SCB5_UART_TX)},
|
||||
{P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION( P12_1_SCB6_UART_TX)},
|
||||
{P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION( P13_1_SCB6_UART_TX)},
|
||||
{P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
|
||||
{P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)},
|
||||
{P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)},
|
||||
{P3_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_1_SCB2_UART_TX)},
|
||||
{P4_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P4_1_SCB7_UART_TX)},
|
||||
{P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
|
||||
{P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
|
||||
{P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
|
||||
{P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
|
||||
{P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
|
||||
{P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
|
||||
{P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
|
||||
{P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
|
||||
{P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)},
|
||||
{P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_UART_RTS[] = {
|
||||
{P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION( P0_4_SCB0_UART_RTS)},
|
||||
{P1_2, UART_7, CYHAL_PIN_OUT_FUNCTION( P1_2_SCB7_UART_RTS)},
|
||||
{P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION( P2_2_SCB1_UART_RTS)},
|
||||
{P3_2, UART_2, CYHAL_PIN_OUT_FUNCTION( P3_2_SCB2_UART_RTS)},
|
||||
{P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION( P5_2_SCB5_UART_RTS)},
|
||||
{P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION( P6_2_SCB3_UART_RTS)},
|
||||
{P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION( P6_6_SCB6_UART_RTS)},
|
||||
{P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION( P7_2_SCB4_UART_RTS)},
|
||||
{P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION( P8_2_SCB4_UART_RTS)},
|
||||
{P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION( P9_2_SCB2_UART_RTS)},
|
||||
{P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION( P10_2_SCB1_UART_RTS)},
|
||||
{P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION( P11_2_SCB5_UART_RTS)},
|
||||
{P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION( P12_2_SCB6_UART_RTS)},
|
||||
{P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
|
||||
{P1_2, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_UART_RTS)},
|
||||
{P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)},
|
||||
{P3_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_UART_RTS)},
|
||||
{P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
|
||||
{P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
|
||||
{P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
|
||||
{P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
|
||||
{P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
|
||||
{P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
|
||||
{P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)},
|
||||
{P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
|
||||
{P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_UART_CTS[] = {
|
||||
{P0_5, UART_0, CYHAL_PIN_IN_FUNCTION( P0_5_SCB0_UART_CTS)},
|
||||
{P1_3, UART_7, CYHAL_PIN_IN_FUNCTION( P1_3_SCB7_UART_CTS)},
|
||||
{P2_3, UART_1, CYHAL_PIN_IN_FUNCTION( P2_3_SCB1_UART_CTS)},
|
||||
{P3_3, UART_2, CYHAL_PIN_IN_FUNCTION( P3_3_SCB2_UART_CTS)},
|
||||
{P5_3, UART_5, CYHAL_PIN_IN_FUNCTION( P5_3_SCB5_UART_CTS)},
|
||||
{P6_3, UART_3, CYHAL_PIN_IN_FUNCTION( P6_3_SCB3_UART_CTS)},
|
||||
{P6_7, UART_6, CYHAL_PIN_IN_FUNCTION( P6_7_SCB6_UART_CTS)},
|
||||
{P7_3, UART_4, CYHAL_PIN_IN_FUNCTION( P7_3_SCB4_UART_CTS)},
|
||||
{P8_3, UART_4, CYHAL_PIN_IN_FUNCTION( P8_3_SCB4_UART_CTS)},
|
||||
{P9_3, UART_2, CYHAL_PIN_IN_FUNCTION( P9_3_SCB2_UART_CTS)},
|
||||
{P10_3, UART_1, CYHAL_PIN_IN_FUNCTION( P10_3_SCB1_UART_CTS)},
|
||||
{P11_3, UART_5, CYHAL_PIN_IN_FUNCTION( P11_3_SCB5_UART_CTS)},
|
||||
{P12_3, UART_6, CYHAL_PIN_IN_FUNCTION( P12_3_SCB6_UART_CTS)},
|
||||
{P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
|
||||
{P1_3, UART_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_UART_CTS)},
|
||||
{P2_3, UART_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)},
|
||||
{P3_3, UART_2, CYHAL_PIN_IN_FUNCTION(P3_3_SCB2_UART_CTS)},
|
||||
{P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
|
||||
{P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
|
||||
{P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
|
||||
{P7_3, UART_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
|
||||
{P8_3, UART_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)},
|
||||
{P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
|
||||
{P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)},
|
||||
{P11_3, UART_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
|
||||
{P12_3, UART_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
#endif // DEVICE_SERIAL
|
||||
|
|
@ -97,39 +97,43 @@ const PinMap PinMap_UART_CTS[] = {
|
|||
#if DEVICE_I2C
|
||||
//*** I2C ***
|
||||
const PinMap PinMap_I2C_SCL[] = {
|
||||
{P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION( P0_2_SCB0_I2C_SCL)},
|
||||
{P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION( P1_0_SCB7_I2C_SCL)},
|
||||
{P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION( P2_0_SCB1_I2C_SCL)},
|
||||
{P3_0, I2C_2, CYHAL_PIN_OD_FUNCTION( P3_0_SCB2_I2C_SCL)},
|
||||
{P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION( P4_0_SCB7_I2C_SCL)},
|
||||
{P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION( P5_0_SCB5_I2C_SCL)},
|
||||
{P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION( P6_0_SCB3_I2C_SCL)},
|
||||
{P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION( P6_4_SCB6_I2C_SCL)},
|
||||
{P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION( P7_0_SCB4_I2C_SCL)},
|
||||
{P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION( P8_0_SCB4_I2C_SCL)},
|
||||
{P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION( P9_0_SCB2_I2C_SCL)},
|
||||
{P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION( P10_0_SCB1_I2C_SCL)},
|
||||
{P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION( P11_0_SCB5_I2C_SCL)},
|
||||
{P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION( P12_0_SCB6_I2C_SCL)},
|
||||
{P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION( P13_0_SCB6_I2C_SCL)},
|
||||
{P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
|
||||
{P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
|
||||
{P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)},
|
||||
{P3_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_0_SCB2_I2C_SCL)},
|
||||
{P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_0_SCB7_I2C_SCL)},
|
||||
{P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
|
||||
{P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
|
||||
{P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
|
||||
{P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
|
||||
{P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
|
||||
{P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
|
||||
{P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
|
||||
{P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
|
||||
{P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
|
||||
{P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
|
||||
{P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)},
|
||||
{P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_I2C_SDA[] = {
|
||||
{P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION( P0_3_SCB0_I2C_SDA)},
|
||||
{P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION( P1_1_SCB7_I2C_SDA)},
|
||||
{P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION( P2_1_SCB1_I2C_SDA)},
|
||||
{P3_1, I2C_2, CYHAL_PIN_OD_FUNCTION( P3_1_SCB2_I2C_SDA)},
|
||||
{P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION( P4_1_SCB7_I2C_SDA)},
|
||||
{P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION( P5_1_SCB5_I2C_SDA)},
|
||||
{P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION( P6_1_SCB3_I2C_SDA)},
|
||||
{P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION( P6_5_SCB6_I2C_SDA)},
|
||||
{P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION( P7_1_SCB4_I2C_SDA)},
|
||||
{P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION( P8_1_SCB4_I2C_SDA)},
|
||||
{P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION( P9_1_SCB2_I2C_SDA)},
|
||||
{P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION( P10_1_SCB1_I2C_SDA)},
|
||||
{P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION( P11_1_SCB5_I2C_SDA)},
|
||||
{P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION( P12_1_SCB6_I2C_SDA)},
|
||||
{P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION( P13_1_SCB6_I2C_SDA)},
|
||||
{P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
|
||||
{P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
|
||||
{P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)},
|
||||
{P3_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_1_SCB2_I2C_SDA)},
|
||||
{P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_1_SCB7_I2C_SDA)},
|
||||
{P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
|
||||
{P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
|
||||
{P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
|
||||
{P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
|
||||
{P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
|
||||
{P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
|
||||
{P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
|
||||
{P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
|
||||
{P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
|
||||
{P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
|
||||
{P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)},
|
||||
{P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
#endif // DEVICE_I2C
|
||||
|
|
@ -137,71 +141,79 @@ const PinMap PinMap_I2C_SDA[] = {
|
|||
#if DEVICE_SPI
|
||||
//*** SPI ***
|
||||
const PinMap PinMap_SPI_MOSI[] = {
|
||||
{P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION( P0_2_SCB0_SPI_MOSI)},
|
||||
{P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION( P1_0_SCB7_SPI_MOSI)},
|
||||
{P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION( P2_0_SCB1_SPI_MOSI)},
|
||||
{P3_0, SPI_2, CYHAL_PIN_OUT_FUNCTION( P3_0_SCB2_SPI_MOSI)},
|
||||
{P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION( P4_0_SCB7_SPI_MOSI)},
|
||||
{P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION( P5_0_SCB5_SPI_MOSI)},
|
||||
{P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION( P6_0_SCB3_SPI_MOSI)},
|
||||
{P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION( P6_4_SCB6_SPI_MOSI)},
|
||||
{P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION( P7_0_SCB4_SPI_MOSI)},
|
||||
{P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION( P8_0_SCB4_SPI_MOSI)},
|
||||
{P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION( P9_0_SCB2_SPI_MOSI)},
|
||||
{P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION( P10_0_SCB1_SPI_MOSI)},
|
||||
{P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION( P11_0_SCB5_SPI_MOSI)},
|
||||
{P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION( P12_0_SCB6_SPI_MOSI)},
|
||||
{P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION( P13_0_SCB6_SPI_MOSI)},
|
||||
{P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
|
||||
{P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
|
||||
{P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)},
|
||||
{P3_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_0_SCB2_SPI_MOSI)},
|
||||
{P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)},
|
||||
{P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
|
||||
{P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
|
||||
{P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
|
||||
{P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
|
||||
{P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
|
||||
{P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
|
||||
{P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
|
||||
{P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
|
||||
{P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
|
||||
{P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
|
||||
{P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)},
|
||||
{P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_SPI_MISO[] = {
|
||||
{P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION( P0_3_SCB0_SPI_MISO)},
|
||||
{P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION( P1_1_SCB7_SPI_MISO)},
|
||||
{P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION( P2_1_SCB1_SPI_MISO)},
|
||||
{P3_1, SPI_2, CYHAL_PIN_IN_FUNCTION( P3_1_SCB2_SPI_MISO)},
|
||||
{P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION( P4_1_SCB7_SPI_MISO)},
|
||||
{P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION( P5_1_SCB5_SPI_MISO)},
|
||||
{P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION( P6_1_SCB3_SPI_MISO)},
|
||||
{P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION( P6_5_SCB6_SPI_MISO)},
|
||||
{P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION( P7_1_SCB4_SPI_MISO)},
|
||||
{P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION( P8_1_SCB4_SPI_MISO)},
|
||||
{P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION( P9_1_SCB2_SPI_MISO)},
|
||||
{P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION( P10_1_SCB1_SPI_MISO)},
|
||||
{P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION( P11_1_SCB5_SPI_MISO)},
|
||||
{P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION( P12_1_SCB6_SPI_MISO)},
|
||||
{P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION( P13_1_SCB6_SPI_MISO)},
|
||||
{P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
|
||||
{P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
|
||||
{P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)},
|
||||
{P3_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P3_1_SCB2_SPI_MISO)},
|
||||
{P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)},
|
||||
{P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
|
||||
{P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
|
||||
{P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
|
||||
{P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
|
||||
{P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
|
||||
{P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
|
||||
{P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
|
||||
{P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
|
||||
{P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
|
||||
{P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
|
||||
{P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)},
|
||||
{P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_SPI_SCLK[] = {
|
||||
{P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION( P0_4_SCB0_SPI_CLK)},
|
||||
{P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION( P1_2_SCB7_SPI_CLK)},
|
||||
{P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION( P2_2_SCB1_SPI_CLK)},
|
||||
{P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION( P3_2_SCB2_SPI_CLK)},
|
||||
{P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION( P5_2_SCB5_SPI_CLK)},
|
||||
{P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION( P6_2_SCB3_SPI_CLK)},
|
||||
{P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION( P6_6_SCB6_SPI_CLK)},
|
||||
{P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION( P7_2_SCB4_SPI_CLK)},
|
||||
{P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION( P8_2_SCB4_SPI_CLK)},
|
||||
{P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION( P9_2_SCB2_SPI_CLK)},
|
||||
{P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION( P10_2_SCB1_SPI_CLK)},
|
||||
{P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION( P11_2_SCB5_SPI_CLK)},
|
||||
{P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION( P12_2_SCB6_SPI_CLK)},
|
||||
{P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
|
||||
{P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)},
|
||||
{P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)},
|
||||
{P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)},
|
||||
{P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
|
||||
{P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
|
||||
{P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
|
||||
{P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
|
||||
{P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
|
||||
{P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
|
||||
{P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
|
||||
{P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
|
||||
{P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
|
||||
{P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
|
||||
{P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
const PinMap PinMap_SPI_SSEL[] = {
|
||||
{P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION( P0_5_SCB0_SPI_SELECT0)},
|
||||
{P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION( P1_3_SCB7_SPI_SELECT0)},
|
||||
{P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION( P2_3_SCB1_SPI_SELECT0)},
|
||||
{P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION( P3_3_SCB2_SPI_SELECT0)},
|
||||
{P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION( P5_3_SCB5_SPI_SELECT0)},
|
||||
{P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION( P6_3_SCB3_SPI_SELECT0)},
|
||||
{P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION( P6_7_SCB6_SPI_SELECT0)},
|
||||
{P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION( P7_3_SCB4_SPI_SELECT0)},
|
||||
{P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION( P8_3_SCB4_SPI_SELECT0)},
|
||||
{P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION( P9_3_SCB2_SPI_SELECT0)},
|
||||
{P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION( P10_3_SCB1_SPI_SELECT0)},
|
||||
{P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION( P11_3_SCB5_SPI_SELECT0)},
|
||||
{P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION( P12_3_SCB6_SPI_SELECT0)},
|
||||
{P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
|
||||
{P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
|
||||
{P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)},
|
||||
{P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
|
||||
{P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
|
||||
{P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
|
||||
{P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
|
||||
{P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
|
||||
{P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
|
||||
{P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
|
||||
{P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
|
||||
{P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
|
||||
{P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
|
||||
{P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
|
||||
{P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
#endif // DEVICE_SPI
|
||||
|
|
@ -415,51 +427,48 @@ const PinMap PinMap_PWM_OUT[] = {
|
|||
|
||||
#if DEVICE_ANALOGIN
|
||||
const PinMap PinMap_ADC[] = {
|
||||
{P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_SAR)},
|
||||
{P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
|
||||
{P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
|
||||
{P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
|
||||
{P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
|
||||
{P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
|
||||
{P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
|
||||
{P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
|
||||
{P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
#endif // DEVICE_ANALOGIN
|
||||
|
||||
#if DEVICE_ANALOGOUT
|
||||
const PinMap PinMap_DAC[] = {
|
||||
{P9_6, DAC_0, CYHAL_PIN_ANALOG_FUNCTION(PCLK_PASS_CLOCK_CTDAC)},
|
||||
{P10_5, DAC_0, CY_GPIO_CFG_CREATE(HSIOM_SEL_AMUXA, CY_GPIO_DM_ANALOG)}, // CTDAC connects to the P10_5 pin through the AMUXA bus
|
||||
{P9_6, DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
|
||||
{NC, NC, 0}
|
||||
};
|
||||
#endif // DEVICE_ANALOGIN
|
||||
|
||||
#if DEVICE_QSPI
|
||||
const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2
|
||||
{P11_7, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_7_SMIF_SPI_CLK, 0)},
|
||||
{NC, NC, 0}
|
||||
const PinMap PinMap_QSPI_SCLK[] = {
|
||||
{P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
|
||||
{NC, NC, 0},
|
||||
};
|
||||
|
||||
// Ensure that the spi_data pins are defined in the order 0 to 7
|
||||
const PinMap PinMap_QSPI_DATA[] = { // does not use PERI clock, uses HFCLK2
|
||||
{P11_6, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_6_SMIF_SPI_DATA0, 0)}, // spi_data0
|
||||
{P11_5, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_5_SMIF_SPI_DATA1, 0)}, // spi_data1
|
||||
{P11_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_4_SMIF_SPI_DATA2, 0)}, // spi_data2
|
||||
{P11_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_3_SMIF_SPI_DATA3, 0)}, // spi_data3
|
||||
{P12_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_0_SMIF_SPI_DATA4, 0)}, // spi_data4
|
||||
{P12_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_1_SMIF_SPI_DATA5, 0)}, // spi_data5
|
||||
{P12_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_2_SMIF_SPI_DATA6, 0)}, // spi_data6
|
||||
{P12_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_3_SMIF_SPI_DATA7, 0)}, // spi_data7
|
||||
{NC, NC, 0}
|
||||
};
|
||||
|
||||
// Ensure that the spi_select pins are defined in the order 0 to 3
|
||||
const PinMap PinMap_QSPI_SSEL[] = { // does not use PERI clock, uses HFCLK2
|
||||
{P11_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0, 0)}, // spi_select0
|
||||
{P11_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1, 0)}, // spi_select1
|
||||
{P11_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2, 0)}, // spi_select2
|
||||
{P12_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3, 0)}, // spi_select3
|
||||
{NC, NC, 0}
|
||||
const PinMap PinMap_QSPI_SSEL[] = {
|
||||
{P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
|
||||
{NC, NC, 0},
|
||||
};
|
||||
const PinMap PinMap_QSPI_DATA0[] = {
|
||||
{P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
|
||||
{NC, NC, 0},
|
||||
};
|
||||
const PinMap PinMap_QSPI_DATA1[] = {
|
||||
{P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
|
||||
{NC, NC, 0},
|
||||
};
|
||||
const PinMap PinMap_QSPI_DATA2[] = {
|
||||
{P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
|
||||
{NC, NC, 0},
|
||||
};
|
||||
const PinMap PinMap_QSPI_DATA3[] = {
|
||||
{P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
|
||||
{NC, NC, 0},
|
||||
};
|
||||
#endif // DEVICE_QSPI
|
||||
|
|
|
|||
|
|
@ -20,11 +20,8 @@
|
|||
#ifndef MBED_PINNAMES_H
|
||||
#define MBED_PINNAMES_H
|
||||
|
||||
#include "cmsis.h"
|
||||
#include "PinNamesTypes.h"
|
||||
#include "PortNames.h"
|
||||
#include "cyhal_pin_package.h"
|
||||
#include "cyhal_utils.h"
|
||||
|
||||
typedef cyhal_gpio_t PinName;
|
||||
|
||||
|
|
@ -68,16 +65,14 @@ typedef cyhal_gpio_t PinName;
|
|||
#define UART_RTS P5_2
|
||||
#define UART_CTS P5_3
|
||||
|
||||
// Reset pin unavailable
|
||||
// Reset pin unavailable
|
||||
|
||||
|
||||
#define SWITCH2 P0_4
|
||||
#define LED1 P13_7
|
||||
#define LED2 P1_5
|
||||
|
||||
#define LED_RED LED1
|
||||
#define LED_GREEN LED2
|
||||
|
||||
#define SWITCH2 P0_4
|
||||
#define USER_BUTTON SWITCH2
|
||||
#define BUTTON1 USER_BUTTON
|
||||
|
||||
|
|
@ -88,48 +83,20 @@ typedef cyhal_gpio_t PinName;
|
|||
#define QSPI_IO_3 P11_3
|
||||
#define QSPI_SEL P11_2
|
||||
|
||||
// Standardized interfaces names
|
||||
#define QSPI_FLASH1_IO0 QSPI_IO_0
|
||||
#define QSPI_FLASH1_IO1 QSPI_IO_1
|
||||
#define QSPI_FLASH1_IO2 QSPI_IO_2
|
||||
#define QSPI_FLASH1_IO3 QSPI_IO_3
|
||||
#define QSPI_FLASH1_SCK QSPI_CLK
|
||||
#define QSPI_FLASH1_CSN QSPI_SEL
|
||||
|
||||
// Standardized interfaces names
|
||||
#define STDIO_UART_TX UART_TX
|
||||
#define STDIO_UART_RX UART_RX
|
||||
#define STDIO_UART_CTS UART_CTS
|
||||
#define STDIO_UART_RTS UART_RTS
|
||||
|
||||
#define CY_STDIO_UART_RX STDIO_UART_RX
|
||||
#define CY_STDIO_UART_TX STDIO_UART_TX
|
||||
#define CY_STDIO_UART_CTS STDIO_UART_CTS
|
||||
#define CY_STDIO_UART_RTS STDIO_UART_RTS
|
||||
|
||||
#define CY_BT_UART_RX BT_UART_RX
|
||||
#define CY_BT_UART_TX BT_UART_TX
|
||||
#define CY_BT_UART_CTS BT_UART_CTS
|
||||
#define CY_BT_UART_RTS BT_UART_RTS
|
||||
|
||||
#define CY_BT_PIN_POWER BT_PIN_POWER
|
||||
#define CY_BT_PIN_HOST_WAKE BT_PIN_HOST_WAKE
|
||||
#define CY_BT_PIN_DEVICE_WAKE BT_PIN_DEVICE_WAKE
|
||||
|
||||
|
||||
#define USBTX UART_TX
|
||||
#define USBRX UART_RX
|
||||
|
||||
#define AOUT P9_6
|
||||
|
||||
// PinName[15-0] = Port[15-8] + Pin[4-0]
|
||||
static inline unsigned CY_PIN(PinName pin)
|
||||
{
|
||||
return pin & 0x07;
|
||||
}
|
||||
|
||||
static inline unsigned CY_PORT(PinName pin)
|
||||
{
|
||||
return (pin >> 8) & 0xFF;
|
||||
}
|
||||
|
||||
// Because MBED pin mapping API does not allow to map multiple instances of the PWM
|
||||
// to be mapped to the same pin, we create special pin names to force 32-bit PWM unit
|
||||
// usage instead of standard 16-bit PWM.
|
||||
|
||||
#define PWM32(pin) CY_PIN_FORCE_PWM_32(pin)
|
||||
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -1,9 +1,9 @@
|
|||
/***************************************************************************//**
|
||||
* \file cybsp_cy8cproto_064_sb.c
|
||||
* \file CY8CPROTO-064-SB/cybsp.c
|
||||
*
|
||||
* Description:
|
||||
* Provides APIs for interacting with the hardware contained on the Cypress
|
||||
* CY8CPROTO-064-SB pioneer kit.
|
||||
* CY8CPROTO-064-SB prototyping kit.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
|
|
@ -23,8 +23,7 @@
|
|||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
//#include "cybsp_retarget.h"
|
||||
#include "cybsp_cy8cproto_064_sb.h"
|
||||
#include "cybsp.h"
|
||||
#include "cycfg.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
|
|
@ -33,16 +32,25 @@ extern "C" {
|
|||
|
||||
cy_rslt_t cybsp_init(void)
|
||||
{
|
||||
cy_rslt_t result = CY_RSLT_SUCCESS;
|
||||
|
||||
init_cycfg_system();
|
||||
cy_rslt_t result = cybsp_led_init(CYBSP_USER_LED1);
|
||||
result |= cybsp_led_init(CYBSP_USER_LED2);
|
||||
result |= cybsp_btn_init(CYBSP_USER_BTN1);
|
||||
|
||||
#if defined(CYBSP_RETARGET_ENABLED)
|
||||
/* Initialize retargetting stdio to 'DEBUG_UART' peripheral */
|
||||
result = cybsp_register_sysclk_pm_callback();
|
||||
|
||||
#ifndef __MBED__
|
||||
if (CY_RSLT_SUCCESS == result)
|
||||
{
|
||||
result = cybsp_retarget_init();
|
||||
/* Initialize User LEDs */
|
||||
result |= cybsp_led_init(CYBSP_USER_LED1);
|
||||
result |= cybsp_led_init(CYBSP_USER_LED2);
|
||||
/* Initialize User Buttons */
|
||||
result |= cybsp_btn_init(CYBSP_USER_BTN1);
|
||||
|
||||
/* Initialize retargetting stdio to 'DEBUG_UART' peripheral */
|
||||
if (CY_RSLT_SUCCESS == result)
|
||||
{
|
||||
result = cybsp_retarget_init();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,36 @@
|
|||
/***************************************************************************//**
|
||||
* \file CY8CPROTO-064-SB/cybsp.h
|
||||
*
|
||||
* Description:
|
||||
* Provides APIs for interacting with the hardware contained on the Cypress
|
||||
* CY8CPROTO-064-SB prototyping kit.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2018-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "cybsp_types.h"
|
||||
#include "cybsp_core.h"
|
||||
#ifndef __MBED__
|
||||
#include "cybsp_retarget.h"
|
||||
#endif /* __MBED__ */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,74 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cybsp_cy8cproto_064_sb.h
|
||||
*
|
||||
* Description:
|
||||
* Provides APIs for interacting with the hardware contained on the Cypress
|
||||
* CY8CPROTO-064-SB pioneer kit.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2018-2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
/**
|
||||
* \addtogroup group_bsp_cy8cproto_064_sb CY8CPROTO-064-SB
|
||||
* \ingroup group_bsp
|
||||
* \{
|
||||
* CY8CPROTO-064-SB PSoC 64 SecureBoot Prototyping Kit is a low-cost Prototyping
|
||||
* Kit based on PSoC 64 SecureBoot MCU to enable customers to prototype and
|
||||
* design with the PSoC 64 SecureBoot device.
|
||||
*
|
||||
* <div class="category">Kit Features:</div>
|
||||
* <ul>
|
||||
* <li>PSoC 64 Secure MCU that combines IoT platform software, a root-of-trust with secure services, and the ultra-low power, hardware-based security capabilities of the PSoC 6 MCU architecture </li>
|
||||
* <li>128 Mb Serial NOR flash</li>
|
||||
* <li>Full-speed USB device interface</li>
|
||||
* </ul>
|
||||
*
|
||||
* <div class="category">Kit Contents:</div>
|
||||
* <ul>
|
||||
* <li>PSoC 64 SecureBoot Prototyping Board</li>
|
||||
* <li>USB Type-A to Micro-B cable</li>
|
||||
* <li>Quick start guide</li>
|
||||
* </ul>
|
||||
*
|
||||
* \defgroup group_bsp_cy8cproto_064_sb_macros Macros
|
||||
* \defgroup group_bsp_cy8cproto_064_sb_functions Functions
|
||||
* \defgroup group_bsp_cy8cproto_064_sb_enums Enumerated Types
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "cybsp_api_core.h"
|
||||
#include "cybsp_types.h"
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** \cond INTERNAL */
|
||||
|
||||
// TODO: add BSP pin mappings
|
||||
|
||||
/** \endcond */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/** \} group_bsp_cy8cproto_064_sb */
|
||||
|
|
@ -23,14 +23,6 @@
|
|||
* limitations under the License.
|
||||
*******************************************************************************/
|
||||
|
||||
/**
|
||||
* \addtogroup group_bsp_cy8cproto_064_sb CY8CPROTO-064-SB
|
||||
* \ingroup group_bsp
|
||||
* \{
|
||||
* \defgroup group_bsp_cy8cproto_064_sb_macros Macros
|
||||
* \defgroup group_bsp_cy8cproto_064_sb_enums Enumerated Types
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "cyhal.h"
|
||||
|
|
@ -40,7 +32,7 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
/**
|
||||
* \addtogroup group_bsp_cy8cproto_064_sb_macros
|
||||
* \addtogroup group_bsp_pins Pin Mappings
|
||||
* \{
|
||||
*/
|
||||
|
||||
|
|
@ -109,10 +101,10 @@ extern "C" {
|
|||
/** Pin: USB Device D- */
|
||||
#define CYBSP_USB_DM P14_1
|
||||
|
||||
/** \} group_bsp_cy8cproto_064_sb_macros */
|
||||
/** \} group_bsp_pins */
|
||||
|
||||
/**
|
||||
* \addtogroup group_bsp_cy8cproto_064_sb_enums
|
||||
* \addtogroup group_bsp_enums Enumerated Types
|
||||
* \{
|
||||
*/
|
||||
|
||||
|
|
@ -148,10 +140,8 @@ typedef enum
|
|||
CYBSP_USER_BTN1 = CYBSP_SW2,
|
||||
} cybsp_btn_t;
|
||||
|
||||
/** \} group_bsp_cy8cproto_064_sb_enums */
|
||||
/** \} group_bsp_enums */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/** \} group_bsp_cy8cproto_064_sb */
|
||||
|
|
|
|||
|
|
@ -1,63 +0,0 @@
|
|||
<?xml version="1.0"?>
|
||||
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 635-->
|
||||
<Configuration app="QSPI" major="2" minor="0">
|
||||
<DevicePath>PSoC 6.xml</DevicePath>
|
||||
<SlotConfigs>
|
||||
<SlotConfig>
|
||||
<SlaveSlot>0</SlaveSlot>
|
||||
<PartNumber>S25FL128S</PartNumber>
|
||||
<MemoryMapped>false</MemoryMapped>
|
||||
<DualQuad>None</DualQuad>
|
||||
<StartAddress>0x18000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
<EndAddress>0x1800FFFF</EndAddress>
|
||||
<WriteEnable>true</WriteEnable>
|
||||
<Encrypt>false</Encrypt>
|
||||
<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
|
||||
<MemoryConfigsPath>S25FL128S</MemoryConfigsPath>
|
||||
<ConfigDataInFlash>false</ConfigDataInFlash>
|
||||
</SlotConfig>
|
||||
<SlotConfig>
|
||||
<SlaveSlot>1</SlaveSlot>
|
||||
<PartNumber>Not used</PartNumber>
|
||||
<MemoryMapped>false</MemoryMapped>
|
||||
<DualQuad>None</DualQuad>
|
||||
<StartAddress>0x18010000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
<EndAddress>0x1801FFFF</EndAddress>
|
||||
<WriteEnable>false</WriteEnable>
|
||||
<Encrypt>false</Encrypt>
|
||||
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
|
||||
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
|
||||
<ConfigDataInFlash>false</ConfigDataInFlash>
|
||||
</SlotConfig>
|
||||
<SlotConfig>
|
||||
<SlaveSlot>2</SlaveSlot>
|
||||
<PartNumber>Not used</PartNumber>
|
||||
<MemoryMapped>false</MemoryMapped>
|
||||
<DualQuad>None</DualQuad>
|
||||
<StartAddress>0x18020000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
<EndAddress>0x1802FFFF</EndAddress>
|
||||
<WriteEnable>false</WriteEnable>
|
||||
<Encrypt>false</Encrypt>
|
||||
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
|
||||
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
|
||||
<ConfigDataInFlash>false</ConfigDataInFlash>
|
||||
</SlotConfig>
|
||||
<SlotConfig>
|
||||
<SlaveSlot>3</SlaveSlot>
|
||||
<PartNumber>Not used</PartNumber>
|
||||
<MemoryMapped>false</MemoryMapped>
|
||||
<DualQuad>None</DualQuad>
|
||||
<StartAddress>0x18030000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
<EndAddress>0x1803FFFF</EndAddress>
|
||||
<WriteEnable>false</WriteEnable>
|
||||
<Encrypt>false</Encrypt>
|
||||
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
|
||||
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
|
||||
<ConfigDataInFlash>false</ConfigDataInFlash>
|
||||
</SlotConfig>
|
||||
</SlotConfigs>
|
||||
</Configuration>
|
||||
|
|
@ -1,85 +0,0 @@
|
|||
/*
|
||||
* mbed Microcontroller Library
|
||||
* Copyright (c) 2017-2018 Future Electronics
|
||||
* Copyright (c) 2019 Cypress Semiconductor Corporation
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file defines hardware resources reserved by device-generated code. These
|
||||
* resources are accessed directly by the Peripheral Driver library (PDL).
|
||||
*
|
||||
* There are four classes of resources that must be declared here:
|
||||
* 1 CYCFG_ASSIGNED_PORTS macro defines which ports and pins are reserved.
|
||||
* You define these as a colon separated list of ports and pins reserved
|
||||
* using macro SRM_PORT(port_num, pins), once for each reserved port.
|
||||
* SRM_PORT macro arguments are port number (in the range 0 ... 14) and
|
||||
* pins, which is a hex value with a bit set for each reserved pin on a port.
|
||||
*
|
||||
* 2 CYCFG_ASSIGNED_DIVIDERS macro defines which clock dividers are reserved.
|
||||
* You define these as a colon separated list of dividers reserved
|
||||
* using macro SRM_DIVIDER(type, reservations), once for each required
|
||||
* divider type.
|
||||
* SRM_DIVIDER arguments are divider type (one of cy_en_divider_types_t
|
||||
* values) and reservations, which is a hex mask value with a bit set for
|
||||
* each reserved divider of a given type.
|
||||
*
|
||||
* 3 CYCFG_ASSIGNED_SCBS macro defines which SCB blocks are reserved.
|
||||
* You define these as a colon separated list of SCBs reserved using
|
||||
* macro SRM_SCB(n), which argument is SCB number in a range 0 ... 7.
|
||||
*
|
||||
* 4 CYCFG_ASSIGNED_TCPWM macro defines which TCPWM blocks are reserved.
|
||||
* You define these as a colon separated list of TCPWMs reserved using
|
||||
* macro SRM_TCPWM(n), which argument is TCPWM number in a range 0 ... 31.
|
||||
*
|
||||
* Examples:
|
||||
* #define CYCFG_ASSIGNED_PORTS SRM_PORT(0, 0x30), SRM_PORT(5, 0x03)
|
||||
*
|
||||
* #define CYCFG_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x01)
|
||||
*
|
||||
* #define CYCFG_ASSIGNED_SCBS SRM_SCB(2)
|
||||
*
|
||||
* #define CYCFG_ASSIGNED_TCPWMS
|
||||
*
|
||||
*/
|
||||
|
||||
/* P0_0 and P0_1 reserved for WCO,
|
||||
* P1_0 reserved for CSD TX,
|
||||
* P2_0 ... P2_5 reserved for SDHC
|
||||
* P6-4, P6-6 and P6_7 reserved for SWD,
|
||||
* P7_1, P7_2 and P7_7 reserved for CSD Capacitors
|
||||
* P8_1 ... P8_7 reserved for CSD Buttons
|
||||
* P11_2 ... P11_7 reserved for QSPI
|
||||
* P14_0 ... P14_1 reserved for USB
|
||||
*/
|
||||
#define CYCFG_ASSIGNED_PORTS SRM_PORT(0, 0x03), SRM_PORT(1, 0x01),\
|
||||
SRM_PORT(2, 0x3f), SRM_PORT(6, 0xd0),\
|
||||
SRM_PORT(7, 0x86), SRM_PORT(8, 0xfe),\
|
||||
SRM_PORT(11, 0xfc), SRM_PORT(14, 0x03)
|
||||
|
||||
/*
|
||||
* 8-bit divider 0 reserved for UDB
|
||||
* 8-bit divider 4 reserved for CSD
|
||||
* 16-bit divider 0 reserved for USB
|
||||
*/
|
||||
#define CYCFG_ASSIGNED_DIVIDERS SRM_DIVIDER(CY_SYSCLK_DIV_8_BIT, 0x11), \
|
||||
SRM_DIVIDER(CY_SYSCLK_DIV_16_BIT, 0x01)
|
||||
|
||||
#define CYCFG_ASSIGNED_SCBS
|
||||
|
||||
#define CYCFG_ASSIGNED_TCPWMS
|
||||
|
||||
/* End of File */
|
||||
|
|
@ -688,7 +688,7 @@ class PSOC6Code:
|
|||
"is not compatible with Cypress Secure Boot target. "
|
||||
"You are using Python " + str(sys.version[:5]) +
|
||||
" which is not supported by CySecureTools. "
|
||||
"Consider installing Python 3.7+ and rebuild target. "
|
||||
"Consider installing Python 3.4+ and rebuild target. "
|
||||
"For more information refver to User Guide https://www.cypress.com/secureboot-sdk-user-guide")
|
||||
else:
|
||||
from tools.targets.PSOC6 import sign_image as psoc6_sign_image
|
||||
|
|
|
|||
Loading…
Reference in New Issue