Make the CY8CKIT_064S2_4343W target TF-M compatible by addding flash and
region definitions from TF-M (at c4f37c18c4a0) and by updating the
CY8CKIT_064S2_4343W linker script to create a flash image compatible
with TF-M.
Signed-off-by: Jaeden Amero <jaeden.amero@arm.com>
There are two timers, Timer0 and Timer1, available on the PSoC64. Timer0
has 8 channels and Timer1 has 24 channels. TF-M regression tests make
use of Timer0 Channel 0 and Timer0 Channel 1. Therefore, reserve the
timer channels used by TF-M. This approach can be replaced once we have
a way to allocate dedicated timers for TF-M and Mbed OS.
Signed-off-by: Devaraj Ranganna <devaraj.ranganna@arm.com>
Signed-off-by: Vikas Katariya <vikas.katariya@arm.com>
For the application(firmware) booted by bootloader(OTA),
the image doesn't need the "flash_config" and "ivt" header.
So update the link file to support both kinds of application
(firmware) booted by bootROM and bootloader.
In default, the compilation will get the image with
"flash_config" and "ivt" header, for example the bootloader
compiling.
When compiling the OTA application image, please add the
line as below in the mbed_app.json file.
"target.macros_add" : ["MBED_APP_COMPILE"]
This will remove the "flash_config" and "ivt" header in the
final image.
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
Update the flash driver to support both Hyper Flash
and QSPI Flash.
In addition, the static function cannot be linked to
SRAM even defined by AT_QUICKACCESS_SECTION_CODE macro.
So remove all "static" modifier for the FLASHIAP
functions.
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
The memset function from c library will be linked in flash
space, it's risk for FLASHIAP. So I wrote flexspi_memset
to replace the memset for IMX FLASHIAP, and put the function
into targets/.../TARGET_IMX/flash_api.c file. All IMX Soc
platforms can declare it as extern and use in their Soc
flexspi driver files.
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
The flash access may fail when implementing flash
initialization. So there is risk for interrupt handler
which linked in flash space.
Add the critical section to avoid the risk.
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
NXP MIMXRT1050 EVK can support Hyper Flash or QSPI Flash with
small hardware reworks. Modify the XIP file to support boot
from the two kinds of Flash device. The Hyper Flash should be
the default device and defined in tartgets.json with the macro
"HYPERFLASH_BOOT". To select the QSPI Flash, just remove the
macro with the below line in any overriding json file.
"target.macros_remove" : ["HYPERFLASH_BOOT"]
Signed-off-by: Gavin Liu <gang.liu@nxp.com>
In case when target.mbed_ram_start and target.mbed_ram_size are not set
neither in targets.json nor in mbed_app.json, the IRAM1 region values
defined in tools/arm_pack_manager/index.json are passed by Mbed CLI as
the linker script preprocessing flags. As a result, wrong addresses of
MBED_RAM_START and MBED_RAM_SIZE are defined in the linker script since
CMSIS DFP pack has no information about RAM split between CM0+ and CM4 applications.
Set the values explicitly in targets.json to ensure the correct RAM layout.
The MBED_ROM_START and MBED_ROM_SIZE provided by CMSIS DFP are already
correct since the linker scripts places CM4 vector table at MBED_APP_START,
taking into account the flash application area of the CM0+ prebuilt application.
Relevant modifications:
1. Support degrading QSPI0/1 to SPI4/5 for normal SPI transfer
2. Fix with BSP crypto driver API change
3. Fix with BSP PDMA driver API change
4. Make necessary modifications to pass FPGA CI Test Shield tests
5. Don't distinguish pinmap among parts e.g. M480 LG. Application users must take care.
Most code doesn't check return code of CLK_WaitClockReady(...). Enlarge timeout to meet most cases.
lp_ticker initialization fails with this issue. Steps for reproducing:
1. System runs in tickless from lp_ticker mode.
2. Arm WDT reset.
3. In next reset cycle, lp_ticker initialization fails (active flag doesn't become active).
- PHY default configuration can be changed
- AutoNegotiation
- Speed
- DuplexMode
- PHY register offset can be updated depending on chosen PHY
All unused parameters are cleaned.
When UART interrupt enabled and WDT reset from power-down mode, in the next
cycle, UART interrupt keeps breaking in and cannot block unless via NVIC. To
get around it, we deliberately make up a signal of WDT wake-up from power-down
mode in the start of boot proces when WDT reset is detected.
Use an RTCC retention register to keep track of user timebase for RTC API. RTC and LP Ticker implementations use the same counter, but they shouldn't share timebases.
By default D0 - D3 pins are used for the bit-banged SPI com channel between mbed target and the FPGA-test-shield.
For some reason, if pins were used as GPIOs and then reconfigured to I2C pins the I2C com does not work on NRF52840.
This commit modifies i2c_configure_twi_instance() function and adds proper initialization of the I2C pins.
Musca-B1 is a Cortex-M33 based target with security extension enabled.
- ARM_MUSCA_B1 is the non-secure target running mbed-os.
- ARM_MUSCA_B1_S is the secure target running TF-M.
- TF-M sources were imported and patched in previous commits.
- TF-M secure bootloader (McuBoot) for MUSCA_B1 is submitted by a
pre-built binary.
- A post-build hook concatenates The secure and non-secure binaries,
signs it and then concatenates the bootloader with the signed binary.
Change-Id: I4b36290941b5f0bb7aa7c12dda2f38b5c1e39ae2
Signed-off-by: Tamas Kaman <tamas.kaman@arm.com>
Signed-off-by: Gabor Abonyi <gabor.abonyi@arm.com>
Static pinmap extension required to use pin_function() and pin_mode() functions instead of pinmap_pinout(). Unfortunatelly pin_function() does not allow passing NC pin.
Call pin_function() and pin_mode() only if MISO/MOSI pin is not NC.
In no MISO case, skip SPI read so that no more write/read delay contribute to SPI inter-frame delay when data is written successively.
Update targets:
- NUMAKER_PFM_NANO130
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M453
- NUMAKER_PFM_M487/NUMAKER_IOT_M487
- NU_PFM_M2351_*
- NUMAKER_IOT_M263A
- NUMAKER_M252KG
Make a Mbed library with Cypress WHD files so it is automatically excluded
when building with the bare metal profile. Create another Mbed library to
group network files that use WHD so they can also be excluded fro the bare
metal profile.
This bug results from BSP update:
- CRPT: Base address of secure or non-secure crypto module, dependent on partition
- CRPT_S: Base address of secure crypto module
- CRPT_NS: Base address of non-secured crypto module
The clock source selection of LPUART depends on System clocks but also on
the serial baudrate. There is a specific computation done in serial driver
targets/target_STM/serial_api.c
At first start-up the LPUART1 clock selected in SetSysClock was anyway
overridden by the serial driver, so this was of no effect. But in case
of deep sleep SetSysClock is called again, while the driver isn't, so
SetSyClock was corrupting the serial clock configuration.
So let's remove these few lines of code which are causing trouble.
Remove an obsolete HAL implementation from LPC408X to fix the GCC_ARM
build with the "-flto" flag.
With the lto enabled, unreferenced buffers defined in ethernet_api.c
were not excluded at link time overflowing the 16kB peripheral SRAM1
(ld error: "section '.AHBSRAM1' will not fit in region 'ETH_RAM'").
The Ethernet HAL API is deprecated in favor of EMAC.
While testing it has been found that all tests are skipped in the FPGA uart test on the NRF52840 target.
This is caused by the following change:
https://github.com/ARMmbed/mbed-os/pull/12379 - Add STDIO UART as restricted for FPGA testing for all targets
NRF targets have MUXed pins and mainly do not provide pin-maps. There are only dummy pin-maps for testing.
These pin-maps hold only pins and do not specify the peripheral or function of the pin (always 0). Because of that if we restrict STDIO uart peripheral (0) all FPGA uart test cases will be skipped.
To fix this we will remove this restriction for NRF52840. Restriction for testing the USBTX, USBRX pins is sufficient in this case.
Align with mainline BSP and fix relevant bugs:
1. Align with SPI module naming
(1) Remove SPI5
(2) Degrade QSPI0 to SPI4 so that it can use for standard SPI
2. Fix some code lacking GPIO H
3. Implement __PC(...) by following BSP instead of with MBED_CALLER_ADDR()
4. Add SCU_IRQHandler(). Change printf(...) with interrupt-safe error(...)
5. Other minor alignment change
The existing logic was insufficient to properly handle odd and even
parity setting, e.g. serial_getc() returned 9-bit data for 8O1
transmission format.
1. Do not disable and enable osillators during deep sleep
entry and exit
2. Increase the deep sleep to pass tests
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
It is required by Mbed HAL API to generate TxIrq interrupt when TXD register is empty (also after enabling TxIrq interrupt):
f73a62afbf/hal/serial_api.h (L144-L147)
The driver uses DMA to perform uart transfer and TxIrq is generated after the transfer is finished.
While enabling TxIrq we will check if TXD reg is empty and manually trigger the interrupt.
1. Re-organize to make clear for all targets/toolchains support in single startup file
2. Inline assembly syntax is limited, esp. on IAR. Try paving the way for accessing external symbols still in inline assembly instead of re-write in assembly.
1. Enable GCC support on non-secure targets
2. Disable GCC support on secure targets becasue of GCC bug (as of 9-2019-q4-major): In non-secure entry function, callee-saved registers must be restored, but they are incorrectly cleared at optimization level "Os".
In STM32 Cube HAL, in interrupt mode (async),
2 bytes can be prepared in hardware registers without any read
(1 in regular register, the other in shift register),
but Only 1 RX byte can stored in hardware register, specially when there is no hardware FIFO.
If interrupt handling is fast enough, each read is made in parralele of the write.
But if interrupt handling is too long or is interrupted for too long,
it can happen that one read byte is lost (overrun).
For STM32F4, Tickless has been deactivated to avoid such issue.
For STM32L0, we don't want to deactivate tickless,
because those chips are specially design for lowpower.
So instead of removing SPI async mode,
we propose to change the HAL behavior specially for L0:
each byte is send only when previous read is performed.
Thus only 1 RX byte at a time which is saved in hardware register.
This prevent overrun, but it introduceS some latency between each byte send,
this is why it is not applied to all STM32 families.
Add a "used" attribute to __vector_handlers to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST. )
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
Add a "used" attribute to __vector_handlers to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST.)
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
Add a "used" attribute to __vector_handlers to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST.)
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
Add a "used" attribute to __vector_handlers to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST.)
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
Add a "used" attribute to __vector_handlers to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST.)
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
Add a "used" attribute to __vector_handlers to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST. )
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
Add a "used" attribute to __vector_handlers to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST. )
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
Add a "used" attribute to interruptVectors to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST. )
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
Add a "used" attribute to hyperflash_config/image_vector_table to fix ARMC6 build with
the "-flto" flag.
(Error: L6236E: No section matches selector - no section to be FIRST/LAST. )
This attribute, attached to a function/variable, means that code must be emitted
for the function even if it appears that the function is not referenced.
Add a "used" attribute to IVT_NAME/blank_checksum
to fix ARMC6 build with the "-flto" flag. (Error: L6236E: No section matches
selector - no section to be FIRST/LAST. )
This attribute, attached to a function, means that code must be emitted
for the function even if it appears that the function is not referenced.
Add a "used" attribute to IVT_NAME/blank_checksum
to fix ARMC6 build with the "-flto" flag. (Error: L6236E: No section matches
selector - no section to be FIRST/LAST. )
This attribute, attached to a function, means that code must be emitted
for the function even if it appears that the function is not referenced.
Add a "used" attribute to ulDebugHeader (placed in signature_section section)
to fix ARMC6 build with the "-flto" flag. (Error: L6236E: No section matches
selector - no section to be FIRST/LAST. )
This attribute, attached to a function, means that code must be emitted
for the function even if it appears that the function is not referenced.
Fix for the error caused by lto on armc6 compiler:
L6137E: Symbol RTC_IRQHandler was not preserved by the LTO codegen but is needed by the image.
lto optimization cause that local symbol RTC_IRQHandler(from rtc_api.c)
somehow interferes with global symbol RTC_IRQHandler (from startup_stm32f070xb.S)
Changing local RTC_IRQHandler to _RTC_IRQHandler fixes problem
Add a "used" attribute to Reset_Handler_Cascade to fix GCC build with
the "-flto" flag.
This attribute, attached to a function, means that code must be emitted
for the function even if it appears that the function is not referenced.
Acording to the description in `gpio_irq_hal_api.h` file `gpio_irq_init()` should return 0 on success.
Currently, it returns 1 causing the FPGA test to fail.
MarceloSalazar
Martin Kojtal
Sree Harsha Angara
Rajkumar Kanagaraj
YARB(Cypress)
Taylor Heck
Roman Okhrimenko
Dustin Crossman
Jaeden Amero
Devaraj Ranganna
Gavin Liu
George Beckstein
George Beckstein
Volodymyr Medvid
heejungPark
Chun-Chieh Li
amq
jeromecoutant
mudassar-ublox
RyoheiHagimoto
Anna Bridge
petroborys
Volodymyr Medvid
Teemu Takaluoma
Tymoteusz Bloch
Evelyne Donnaes
Steven Cooreman
Przemyslaw Stekiel
midd
Tamas Kaman
Alan Mock
Filip Jagodzinski
Bartek Szatkowski
Eduardo Avelar
Hugues Kamba
Stephen Blackheath
Alvin Lee
Laurent Meunier
thegecko
Gabor Abonyi
Michal Paszta
Mahesh Mahadevan
Alexandre Bourdiol
Maciej Bocianski
Filip Jagodzinski
Pawel Zarembski
Qinghao Shi