mirror of https://github.com/ARMmbed/mbed-os.git
STM32 EMAC : more configurable
- PHY default configuration can be changed - AutoNegotiation - Speed - DuplexMode - PHY register offset can be updated depending on chosen PHY All unused parameters are cleaned.pull/12464/head
jeromecoutant
parent
c2c6d251fd
commit
1b40076376
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@ -3,9 +3,37 @@
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"config": {
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"eth-rxbufnb": 4,
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"eth-txbufnb": 4,
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"eth-phyaddr": {
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"eth-phy-address": {
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"help" : "Configures actual PHY address according to pullup/down status of PHYAD pin(s)",
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"value" : 0
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},
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"eth-phy-AutoNegotiation": {
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"help" : "Selects AutoNegotiation mode : ETH_AUTONEGOTIATION_ENABLE / ETH_AUTONEGOTIATION_DISABLE",
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"value" : "ETH_AUTONEGOTIATION_ENABLE"
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},
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"eth-phy-DuplexMode": {
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"help" : "Selects DuplexMode mode : ETH_MODE_FULLDUPLEX / ETH_MODE_HALFDUPLEX",
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"value" : "ETH_MODE_FULLDUPLEX"
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},
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"eth-phy-Speed": {
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"help" : "Selects Speed mode : ETH_SPEED_100M / ETH_SPEED_10M",
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"value" : "ETH_SPEED_100M"
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},
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"eth-phy-reset-delay": {
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"help" : "Reset process time - Default value: 0.5s as specified in LAN8742A datasheet",
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"value" : "500"
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},
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"eth-phy-status-register": {
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"help" : "PHY register Offset with auto-negotiation result - Default value is LAN8742A PHY Special Control/Status Register",
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"value" : "31"
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},
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"eth-phy-speed-status": {
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"help" : "Speed mask information in eth-phy-status-register",
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"value" : "0x0004"
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},
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"eth-phy-duplex-status": {
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"help" : "Duplex mask information in eth-phy-status-register",
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"value" : "0x0010"
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}
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},
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"target_overrides": {
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@ -14,7 +42,7 @@
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"eth-txbufnb": 4
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},
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"ARCH_MAX": {
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"eth-phyaddr": 1
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"eth-phy-address": 1
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}
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}
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}
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@ -43,7 +43,6 @@
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#define THREAD_PRIORITY (osPriorityHigh)
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#define PHY_TASK_PERIOD_MS 200
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#define ETH_PHY_ADDRESS MBED_CONF_STM32_EMAC_ETH_PHYADDR
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#define STM_HWADDR_SIZE (6)
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#define STM_ETH_MTU_SIZE 1500
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@ -279,10 +278,10 @@ bool STM32_EMAC::low_level_init_successful()
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/* Init ETH */
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uint8_t MACAddr[6];
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EthHandle.Instance = ETH;
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EthHandle.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
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EthHandle.Init.Speed = ETH_SPEED_100M;
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EthHandle.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
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EthHandle.Init.PhyAddress = ETH_PHY_ADDRESS;
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EthHandle.Init.AutoNegotiation = MBED_CONF_STM32_EMAC_ETH_PHY_AUTONEGOTIATION;
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EthHandle.Init.Speed = MBED_CONF_STM32_EMAC_ETH_PHY_SPEED;
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EthHandle.Init.DuplexMode = MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEXMODE;
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EthHandle.Init.PhyAddress = MBED_CONF_STM32_EMAC_ETH_PHY_ADDRESS;
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#if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
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MACAddr[0] = MBED_MAC_ADDR_0;
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MACAddr[1] = MBED_MAC_ADDR_1;
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@ -1,4 +1,6 @@
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/* Copyright (c) 2017 ARM Limited
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* Copyright (c) 2017 STMicroelectronics
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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@ -176,4 +178,4 @@ private:
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int phy_task_handle; /**< Handle for phy task event */
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};
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#endif /* K64F_EMAC_H_ */
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#endif /* STM32_EMAC_H_ */
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@ -162,75 +162,52 @@
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/* ################## Ethernet peripheral configuration ##################### */
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/* Section 1 : Ethernet peripheral configuration */
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/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
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#define MAC_ADDR0 2U
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#define MAC_ADDR1 0U
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#define MAC_ADDR2 0U
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#define MAC_ADDR3 0U
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#define MAC_ADDR4 0U
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#define MAC_ADDR5 0U
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/* Definition of the Ethernet driver buffers size and count */
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#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
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#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
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/* Definition of the Ethernet driver buffers size and count */
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#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
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#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
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#ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB
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#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
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#endif
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#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB
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#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
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/* default value in features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json */
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#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
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#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
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#else
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/* ex: bare metal profile */
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#define ETH_RXBUFNB 0 /* Rx buffers of size ETH_RX_BUF_SIZE */
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#define ETH_TXBUFNB 0 /* Tx buffers of size ETH_TX_BUF_SIZE */
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#endif
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/* Section 2: PHY configuration section */
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/* DP83848 PHY Address*/
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#define DP83848_PHY_ADDRESS 0x01U
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/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
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#define PHY_RESET_DELAY 0x000000FFU
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/* PHY Configuration delay */
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/* PHY delay */
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#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
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#define PHY_RESET_DELAY MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
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#else
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#define PHY_RESET_DELAY 0
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#endif
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#define PHY_CONFIG_DELAY 0x00000FFFU
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#define PHY_READ_TO 0x0000FFFFU
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#define PHY_WRITE_TO 0x0000FFFFU
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/* Section 3: Common PHY Registers */
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#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
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#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
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#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
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#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
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#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
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#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
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#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
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#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
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#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
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#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
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#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
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#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
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#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
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#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
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#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
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#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
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#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
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#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
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#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
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#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
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#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
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/* Section 4: Extended PHY Registers */
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#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
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#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
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#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
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#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
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#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
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#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
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#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
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#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
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#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
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#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
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#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER
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#define PHY_SR MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER /*!< PHY status register Offset */
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#define PHY_SPEED_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_SPEED_STATUS /*!< PHY Speed mask */
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#define PHY_DUPLEX_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEX_STATUS /*!< PHY Duplex mask */
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#else
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#define PHY_SR 0
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#define PHY_SPEED_STATUS 0
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#define PHY_DUPLEX_STATUS 0
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#endif
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/* ################## SPI peripheral configuration ########################## */
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@ -170,75 +170,52 @@
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/* ################## Ethernet peripheral configuration ##################### */
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/* Section 1 : Ethernet peripheral configuration */
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/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
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#define MAC_ADDR0 2U
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#define MAC_ADDR1 0U
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#define MAC_ADDR2 0U
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#define MAC_ADDR3 0U
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#define MAC_ADDR4 0U
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#define MAC_ADDR5 0U
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/* Definition of the Ethernet driver buffers size and count */
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#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
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#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
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#ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB
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#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
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#endif
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#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB
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#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
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/* default value in features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json */
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#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
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#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
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#else
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/* ex: bare metal profile */
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#define ETH_RXBUFNB 0 /* Rx buffers of size ETH_RX_BUF_SIZE */
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#define ETH_TXBUFNB 0 /* Tx buffers of size ETH_TX_BUF_SIZE */
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#endif
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/* Section 2: PHY configuration section */
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/* DP83848 PHY Address*/
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#define DP83848_PHY_ADDRESS 0x01U
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/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
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#define PHY_RESET_DELAY 0x000000FFU
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/* PHY Configuration delay */
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/* PHY delay */
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#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
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#define PHY_RESET_DELAY MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
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#else
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#define PHY_RESET_DELAY 0
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#endif
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#define PHY_CONFIG_DELAY 0x00000FFFU
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#define PHY_READ_TO 0x0000FFFFU
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#define PHY_WRITE_TO 0x0000FFFFU
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/* Section 3: Common PHY Registers */
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#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
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#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
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#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
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#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
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#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
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#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
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#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */
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#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */
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#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */
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#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */
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#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */
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#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */
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#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */
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#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
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#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
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#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */
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#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
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#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
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#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
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#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
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#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
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/* Section 4: Extended PHY Registers */
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#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
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#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
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#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
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#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
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#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
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#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
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#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */
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#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */
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#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */
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#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */
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#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER
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#define PHY_SR MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER /*!< PHY status register Offset */
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#define PHY_SPEED_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_SPEED_STATUS /*!< PHY Speed mask */
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#define PHY_DUPLEX_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEX_STATUS /*!< PHY Duplex mask */
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#else
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#define PHY_SR 0
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#define PHY_SPEED_STATUS 0
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#define PHY_DUPLEX_STATUS 0
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#endif
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/* ################## SPI peripheral configuration ########################## */
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@ -196,41 +196,29 @@
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/* ################## Ethernet peripheral configuration ##################### */
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/* Section 1 : Ethernet peripheral configuration */
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/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
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#define MAC_ADDR0 2U
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#define MAC_ADDR1 0U
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#define MAC_ADDR2 0U
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#define MAC_ADDR3 0U
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#define MAC_ADDR4 0U
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#define MAC_ADDR5 0U
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/* Definition of the Ethernet driver buffers size and count */
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/* Definition of the Ethernet driver buffers size and count */
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#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
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#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
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#ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB
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#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
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/* default value in features/netsocket/emac-drivers/TARGET_STM/mbed_lib.json */
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#define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */
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#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
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#else
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#define ETH_RXBUFNB 4 /* Rx buffers of size ETH_RX_BUF_SIZE */
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#endif
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#ifdef MBED_CONF_STM32_EMAC_ETH_TXBUFNB
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#define ETH_TXBUFNB MBED_CONF_STM32_EMAC_ETH_TXBUFNB /* Tx buffers of size ETH_TX_BUF_SIZE */
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#else
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#define ETH_TXBUFNB 4 /* Rx buffers of size ETH_TX_BUF_SIZE */
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/* ex: bare metal profile */
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#define ETH_RXBUFNB 0 /* Rx buffers of size ETH_RX_BUF_SIZE */
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#define ETH_TXBUFNB 0 /* Tx buffers of size ETH_TX_BUF_SIZE */
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#endif
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/* Section 2: PHY configuration section */
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/* DP83848 PHY Address*/
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#define DP83848_PHY_ADDRESS 0x01U
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/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
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#define PHY_RESET_DELAY 0x000000FFU
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/* PHY Configuration delay */
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/* PHY delay */
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#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
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#define PHY_RESET_DELAY MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY
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#else
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#define PHY_RESET_DELAY 0
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#endif
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#define PHY_CONFIG_DELAY 0x00000FFFU
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||||
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||||
#define PHY_READ_TO 0x0000FFFFU
|
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#define PHY_WRITE_TO 0x0000FFFFU
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@ -240,35 +228,20 @@
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#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */
|
||||
|
||||
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */
|
||||
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */
|
||||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */
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||||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */
|
||||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */
|
||||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */
|
||||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */
|
||||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */
|
||||
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */
|
||||
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */
|
||||
|
||||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */
|
||||
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
|
||||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */
|
||||
|
||||
/* Section 4: Extended PHY Registers */
|
||||
|
||||
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */
|
||||
#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */
|
||||
#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */
|
||||
|
||||
#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */
|
||||
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */
|
||||
|
||||
#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */
|
||||
#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */
|
||||
|
||||
#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */
|
||||
#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */
|
||||
#ifdef MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER
|
||||
#define PHY_SR MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER /*!< PHY status register Offset */
|
||||
#define PHY_SPEED_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_SPEED_STATUS /*!< PHY Speed mask */
|
||||
#define PHY_DUPLEX_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEX_STATUS /*!< PHY Duplex mask */
|
||||
#else
|
||||
#define PHY_SR 0
|
||||
#define PHY_SPEED_STATUS 0
|
||||
#define PHY_DUPLEX_STATUS 0
|
||||
#endif
|
||||
|
||||
/* ################## SPI peripheral configuration ########################## */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue