targets:MIMXRT1050: Add QSPI Flash boot support

NXP MIMXRT1050 EVK can support Hyper Flash or QSPI Flash with
small hardware reworks. Modify the XIP file to support boot
from the two kinds of Flash device. The Hyper Flash should be
the default device and defined in tartgets.json with the macro
"HYPERFLASH_BOOT". To select the QSPI Flash, just remove the
macro with the below line in any overriding json file.
	"target.macros_remove" : ["HYPERFLASH_BOOT"]

Signed-off-by: Gavin Liu <gang.liu@nxp.com>

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/xip/evkbimxrt1050_flexspi_nor_config.c

@@ -22,34 +22,59 @@ __attribute__((section(".boot_hdr.conf"), used))
 #pragma location = ".boot_hdr.conf"
 #endif
 
+#ifdef HYPERFLASH_BOOT
 const flexspi_nor_config_t hyperflash_config = {
-    .memConfig =
-        {
-            .tag = FLEXSPI_CFG_BLK_TAG,
-            .version = FLEXSPI_CFG_BLK_VERSION,
-            .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
-            .csHoldTime = 3u,
-            .csSetupTime = 3u,
-            .columnAddressWidth = 3u,
-            // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
-            .controllerMiscOption =
-                (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
-                (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
-            .sflashPadType = kSerialFlash_8Pads,
-            .serialClkFreq = kFlexSpiSerialClk_133MHz,
-            .sflashA1Size = 64u * 1024u * 1024u,
-            .dataValidTime = {16u, 16u},
-            .lookupTable =
-                {
-                    // Read LUTs
-                    FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
-                    FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
-                    FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
-                },
+    .memConfig = {
+        .tag = FLEXSPI_CFG_BLK_TAG,
+        .version = FLEXSPI_CFG_BLK_VERSION,
+        .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad,
+        .csHoldTime = 3u,
+        .csSetupTime = 3u,
+        .columnAddressWidth = 3u,
+        // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
+        .controllerMiscOption =
+        (1u << kFlexSpiMiscOffset_DdrModeEnable) | (1u << kFlexSpiMiscOffset_WordAddressableEnable) |
+        (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | (1u << kFlexSpiMiscOffset_DiffClkEnable),
+        .sflashPadType = kSerialFlash_8Pads,
+        .serialClkFreq = kFlexSpiSerialClk_133MHz,
+        .sflashA1Size = 64u * 1024u * 1024u,
+        .dataValidTime = {16u, 16u},
+        .lookupTable = {
+            // Read LUTs
+            FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xA0, RADDR_DDR, FLEXSPI_8PAD, 0x18),
+            FLEXSPI_LUT_SEQ(CADDR_DDR, FLEXSPI_8PAD, 0x10, DUMMY_DDR, FLEXSPI_8PAD, 0x06),
+            FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
         },
+    },
     .pageSize = 512u,
     .sectorSize = 256u * 1024u,
     .blockSize = 256u * 1024u,
     .isUniformBlockSize = true,
 };
+#else
+const flexspi_nor_config_t qspiflash_config = {
+    .memConfig = {
+        .tag = FLEXSPI_CFG_BLK_TAG,
+        .version = FLEXSPI_CFG_BLK_VERSION,
+        .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
+        .csHoldTime = 3u,
+        .csSetupTime = 3u,
+        .columnAddressWidth = 0u,
+        .configCmdEnable = 0u,
+        .controllerMiscOption = 0u,
+        .deviceType = kFlexSpiDeviceType_SerialNOR,
+        .sflashPadType = kSerialFlash_4Pads,
+        .serialClkFreq = kFlexSpiSerialClk_133MHz,
+        .lutCustomSeqEnable = 0u,
+        .sflashA1Size = 0x00800000u, /* 8MB/64Mbit */
+        .lookupTable = {
+            // Fast read sequence
+            [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
+            [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x02),
+            [2] = FLEXSPI_LUT_SEQ(STOP, 0, 0, STOP, 0, 0),
+            [3] = FLEXSPI_LUT_SEQ(STOP, 0, 0, STOP, 0, 0),
+        },
+    },
+};
+#endif
 #endif /* XIP_BOOT_HEADER_ENABLE */

targets/targets.json

@@ -2890,6 +2890,7 @@
             "XIP_BOOT_HEADER_ENABLE=1",
             "XIP_EXTERNAL_FLASH=1",
             "XIP_BOOT_HEADER_DCD_ENABLE=1",
+            "HYPERFLASH_BOOT",
             "FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE=1",
             "SKIP_SYSCLK_INIT",
             "FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE",