1. For SHA AC, use atomic flag to manage its ownership.
(1) Nuvoton SHA AC doesn't support SHA context save & restore, so S/W
SHA fallback has been supported before. To make non-blocking 'acquire'
semantics clearer, introduce 'try_acquire' to substitute for 'acquire'.
(2) No biting CPU due to mechanism above.
(3) No deadlock due to mechanism above.
2. For AES/DES/ECC AC, change to mutex to manage their ownership.
(1) Change crypto-misc.c to crypto-misc.cpp to utilize C++ SingletonPtr
which guarantees thread-safe mutex construct-on-first-use.
(2) With change to crypto-misc.cpp, add 'extern "C"' modifier to CRYPTO_IRQHandler()
to avoid name mangling in C++.
(3) No priority inversion because mutex has osMutexPrioInherit attribute
bit set.
(4) No deadlock because these AC are all locked for a short sequence
of operations rather than the whole lifetime of mbedtls context.
(5) For double mbedtls_internal_ecp_init() issue, it has been fixed in upper
mbedtls layer. So no need to change ecc init/free flow.
This PR addresses the issue of #8124.
It updates and enriches the wifi connection error type to adapt the Network Socket test plan requirement.
In the meantime, it increases the heap size that allows the transmission of larger packet size.
Description
1. Increase heap size in lwipstack\mbed_lib.json to fulfill bursty TCP and UDP transmission requirement.
2. Modify and enrich wifi connection error types in TARGET_AMEBA\RTWInterface.cpp to adapt the decision logic of the wifi test cases.
3. Add new static constants in TARGET_AMEBA\RTWInterface.h, including 'SSID_MAX_LENGTH', 'PASSPHRASE_MAX_LENGTH' and 'PASSPHRASE_MIN_LENGTH' to help verifying the validity of ssid and passphrase.
Pull request type
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change
Add support for the KW41Z side of the RapidIoT platform. This requires the latest
DAPLink binary to be programmed on the RapidIoT platform, binary can be downloaded
from the below link:
https://armmbed.github.io/DAPLink/
Also, the KW41Z side on RapidIoT does not have a serial port connected to the Debug
terminal. Therefore a SerialPassThrough program should be flashed and running on the
K64F side of RapidIoT platform for the mbed tests to pass.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
targets.json was not specifying the same macro name as the code was
checking for, so setting was ineffective.
Making this work tripped up not-supported checks in ARMv8-M - rather than deal
with making this work, support it instead.
Both ARMv7-M and ARMv8-M slightly reduce code size and runtime impact if
mpu-rom-end is 0x1fffffff, using one fewer region.
This means default setup for ARMv8-M now requires 5 regions, with
mpu-rom-end set to default 0x0fffffff, but this can be put back to 4 by
changing the setting.
### Description
PR #8607 will cause problems for the NRF52832 and the NRF52840
in the online compiler starting with 5.10.2. This PR prevents this problem
by using a toggle in `targets.json` to enable these new defines for every
target except for the NRF52832 and NRF52840.
### Pull request type
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change
The cause of the pelion-enablement test failures for Nuvoton boards
is not caused by or related to the MPU so this patch re-enables the
MPU for these boards.
The cause of the pelion-enablement test failures for the
UBLOX_C030_U201 has been identified and corrected so this patch
re-enables the MPU for this board.
This reverts commit b217c5fe4d.
Turn off MPU for the UBLOX_C030 and MCU_M480 and all targets derived
from these. When the MPU is enabled on these platforms they do not
pass the pelion-enablement tests. Once the root cause is determined
and fixed the MPU can be re-enabled for these targets.
1. Resolve the Error: L6218E: Undefined symbol flash_get_erase_value
2. Bug fix (ADC, USART, etc.)
3. Modify the wrong name (TATGET_GigaDevice-->TARGET_GigaDevice)
4. Add new targets (GD32-F450ZI and GD32-E103VB) support to target.json
5. Add INITIAL_SP macro for GD32-F450ZI and GD32-E103VB
StackTop calculation was not adjusted when ram size was increased by using al 3 ram regions.
This caused memory allocation failures althogh enough free heap was reported
* Modify linker scripts to be compatible with bootloader and PSA
* Add memory protection
* Modify original post-build step to allow link with PSA binaries
* Config kvstore for ITS on FUTURE_SEQUANA_PSA
* Enable PSA-Crypto on PSoC6 with NVSeed
Connection status issue corrected. If the link layer status changes,
the connection status callback is now called correctly.
mbedtls headers from library are removed and the mbed-os one's are used.
When using UARTSerial sending data over the uart follows the sequence
below:
<-TX done ISR runs and sets a software interrupt to pending
<-Software interrupt fires:
-disables TX done interrupt
-calls UARTSerial TX handler which sends bytes until the uart
buffer filled (writeable returns false). Sending a byte
re-enables the TX done interrupt continuing the cycle
Due to this sequence, if the UARTSerial TX handler does not send a byte
then the transmit state machine mentioned above will get stuck with
the TX done interrupt disabled. The events causing this failure:
<-TX done ISR runs and sets a software interrupt to pending
<-Software interrupt fires:
-disables TX done interrupt
-calls UARTSerial TX handler:
-checks writeable which is true and sends a byte
<- interrupted by a higher priority interrrupt
<- TX done ISR runs, setting software interrupt to
pending again
-checks writeable which is true and sends a second byte
-Software interrupt finishes
<-Software interrupt fires:
-disables TX done interrupt
-calls UARTSerial TX handler:
-checks writeable which is false and DOES NOT SEND A BYTE
-Software interrupt finishes, the TX interrupt is still disabled
*-Byte gets sent but TX done ISR does not fire
This patch prevents the TX lockup by removing the code in the
software interrupt which disables the TX done interrupt. Disabling the
TX done interrupt at this point is not necessary so this code is safe
to remove.
With support for checking H/W UART initialized or not, we can simplify stdio management:
1. When serial_init(&stdio_uart) calls in, just set the 'stdio_uart_inited' flag.
2. When serial_free(&stdio_uart) calls in, just clear the 'stdio_uart_inited' flag.
Except above, we needn't make special handling with 'stdio_uart'.
The same H/W UART may be shared by multiple serial_t objects. This fix tries to avoid
re-configuring the same H/W UART in serial_init() when there are multiple serial_t
objects constructed. To re-configure UART, call serial_baud() and serial_format()
explicitly. This can avoid confusion when e.g. a newly constructed serial_t object
changes baudrate unexpectedly in serial_init().
Implement the following:
KVStore base class
TDBStore class
FileSystemStore class
SecureStore class
Global APIs
Configuration framework
Design documentation
RAM/ROM sizes in tools were updated to report entire device size, and in M2351
they were used earlier to report secure/non-secure partition size.
M2351 files are updated to take full RAM/ROM device size and derive secure
and non-secure partition size based on that.
When initializing serial disable all interrupts as some of these may
have been enabled by a bootloader. This ensures that the NRF52
serial driver remains compatible with any bootloader version.
Make the following enhancement:
-Support serial port use without flow control
-Prevent dropped bytes by updating flow control handling
-Remove dead code
Serial port use without flow control:
In the prior implementation there was a window of time between
reloading DMA buffers after a timeout where bytes could be dropped.
This is because the uart needed to be turned off in order to flush the
bytes in the DMA buffer.
This change configures the DMA buffer to only receive one byte at a
time so there is no need to disable the uart to flush it. After each
byte is received the DMA transfer will be over so the transfer will
never be partially complete and need flushing. Since the uart is
always on it is safe to use it even without flow control.
Prevent dropped bytes by updating flow control handling:
To prevent dropped bytes due to high latency the flow control handling
of the RTS line was configured to be asserted automatically by
hardware after each byte. Once the CPU has read the byte and setup
the next receive buffer the RTS line is deasserted to the transfer can
continue. This ensure that when flow control is enabled data won't be
lost due to interrupt latency.
Remove dead code:
With the above changes there is a lot of dead code, such as the timer
handling code. This patch removes the code that is no longer used.
### Description
The Mbed 2 release was broken for FF_LPC546XX as it would include
the entire mbed 2 build of the LPC546XX. This PR seperates these 2
builds completely by:
* Removing non-shared extra labels from the MCU_LPC546XX target
* Moving the target implementation to a shared target directory
### Pull request type
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Breaking change
Busy-wait before sending a charecter instead of after. If
serial_writeable has been called first, the busy-wait loop will
be skipped.
Added initialization code to ensure NRF_UARTE_EVENT_TXDRDY is
armed correctly.
In nordic_nrf5_uart_event_handler if the events NRF_UARTE_EVENT_ENDRX
and NRF_UARTE_EVENT_RXSTARTED become pending after the check for
NRF_UARTE_EVENT_ENDRX but before the check for
NRF_UARTE_EVENT_RXSTARTED the RX DMA buffers will be setup incorrectly
by nordic_nrf5_uart_event_handler_rxstarted because active_bank hasn't
been updated. This cause dropped and incorrect data.
This patch fixes that problem by adding a second check for
NRF_UARTE_EVENT_ENDRX after checking for NRF_UARTE_EVENT_RXSTARTED
and skipping processing if NRF_UARTE_EVENT_ENDRX is set. The
subsequent interrupt will process both in the correct order. This
ensures that these events cannot be handled out of order and thus fixes
the corruption.
This commit represents the second stage of the low power implementations
that are required from Mbed 5.10 onwards. Besides the default hal
implementations (rtc_api.c and sleep.c), the PL031 RTC's native driver
needed to be added. Due to HW limitations in SSE-050 and the CM3DS,
Deep Sleep couldn't be implemented, therefore it is functionally
identical to Sleep (WFI).
Change-Id: Ibed2bdb452f48c98024dc7ef07fb51a4425e0a80
Signed-off-by: Bence Kaposzta <bence.kaposzta@arm.com>
This commit represents the first stage of the low power implementations
that are required from Mbed 5.10 onwards. The LP ticker has been
implemented using a CMSDK Dual Timer's both timers (HW prescaler needed
to operate in the specified frequency domain), whereas the us ticker
uses one CMSDK Timer. Besides the default hal implementations (lp_ticker.c
and us_ticker.c), the CMSDK Dual Timer's native driver needed to be added.
Change-Id: I0b16b93dfac7753bebf430a2ce77761cb9c43ee5
Signed-off-by: Bence Kaposzta <bence.kaposzta@arm.com>
`flash_get_erase_value` is added in hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c
duplicate copy of same function in targets/TARGET_NUVOTON/TARGET_M2351/flash_api.c
resulted in build issues with secure build
hex files subfolder moved up one level to avoid license confusion.
Removed non-TLS implementation of TRNG. Removed unused crypto libraries and headers.
Replaced Cypress copyright licence per agreement.
Removed unsed eeprom emulation middleware files.
Renamed assembler files from *.s to *.S
Removed "device_name" from targets.json definitions as it is not supoprted yet.
Exporter hooks removed completely.
Cleanup and improvements to the comments, including removal of the redundant doxygen comments.
Code run through astyle. Additionally:
- changes to drivers/Timer.cpp reverted
- ipcpipe_transport.* files removed as they are not used for now,
- fixed condition in stdio_init.cpp to perform serial initialization only when STDIO is enabled,
- added missing resurce manager call in PWM initialization,
- us_ticker initialization changed to use pre-reserved clock divider (to avoid resource manager call).
Changed reporting level from info to debug in PSOC6.py.
Added missing includes for function declarations in startup files.
Fixed (removed) garbadge text in psoc6_utils.c
Precompiled binaries updated for recent changes in psoc6_utils.c and moved to a separate folder; README and LICENSE files added.
1. In drivers/Timer.cpp make sure that hardware timer is initialized outside of critical section.
This is because on PSoC 6 hardware resources are shared between both cores
and we have to make sure that the other core is not already using a particular resource.
This mechanism is based on interprocessor communication taht cannot be handled iside of
critical section.
2. Added support for post-binary hook function for PSoC 6 targets, so the hex image for M0+ CPU core
can be merged with M4 core image for the final image.
3. Added possibility to use hook function from exportes, so the M0+ hex image could be included
in the generated project.
4. Included hex images in the build dependency list, so the update of image is catched by the
build process.
1. Complete set of HAL drivers for all peripherals of CY8C63xx PSoC chips.
2. Cypress PDL library updated to official 3.0.1 version.
3. Tree structure reorganized and cleaned up:
+ TARGET_Cypress
+--+ TARGET_PSOC6+ -> code & libs applicable to all PSoC 6 based devices
+--+ TARGET_CY86XX -> code & libs applicable to PSoC 63 based devices
| +--- TARGET_MCU_PSOC6_M0 -> code & libs applicable to PSoC6 Corted M0+ core
| +--- TARGET_MCU_PSOC6_M4 -> code & libs applicable to PSoC6 Corted M0F core
|
+--+ TARGET_FUTURE_SEQUANA -> code applicable to Sequana board, both cores
+--- TARGET_FUTURE_SEQUANA_M0 -> code applicable only to M0+ core on Sequana board
Ethernet controller. To ensure proper operation, some methods
needed to be updated in the SMSC9220's native driver as well.
It passes all related Greentea tests, however when supervised by
the Python environment it tends to fail because of Timeout.
The current timeout is set to 1200s that seems to be a little bit short
to finish all test cases, the timeout happens towards the end of the
last test case.
Change-Id: I914608c34828b493a80e133cd132537a297bfc84
Signed-off-by: Bence Kaposzta <bence.kaposzta@arm.com>
Due to buggy flow control logic in the UARTE, the stop signal
is not being set as it is supposed to when the the module is
not ready to receive data.
This commit signals the sender to halt transmitting when a DMA
buffer is full and only continue again when the atomic FIFO
buffer has been emptied. This allows platforms with hardware
flow control to minimize all buffers and rely on flow control
instead.
Only deep sleep when the wakeup time is more than
MBED_CONF_TARGET_DEEP_SLEEP_LATENCY ms in the future.
This ensures that RTOS events are handled at the correct time. Note -
when deep sleep is allow interrupt latency may still be as high as
10ms.
Cruz Monrreal
Leszek Rusinowicz
ccli8
Russ Butler
j3hill
jeromecoutant
Lu
Martin Kojtal
fluidblue
Mahesh Mahadevan
Laurent Louf
Anna Bridge
test user
vervaekejonathan
Kevin Bracey
Jimmy Brisson
Steve Cartmell
Toyomasa Watarai
toyowata
Juho Eskeli
c_jin
Qinghao Shi
Oren Cohen
JojoS62
TomoYamanaka
Derek Miller
Wilfried Chauveau
Kari Haapalehto
Russ Butler
Vincent Coubard
Donatien Garnier
Netanel Gonen
Danny Shavit
bcostm
Nir Sonnenschein
David Saada
Ganesh Ramachandran
Deepika
Przemyslaw Stekiel
Bence Káposzta
chao_king
Marcus Chang
Senthil Ramakrishnan
Ashok Rao
zhangzhenwu
Yoshihiro TSUBOI
Bence Kaposzta
Teppo Järvelin
shileiyu
Adam Heinrich
Leon Lindenfelser
Adrien Chardon
Ammad Rehmat
Yossi Levy
micgur01