[Nuvoton] Avoid re-configuring UART in serial_init() for the same H/W UART

The same H/W UART may be shared by multiple serial_t objects. This fix tries to avoid
re-configuring the same H/W UART in serial_init() when there are multiple serial_t
objects constructed. To re-configure UART, call serial_baud() and serial_format()
explicitly. This can avoid confusion when e.g. a newly constructed serial_t object
changes baudrate unexpectedly in serial_init().
pull/8900/head
ccli8 2018-11-28 16:26:21 +08:00
parent 6b16112962
commit ae98b94a10
5 changed files with 58 additions and 62 deletions

View File

@ -200,36 +200,34 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
if (! var->ref_cnt) {
do {
/* Reset module
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
SYS_ResetModule_S(modinit->rsetidx);
/* Reset module
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
SYS_ResetModule_S(modinit->rsetidx);
/* Select IP clock source
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_EnableModuleClock_S(modinit->clkidx);
/* Select IP clock source
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
} while (0);
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_EnableModuleClock_S(modinit->clkidx);
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
// Configure the UART module and set its baudrate
serial_baud(obj, 9600);
// Configure data bits, parity, and stop bits
serial_format(obj, 8, ParityNone, 1);
}
var->ref_cnt ++;
// Configure the UART module and set its baudrate
serial_baud(obj, 9600);
// Configure data bits, parity, and stop bits
serial_format(obj, 8, ParityNone, 1);
obj->serial.vec = var->vec;
obj->serial.irq_en = 0;

View File

@ -172,7 +172,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
if (! var->ref_cnt) {
// Reset this module
SYS_ResetModule(modinit->rsetidx);
// Select IP clock source
CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
// Enable IP clock
@ -180,14 +180,14 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
// Configure the UART module and set its baudrate
serial_baud(obj, 9600);
// Configure data bits, parity, and stop bits
serial_format(obj, 8, ParityNone, 1);
}
var->ref_cnt ++;
// Configure the UART module and set its baudrate
serial_baud(obj, 9600);
// Configure data bits, parity, and stop bits
serial_format(obj, 8, ParityNone, 1);
obj->serial.vec = var->vec;
obj->serial.irq_en = 0;

View File

@ -200,26 +200,24 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
if (! var->ref_cnt) {
do {
// Reset this module
SYS_ResetModule(modinit->rsetidx);
// Reset this module
SYS_ResetModule(modinit->rsetidx);
// Select IP clock source
CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
// Enable IP clock
CLK_EnableModuleClock(modinit->clkidx);
// Select IP clock source
CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
// Enable IP clock
CLK_EnableModuleClock(modinit->clkidx);
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
} while (0);
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
// Configure the UART module and set its baudrate
serial_baud(obj, 9600);
// Configure data bits, parity, and stop bits
serial_format(obj, 8, ParityNone, 1);
}
var->ref_cnt ++;
// Configure the UART module and set its baudrate
serial_baud(obj, 9600);
// Configure data bits, parity, and stop bits
serial_format(obj, 8, ParityNone, 1);
obj->serial.vec = var->vec;
obj->serial.irq_en = 0;

View File

@ -137,7 +137,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
if (! var->ref_cnt) {
// Reset this module
SYS_ResetModule(modinit->rsetidx);
// Select IP clock source
CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
// Enable IP clock
@ -145,17 +145,17 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
// Configure the UART module and set its baudrate
serial_baud(obj, 9600);
// Configure data bits, parity, and stop bits
serial_format(obj, 8, ParityNone, 1);
}
var->ref_cnt ++;
// Configure the UART module and set its baudrate
serial_baud(obj, 9600);
// Configure data bits, parity, and stop bits
serial_format(obj, 8, ParityNone, 1);
obj->serial.vec = var->vec;
obj->serial.irq_en = 0;
#if DEVICE_SERIAL_ASYNCH
obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
obj->serial.dma_usage_rx = DMA_USAGE_NEVER;

View File

@ -202,7 +202,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
if (! var->ref_cnt) {
// Reset this module
SYS_ResetModule(modinit->rsetidx);
// Select IP clock source
CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
// Enable IP clock
@ -210,14 +210,14 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
// Configure the UART module and set its baudrate
serial_baud(obj, 9600);
// Configure data bits, parity, and stop bits
serial_format(obj, 8, ParityNone, 1);
}
var->ref_cnt ++;
// Configure the UART module and set its baudrate
serial_baud(obj, 9600);
// Configure data bits, parity, and stop bits
serial_format(obj, 8, ParityNone, 1);
obj->serial.vec = var->vec;
obj->serial.irq_en = 0;