mirror of https://github.com/ARMmbed/mbed-os.git
[Nuvoton] Avoid re-configuring UART in serial_init() for the same H/W UART
The same H/W UART may be shared by multiple serial_t objects. This fix tries to avoid re-configuring the same H/W UART in serial_init() when there are multiple serial_t objects constructed. To re-configure UART, call serial_baud() and serial_format() explicitly. This can avoid confusion when e.g. a newly constructed serial_t object changes baudrate unexpectedly in serial_init().pull/8900/head
parent
6b16112962
commit
ae98b94a10
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@ -200,36 +200,34 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
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struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
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if (! var->ref_cnt) {
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do {
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/* Reset module
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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SYS_ResetModule_S(modinit->rsetidx);
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/* Reset module
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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SYS_ResetModule_S(modinit->rsetidx);
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/* Select IP clock source
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
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/* Enable IP clock
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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CLK_EnableModuleClock_S(modinit->clkidx);
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/* Select IP clock source
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
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pinmap_pinout(tx, PinMap_UART_TX);
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pinmap_pinout(rx, PinMap_UART_RX);
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} while (0);
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/* Enable IP clock
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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CLK_EnableModuleClock_S(modinit->clkidx);
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pinmap_pinout(tx, PinMap_UART_TX);
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pinmap_pinout(rx, PinMap_UART_RX);
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// Configure the UART module and set its baudrate
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serial_baud(obj, 9600);
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// Configure data bits, parity, and stop bits
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serial_format(obj, 8, ParityNone, 1);
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}
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var->ref_cnt ++;
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// Configure the UART module and set its baudrate
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serial_baud(obj, 9600);
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// Configure data bits, parity, and stop bits
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serial_format(obj, 8, ParityNone, 1);
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obj->serial.vec = var->vec;
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obj->serial.irq_en = 0;
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@ -172,7 +172,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
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if (! var->ref_cnt) {
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// Reset this module
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SYS_ResetModule(modinit->rsetidx);
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// Select IP clock source
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CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
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// Enable IP clock
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@ -180,14 +180,14 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
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pinmap_pinout(tx, PinMap_UART_TX);
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pinmap_pinout(rx, PinMap_UART_RX);
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// Configure the UART module and set its baudrate
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serial_baud(obj, 9600);
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// Configure data bits, parity, and stop bits
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serial_format(obj, 8, ParityNone, 1);
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}
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var->ref_cnt ++;
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// Configure the UART module and set its baudrate
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serial_baud(obj, 9600);
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// Configure data bits, parity, and stop bits
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serial_format(obj, 8, ParityNone, 1);
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obj->serial.vec = var->vec;
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obj->serial.irq_en = 0;
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@ -200,26 +200,24 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
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struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
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if (! var->ref_cnt) {
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do {
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// Reset this module
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SYS_ResetModule(modinit->rsetidx);
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// Reset this module
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SYS_ResetModule(modinit->rsetidx);
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// Select IP clock source
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CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
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// Enable IP clock
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CLK_EnableModuleClock(modinit->clkidx);
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// Select IP clock source
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CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
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// Enable IP clock
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CLK_EnableModuleClock(modinit->clkidx);
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pinmap_pinout(tx, PinMap_UART_TX);
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pinmap_pinout(rx, PinMap_UART_RX);
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} while (0);
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pinmap_pinout(tx, PinMap_UART_TX);
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pinmap_pinout(rx, PinMap_UART_RX);
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// Configure the UART module and set its baudrate
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serial_baud(obj, 9600);
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// Configure data bits, parity, and stop bits
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serial_format(obj, 8, ParityNone, 1);
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}
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var->ref_cnt ++;
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// Configure the UART module and set its baudrate
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serial_baud(obj, 9600);
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// Configure data bits, parity, and stop bits
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serial_format(obj, 8, ParityNone, 1);
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obj->serial.vec = var->vec;
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obj->serial.irq_en = 0;
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@ -137,7 +137,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
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if (! var->ref_cnt) {
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// Reset this module
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SYS_ResetModule(modinit->rsetidx);
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// Select IP clock source
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CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
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// Enable IP clock
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@ -145,17 +145,17 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
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pinmap_pinout(tx, PinMap_UART_TX);
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pinmap_pinout(rx, PinMap_UART_RX);
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// Configure the UART module and set its baudrate
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serial_baud(obj, 9600);
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// Configure data bits, parity, and stop bits
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serial_format(obj, 8, ParityNone, 1);
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}
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var->ref_cnt ++;
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// Configure the UART module and set its baudrate
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serial_baud(obj, 9600);
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// Configure data bits, parity, and stop bits
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serial_format(obj, 8, ParityNone, 1);
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obj->serial.vec = var->vec;
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obj->serial.irq_en = 0;
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#if DEVICE_SERIAL_ASYNCH
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obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
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obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
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@ -202,7 +202,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
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if (! var->ref_cnt) {
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// Reset this module
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SYS_ResetModule(modinit->rsetidx);
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// Select IP clock source
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CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
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// Enable IP clock
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@ -210,14 +210,14 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
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pinmap_pinout(tx, PinMap_UART_TX);
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pinmap_pinout(rx, PinMap_UART_RX);
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// Configure the UART module and set its baudrate
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serial_baud(obj, 9600);
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// Configure data bits, parity, and stop bits
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serial_format(obj, 8, ParityNone, 1);
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}
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var->ref_cnt ++;
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// Configure the UART module and set its baudrate
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serial_baud(obj, 9600);
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// Configure data bits, parity, and stop bits
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serial_format(obj, 8, ParityNone, 1);
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obj->serial.vec = var->vec;
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obj->serial.irq_en = 0;
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