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MIMXRT1050_EVK: Update the SDK clock driver 

This fixes build failures seen with GCC_ARM

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
pull/8190/head
Mahesh Mahadevan 2018-11-07 09:53:31 -06:00
parent 12c6b1bd88
commit d5cf53aba1
2 changed files with 514 additions and 186 deletions
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430
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.c
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@ -1,34 +1,8 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_clock.h"
@ -36,15 +10,47 @@
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.clock"
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to
achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected
in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */
#if __FPU_USED
#if ((defined(__ICCARM__)) || (defined(__GNUC__)))
#if (__ARMVFP__ >= __ARMFPV5__) && \
(__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/
typedef double clock_64b_t;
#else
typedef uint64_t clock_64b_t;
#endif
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
#if defined __TARGET_FPU_FPV5_D16
typedef double clock_64b_t;
#else
typedef uint64_t clock_64b_t;
#endif
#else
typedef uint64_t clock_64b_t;
#endif
#else
typedef uint64_t clock_64b_t;
#endif
/*******************************************************************************
* Variables
******************************************************************************/
/* External XTAL (OSC) clock frequency. */
uint32_t g_xtalFreq;
volatile uint32_t g_xtalFreq;
/* External RTC XTAL clock frequency. */
uint32_t g_rtcXtalFreq;
volatile uint32_t g_rtcXtalFreq;
/*******************************************************************************
* Prototypes
@ -127,6 +133,20 @@ static uint32_t CLOCK_GetPeriphClkFreq(void)
return freq;
}
/*!
* brief Initialize the external 24MHz clock.
*
* This function supports two modes:
* 1. Use external crystal oscillator.
* 2. Bypass the external crystal oscillator, using input source clock directly.
*
* After this function, please call ref CLOCK_SetXtal0Freq to inform clock driver
* the external clock frequency.
*
* param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
* note This device does not support bypass external crystal oscillator, so
* the input parameter should always be false.
*/
void CLOCK_InitExternalClk(bool bypassXtalOsc)
{
/* This device does not support bypass XTAL OSC. */
@ -143,11 +163,26 @@ void CLOCK_InitExternalClk(bool bypassXtalOsc)
CCM_ANALOG->MISC0_CLR = CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK;
}
/*!
* brief Deinitialize the external 24MHz clock.
*
* This function disables the external 24MHz clock.
*
* After this function, please call ref CLOCK_SetXtal0Freq to set external clock
* frequency to 0.
*/
void CLOCK_DeinitExternalClk(void)
{
CCM_ANALOG->MISC0_SET = CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK; /* Power down */
}
/*!
* brief Switch the OSC.
*
* This function switches the OSC source for SoC.
*
* param osc OSC source to switch to.
*/
void CLOCK_SwitchOsc(clock_osc_t osc)
{
if (osc == kCLOCK_RcOsc)
@ -156,16 +191,110 @@ void CLOCK_SwitchOsc(clock_osc_t osc)
XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_CLR_OSC_SEL_MASK;
}
/*!
* brief Initialize the RC oscillator 24MHz clock.
*/
void CLOCK_InitRcOsc24M(void)
{
XTALOSC24M->LOWPWR_CTRL |= XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK;
}
/*!
* brief Power down the RCOSC 24M clock.
*/
void CLOCK_DeinitRcOsc24M(void)
{
XTALOSC24M->LOWPWR_CTRL &= ~XTALOSC24M_LOWPWR_CTRL_RC_OSC_EN_MASK;
}
/*!
* brief Gets the AHB clock frequency.
*
* return The AHB clock frequency value in hertz.
*/
uint32_t CLOCK_GetAhbFreq(void)
{
return CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
}
/*!
* brief Gets the SEMC clock frequency.
*
* return The SEMC clock frequency value in hertz.
*/
uint32_t CLOCK_GetSemcFreq(void)
{
uint32_t freq;
/* SEMC alternative clock ---> SEMC Clock */
if (CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK)
{
/* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */
if (CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
{
freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1);
}
/* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */
else
{
freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2);
}
}
/* Periph_clk ---> SEMC Clock */
else
{
freq = CLOCK_GetPeriphClkFreq();
}
freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U);
return freq;
}
/*!
* brief Gets the IPG clock frequency.
*
* return The IPG clock frequency value in hertz.
*/
uint32_t CLOCK_GetIpgFreq(void)
{
return CLOCK_GetAhbFreq() / (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U);
}
/*!
* brief Gets the PER clock frequency.
*
* return The PER clock frequency value in hertz.
*/
uint32_t CLOCK_GetPerClkFreq(void)
{
uint32_t freq;
/* Osc_clk ---> PER Clock*/
if (CCM->CSCMR1 & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
{
freq = CLOCK_GetOscFreq();
}
/* Periph_clk ---> AHB Clock ---> IPG Clock ---> PER Clock */
else
{
freq = CLOCK_GetFreq(kCLOCK_IpgClk);
}
freq /= (((CCM->CSCMR1 & CCM_CSCMR1_PERCLK_PODF_MASK) >> CCM_CSCMR1_PERCLK_PODF_SHIFT) + 1U);
return freq;
}
/*!
* brief Gets the clock frequency for a specific clock name.
*
* This function checks the current clock configurations and then calculates
* the clock frequency for a specific clock name defined in clock_name_t.
*
* param clockName Clock names defined in clock_name_t
* return Clock frequency value in hertz
*/
uint32_t CLOCK_GetFreq(clock_name_t name)
{
uint32_t freq;
@ -173,42 +302,20 @@ uint32_t CLOCK_GetFreq(clock_name_t name)
switch (name)
{
case kCLOCK_CpuClk:
/* Periph_clk ---> AHB Clock */
case kCLOCK_AhbClk:
/* Periph_clk ---> AHB Clock */
freq =
CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
freq = CLOCK_GetAhbFreq();
break;
case kCLOCK_SemcClk:
/* SEMC alternative clock ---> SEMC Clock */
if (CCM->CBCDR & CCM_CBCDR_SEMC_CLK_SEL_MASK)
{
/* PLL3 PFD1 ---> SEMC alternative clock ---> SEMC Clock */
if (CCM->CBCDR & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
{
freq = CLOCK_GetUsb1PfdFreq(kCLOCK_Pfd1);
}
/* PLL2 PFD2 ---> SEMC alternative clock ---> SEMC Clock */
else
{
freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd2);
}
}
/* Periph_clk ---> SEMC Clock */
else
{
freq = CLOCK_GetPeriphClkFreq();
}
freq /= (((CCM->CBCDR & CCM_CBCDR_SEMC_PODF_MASK) >> CCM_CBCDR_SEMC_PODF_SHIFT) + 1U);
freq = CLOCK_GetSemcFreq();
break;
case kCLOCK_IpgClk:
/* Periph_clk ---> AHB Clock ---> IPG Clock */
freq =
CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
freq /= (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U);
freq = CLOCK_GetIpgFreq();
break;
case kCLOCK_PerClk:
freq = CLOCK_GetPerClkFreq();
break;
case kCLOCK_OscClk:
@ -273,6 +380,17 @@ uint32_t CLOCK_GetFreq(clock_name_t name)
return freq;
}
/*! brief Enable USB HS clock.
*
* This function only enables the access to USB HS prepheral, upper layer
* should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
* clock to use USB HS.
*
* param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused.
* param freq USB HS does not care about the clock source, so this parameter is ignored.
* retval true The clock is set successfully.
* retval false The clock source is invalid to get proper USB HS clock.
*/
bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
{
CCM->CCGR6 |= CCM_CCGR6_CG0_MASK;
@ -287,6 +405,17 @@ bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
return true;
}
/*! brief Enable USB HS clock.
*
* This function only enables the access to USB HS prepheral, upper layer
* should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
* clock to use USB HS.
*
* param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused.
* param freq USB HS does not care about the clock source, so this parameter is ignored.
* retval true The clock is set successfully.
* retval false The clock source is invalid to get proper USB HS clock.
*/
bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
{
CCM->CCGR6 |= CCM_CCGR6_CG0_MASK;
@ -301,12 +430,21 @@ bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
return true;
}
/*! brief Enable USB HS PHY PLL clock.
*
* This function enables the internal 480MHz USB PHY PLL clock.
*
* param src USB HS PHY PLL clock source.
* param freq The frequency specified by src.
* retval true The clock is set successfully.
* retval false The clock source is invalid to get proper USB HS clock.
*/
bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
{
const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
{
CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
}
else
{
@ -321,12 +459,23 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
return true;
}
/*! brief Disable USB HS PHY PLL clock.
*
* This function disables USB HS PHY PLL clock.
*/
void CLOCK_DisableUsbhs0PhyPllClock(void)
{
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
}
/*!
* brief Initialize the ARM PLL.
*
* This function initialize the ARM PLL with specific settings
*
* param config configuration to set to PLL.
*/
void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)
{
/* Bypass PLL first */
@ -345,11 +494,21 @@ void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)
CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK;
}
/*!
* brief De-initialize the ARM PLL.
*/
void CLOCK_DeinitArmPll(void)
{
CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_POWERDOWN_MASK;
}
/*!
* brief Initialize the System PLL.
*
* This function initializes the System PLL with specific settings
*
* param config Configuration to set to PLL.
*/
void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
{
/* Bypass PLL first */
@ -360,6 +519,15 @@ void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
(CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) |
CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider);
/* Initialize the fractional mode */
CCM_ANALOG->PLL_SYS_NUM = CCM_ANALOG_PLL_SYS_NUM_A(config->numerator);
CCM_ANALOG->PLL_SYS_DENOM = CCM_ANALOG_PLL_SYS_DENOM_B(config->denominator);
/* Initialize the spread spectrum mode */
CCM_ANALOG->PLL_SYS_SS = CCM_ANALOG_PLL_SYS_SS_STEP(config->ss_step) |
CCM_ANALOG_PLL_SYS_SS_ENABLE(config->ss_enable) |
CCM_ANALOG_PLL_SYS_SS_STOP(config->ss_stop);
while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0)
{
}
@ -368,11 +536,21 @@ void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK;
}
/*!
* brief De-initialize the System PLL.
*/
void CLOCK_DeinitSysPll(void)
{
CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_POWERDOWN_MASK;
}
/*!
* brief Initialize the USB1 PLL.
*
* This function initializes the USB1 PLL with specific settings
*
* param config Configuration to set to PLL.
*/
void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config)
{
/* Bypass PLL first */
@ -391,11 +569,21 @@ void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config)
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK;
}
/*!
* brief Deinitialize the USB1 PLL.
*/
void CLOCK_DeinitUsb1Pll(void)
{
CCM_ANALOG->PLL_USB1 = 0U;
}
/*!
* brief Initialize the USB2 PLL.
*
* This function initializes the USB2 PLL with specific settings
*
* param config Configuration to set to PLL.
*/
void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config)
{
/* Bypass PLL first */
@ -414,11 +602,21 @@ void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config)
CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_BYPASS_MASK;
}
/*!
* brief Deinitialize the USB2 PLL.
*/
void CLOCK_DeinitUsb2Pll(void)
{
CCM_ANALOG->PLL_USB2 = 0U;
}
/*!
* brief Initializes the Audio PLL.
*
* This function initializes the Audio PLL with specific settings
*
* param config Configuration to set to PLL.
*/
void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
{
uint32_t pllAudio;
@ -491,11 +689,21 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
}
/*!
* brief De-initialize the Audio PLL.
*/
void CLOCK_DeinitAudioPll(void)
{
CCM_ANALOG->PLL_AUDIO = CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK;
}
/*!
* brief Initialize the video PLL.
*
* This function configures the Video PLL with specific settings
*
* param config configuration to set to PLL.
*/
void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)
{
uint32_t pllVideo;
@ -567,11 +775,21 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)
CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
}
/*!
* brief De-initialize the Video PLL.
*/
void CLOCK_DeinitVideoPll(void)
{
CCM_ANALOG->PLL_VIDEO = CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK;
}
/*!
* brief Initialize the ENET PLL.
*
* This function initializes the ENET PLL with specific settings.
*
* param config Configuration to set to PLL.
*/
void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
{
uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider);
@ -602,16 +820,29 @@ void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK;
}
/*!
* brief Deinitialize the ENET PLL.
*
* This function disables the ENET PLL.
*/
void CLOCK_DeinitEnetPll(void)
{
CCM_ANALOG->PLL_ENET = CCM_ANALOG_PLL_ENET_POWERDOWN_MASK;
}
/*!
* brief Get current PLL output frequency.
*
* This function get current output frequency of specific PLL
*
* param pll pll name to get frequency.
* return The PLL output frequency in hertz.
*/
uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
{
uint32_t freq;
uint32_t divSelect;
uint64_t freqTmp;
clock_64b_t freqTmp;
const uint32_t enetRefClkFreq[] = {
25000000U, /* 25M */
@ -644,8 +875,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
break;
case kCLOCK_PllSys:
/* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
freqTmp =
((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_SYS_NUM))) /
((clock_64b_t)(CCM_ANALOG->PLL_SYS_DENOM));
if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
{
@ -668,8 +899,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
divSelect =
(CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT;
freqTmp =
((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_NUM))) /
((clock_64b_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
freq = freq * divSelect + (uint32_t)freqTmp;
@ -723,8 +954,8 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
divSelect =
(CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT;
freqTmp =
((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_VIDEO_DENOM));
freqTmp = ((clock_64b_t)freq * ((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_NUM))) /
((clock_64b_t)(CCM_ANALOG->PLL_VIDEO_DENOM));
freq = freq * divSelect + (uint32_t)freqTmp;
@ -794,6 +1025,16 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
return freq;
}
/*!
* brief Initialize the System PLL PFD.
*
* This function initializes the System PLL PFD. During new value setting,
* the clock output is disabled to prevent glitch.
*
* param pfd Which PFD clock to enable.
* param pfdFrac The PFD FRAC value.
* note It is recommended that PFD settings are kept between 12-35.
*/
void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac)
{
uint32_t pfdIndex = (uint32_t)pfd;
@ -809,11 +1050,28 @@ void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac)
CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_FRAC(pfdFrac) << (8 * pfdIndex));
}
/*!
* brief De-initialize the System PLL PFD.
*
* This function disables the System PLL PFD.
*
* param pfd Which PFD clock to disable.
*/
void CLOCK_DeinitSysPfd(clock_pfd_t pfd)
{
CCM_ANALOG->PFD_528 |= CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfd);
}
/*!
* brief Initialize the USB1 PLL PFD.
*
* This function initializes the USB1 PLL PFD. During new value setting,
* the clock output is disabled to prevent glitch.
*
* param pfd Which PFD clock to enable.
* param pfdFrac The PFD FRAC value.
* note It is recommended that PFD settings are kept between 12-35.
*/
void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac)
{
uint32_t pfdIndex = (uint32_t)pfd;
@ -829,11 +1087,26 @@ void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac)
CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_FRAC(pfdFrac) << (8 * pfdIndex));
}
/*!
* brief De-initialize the USB1 PLL PFD.
*
* This function disables the USB1 PLL PFD.
*
* param pfd Which PFD clock to disable.
*/
void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd)
{
CCM_ANALOG->PFD_480 |= CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfd);
}
/*!
* brief Get current System PLL PFD output frequency.
*
* This function get current output frequency of specific System PLL PFD
*
* param pfd pfd name to get frequency.
* return The PFD output frequency in hertz.
*/
uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd)
{
uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
@ -865,6 +1138,14 @@ uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd)
return freq;
}
/*!
* brief Get current USB1 PLL PFD output frequency.
*
* This function get current output frequency of specific USB1 PLL PFD
*
* param pfd pfd name to get frequency.
* return The PFD output frequency in hertz.
*/
uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd)
{
uint32_t freq = CLOCK_GetPllFreq(kCLOCK_PllUsb1);
@ -896,6 +1177,15 @@ uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd)
return freq;
}
/*! brief Enable USB HS PHY PLL clock.
*
* This function enables the internal 480MHz USB PHY PLL clock.
*
* param src USB HS PHY PLL clock source.
* param freq The frequency specified by src.
* retval true The clock is set successfully.
* retval false The clock source is invalid to get proper USB HS clock.
*/
bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
{
const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
@ -910,8 +1200,12 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
return true;
}
/*! brief Disable USB HS PHY PLL clock.
*
* This function disables USB HS PHY PLL clock.
*/
void CLOCK_DisableUsbhs1PhyPllClock(void)
{
CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK;
CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK;
USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
}

270
targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/drivers/fsl_clock.h
View File

@ -1,34 +1,8 @@
/*
* The Clear BSD License
* Copyright 2017 NXP
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted (subject to the limitations in the disclaimer below) provided
* that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CLOCK_H_
@ -49,7 +23,7 @@
*
* When set to 0, peripheral drivers will enable clock in initialize function
* and disable clock in de-initialize function. When set to 1, peripheral
* driver will not control the clock, application could contol the clock out of
* driver will not control the clock, application could control the clock out of
* the driver.
*
* @note All drivers share this feature switcher. If it is set to 1, application
@ -65,18 +39,47 @@
/*! @name Driver version */
/*@{*/
/*! @brief CLOCK driver version 2.1.2. */
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
/*! @brief CLOCK driver version 2.1.5. */
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
/* analog pll definition */
#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
/*@}*/
#define CCM_TUPLE(reg, shift, mask, busyShift) \
((((uint32_t)(&((CCM_Type *)0U)->reg)) & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | \
((busyShift) << 26U))
/*!
* @brief CCM registers offset.
*/
#define CCSR_OFFSET 0x0C
#define CBCDR_OFFSET 0x14
#define CBCMR_OFFSET 0x18
#define CSCMR1_OFFSET 0x1C
#define CSCMR2_OFFSET 0x20
#define CSCDR1_OFFSET 0x24
#define CDCDR_OFFSET 0x30
#define CSCDR2_OFFSET 0x38
#define CSCDR3_OFFSET 0x3C
#define CACRR_OFFSET 0x10
#define CS1CDR_OFFSET 0x28
#define CS2CDR_OFFSET 0x2C
/*!
* @brief CCM Analog registers offset.
*/
#define PLL_ARM_OFFSET 0x00
#define PLL_SYS_OFFSET 0x30
#define PLL_USB1_OFFSET 0x10
#define PLL_AUDIO_OFFSET 0x70
#define PLL_VIDEO_OFFSET 0xA0
#define PLL_ENET_OFFSET 0xE0
#define PLL_USB2_OFFSET 0x20
#define CCM_TUPLE(reg, shift, mask, busyShift) \
(int)((reg & 0xFFU) | ((shift) << 8U) | \
((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU))))
#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU)
#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU))))
@ -87,7 +90,7 @@
/*!
* @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
*/
#define CCM_ANALOG_TUPLE(reg, shift) ((((uint32_t)(&((CCM_ANALOG_Type *)0U)->reg) & 0xFFFU) << 16U) | (shift))
#define CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) | (shift))
#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
(*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off)))
@ -97,7 +100,7 @@
* @brief clock1PN frequency.
*/
#define CLKPN_FREQ 0U
/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
*
* The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
@ -108,14 +111,14 @@
* CLOCK_SetXtalFreq(240000000); // Set the XTAL value to clock driver.
* @endcode
*/
extern uint32_t g_xtalFreq;
extern volatile uint32_t g_xtalFreq;
/*! @brief External RTC XTAL (32K OSC) clock frequency.
*
* The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
* function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
*/
extern uint32_t g_rtcXtalFreq;
extern volatile uint32_t g_rtcXtalFreq;
/* For compatible with other platforms */
#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
@ -394,31 +397,32 @@ typedef enum _clock_name
kCLOCK_AhbClk = 0x1U, /*!< AHB clock */
kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */
kCLOCK_IpgClk = 0x3U, /*!< IPG clock */
kCLOCK_PerClk = 0x4U, /*!< PER clock */
kCLOCK_OscClk = 0x4U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
kCLOCK_RtcClk = 0x5U, /*!< RTC clock. (RTCCLK) */
kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */
kCLOCK_ArmPllClk = 0x6U, /*!< ARMPLLCLK. */
kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */
kCLOCK_Usb1PllClk = 0x7U, /*!< USB1PLLCLK. */
kCLOCK_Usb1PllPfd0Clk = 0x8U, /*!< USB1PLLPDF0CLK. */
kCLOCK_Usb1PllPfd1Clk = 0x9U, /*!< USB1PLLPFD1CLK. */
kCLOCK_Usb1PllPfd2Clk = 0xAU, /*!< USB1PLLPFD2CLK. */
kCLOCK_Usb1PllPfd3Clk = 0xBU, /*!< USB1PLLPFD3CLK. */
kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */
kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */
kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */
kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */
kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */
kCLOCK_Usb2PllClk = 0xCU, /*!< USB2PLLCLK. */
kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */
kCLOCK_SysPllClk = 0xDU, /*!< SYSPLLCLK. */
kCLOCK_SysPllPfd0Clk = 0xEU, /*!< SYSPLLPDF0CLK. */
kCLOCK_SysPllPfd1Clk = 0xFU, /*!< SYSPLLPFD1CLK. */
kCLOCK_SysPllPfd2Clk = 0x10U, /*!< SYSPLLPFD2CLK. */
kCLOCK_SysPllPfd3Clk = 0x11U, /*!< SYSPLLPFD3CLK. */
kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */
kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */
kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */
kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */
kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */
kCLOCK_EnetPll0Clk = 0x12U, /*!< Enet PLLCLK ref_enetpll0. */
kCLOCK_EnetPll1Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll1. */
kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */
kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */
kCLOCK_AudioPllClk = 0x14U, /*!< Audio PLLCLK. */
kCLOCK_VideoPllClk = 0x15U, /*!< Video PLLCLK. */
kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */
kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */
} clock_name_t;
#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
@ -591,84 +595,84 @@ typedef enum _clock_mode_t
*/
typedef enum _clock_mux
{
kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR,
kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
kCLOCK_PeriphMux = CCM_TUPLE(CBCDR,
kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
CCM_CBCDR_PERIPH_CLK_SEL_MASK,
CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR,
kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< semc mux name */
kCLOCK_SemcMux = CCM_TUPLE(
CBCDR, CCM_CBCDR_SEMC_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */
CBCDR_OFFSET, CCM_CBCDR_SEMC_CLK_SEL_SHIFT, CCM_CBCDR_SEMC_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< semc mux name */
kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR,
kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
kCLOCK_TraceMux = CCM_TUPLE(
CBCMR, CCM_CBCMR_TRACE_CLK_SEL_SHIFT, CCM_CBCMR_TRACE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< trace mux name */
kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR,
CBCMR_OFFSET, CCM_CBCMR_TRACE_CLK_SEL_SHIFT, CCM_CBCMR_TRACE_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< trace mux name */
kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
kCLOCK_LpspiMux = CCM_TUPLE(
CBCMR, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
CBCMR_OFFSET, CCM_CBCMR_LPSPI_CLK_SEL_SHIFT, CCM_CBCMR_LPSPI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1,
kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1,
kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */
kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1,
kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */
kCLOCK_Sai3Mux = CCM_TUPLE(
CSCMR1, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
CSCMR1_OFFSET, CCM_CSCMR1_SAI3_CLK_SEL_SHIFT, CCM_CSCMR1_SAI3_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
kCLOCK_Sai2Mux = CCM_TUPLE(
CSCMR1, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
CSCMR1_OFFSET, CCM_CSCMR1_SAI2_CLK_SEL_SHIFT, CCM_CSCMR1_SAI2_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
kCLOCK_Sai1Mux = CCM_TUPLE(
CSCMR1, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1,
CSCMR1_OFFSET, CCM_CSCMR1_SAI1_CLK_SEL_SHIFT, CCM_CSCMR1_SAI1_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< perclk mux name */
kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2,
kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET,
CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT,
CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */
kCLOCK_CanMux = CCM_TUPLE(
CSCMR2, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */
CSCMR2_OFFSET, CCM_CSCMR2_CAN_CLK_SEL_SHIFT, CCM_CSCMR2_CAN_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< can mux name */
kCLOCK_UartMux = CCM_TUPLE(
CSCDR1, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */
CSCDR1_OFFSET, CCM_CSCDR1_UART_CLK_SEL_SHIFT, CCM_CSCDR1_UART_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< uart mux name */
kCLOCK_SpdifMux = CCM_TUPLE(
CDCDR, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */
kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR,
CDCDR_OFFSET, CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT, CCM_CDCDR_SPDIF0_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< spdif mux name */
kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET,
CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT,
CCM_CDCDR_FLEXIO1_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
kCLOCK_Lpi2cMux = CCM_TUPLE(
CSCDR2, CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, CCM_CSCDR2_LPI2C_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2,
CSCDR2_OFFSET, CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT, CCM_CSCDR2_LPI2C_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET,
CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT,
CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK,
CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */
kCLOCK_CsiMux = CCM_TUPLE(
CSCDR3, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */
CSCDR3_OFFSET, CCM_CSCDR3_CSI_CLK_SEL_SHIFT, CCM_CSCDR3_CSI_CLK_SEL_MASK, CCM_NO_BUSY_WAIT), /*!< csi mux name */
} clock_mux_t;
/*!
@ -682,104 +686,104 @@ typedef enum _clock_mux
typedef enum _clock_div
{
kCLOCK_ArmDiv = CCM_TUPLE(
CACRR, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
CACRR_OFFSET, CCM_CACRR_ARM_PODF_SHIFT, CCM_CACRR_ARM_PODF_MASK, CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR,
kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */
kCLOCK_SemcDiv = CCM_TUPLE(CBCDR,
kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
CCM_CBCDR_SEMC_PODF_SHIFT,
CCM_CBCDR_SEMC_PODF_MASK,
CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */
kCLOCK_AhbDiv = CCM_TUPLE(
CBCDR, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
CBCDR_OFFSET, CCM_CBCDR_AHB_PODF_SHIFT, CCM_CBCDR_AHB_PODF_MASK, CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
kCLOCK_IpgDiv =
CCM_TUPLE(CBCDR, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
CCM_TUPLE(CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
kCLOCK_LpspiDiv = CCM_TUPLE(
CBCMR, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
kCLOCK_LcdifDiv = CCM_TUPLE(
CBCMR, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */
CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */
kCLOCK_FlexspiDiv = CCM_TUPLE(
CSCMR1, CCM_CSCMR1_FLEXSPI_PODF_SHIFT, CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi div name */
CSCMR1_OFFSET, CCM_CSCMR1_FLEXSPI_PODF_SHIFT, CCM_CSCMR1_FLEXSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< flexspi div name */
kCLOCK_PerclkDiv = CCM_TUPLE(
CSCMR1, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */
CSCMR1_OFFSET, CCM_CSCMR1_PERCLK_PODF_SHIFT, CCM_CSCMR1_PERCLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< perclk div name */
kCLOCK_CanDiv = CCM_TUPLE(
CSCMR2, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */
CSCMR2_OFFSET, CCM_CSCMR2_CAN_CLK_PODF_SHIFT, CCM_CSCMR2_CAN_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< can div name */
kCLOCK_TraceDiv = CCM_TUPLE(
CSCDR1, CCM_CSCDR1_TRACE_PODF_SHIFT, CCM_CSCDR1_TRACE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< trace div name */
CSCDR1_OFFSET, CCM_CSCDR1_TRACE_PODF_SHIFT, CCM_CSCDR1_TRACE_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< trace div name */
kCLOCK_Usdhc2Div = CCM_TUPLE(
CSCDR1, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */
CSCDR1_OFFSET, CCM_CSCDR1_USDHC2_PODF_SHIFT, CCM_CSCDR1_USDHC2_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */
kCLOCK_Usdhc1Div = CCM_TUPLE(
CSCDR1, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */
CSCDR1_OFFSET, CCM_CSCDR1_USDHC1_PODF_SHIFT, CCM_CSCDR1_USDHC1_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */
kCLOCK_UartDiv = CCM_TUPLE(
CSCDR1, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */
CSCDR1_OFFSET, CCM_CSCDR1_UART_CLK_PODF_SHIFT, CCM_CSCDR1_UART_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< uart div name */
kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR,
kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET,
CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT,
CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */
kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR,
kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
CCM_CS1CDR_SAI3_CLK_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
kCLOCK_Sai3Div = CCM_TUPLE(
CS1CDR, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */
kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR,
CS1CDR_OFFSET, CCM_CS1CDR_SAI3_CLK_PODF_SHIFT, CCM_CS1CDR_SAI3_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai3 div name */
kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT,
CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR,
kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
CCM_CS1CDR_SAI1_CLK_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
kCLOCK_Sai1Div = CCM_TUPLE(
CS1CDR, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */
CS1CDR_OFFSET, CCM_CS1CDR_SAI1_CLK_PODF_SHIFT, CCM_CS1CDR_SAI1_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai1 div name */
kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR,
kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
CCM_CS2CDR_SAI2_CLK_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */
kCLOCK_Sai2Div = CCM_TUPLE(
CS2CDR, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */
CS2CDR_OFFSET, CCM_CS2CDR_SAI2_CLK_PODF_SHIFT, CCM_CS2CDR_SAI2_CLK_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< sai2 div name */
kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR,
kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR,
kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< spdif div name */
kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR,
kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET,
CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT,
CCM_CDCDR_FLEXIO1_CLK_PRED_MASK,
CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR,
kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET,
CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT,
CCM_CDCDR_FLEXIO1_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< flexio1 div name */
kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2,
kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
kCLOCK_LcdifPreDiv = CCM_TUPLE(
CSCDR2, CCM_CSCDR2_LCDIF_PRED_SHIFT, CCM_CSCDR2_LCDIF_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */
CSCDR2_OFFSET, CCM_CSCDR2_LCDIF_PRED_SHIFT, CCM_CSCDR2_LCDIF_PRED_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */
kCLOCK_CsiDiv =
CCM_TUPLE(CSCDR3, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */
CCM_TUPLE(CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */
} clock_div_t;
/*! @brief USB clock source definition. */
typedef enum _clock_usb_src
{
kCLOCK_Usb480M = 0, /*!< Use 480M. */
kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not
kCLOCK_Usb480M = 0, /*!< Use 480M. */
kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
care the clock source. */
} clock_usb_src_t;
@ -822,6 +826,9 @@ typedef struct _clock_sys_pll_config
uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
uint16_t ss_stop; /*!< Stop value to get frequency change. */
uint8_t ss_enable; /*!< Enable spread spectrum modulation */
uint16_t ss_step; /*!< Step value to get frequency change step. */
} clock_sys_pll_config_t;
@ -864,17 +871,17 @@ typedef struct _clock_enet_pll_config
/*! @brief PLL name */
typedef enum _clock_pll
{
kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */
kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */
kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */
kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */
kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */
kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */
kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */
kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */
kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */
kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */
} clock_pll_t;
@ -1031,6 +1038,34 @@ static inline uint32_t CLOCK_GetOscFreq(void)
return (XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) ? 24000000UL : g_xtalFreq;
}
/*!
* @brief Gets the AHB clock frequency.
*
* @return The AHB clock frequency value in hertz.
*/
uint32_t CLOCK_GetAhbFreq(void);
/*!
* @brief Gets the SEMC clock frequency.
*
* @return The SEMC clock frequency value in hertz.
*/
uint32_t CLOCK_GetSemcFreq(void);
/*!
* @brief Gets the IPG clock frequency.
*
* @return The IPG clock frequency value in hertz.
*/
uint32_t CLOCK_GetIpgFreq(void);
/*!
* @brief Gets the PER clock frequency.
*
* @return The PER clock frequency value in hertz.
*/
uint32_t CLOCK_GetPerClkFreq(void);
/*!
* @brief Gets the clock frequency for a specific clock name.
*
@ -1133,7 +1168,6 @@ void CLOCK_InitRcOsc24M(void);
void CLOCK_DeinitRcOsc24M(void);
/* @} */
/*! @brief Enable USB HS clock.
*
* This function only enables the access to USB HS prepheral, upper layer