ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added missing README files for Cypress PDL library. 

hex files subfolder moved up one level to avoid license confusion.
Removed non-TLS implementation of TRNG. Removed unused crypto libraries and headers.
Replaced Cypress copyright licence per agreement.
Removed unsed eeprom emulation middleware files.
Renamed assembler files from *.s to *.S
Removed "device_name" from targets.json definitions as it is not supoprted yet.
pull/8491/head
Leszek Rusinowicz 2018-10-29 13:52:35 +01:00
parent 7d322dcd41
commit 8f528277fd
162 changed files with 2972 additions and 7928 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/PDL_Version.txt Normal file
View File

@ -0,0 +1,2 @@
version 3.0.1

5
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/README.md Normal file
View File

@ -0,0 +1,5 @@
README for Cypress Peripheral Driver Library
============================================
This folder tree contains parts (binary-only libraries and M0/M4 core specific files) of Cypress Peripheral Driver Library (PDL) necessary to support PSoC 6 MCUs. Library names have been changed (vs. standard PDL version) by prepending a "lib" prefix to fit Mbed OS build system conventions.
See [Cypress PDL page](http://www.cypress.com/documentation/software-and-drivers/peripheral-driver-library-pdl) for details.

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm0plus.sct
View File

@ -27,9 +27,7 @@
;*******************************************************************************
;* \copyright
;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
;* You may use this file only in accordance with the license, terms, conditions,
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
;* SPDX-License-Identifier: Apache-2.0
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.

BIN
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/libcy_ble_stack_mdk_controller_ipc_cm0p.a
View File

Binary file not shown.

BIN
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/libcy_ble_stack_mdk_controller_uart_cm0p.a
View File

Binary file not shown.

BIN
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/libcy_ble_stack_mdk_radio_max_cm0p.a
View File

Binary file not shown.

BIN
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/libcy_crypto_client_mdk.a
View File

Binary file not shown.

BIN
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/libcy_crypto_server_mdk_base.a
View File

Binary file not shown.

BIN
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/libcy_crypto_server_mdk_extra.a
View File

Binary file not shown.

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm0plus.s → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm0plus.S
View File

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm0plus.ld
View File

@ -20,9 +20,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")

BIN
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/libcy_crypto_client_gcc.a
View File

Binary file not shown.

BIN
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/libcy_crypto_server_gcc_base.a
View File

Binary file not shown.

BIN
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_GCC_ARM/libcy_crypto_server_gcc_extra.a
View File

Binary file not shown.

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/cy8c6xx7_cm0plus.icf
View File

@ -20,9 +20,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/

BIN
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/libcy_crypto_client_mdk.a
View File

Binary file not shown.

BIN
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/libcy_crypto_server_mdk_base.a
View File

Binary file not shown.

BIN
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/libcy_crypto_server_mdk_extra.a
View File

Binary file not shown.

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/startup_psoc63_cm0plus.s → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/device/TOOLCHAIN_IAR/startup_psoc63_cm0plus.S
View File

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M0/system_psoc63_cm0plus.c
View File

@ -7,13 +7,9 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Future Electronics
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/*
* Copyright (c) 20017-2018 Future Electronics
*/
#include <stdint.h>
#include <stdbool.h>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/PDL_Version.txt Normal file
View File

@ -0,0 +1,2 @@
version 3.0.1

5
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/README.md Normal file
View File

@ -0,0 +1,5 @@
README for Cypress Peripheral Driver Library
============================================
This folder tree contains parts (binary-only libraries and M0/M4 core specific files) of Cypress Peripheral Driver Library (PDL) necessary to support PSoC 6 MCUs. Library names have been changed (vs. standard PDL version) by prepending a "lib" prefix to fit Mbed OS build system conventions.
See [Cypress PDL page](http://www.cypress.com/documentation/software-and-drivers/peripheral-driver-library-pdl) for details.

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/cy8c6xx7_cm4_dual.sct
View File

@ -27,9 +27,7 @@
;*******************************************************************************
;* \copyright
;* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
;* You may use this file only in accordance with the license, terms, conditions,
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
;* SPDX-License-Identifier: Apache-2.0
;******************************************************************************/
; The defines below describe the location and size of blocks of memory in the target.

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm4.s → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_ARM_STD/startup_psoc63_cm4.S
View File

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_GCC_ARM/cy8c6xx7_cm4_dual.ld
View File

@ -20,9 +20,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/cy8c6xx7_cm4_dual.icf
View File

@ -20,9 +20,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/*###ICF### Section handled by ICF editor, don't touch! ****/

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/startup_psoc63_cm4.s → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/TOOLCHAIN_IAR/startup_psoc63_cm4.S
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/hex/LICENSE.txt → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/LICENSE.txt
View File

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/hex/README.md → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/README.md
View File

@ -2,6 +2,7 @@ README for pre-compiled PSoC 6 Cortex M0+ core images
=====================================================
This folder contains precompiled program images for the CM0+ core of the PSoC 6(63xx) MCU suitable for use with MBed OS applications running on CM4 core. Two images are available:
* `psoc63_m0_default_1.01.hex`
This image contains basic code, that brings up the chip, starts CM4 core and puts CM0+ core into a deep sleep. It is suitable for use with all Mbed applications except those intendif to use BLE feature.

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/hex/psoc63_m0_ble_controller_1.01.hex → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_ble_controller_1.01.hex
View File

0
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/device/hex/psoc63_m0_default_1.01.hex → targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/hex/psoc63_m0_default_1.01.hex
View File

8
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/TARGET_MCU_PSOC6_M4/system_psoc63_cm4.c
View File

@ -7,13 +7,9 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Future Electronics
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/*
* Copyright (c) 20017-2018 Future Electronics
*/
#include <stdint.h>
#include <stdbool.h>

34
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cmsis.h
View File

@ -1,32 +1,18 @@
/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) XXX
* All rights reserved.
* Copyright (c) 2017-2018 Future Electronics
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* http://www.apache.org/licenses/LICENSE-2.0
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_CMSIS_H

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy8c6347bzi_bld53.h
View File

@ -10,10 +10,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef _CY8C6347BZI_BLD53_H_

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_device_headers.h
View File

@ -10,10 +10,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef _CY_DEVICE_HEADERS_H_

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_ipc_config.c
View File

@ -9,9 +9,7 @@
*
********************************************************************************
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ipc/cy_ipc_drv.h"

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cy_ipc_config.h
View File

@ -8,10 +8,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef CY_IPC_CONFIG_H

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/cymetadata.c
View File

@ -8,10 +8,8 @@
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2007-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
********************************************************************************/

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/gpio_psoc63_116_bga_ble.h
View File

@ -10,10 +10,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef _GPIO_PSOC63_116_BGA_BLE_H_

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/psoc63_config.h
View File

@ -10,10 +10,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef _PSOC63_CONFIG_H_
@ -84,10 +82,10 @@ typedef enum
} en_clk_dst_t;
/* Trigger Group */
/* This section contains the enums related to the Trigger multiplexer (TrigMux) driver.
/* This section contains the enums related to the Trigger multiplexer (TrigMux) driver.
* The constants are divided into four types because each signal of the TrigMux driver has a path
* through two multiplexers: the reduction multiplexer and the distribution multiplexer. This
* requires two calls for Cy_TrigMux_Connect() function. The first call - for the reduction
* through two multiplexers: the reduction multiplexer and the distribution multiplexer. This
* requires two calls for Cy_TrigMux_Connect() function. The first call - for the reduction
* multiplexer, the second call - for the distribution multiplexer.
*
* The four types of inputs/output parameters:
@ -96,7 +94,7 @@ typedef enum
* 3) Parameters for distribution multiplexer's inputs (intermediate signals);
* 4) Parameters for distribution multiplexer's outputs (output signals of TrigMux).
*
* The Cy_TrigMux_Connect() inTrig parameter can have 1) and 3) types parameters. The outTrig
* The Cy_TrigMux_Connect() inTrig parameter can have 1) and 3) types parameters. The outTrig
* parameter can have 2) and 4) types parameters.
* The names of the constants for these parameters have the following format:
*
@ -108,7 +106,7 @@ typedef enum
*
* Example:
* TRIG11_IN_TCPWM0_TR_OVERFLOW3 - the TCPWM0 tr_overflow[3] input of reduction multiplexer#11.
*
*
* 2) For reduction multiplexer's outputs:
* TRIG<REDMULT>_OUT_TR_GROUP<DISTMULT >_INPUT<DISTMULTINPUT>
* <REDMULT> - the reduction multiplexer number;
@ -116,7 +114,7 @@ typedef enum
* <DISTMULTINPUT> - the input number of the distribution multiplexer.
*
* Example:
* TRIG11_OUT_TR_GROUP0_INPUT23 - Input#23 of the distribution multiplexer#0 is the destination
* TRIG11_OUT_TR_GROUP0_INPUT23 - Input#23 of the distribution multiplexer#0 is the destination
* of the reduction multiplexer#11.
*
* 3) For distribution multiplexer's inputs:
@ -126,9 +124,9 @@ typedef enum
* <REDMULTOUTPUT> - the output number of the reduction multiplexer;
*
* Example:
* TRIG0_IN_TR_GROUP11_OUTPUT15 - Output#15 of the reduction multiplexer#11 is the source of the
* TRIG0_IN_TR_GROUP11_OUTPUT15 - Output#15 of the reduction multiplexer#11 is the source of the
* distribution multiplexer#0.
*
*
* 4) For distribution multiplexer's outputs:
* TRIG<DISTMULT>_OUT_<IPDEST><IPNUM>
* <REDMULT> - the distribution multiplexer number;

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8C63XX/device/system_psoc63.h
View File

@ -7,9 +7,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_FUTURE_SEQUANA/TARGET_FUTURE_SEQUANA_M0/board_config.c
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: cyfitter_cfg.c
* File Name: board_config.c (formerly cyfitter_cfg.c)
*
* PSoC Creator 4.2
*
@ -10,14 +10,10 @@
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2017 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2007-2018, Cypress Semiconductor Corporation. All rights reserved.
* Copyright 2017-2018, Future Electronics
* SPDX-License-Identifier: Apache-2.0
********************************************************************************/
/*
* Copyright (c) 20017-2018 Future Electronics
*/
#include <string.h>
#include "device.h"

2
targets/TARGET_Cypress/TARGET_PSOC6/device/PDL_Version.txt Normal file
View File

@ -0,0 +1,2 @@
version 3.0.1

4
targets/TARGET_Cypress/TARGET_PSOC6/device/README.md Normal file
View File

@ -0,0 +1,4 @@
README for Cypress Peripheral Driver Library
============================================
This folder tree contains parts of Cypress Peripheral Driver Library (PDL) necessary to support PSoC 6 MCUs. See [Cypress PDL page](http://www.cypress.com/documentation/software-and-drivers/peripheral-driver-library-pdl) for details.

1705
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/crypto/cy_crypto.h
View File

File diff suppressed because it is too large Load Diff

733
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/crypto/cy_crypto_common.h
View File

@ -1,733 +0,0 @@
/***************************************************************************//**
* \file cy_crypto_common.h
* \version 2.0
*
* \brief
* This file provides common constants and parameters
* for the Crypto driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CRYPTO_COMMON_H)
#define CY_CRYPTO_COMMON_H
#include <stddef.h>
#include <stdbool.h>
#include "cy_device_headers.h"
#include "sysint/cy_sysint.h"
#include "syslib/cy_syslib.h"
#ifndef CY_IP_MXCRYPTO
#error "The CRYPTO driver is not supported on this device"
#endif
#if (CPUSS_CRYPTO_PRESENT == 1)
#define CY_CRYPTO_CORE_ENABLE (1)
/** Driver major version */
#define CY_CRYPTO_DRV_VERSION_MAJOR 2
/** Driver minor version */
#define CY_CRYPTO_DRV_VERSION_MINOR 0
/** Defines the Crypto notify interrupt number */
#define CY_CRYPTO_IPC_INTR_NOTIFY_NUM CY_IPC_INTR_CRYPTO_SRV
/** Defines the Crypto release interrupt number */
#define CY_CRYPTO_IPC_INTR_RELEASE_NUM CY_IPC_INTR_CRYPTO_CLI
/**
* \addtogroup group_crypto_macros
* \{
*/
/** Defines Crypto_Sync blocking execution type parameter */
#define CY_CRYPTO_SYNC_BLOCKING (true)
/** Defines Crypto_Sync non-blocking execution type parameter */
#define CY_CRYPTO_SYNC_NON_BLOCKING (false)
/** Defines the Crypto DES key size (in bytes) */
#define CY_CRYPTO_DES_KEY_SIZE (8u)
/** Defines the Crypto TDES key size (in bytes) */
#define CY_CRYPTO_TDES_KEY_SIZE (24u)
/** Defines the Crypto AES block size (in bytes) */
#define CY_CRYPTO_AES_BLOCK_SIZE (16u)
/** Defines the Crypto AES_128 key maximum size (in bytes) */
#define CY_CRYPTO_AES_128_KEY_SIZE (16u)
/** Defines the Crypto AES_192 key maximum size (in bytes) */
#define CY_CRYPTO_AES_192_KEY_SIZE (24u)
/** Defines the Crypto AES_256 key maximum size (in bytes) */
#define CY_CRYPTO_AES_256_KEY_SIZE (32u)
/** Defines size of the AES block, in four-byte words */
#define CY_CRYPTO_AES_BLOCK_SIZE_U32 (uint32_t)(CY_CRYPTO_AES_BLOCK_SIZE / 4ul)
#if (CPUSS_CRYPTO_SHA == 1)
/** Hash size for the SHA1 mode (in bytes) */
#define CY_CRYPTO_SHA1_DIGEST_SIZE (20u)
/** Hash size for the SHA224 mode (in bytes) */
#define CY_CRYPTO_SHA224_DIGEST_SIZE (28u)
/** Hash size for the SHA256 mode (in bytes) */
#define CY_CRYPTO_SHA256_DIGEST_SIZE (32u)
/** Hash size for the SHA384 mode (in bytes) */
#define CY_CRYPTO_SHA384_DIGEST_SIZE (48u)
/** Hash size for the SHA512 mode (in bytes) */
#define CY_CRYPTO_SHA512_DIGEST_SIZE (64u)
/** Hash size for the SHA512_224 mode (in bytes) */
#define CY_CRYPTO_SHA512_224_DIGEST_SIZE (28u)
/** Hash size for the SHA512_256 mode (in bytes) */
#define CY_CRYPTO_SHA512_256_DIGEST_SIZE (32u)
#endif /* #if (CPUSS_CRYPTO_SHA == 1) */
#if (CPUSS_CRYPTO_VU == 1)
/** Processed message size for the RSA 1024Bit mode (in bytes) */
#define CY_CRYPTO_RSA1024_MESSAGE_SIZE (128)
/** Processed message size for the RSA 1536Bit mode (in bytes) */
#define CY_CRYPTO_RSA1536_MESSAGE_SIZE (192)
/** Processed message size for the RSA 2048Bit mode (in bytes) */
#define CY_CRYPTO_RSA2048_MESSAGE_SIZE (256)
#endif /* #if (CPUSS_CRYPTO_VU == 1) */
/** Crypto Driver PDL ID */
#define CY_CRYPTO_ID CY_PDL_DRV_ID(0x0Cu)
/** \} group_crypto_macros */
/**
* \addtogroup group_crypto_config_structure
* \{
*/
/** The Crypto user callback function type.
Callback is called at the end of Crypto calculation. */
typedef void (*cy_crypto_callback_ptr_t)(void);
/** The Crypto configuration structure. */
typedef struct
{
/** Defines the IPC channel used for client-server data exchange */
uint32_t ipcChannel;
/** Specifies the IPC notifier channel (IPC interrupt structure number)
to notify server that data for the operation is prepared */
uint32_t acquireNotifierChannel;
/** Specifies the IPC notifier channel (IPC interrupt structure number)
to notify client that operation is complete and data is valid */
uint32_t releaseNotifierChannel;
/** Specifies the release notifier interrupt configuration. It used for
internal purposes and user doesn't fill it. */
cy_stc_sysint_t releaseNotifierConfig;
/** User callback function.
If this field is NOT NULL, it called when Crypto operation
is complete. */
cy_crypto_callback_ptr_t userCompleteCallback;
#if (CY_CRYPTO_CORE_ENABLE)
/** Server-side user IRQ handler function, called when data for the
operation is prepared to process.
- If this field is NULL, server will use own interrupt handler
to get data.
- If this field is not NULL, server will call this interrupt handler.
This interrupt handler must call the
\ref Cy_Crypto_Server_GetDataHandler to get data to process.
Note: In the second case user should process data separately and
clear interrupt by calling \ref Cy_Crypto_Server_Process.
This model is used in the
multitasking environment. */
cy_israddress userGetDataHandler;
/** Server-side user IRQ handler function, called when a Crypto hardware
error occurs (interrupt was raised).
- If this field is NULL - server will use own interrupt handler
for error processing.
- If this field is not NULL - server will call this interrupt handler.
This interrupt handler must call the
\ref Cy_Crypto_Server_ErrorHandler to clear the interrupt. */
cy_israddress userErrorHandler;
/** Specifies the prepared data notifier interrupt configuration. It used
for internal purposes and user doesn't fill it. */
cy_stc_sysint_t acquireNotifierConfig;
/** Specifies the hardware error processing interrupt configuration. It used
for internal purposes and user doesn't fill it. */
cy_stc_sysint_t cryptoErrorIntrConfig;
#endif /* (CY_CRYPTO_CORE_ENABLE) */
} cy_stc_crypto_config_t;
/** \} group_crypto_config_structure */
/**
* \addtogroup group_crypto_cli_data_structures
* \{
*/
#if (CPUSS_CRYPTO_VU == 1)
/**
* Firmware allocates memory and provides a pointer to this structure in
* function calls. Firmware does not write or read values in this structure.
* The driver uses this structure to store and manipulate the RSA public key and
* additional coefficients to accelerate RSA calculation.
*
* RSA key contained from two fields:
* - n - modulus part of the key
* - e - exponent part of the key.
*
* Other fields are accelerating coefficients and can be calculated by
* \ref Cy_Crypto_Rsa_CalcCoefs.
*
* \note The <b>modulus</b> and <b>exponent</b> values in the
* \ref cy_stc_crypto_rsa_pub_key_t must also be in little-endian order.<br>
* Use \ref Cy_Crypto_Rsa_InvertEndianness function to convert to or from
* little-endian order.
*
*/
typedef struct
{
/** The pointer to the modulus part of public key. */
uint8_t *moduloPtr;
/** The modulus length, in bits, maximum supported size is 2048Bit */
uint32_t moduloLength;
/** The pointer to the exponent part of public key */
uint8_t *pubExpPtr;
/** The exponent length, in bits, maximum supported size is 256Bit */
uint32_t pubExpLength;
/** The pointer to the Barrett coefficient. Memory for it should be
allocated by user with size moduloLength + 1. */
uint8_t *barretCoefPtr;
/** The pointer to the binary inverse of the modulo. Memory for it
should be allocated by user with size moduloLength. */
uint8_t *inverseModuloPtr;
/** The pointer to the (2^moduloLength mod modulo). Memory for it should
be allocated by user with size moduloLength */
uint8_t *rBarPtr;
} cy_stc_crypto_rsa_pub_key_t;
#endif /* #if (CPUSS_CRYPTO_VU == 1) */
/** Structure for storing a description of a Crypto hardware error */
typedef struct
{
/**
Captures error description information:
for INSTR_OPC_ERROR: - violating the instruction.
for INSTR_CC_ERROR : - violating the instruction condition code.
for BUS_ERROR : - violating the transfer address. */
uint32_t errorStatus0;
/**
[31] - Specifies if ERROR_STATUS0 and ERROR_STATUS1 capture valid
error-information.
[26..24] - The error source:
"0": INSTR_OPC_ERROR - an instruction decoder error.
"1": INSTR_CC_ERROR - an instruction condition code-error.
"2": BUS_ERROR - a bus master interface AHB-Lite bus-error.
"3": TR_AP_DETECT_ERROR.
[23..0] - Captures error description information.
For BUS_ERROR:
- violating the transfer, read the attribute (DATA23[0]).
- violating the transfer, the size attribute (DATA23[5:4]).
"0": an 8-bit transfer;
"1": 16 bits transfer;
"2": 32-bit transfer. */
uint32_t errorStatus1;
} cy_stc_crypto_hw_error_t;
/** \} group_crypto_cli_data_structures */
/** The Crypto library functionality level. */
typedef enum
{
CY_CRYPTO_NO_LIBRARY = 0x00u,
CY_CRYPTO_BASE_LIBRARY = 0x01u,
CY_CRYPTO_EXTRA_LIBRARY = 0x02u,
CY_CRYPTO_FULL_LIBRARY = 0x03u,
} cy_en_crypto_lib_info_t;
/**
* \addtogroup group_crypto_enums
* \{
*/
#if (CPUSS_CRYPTO_AES == 1)
/** The key length options for the AES method. */
typedef enum
{
CY_CRYPTO_KEY_AES_128 = 0x00u, /**< The AES key size is 128 bits */
CY_CRYPTO_KEY_AES_192 = 0x01u, /**< The AES key size is 192 bits */
CY_CRYPTO_KEY_AES_256 = 0x02u /**< The AES key size is 256 bits */
} cy_en_crypto_aes_key_length_t;
#endif /* #if (CPUSS_CRYPTO_AES == 1) */
/** Defines the direction of the Crypto methods */
typedef enum
{
/** The forward mode, plain text will be encrypted into cipher text */
CY_CRYPTO_ENCRYPT = 0x00u,
/** The reverse mode, cipher text will be decrypted into plain text */
CY_CRYPTO_DECRYPT = 0x01u
} cy_en_crypto_dir_mode_t;
#if (CPUSS_CRYPTO_SHA == 1)
/** Defines modes of SHA method */
typedef enum
{
#if (CPUSS_CRYPTO_SHA1 == 1)
CY_CRYPTO_MODE_SHA1 = 0x00u, /**< Sets the SHA1 mode */
#endif /* #if (CPUSS_CRYPTO_SHA1 == 1) */
#if (CPUSS_CRYPTO_SHA256 == 1)
CY_CRYPTO_MODE_SHA224 = 0x11u, /**< Sets the SHA224 mode */
CY_CRYPTO_MODE_SHA256 = 0x01u, /**< Sets the SHA256 mode */
#endif /* #if (CPUSS_CRYPTO_SHA256 == 1) */
#if (CPUSS_CRYPTO_SHA512 == 1)
CY_CRYPTO_MODE_SHA384 = 0x12u, /**< Sets the SHA384 mode */
CY_CRYPTO_MODE_SHA512 = 0x02u, /**< Sets the SHA512 mode */
CY_CRYPTO_MODE_SHA512_256 = 0x22u, /**< Sets the SHA512/256 mode */
CY_CRYPTO_MODE_SHA512_224 = 0x32u /**< Sets the SHA512/224 mode */
#endif /* #if (CPUSS_CRYPTO_SHA512 == 1) */
} cy_en_crypto_sha_mode_t;
#endif /* #if (CPUSS_CRYPTO_SHA == 1) */
/** Signature verification status */
typedef enum
{
CY_CRYPTO_RSA_VERIFY_SUCCESS = 0x00u, /**< PKCS1-v1.5 verify SUCCESS */
CY_CRYPTO_RSA_VERIFY_FAIL = 0x01u /**< PKCS1-v1.5 verify FAILED */
} cy_en_crypto_rsa_ver_result_t;
/** Errors of the Crypto block */
typedef enum
{
/** Operation completed successfully. */
CY_CRYPTO_SUCCESS = 0x00u,
/** A hardware error occurred, detailed information is in stc_crypto_hw_error_t. */
CY_CRYPTO_HW_ERROR = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x01u,
/** The size of input data is not multiple of 16. */
CY_CRYPTO_SIZE_NOT_X16 = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x02u,
/** The key for the DES method is weak. */
CY_CRYPTO_DES_WEAK_KEY = CY_CRYPTO_ID | CY_PDL_STATUS_WARNING | 0x03u,
/** Communication between the client and server via IPC is broken. */
CY_CRYPTO_COMM_FAIL = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x04u,
/** The Crypto server is not started. */
CY_CRYPTO_SERVER_NOT_STARTED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x06u,
/** The Crypto server in process state. */
CY_CRYPTO_SERVER_BUSY = CY_CRYPTO_ID | CY_PDL_STATUS_INFO | 0x07u,
/** The Crypto driver is not initialized. */
CY_CRYPTO_NOT_INITIALIZED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x08u,
/** The Crypto hardware is not enabled. */
CY_CRYPTO_HW_NOT_ENABLED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x09u,
/** The Crypto operation is not supported. */
CY_CRYPTO_NOT_SUPPORTED = CY_CRYPTO_ID | CY_PDL_STATUS_ERROR | 0x0Au
} cy_en_crypto_status_t;
/** \} group_crypto_enums */
/** \cond INTERNAL */
/** Instruction to communicate between Client and Server */
typedef enum
{
CY_CRYPTO_INSTR_UNKNOWN = 0x00u,
CY_CRYPTO_INSTR_ENABLE = 0x01u,
CY_CRYPTO_INSTR_DISABLE = 0x02u,
#if (CPUSS_CRYPTO_PR == 1)
CY_CRYPTO_INSTR_PRNG_INIT = 0x03u,
CY_CRYPTO_INSTR_PRNG = 0x04u,
#endif /* #if (CPUSS_CRYPTO_PR == 1) */
#if (CPUSS_CRYPTO_TR == 1)
CY_CRYPTO_INSTR_TRNG_INIT = 0x05u,
CY_CRYPTO_INSTR_TRNG = 0x06u,
#endif /* #if (CPUSS_CRYPTO_PR == 1) */
#if (CPUSS_CRYPTO_AES == 1)
CY_CRYPTO_INSTR_AES_INIT = 0x07u,
CY_CRYPTO_INSTR_AES_ECB = 0x08u,
CY_CRYPTO_INSTR_AES_CBC = 0x09u,
CY_CRYPTO_INSTR_AES_CFB = 0x0Au,
CY_CRYPTO_INSTR_AES_CTR = 0x0Bu,
CY_CRYPTO_INSTR_CMAC = 0x0Cu,
#endif /* #if (CPUSS_CRYPTO_AES == 1) */
#if (CPUSS_CRYPTO_SHA == 1)
CY_CRYPTO_INSTR_SHA = 0x0Du,
#endif /* #if (CPUSS_CRYPTO_SHA == 1) */
#if (CPUSS_CRYPTO_SHA == 1)
CY_CRYPTO_INSTR_HMAC = 0x0Eu,
#endif /* #if (CPUSS_CRYPTO_SHA == 1) */
#if (CPUSS_CRYPTO_STR == 1)
CY_CRYPTO_INSTR_MEM_CPY = 0x0Fu,
CY_CRYPTO_INSTR_MEM_SET = 0x10u,
CY_CRYPTO_INSTR_MEM_CMP = 0x11u,
CY_CRYPTO_INSTR_MEM_XOR = 0x12u,
#endif /* #if (CPUSS_CRYPTO_STR == 1) */
#if (CPUSS_CRYPTO_CRC == 1)
CY_CRYPTO_INSTR_CRC_INIT = 0x13u,
CY_CRYPTO_INSTR_CRC = 0x14u,
#endif /* #if (CPUSS_CRYPTO_CRC == 1) */
#if (CPUSS_CRYPTO_DES == 1)
CY_CRYPTO_INSTR_DES = 0x15u,
CY_CRYPTO_INSTR_3DES = 0x16u,
#endif /* #if (CPUSS_CRYPTO_DES == 1) */
#if (CPUSS_CRYPTO_VU == 1)
CY_CRYPTO_INSTR_RSA_PROC = 0x17u,
CY_CRYPTO_INSTR_RSA_COEF = 0x18u,
#endif /* #if (CPUSS_CRYPTO_VU == 1) */
#if (CPUSS_CRYPTO_SHA == 1)
CY_CRYPTO_INSTR_RSA_VER = 0x19u,
#endif /* #if (CPUSS_CRYPTO_SHA == 1) */
CY_CRYPTO_INSTR_SRV_INFO = 0x55u
} cy_en_crypto_comm_instr_t;
/** \endcond */
/**
* \addtogroup group_crypto_cli_data_structures
* \{
*/
#if (CPUSS_CRYPTO_AES == 1)
/** Structure for storing the AES state */
typedef struct
{
/** Pointer to AES key */
uint32_t *key;
/** Pointer to AES inversed key */
uint32_t *invKey;
/** AES key length */
cy_en_crypto_aes_key_length_t keyLength;
/** AES processed block index (for CMAC, SHA operations) */
uint32_t blockIdx;
} cy_stc_crypto_aes_state_t;
#endif /* #if (CPUSS_CRYPTO_AES == 1) */
/** \} group_crypto_cli_data_structures */
/*************************************************************
* Structures used for communication between Client and Server
***************************************************************/
/**
* \addtogroup group_crypto_srv_data_structures
* \{
*/
/**
* Firmware allocates memory and provides a pointer to this structure in
* function calls. Firmware does not write or read values in this structure.
* The driver uses this structure to store and manipulate the server
* context.
*/
typedef struct
{
/** IPC communication channel number */
uint32_t ipcChannel;
/** IPC acquire interrupt channel number */
uint32_t acquireNotifierChannel;
/** IPC release interrupt channel number */
cy_israddress getDataHandlerPtr;
/** Crypto hardware errors interrupt handler */
cy_israddress errorHandlerPtr;
/** Acquire notifier interrupt configuration */
cy_stc_sysint_t acquireNotifierConfig;
/** Crypto hardware errors interrupt configuration */
cy_stc_sysint_t cryptoErrorIntrConfig;
/** Hardware error occurrence flag */
bool isHwErrorOccured;
} cy_stc_crypto_server_context_t;
/** \} group_crypto_srv_data_structures */
/**
* \addtogroup group_crypto_cli_data_structures
* \{
*/
/**
* Firmware allocates memory and provides a pointer to this structure in
* function calls. Firmware does not write or read values in this structure.
* The driver uses this structure to store and manipulate the global
* context.
*/
typedef struct
{
/** Operation instruction code */
cy_en_crypto_comm_instr_t instr;
/** Response from executed crypto function */
cy_en_crypto_status_t resp;
/** Hardware processing errors */
cy_stc_crypto_hw_error_t hwErrorStatus;
/** IPC communication channel number */
uint32_t ipcChannel;
/** IPC acquire interrupt channel number */
uint32_t acquireNotifierChannel;
/** IPC release interrupt channel number */
uint32_t releaseNotifierChannel;
/** User callback for Crypto HW calculation complete event */
cy_crypto_callback_ptr_t userCompleteCallback;
/** Release notifier interrupt configuration */
cy_stc_sysint_t releaseNotifierConfig;
/** Pointer to the crypto function specific context data */
void *xdata;
} cy_stc_crypto_context_t;
#if (CPUSS_CRYPTO_DES == 1)
/**
* Firmware allocates memory and provides a pointer to this structure in
* function calls. Firmware does not write or read values in this structure.
* The driver uses this structure to store and manipulate the DES operational
* context.
*/
typedef struct
{
/** Operation direction (Encrypt / Decrypt) */
cy_en_crypto_dir_mode_t dirMode;
/** Pointer to key data */
uint32_t *key;
/** Pointer to data destination block */
uint32_t *dst;
/** Pointer to data source block */
uint32_t *src;
} cy_stc_crypto_context_des_t;
#endif /* #if (CPUSS_CRYPTO_DES == 1) */
#if (CPUSS_CRYPTO_AES == 1)
/**
* Firmware allocates memory and provides a pointer to this structure in
* function calls. Firmware does not write or read values in this structure.
* The driver uses this structure to store and manipulate the AES operational
* context.
*/
typedef struct
{
/** AES state data */
cy_stc_crypto_aes_state_t aesState;
/** Operation direction (Encrypt / Decrypt) */
cy_en_crypto_dir_mode_t dirMode;
/** Operation data size */
uint32_t srcSize;
/** Size of the last non-complete block (for CTR mode only) */
uint32_t *srcOffset;
/** Initialization vector, in the CTR mode is used as nonceCounter */
uint32_t *ivPtr;
/** AES processed block pointer (for CTR mode only) */
uint32_t *streamBlock;
/** Pointer to data destination block */
uint32_t *dst;
/** Pointer to data source block */
uint32_t *src;
} cy_stc_crypto_context_aes_t;
#endif /* #if (CPUSS_CRYPTO_AES == 1) */
#if (CPUSS_CRYPTO_SHA == 1)
/**
* Firmware allocates memory and provides a pointer to this structure in
* function calls. Firmware does not write or read values in this structure.
* The driver uses this structure to store and manipulate the SHA operational
* context.
*/
typedef struct
{
/** Pointer to data source block */
uint32_t *message;
/** Operation data size */
uint32_t messageSize;
/** Pointer to data destination block */
uint32_t *dst;
/** SHA mode */
cy_en_crypto_sha_mode_t mode;
/** Pointer to key data (for HMAC only) */
uint32_t *key;
/** Key data length (for HMAC only) */
uint32_t keyLength;
} cy_stc_crypto_context_sha_t;
#endif /* #if (CPUSS_CRYPTO_SHA == 1) */
#if (CPUSS_CRYPTO_PR == 1)
/**
* Firmware allocates memory and provides a pointer to this structure in
* function calls. Firmware does not write or read values in this structure.
* The driver uses this structure to store and manipulate the PRNG operational
* context.
*/
typedef struct
{
uint32_t lfsr32InitState; /**< lfsr32 initialization data */
uint32_t lfsr31InitState; /**< lfsr31 initialization data */
uint32_t lfsr29InitState; /**< lfsr29 initialization data */
uint32_t max; /**< Maximum of the generated value */
uint32_t *prngNum; /**< Pointer to generated value */
} cy_stc_crypto_context_prng_t;
#endif /* #if (CPUSS_CRYPTO_PR == 1) */
#if (CPUSS_CRYPTO_TR == 1)
/**
* Firmware allocates memory and provides a pointer to this structure in
* function calls. Firmware does not write or read values in this structure.
* The driver uses this structure to store and manipulate the TRNG operational
* context.
*/
typedef struct
{
/**
The polynomial for the programmable Galois ring oscillator (TR_GARO_CTL).
The polynomial is represented WITHOUT the high order bit (this bit is
always assumed '1').
The polynomial should be aligned so that more significant bits
(bit 30 and down) contain the polynomial and less significant bits
(bit 0 and up) contain padding '0's. */
uint32_t GAROPol;
/**
The polynomial for the programmable Fibonacci ring oscillator(TR_FIRO_CTL).
The polynomial is represented WITHOUT the high order bit (this bit is
always assumed '1').
The polynomial should be aligned so that more significant bits
(bit 30 and down) contain the polynomial and less significant bits
(bit 0 and up) contain padding '0's. */
uint32_t FIROPol;
/** Maximum of the generated value */
uint32_t max;
/** Pointer to generated value */
uint32_t *trngNum;
} cy_stc_crypto_context_trng_t;
#endif /* #if (CPUSS_CRYPTO_TR == 1) */
#if (CPUSS_CRYPTO_STR == 1)
/**
* Firmware allocates memory and provides a pointer to this structure in
* function calls. Firmware does not write or read values in this structure.
* The driver uses this structure to store and manipulate the STR operational
* context.
*/
typedef struct
{
void const *src0; /**< Pointer to 1-st string source */
void const *src1; /**< Pointer to 2-nd string source */
void *dst; /**< Pointer to string destination */
uint32_t dataSize; /**< Operation data size */
uint32_t data; /**< Operation data value (for memory setting) */
} cy_stc_crypto_context_str_t;
#endif /* #if (CPUSS_CRYPTO_STR == 1) */
#if (CPUSS_CRYPTO_CRC == 1)
/**
* Firmware allocates memory and provides a pointer to this structure in
* function calls. Firmware does not write or read values in this structure.
* The driver uses this structure to store and manipulate the CRC operational
* context.
*/
typedef struct
{
void* srcData; /**< Pointer to data source block */
uint32_t dataSize; /**< Operation data size */
uint32_t *crc; /**< Pointer to CRC destination variable */
uint32_t polynomial; /**< Polynomial for CRC calculate */
uint32_t lfsrInitState; /**< CRC calculation initial value */
uint32_t dataReverse; /**< Input data reverse flag */
uint32_t dataXor; /**< Input data XOR flag */
uint32_t remReverse; /**< Output data reverse flag */
uint32_t remXor; /**< Output data XOR flag */
} cy_stc_crypto_context_crc_t;
#endif /* #if (CPUSS_CRYPTO_CRC == 1) */
/**
* Firmware allocates memory and provides a pointer to this structure in
* function calls. Firmware does not write or read values in this structure.
* The driver uses this structure to store and manipulate the RSA verifying
* context.
*/
typedef struct
{
/** Pointer to verification result /ref cy_en_crypto_rsa_ver_result_t */
cy_en_crypto_rsa_ver_result_t *verResult;
/** SHA digest type, used with SHA calculation of the message */
cy_en_crypto_sha_mode_t digestType;
/** SHA digest of the message, calculated with digestType */
uint32_t const *hash;
/** Previously decrypted RSA signature */
uint32_t const *decryptedSignature;
/** Length of the decrypted RSA signature */
uint32_t decryptedSignatureLength;
} cy_stc_crypto_context_rsa_ver_t;
#if (CPUSS_CRYPTO_VU == 1)
/**
* Firmware allocates memory and provides a pointer to this structure in
* function calls. Firmware does not write or read values in this structure.
* The driver uses this structure to store and manipulate the RSA operational
* context.
*/
typedef struct
{
/** Pointer to key data */
cy_stc_crypto_rsa_pub_key_t const *key;
/** Pointer to data source block */
uint32_t const *message;
/** Operation data size */
uint32_t messageSize;
/** Pointer to data destination block */
uint32_t *result;
} cy_stc_crypto_context_rsa_t;
#endif /* #if (CPUSS_CRYPTO_VU == 1) */
/** \} group_crypto_cli_data_structures */
#endif /* (CPUSS_CRYPTO_PRESENT == 1) */
#endif /* #if !defined(CY_CRYPTO_COMMON_H) */
/* [] END OF FILE */

69
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/crypto/cy_crypto_config.c
View File

@ -1,69 +0,0 @@
/***************************************************************************//**
* \file
* \version 2.0
*
* Description:
* This C file is not intended to be part of the Crypto driver. It is the code
* required to configure the crypto driver by user.
*
********************************************************************************
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cy_crypto_config.h"
#include "ipc/cy_ipc_drv.h"
#include "sysint/cy_sysint.h"
/** The Crypto configuration structure. */
const cy_stc_crypto_config_t cryptoConfig =
{
/* .ipcChannel */ CY_IPC_CHAN_CRYPTO,
/* .acquireNotifierChannel */ CY_CRYPTO_IPC_INTR_NOTIFY_NUM,
/* .releaseNotifierChannel */ CY_CRYPTO_IPC_INTR_RELEASE_NUM,
/* .releaseNotifierConfig */ {
#if (CY_CPU_CORTEX_M0P)
/* .intrSrc */ CY_CRYPTO_CM0_RELEASE_INTR_NR,
/* .cm0pSrc */ (cy_en_intr_t)CY_IPC_INTR_NUM_TO_VECT((int32_t)CY_CRYPTO_IPC_INTR_RELEASE_NUM),
#else
/* .intrSrc */ (IRQn_Type)CY_IPC_INTR_NUM_TO_VECT((int32_t)CY_CRYPTO_IPC_INTR_RELEASE_NUM),
#endif
/* .intrPriority */ CY_CRYPTO_RELEASE_INTR_PR,
},
/* .userCompleteCallback */ NULL
#if (CY_CRYPTO_CORE_ENABLE)
,
/* .userGetDataHandler */ NULL,
/* .userErrorHandler */ NULL,
/* .acquireNotifierConfig */ {
#if (CY_CPU_CORTEX_M0P)
/* .intrSrc */ CY_CRYPTO_CM0_NOTIFY_INTR_NR,
/* .cm0pSrc */ (cy_en_intr_t)CY_IPC_INTR_NUM_TO_VECT((int32_t)CY_CRYPTO_IPC_INTR_NOTIFY_NUM),
#else
/* .intrSrc */ (IRQn_Type)CY_IPC_INTR_NUM_TO_VECT((int32_t)CY_CRYPTO_IPC_INTR_NOTIFY_NUM),
#endif
/* .intrPriority */ CY_CRYPTO_NOTIFY_INTR_PR,
},
/* .cryptoErrorIntrConfig */ {
#if (CY_CPU_CORTEX_M0P)
/* .intrSrc */ CY_CRYPTO_CM0_ERROR_INTR_NR,
/* .cm0pSrc */ cpuss_interrupt_crypto_IRQn,
#else
/* .intrSrc */ cpuss_interrupt_crypto_IRQn,
#endif
/* .intrPriority */ CY_CRYPTO_ERROR_INTR_PR,
}
#endif
};
/* [] END OF FILE */

57
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/crypto/cy_crypto_config.h
View File

@ -1,57 +0,0 @@
/***************************************************************************//**
* \file cy_crypto_config.h
* \version 2.0
*
* \brief
* This file provides user parameters for the Crypto driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CRYPTO_CONFIG_H)
#define CY_CRYPTO_CONFIG_H
#include "cy_device_headers.h"
#include "crypto/cy_crypto_common.h"
/* Defines to configure Crypto driver */
extern const cy_stc_crypto_config_t cryptoConfig;
/**
* \addtogroup group_crypto_config_macros
* \{
*
* These constants defines an interrupts settings for IPC channel used for the
* client-server communications.
*
* On the CM4 core crypto driver uses IPC hardware depended interrupt sources.
*
* For CM0+ core user must define the multiplexed interrupt sources by yourself.
*/
/** Number of Crypto Notify interrupt mapped to CM0+ */
#define CY_CRYPTO_CM0_NOTIFY_INTR_NR (NvicMux2_IRQn)
/** Priority of Crypto Notify interrupt, equal to CM0+ and CM4 cores */
#define CY_CRYPTO_NOTIFY_INTR_PR (2u)
/** Number of Crypto Release interrupt mapped to CM0+ */
#define CY_CRYPTO_CM0_RELEASE_INTR_NR (NvicMux30_IRQn)
/** Priority of Crypto Release interrupt, equal to CM0+ and CM4 cores */
#define CY_CRYPTO_RELEASE_INTR_PR (2u)
/** Number of Crypto Error interrupt mapped to CM0+ */
#define CY_CRYPTO_CM0_ERROR_INTR_NR (NvicMux31_IRQn)
/** Priority of Crypto Error interrupt mapped to CM0+ */
#define CY_CRYPTO_ERROR_INTR_PR (2u)
/** \} group_crypto_config_macros */
#endif /* #if !defined(CY_CRYPTO_CONFIG_H) */
/* [] END OF FILE */

125
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/crypto/cy_crypto_server.h
View File

@ -1,125 +0,0 @@
/***************************************************************************//**
* \file cy_crypto_server.h
* \version 2.0
*
* \brief
* This file provides the prototypes for common API
* in the Crypto driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_CRYPTO_SERVER_H)
#define CY_CRYPTO_SERVER_H
#include "crypto/cy_crypto_common.h"
#include "syslib/cy_syslib.h"
#if (CY_CRYPTO_CORE_ENABLE)
#if (CPUSS_CRYPTO_PRESENT == 1)
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_crypto_srv_functions
* \{
*/
/*******************************************************************************
* Function Name: Cy_Crypto_Server_Start
****************************************************************************//**
*
* This function starts the Crypto server on the CM0+ core, sets up an interrupt
* for the IPC Crypto channel on the CM0+ core, sets up an interrupt
* to catch Crypto HW errors. Should be invoked only on CM0.
*
* This function available for CM0+ core only.
*
* \param config
* The Crypto configuration structure.
*
* \param context
* The pointer to the \ref cy_stc_crypto_server_context_t structure that stores
* the Crypto server context.
*
* \return
* A Crypto status \ref cy_en_crypto_status_t.
*
*******************************************************************************/
cy_en_crypto_status_t Cy_Crypto_Server_Start(cy_stc_crypto_config_t const *config,
cy_stc_crypto_server_context_t *context);
/*******************************************************************************
* Function Name: Cy_Crypto_Server_Stop
****************************************************************************//**
*
* This function stops the Crypto server by disabling the IPC notify interrupt
* and Crypto error interrupt. Should be invoked only on CM0.
*
* This function available for CM0+ core only.
*
* \return
* A Crypto status \ref cy_en_crypto_status_t.
*
*******************************************************************************/
cy_en_crypto_status_t Cy_Crypto_Server_Stop(void);
/*******************************************************************************
* Function Name: Cy_Crypto_Server_Process
****************************************************************************//**
*
* This function parses input data received from the Crypto Client,
* runs the appropriate Crypto function and releases the Crypto IPC channel.
*
* This function available for CM0+ core only.
*
*******************************************************************************/
void Cy_Crypto_Server_Process(void);
/*******************************************************************************
* Function Name: Cy_Crypto_Server_GetDataHandler
****************************************************************************//**
*
* This function is a IPC Crypto channel notify interrupt-routine.
* It receives information from the Crypto client,
* runs the process if user not setup own handler.
*
* This function available for CM0+ core only.
*
*******************************************************************************/
void Cy_Crypto_Server_GetDataHandler(void);
/*******************************************************************************
* Function Name: Cy_Crypto_Server_ErrorHandler
****************************************************************************//**
*
* This function is a routine to handle an interrupt caused by the Crypto hardware error.
*
* This function available for CM0+ core only.
*
*******************************************************************************/
void Cy_Crypto_Server_ErrorHandler(void);
/** \} group_crypto_srv_functions */
#if defined(__cplusplus)
}
#endif
#endif /* #if (CPUSS_CRYPTO_PRESENT == 1) */
#endif /* #if (CY_CRYPTO_CORE_ENABLE) */
#endif /* #if !defined(CY_CRYPTO_SERVER_H) */
/* [] END OF FILE */

6
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctb/cy_ctb.c
View File

@ -7,10 +7,8 @@
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ctb/cy_ctb.h"

6
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctb/cy_ctb.h
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**

6
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctdac/cy_ctdac.c
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ctdac/cy_ctdac.h"

6
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ctdac/cy_ctdac.h
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**

66
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/dma/cy_dma.c
View File

@ -7,10 +7,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_dma.h"
@ -54,7 +52,7 @@ cy_en_dma_status_t Cy_DMA_Descriptor_Init(cy_stc_dma_descriptor_t * descriptor,
CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(config->channelState));
CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(config->dataSize));
CY_ASSERT_L3(CY_DMA_IS_TYPE_VALID(config->descriptorType));
descriptor->ctl =
_VAL2FLD(CY_DMA_CTL_RETRIG, config->retrigger) |
_VAL2FLD(CY_DMA_CTL_INTR_TYPE, config->interruptType) |
@ -82,37 +80,37 @@ cy_en_dma_status_t Cy_DMA_Descriptor_Init(cy_stc_dma_descriptor_t * descriptor,
CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->srcXincrement));
CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->dstXincrement));
CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(config->xCount));
descriptor->xCtl =
_VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcXincrement) |
_VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstXincrement) |
/* Convert the data count from the user's range (1-256) into the machine range (0-255). */
_VAL2FLD(CY_DMA_CTL_COUNT, config->xCount - 1UL);
descriptor->yCtl = (uint32_t)config->nextDescriptor;
break;
}
case CY_DMA_2D_TRANSFER:
{
{
CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->srcXincrement));
CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->dstXincrement));
CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(config->xCount));
CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->srcYincrement));
CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(config->dstYincrement));
CY_ASSERT_L2(CY_DMA_IS_COUNT_VALID(config->yCount));
descriptor->xCtl =
_VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcXincrement) |
_VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstXincrement) |
/* Convert the data count from the user's range (1-256) into the machine range (0-255). */
_VAL2FLD(CY_DMA_CTL_COUNT, config->xCount - 1UL);
descriptor->yCtl =
_VAL2FLD(CY_DMA_CTL_SRC_INCR, config->srcYincrement) |
_VAL2FLD(CY_DMA_CTL_DST_INCR, config->dstYincrement) |
/* Convert the data count from the user's range (1-256) into the machine range (0-255). */
_VAL2FLD(CY_DMA_CTL_COUNT, config->yCount - 1UL);
descriptor->nextPtr = (uint32_t)config->nextDescriptor;
break;
}
@ -178,7 +176,7 @@ cy_en_dma_status_t Cy_DMA_Channel_Init(DW_Type * base, uint32_t channel, cy_stc_
if (((CY_DMA_IS_DW_CH_NR_VALID(base, channel)) && (NULL != channelConfig) && (NULL != channelConfig->descriptor)))
{
CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(channelConfig->priority));
/* Set the current descriptor */
base->CH_STRUCT[channel].CH_CURR_PTR = (uint32_t)channelConfig->descriptor;
@ -210,7 +208,7 @@ cy_en_dma_status_t Cy_DMA_Channel_Init(DW_Type * base, uint32_t channel, cy_stc_
void Cy_DMA_Channel_DeInit(DW_Type * base, uint32_t channel)
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
base->CH_STRUCT[channel].CH_CTL = 0UL;
base->CH_STRUCT[channel].CH_IDX = 0UL;
base->CH_STRUCT[channel].CH_CURR_PTR = 0UL;
@ -226,8 +224,8 @@ void Cy_DMA_Channel_DeInit(DW_Type * base, uint32_t channel)
*
* Based on the descriptor type, the offset of the address for the next descriptor may
* vary. For the single-transfer descriptor type, this register is at offset 0x0c.
* For the 1D-transfer descriptor type, this register is at offset 0x10.
* For the 2D-transfer descriptor type, this register is at offset 0x14.
* For the 1D-transfer descriptor type, this register is at offset 0x10.
* For the 2D-transfer descriptor type, this register is at offset 0x14.
*
* \param descriptor
* The descriptor structure instance declared by the user/component.
@ -239,21 +237,21 @@ void Cy_DMA_Channel_DeInit(DW_Type * base, uint32_t channel)
void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor)
{
CY_ASSERT_L1(NULL != descriptor);
switch((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl))
{
case CY_DMA_SINGLE_TRANSFER:
descriptor->xCtl = (uint32_t)nextDescriptor;
break;
case CY_DMA_1D_TRANSFER:
descriptor->yCtl = (uint32_t)nextDescriptor;
break;
case CY_DMA_2D_TRANSFER:
descriptor->nextPtr = (uint32_t)nextDescriptor;
break;
default:
/* Unsupported type of descriptor */
break;
@ -269,8 +267,8 @@ void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, c
*
* Based on the descriptor type, the offset of the address for the next descriptor may
* vary. For a single-transfer descriptor type, this register is at offset 0x0c.
* For the 1D-transfer descriptor type, this register is at offset 0x10.
* For the 2D-transfer descriptor type, this register is at offset 0x14.
* For the 1D-transfer descriptor type, this register is at offset 0x10.
* For the 2D-transfer descriptor type, this register is at offset 0x14.
*
* \param descriptor
* The descriptor structure instance declared by the user/component.
@ -282,28 +280,28 @@ void Cy_DMA_Descriptor_SetNextDescriptor(cy_stc_dma_descriptor_t * descriptor, c
cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor(cy_stc_dma_descriptor_t const * descriptor)
{
cy_stc_dma_descriptor_t * retVal = NULL;
CY_ASSERT_L1(NULL != descriptor);
switch((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl))
{
case CY_DMA_SINGLE_TRANSFER:
retVal = (cy_stc_dma_descriptor_t*) descriptor->xCtl;
break;
case CY_DMA_1D_TRANSFER:
retVal = (cy_stc_dma_descriptor_t*) descriptor->yCtl;
break;
case CY_DMA_2D_TRANSFER:
retVal = (cy_stc_dma_descriptor_t*) descriptor->nextPtr;
break;
default:
/* An unsupported type of the descriptor */
break;
}
return (retVal);
}
@ -315,19 +313,19 @@ cy_stc_dma_descriptor_t * Cy_DMA_Descriptor_GetNextDescriptor(cy_stc_dma_descrip
* Sets the descriptor's type for the specified descriptor.
* Moves the next descriptor register value into the proper place in accordance
* to the actual descriptor type.
* During the descriptor's type changing, the Xloop and Yloop settings, such as
* data count and source/destination increment (i.e. the content of the
* xCtl and yCtl descriptor registers) might be lost (overriden by the
* During the descriptor's type changing, the Xloop and Yloop settings, such as
* data count and source/destination increment (i.e. the content of the
* xCtl and yCtl descriptor registers) might be lost (overriden by the
* next descriptor value) because of the different descriptor registers structures
* for different descriptor types. Set up carefully the Xloop
* (and Yloop, if used) data count and source/destination increment if the
* descriptor type is changed from a simpler to a more complicated type
* descriptor type is changed from a simpler to a more complicated type
* ("single transfer" -> "1D", "1D" -> "2D", etc.).
*
*
* \param descriptor
* The descriptor structure instance declared by the user/component.
*
* \param descriptorType
* \param descriptorType
* The descriptor type \ref cy_en_dma_descriptor_type_t.
*
*******************************************************************************/
@ -335,7 +333,7 @@ void Cy_DMA_Descriptor_SetDescriptorType(cy_stc_dma_descriptor_t * descriptor, c
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L3(CY_DMA_IS_TYPE_VALID(descriptorType));
if (descriptorType != Cy_DMA_Descriptor_GetDescriptorType(descriptor)) /* Don't perform if the type is not changed */
{
/* Store the current nextDescriptor pointer. */

200
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/dma/cy_dma.h
View File

@ -7,10 +7,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
@ -21,11 +19,11 @@
* The DMA channel can be used in any project to transfer data
* without CPU intervention basing on a hardware trigger signal from another component.
*
* A device may support more than one DMA hardware block. Each block has a set of
* registers, a base hardware address, and supports multiple channels.
* Many API functions for the DMA driver require a base hardware address and
* A device may support more than one DMA hardware block. Each block has a set of
* registers, a base hardware address, and supports multiple channels.
* Many API functions for the DMA driver require a base hardware address and
* channel number. Ensure that you use the correct hardware address for the DMA block in use.
*
*
* Features:
* * Devices support up to two DMA hardware blocks
* * Each DMA block supports up to 16 DMA channels
@ -38,14 +36,14 @@
*
* To set up a DMA driver, initialize a descriptor,
* intialize and enable a channel, and enable the DMA block.
*
* To set up a descriptor, provide the configuration parameters for the
* descriptor in the \ref cy_stc_dma_descriptor_config_t structure. Then call the
* \ref Cy_DMA_Descriptor_Init function to initialize the descriptor in SRAM. You can
* modify the source and destination addresses dynamically by calling
*
* To set up a descriptor, provide the configuration parameters for the
* descriptor in the \ref cy_stc_dma_descriptor_config_t structure. Then call the
* \ref Cy_DMA_Descriptor_Init function to initialize the descriptor in SRAM. You can
* modify the source and destination addresses dynamically by calling
* \ref Cy_DMA_Descriptor_SetSrcAddress and \ref Cy_DMA_Descriptor_SetDstAddress.
*
* To set up a DMA channel, provide a filled \ref cy_stc_dma_channel_config_t
*
* To set up a DMA channel, provide a filled \ref cy_stc_dma_channel_config_t
* structure. Call the \ref Cy_DMA_Channel_Init function, specifying the channel
* number. Use \ref Cy_DMA_Channel_Enable to enable the configured DMA channel.
*
@ -60,15 +58,15 @@
* in a typical user application:
* \image html dma.png
*
* <B>NOTE:</B> Even if a DMA channel is enabled, it is not operational until
* <B>NOTE:</B> Even if a DMA channel is enabled, it is not operational until
* the DMA block is enabled using function \ref Cy_DMA_Enable.\n
* <B>NOTE:</B> if the DMA descriptor is configured to generate an interrupt,
* the interrupt must be enabled using the \ref Cy_DMA_Channel_SetInterruptMask
* <B>NOTE:</B> if the DMA descriptor is configured to generate an interrupt,
* the interrupt must be enabled using the \ref Cy_DMA_Channel_SetInterruptMask
* function for each DMA channel.
*
* For example:
* \snippet dma/dma_v2_0_sut_00.cydsn/main_cm4.c Cy_DMA_Snippet
*
*
* \section group_dma_more_information More Information.
* See: the DMA chapter of the device technical reference manual (TRM);
* the DMA Component datasheet;
@ -120,10 +118,10 @@
* The \ref Cy_DMA_Descriptor_Init function sets a full bunch of descriptor
* settings, and the rest of the descriptor API is a get/set interface
* to each of the descriptor settings.
* * There is a group of macros to support the backward compatibility with most
* * There is a group of macros to support the backward compatibility with most
* of the driver version 1.0 API. But, it is strongly recommended to use
* the new v2.0 interface in new designs (do not just copy-paste from old
* projects). To enable the backward compatibility support, the CY_DMA_BWC
* projects). To enable the backward compatibility support, the CY_DMA_BWC
* definition should be changed to "1".</td>
* <td></td>
* </tr>
@ -180,11 +178,11 @@ extern "C" {
/** The DMA driver identifier */
#define CY_DMA_ID (CY_PDL_DRV_ID(0x13U))
/** The DMA channel interrupt mask */
#define CY_DMA_INTR_MASK (0x01UL)
/** The backward compatibility flag. Enables a group of macros which provide
/** The backward compatibility flag. Enables a group of macros which provide
* the backward compatibility with most of the DMA driver version 1.0 interface. */
#ifndef CY_DMA_BWC
#define CY_DMA_BWC (0U)
@ -261,7 +259,7 @@ typedef enum
} cy_en_dma_channel_state_t;
/** This enum has the return values of the DMA driver */
typedef enum
typedef enum
{
CY_DMA_SUCCESS = 0x00UL, /**< Success. */
CY_DMA_BAD_PARAM = CY_DMA_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< The input parameters passed to the DMA API are not valid. */
@ -281,26 +279,26 @@ typedef enum
(CY_DMA_RETRIG_4CYC == (retrigger)) || \
(CY_DMA_RETRIG_16CYC == (retrigger)) || \
(CY_DMA_WAIT_FOR_REACT == (retrigger)))
#define CY_DMA_IS_TRIG_TYPE_VALID(trigType) ((CY_DMA_1ELEMENT == (trigType)) || \
(CY_DMA_X_LOOP == (trigType)) || \
(CY_DMA_DESCR == (trigType)) || \
(CY_DMA_DESCR_CHAIN == (trigType)))
#define CY_DMA_IS_XFER_SIZE_VALID(xferSize) ((CY_DMA_TRANSFER_SIZE_DATA == (xferSize)) || \
(CY_DMA_TRANSFER_SIZE_WORD == (xferSize)))
#define CY_DMA_IS_CHANNEL_STATE_VALID(state) ((CY_DMA_CHANNEL_ENABLED == (state)) || \
(CY_DMA_CHANNEL_DISABLED == (state)))
#define CY_DMA_IS_DATA_SIZE_VALID(dataSize) ((CY_DMA_BYTE == (dataSize)) || \
(CY_DMA_HALFWORD == (dataSize)) || \
(CY_DMA_WORD == (dataSize)))
#define CY_DMA_IS_TYPE_VALID(descrType) ((CY_DMA_SINGLE_TRANSFER == (descrType)) || \
(CY_DMA_1D_TRANSFER == (descrType)) || \
(CY_DMA_2D_TRANSFER == (descrType)))
#define CY_DMA_IS_DW_CH_NR_VALID(dwNr, chNr) (((0U != CPUSS_DW0_PRESENT) && (DW0 == (dwNr)) && ((chNr) < CPUSS_DW0_CH_NR)) || \
((0U != CPUSS_DW1_PRESENT) && (DW1 == (dwNr)) && ((chNr) < CPUSS_DW1_CH_NR)))
@ -339,14 +337,14 @@ typedef enum
* \{
*/
/**
* DMA descriptor structure type. It is a user/component-declared structure
/**
* DMA descriptor structure type. It is a user/component-declared structure
* allocated in RAM. The DMA HW requires a pointer to this structure to work with it.
*
* For advanced users: the descriptor can be allocated even in Flash, then the user
* manually predefines all the structure items with constants,
* manually predefines all the structure items with constants,
* bacause most of the driver's API (especially functions modifying
* descriptors, including \ref Cy_DMA_Descriptor_Init()) can't work with
* descriptors, including \ref Cy_DMA_Descriptor_Init()) can't work with
* read-only descriptors.
*/
typedef struct
@ -422,7 +420,7 @@ __STATIC_INLINE void * Cy_DMA_GetActiveDstAddress(DW_Type const * base);
cy_en_dma_status_t Cy_DMA_Descriptor_Init (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_config_t const * config);
void Cy_DMA_Descriptor_DeInit(cy_stc_dma_descriptor_t * descriptor);
void Cy_DMA_Descriptor_SetNextDescriptor (cy_stc_dma_descriptor_t * descriptor, cy_stc_dma_descriptor_t const * nextDescriptor);
void Cy_DMA_Descriptor_SetDescriptorType (cy_stc_dma_descriptor_t * descriptor, cy_en_dma_descriptor_type_t descriptorType);
__STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress (cy_stc_dma_descriptor_t * descriptor, void const * srcAddress);
@ -623,7 +621,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcAddress(cy_stc_dma_descriptor_t * d
****************************************************************************//**
*
* Returns the source address parameter of the specified descriptor.
*
*
* \param descriptor
* The descriptor structure instance declared by the user/component.
*
@ -661,7 +659,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetDstAddress(cy_stc_dma_descriptor_t * d
****************************************************************************//**
*
* Returns the destination address parameter of the specified descriptor.
*
*
* \param descriptor
* The descriptor structure instance declared by the user/component.
*
@ -692,7 +690,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(interruptType));
descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_INTR_TYPE, interruptType);
}
@ -708,12 +706,12 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetInterruptType(cy_stc_dma_descriptor_t
*
* \return
* The Interrupt-Type \ref cy_en_dma_trigger_type_t.
*
*
*******************************************************************************/
__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetInterruptType(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_INTR_TYPE, descriptor->ctl));
}
@ -735,7 +733,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerInType));
descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_TR_IN_TYPE, triggerInType);
}
@ -751,12 +749,12 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerInType(cy_stc_dma_descriptor_t
*
* \return
* The Trigger-In-Type \ref cy_en_dma_trigger_type_t
*
*
*******************************************************************************/
__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerInType(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_IN_TYPE, descriptor->ctl));
}
@ -778,7 +776,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(triggerOutType));
descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_TR_OUT_TYPE, triggerOutType);
}
@ -794,12 +792,12 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetTriggerOutType(cy_stc_dma_descriptor_t
*
* \return
* The Trigger-Out-Type parameter \ref cy_en_dma_trigger_type_t.
*
*
*******************************************************************************/
__STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
return((cy_en_dma_trigger_type_t) _FLD2VAL(CY_DMA_CTL_TR_OUT_TYPE, descriptor->ctl));
}
@ -815,13 +813,13 @@ __STATIC_INLINE cy_en_dma_trigger_type_t Cy_DMA_Descriptor_GetTriggerOutType(cy_
*
* \param dataSize
* The Data Element Size \ref cy_en_dma_data_size_t
*
*
*******************************************************************************/
__STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * descriptor, cy_en_dma_data_size_t dataSize)
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(dataSize));
descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_DATA_SIZE, dataSize);
}
@ -837,12 +835,12 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetDataSize(cy_stc_dma_descriptor_t * des
*
* \return
* The Data Element Size \ref cy_en_dma_data_size_t.
*
*
*******************************************************************************/
__STATIC_INLINE cy_en_dma_data_size_t Cy_DMA_Descriptor_GetDataSize(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
return((cy_en_dma_data_size_t) _FLD2VAL(CY_DMA_CTL_DATA_SIZE, descriptor->ctl));
}
@ -880,12 +878,12 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetSrcTransferSize(cy_stc_dma_descriptor_
*
* \return
* The Source Transfer Size \ref cy_en_dma_transfer_size_t.
*
*
*******************************************************************************/
__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetSrcTransferSize(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_SRC_SIZE, descriptor->ctl));
}
@ -907,7 +905,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(dstTransferSize));
descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_DST_SIZE, dstTransferSize);
}
@ -923,12 +921,12 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetDstTransferSize(cy_stc_dma_descriptor_
*
* \return
* The Destination Transfer Size \ref cy_en_dma_transfer_size_t
*
*
*******************************************************************************/
__STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
return((cy_en_dma_transfer_size_t) _FLD2VAL(CY_DMA_CTL_DST_SIZE, descriptor->ctl));
}
@ -937,13 +935,13 @@ __STATIC_INLINE cy_en_dma_transfer_size_t Cy_DMA_Descriptor_GetDstTransferSize(c
* Function Name: Cy_DMA_Descriptor_SetRetrigger
****************************************************************************//**
*
* Sets the retrigger value which specifies whether the controller should
* Sets the retrigger value which specifies whether the controller should
* wait for the input trigger to be deactivated.
*
* \param descriptor
* The descriptor structure instance declared by the user/component.
*
* \param retrigger
* \param retrigger
* The \ref cy_en_dma_retrigger_t parameter specifies whether the controller
* should wait for the input trigger to be deactivated.
*
@ -952,7 +950,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * de
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L3(CY_DMA_IS_RETRIGGER_VALID(retrigger));
descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_RETRIG, retrigger);
}
@ -961,7 +959,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * de
* Function Name: Cy_DMA_Descriptor_GetRetrigger
****************************************************************************//**
*
* Returns a value which specifies whether the controller should
* Returns a value which specifies whether the controller should
* wait for the input trigger to be deactivated.
*
* \param descriptor
@ -969,12 +967,12 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetRetrigger(cy_stc_dma_descriptor_t * de
*
* \return
* The Retrigger setting \ref cy_en_dma_retrigger_t.
*
*
*******************************************************************************/
__STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
return((cy_en_dma_retrigger_t) _FLD2VAL(CY_DMA_CTL_RETRIG, descriptor->ctl));
}
@ -990,12 +988,12 @@ __STATIC_INLINE cy_en_dma_retrigger_t Cy_DMA_Descriptor_GetRetrigger(cy_stc_dma_
*
* \return
* The descriptor type \ref cy_en_dma_descriptor_type_t
*
*
*******************************************************************************/
__STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
return((cy_en_dma_descriptor_type_t) _FLD2VAL(CY_DMA_CTL_TYPE, descriptor->ctl));
}
@ -1009,7 +1007,7 @@ __STATIC_INLINE cy_en_dma_descriptor_type_t Cy_DMA_Descriptor_GetDescriptorType(
* \param descriptor
* The descriptor structure instance declared by the user/component.
*
* \param channelState
* \param channelState
* The channel state \ref cy_en_dma_channel_state_t.
*
*******************************************************************************/
@ -1017,7 +1015,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t *
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(channelState));
descriptor->ctl = _CLR_SET_FLD32U(descriptor->ctl, CY_DMA_CTL_CH_DISABLE, channelState);
}
@ -1033,12 +1031,12 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetChannelState(cy_stc_dma_descriptor_t *
*
* \return
* The Channel State setting \ref cy_en_dma_channel_state_t
*
*
*******************************************************************************/
__STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
return((cy_en_dma_channel_state_t) _FLD2VAL(CY_DMA_CTL_CH_DISABLE, descriptor->ctl));
}
@ -1055,7 +1053,7 @@ __STATIC_INLINE cy_en_dma_channel_state_t Cy_DMA_Descriptor_GetChannelState(cy_s
*
* \param xCount
* The number of data elements to transfer in the X loop.
*
*
*******************************************************************************/
__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t xCount)
{
@ -1079,7 +1077,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDataCount(cy_stc_dma_descriptor_t
*
* \return
* The number of data elements to transfer in the X loop.
*
*
*******************************************************************************/
__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetXloopDataCount(cy_stc_dma_descriptor_t const * descriptor)
{
@ -1109,7 +1107,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descripto
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(srcXincrement));
descriptor->xCtl = _CLR_SET_FLD32U(descriptor->xCtl, CY_DMA_CTL_SRC_INCR, srcXincrement);
}
@ -1126,13 +1124,13 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopSrcIncrement(cy_stc_dma_descripto
*
* \return
* The value of the source increment.
*
*
*******************************************************************************/
__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->xCtl));
}
@ -1149,14 +1147,14 @@ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopSrcIncrement(cy_stc_dma_descri
*
* \param dstXincrement
* The value of the destination increment. The valid range is -2048 ... 2047.
*
*
*******************************************************************************/
__STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t dstXincrement)
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(dstXincrement));
descriptor->xCtl = _CLR_SET_FLD32U(descriptor->xCtl, CY_DMA_CTL_DST_INCR, dstXincrement);
}
@ -1173,13 +1171,13 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetXloopDstIncrement(cy_stc_dma_descripto
*
* \return
* The value of the destination increment.
*
*
*******************************************************************************/
__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L1(CY_DMA_SINGLE_TRANSFER != Cy_DMA_Descriptor_GetDescriptorType(descriptor));
return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->xCtl));
}
@ -1196,7 +1194,7 @@ __STATIC_INLINE int32_t Cy_DMA_Descriptor_GetXloopDstIncrement(cy_stc_dma_descri
*
* \param yCount
* The number of X loops to execute in the Y loop.
*
*
*******************************************************************************/
__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t * descriptor, uint32_t yCount)
{
@ -1220,7 +1218,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDataCount(cy_stc_dma_descriptor_t
*
* \return
* The number of X loops to execute in the Y loop.
*
*
*******************************************************************************/
__STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descriptor_t const * descriptor)
{
@ -1243,14 +1241,14 @@ __STATIC_INLINE uint32_t Cy_DMA_Descriptor_GetYloopDataCount(cy_stc_dma_descript
*
* \param srcYincrement
* The value of the source increment. The valid range is -2048 ... 2047.
*
*
*******************************************************************************/
__STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descriptor_t * descriptor, int32_t srcYincrement)
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(srcYincrement));
descriptor->yCtl = _CLR_SET_FLD32U(descriptor->yCtl, CY_DMA_CTL_SRC_INCR, srcYincrement);
}
@ -1267,13 +1265,13 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopSrcIncrement(cy_stc_dma_descripto
*
* \return
* The value of source increment.
*
*
*******************************************************************************/
__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopSrcIncrement(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
return ((int32_t) _FLD2VAL(CY_DMA_CTL_SRC_INCR, descriptor->yCtl));
}
@ -1297,7 +1295,7 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descripto
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
CY_ASSERT_L2(CY_DMA_IS_INCR_VALID(dstYincrement));
descriptor->yCtl = _CLR_SET_FLD32U(descriptor->yCtl, CY_DMA_CTL_DST_INCR, dstYincrement);
}
@ -1307,20 +1305,20 @@ __STATIC_INLINE void Cy_DMA_Descriptor_SetYloopDstIncrement(cy_stc_dma_descripto
****************************************************************************//**
*
* Returns the destination increment parameter for the Y loop of the specified
* descriptor (for 2D descriptors only).
* descriptor (for 2D descriptors only).
*
* \param descriptor
* The descriptor structure instance declared by the user/component.
*
* \return
* The value of the destination increment.
*
*
*******************************************************************************/
__STATIC_INLINE int32_t Cy_DMA_Descriptor_GetYloopDstIncrement(cy_stc_dma_descriptor_t const * descriptor)
{
CY_ASSERT_L1(NULL != descriptor);
CY_ASSERT_L1(CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(descriptor));
return ((int32_t) _FLD2VAL(CY_DMA_CTL_DST_INCR, descriptor->yCtl));
}
@ -1354,7 +1352,7 @@ __STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t chann
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
CY_ASSERT_L1(NULL != descriptor);
base->CH_STRUCT[channel].CH_CURR_PTR = (uint32_t)descriptor;
base->CH_STRUCT[channel].CH_IDX &= (uint32_t) ~(DW_CH_STRUCT_CH_IDX_X_IDX_Msk | DW_CH_STRUCT_CH_IDX_Y_IDX_Msk);
}
@ -1376,7 +1374,7 @@ __STATIC_INLINE void Cy_DMA_Channel_SetDescriptor(DW_Type * base, uint32_t chann
__STATIC_INLINE void Cy_DMA_Channel_Enable(DW_Type * base, uint32_t channel)
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
base->CH_STRUCT[channel].CH_CTL |= DW_CH_STRUCT_CH_CTL_ENABLED_Msk;
}
@ -1397,7 +1395,7 @@ __STATIC_INLINE void Cy_DMA_Channel_Enable(DW_Type * base, uint32_t channel)
__STATIC_INLINE void Cy_DMA_Channel_Disable(DW_Type * base, uint32_t channel)
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
base->CH_STRUCT[channel].CH_CTL &= (uint32_t) ~DW_CH_STRUCT_CH_CTL_ENABLED_Msk;
}
@ -1422,7 +1420,7 @@ __STATIC_INLINE void Cy_DMA_Channel_SetPriority(DW_Type * base, uint32_t channel
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
CY_ASSERT_L2(CY_DMA_IS_PRIORITY_VALID(priority));
base->CH_STRUCT[channel].CH_CTL = _CLR_SET_FLD32U(base->CH_STRUCT[channel].CH_CTL, DW_CH_STRUCT_CH_CTL_PRIO, priority);
}
@ -1446,7 +1444,7 @@ __STATIC_INLINE void Cy_DMA_Channel_SetPriority(DW_Type * base, uint32_t channel
__STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority(DW_Type const * base, uint32_t channel)
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
return ((uint32_t) _FLD2VAL(DW_CH_STRUCT_CH_CTL_PRIO, base->CH_STRUCT[channel].CH_CTL));
}
@ -1470,7 +1468,7 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetPriority(DW_Type const * base, uint32
__STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW_Type const * base, uint32_t channel)
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
return ((cy_stc_dma_descriptor_t*)(base->CH_STRUCT[channel].CH_CURR_PTR));
}
@ -1495,7 +1493,7 @@ __STATIC_INLINE cy_stc_dma_descriptor_t * Cy_DMA_Channel_GetCurrentDescriptor(DW
__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base, uint32_t channel)
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
return (base->CH_STRUCT[channel].INTR);
}
@ -1519,7 +1517,7 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatus(DW_Type const * base,
__STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const * base, uint32_t channel)
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
return ((cy_en_dma_intr_cause_t) _FLD2VAL(DW_CH_STRUCT_CH_STATUS_INTR_CAUSE, base->CH_STRUCT[channel].CH_STATUS));
}
@ -1540,7 +1538,7 @@ __STATIC_INLINE cy_en_dma_intr_cause_t Cy_DMA_Channel_GetStatus(DW_Type const *
__STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt(DW_Type * base, uint32_t channel)
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
base->CH_STRUCT[channel].INTR = CY_DMA_INTR_MASK;
(void) base->CH_STRUCT[channel].INTR;
}
@ -1562,7 +1560,7 @@ __STATIC_INLINE void Cy_DMA_Channel_ClearInterrupt(DW_Type * base, uint32_t chan
__STATIC_INLINE void Cy_DMA_Channel_SetInterrupt(DW_Type * base, uint32_t channel)
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
base->CH_STRUCT[channel].INTR_SET = CY_DMA_INTR_MASK;
}
@ -1586,7 +1584,7 @@ __STATIC_INLINE void Cy_DMA_Channel_SetInterrupt(DW_Type * base, uint32_t channe
__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptMask(DW_Type const * base, uint32_t channel)
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
return (base->CH_STRUCT[channel].INTR_MASK);
}
@ -1633,7 +1631,7 @@ __STATIC_INLINE void Cy_DMA_Channel_SetInterruptMask(DW_Type * base, uint32_t ch
__STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const * base, uint32_t channel)
{
CY_ASSERT_L1(CY_DMA_IS_DW_CH_NR_VALID(base, channel));
return (base->CH_STRUCT[channel].INTR_MASKED);
}
@ -1686,14 +1684,14 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const *
#define CY_DMA_TRIGOUT_X_LOOP_CMPLT (CY_DMA_X_LOOP)
#define CY_DMA_TRIGOUT_DESCR_CMPLT (CY_DMA_DESCR)
#define CY_DMA_TRIGOUT_DESCRCHAIN_CMPLT (CY_DMA_DESCR_CHAIN)
#define CY_DMA_TRIGIN_1ELEMENT (CY_DMA_1ELEMENT)
#define CY_DMA_TRIGIN_XLOOP (CY_DMA_X_LOOP)
#define CY_DMA_TRIGIN_DESCR (CY_DMA_DESCR)
#define CY_DMA_TRIGIN_DESCRCHAIN (CY_DMA_DESCR_CHAIN)
#define CY_DMA_INVALID_INPUT_PARAMETERS (CY_DMA_BAD_PARAM)
#define CY_DMA_RETDIG_IM (CY_DMA_RETRIG_IM)
#define CY_DMA_RETDIG_4CYC (CY_DMA_RETRIG_4CYC)
#define CY_DMA_RETDIG_16CYC (CY_DMA_RETRIG_16CYC)
@ -1705,7 +1703,7 @@ __STATIC_INLINE uint32_t Cy_DMA_Channel_GetInterruptStatusMasked(DW_Type const *
#define DESCR_X_CTL xCtl
#define DESCR_Y_CTL yCtl
#define DESCR_NEXT_PTR nextPtr
/* Descriptor structure bit-fields */
#define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL
#define DW_DESCR_STRUCT_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL

30
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/efuse/cy_efuse.c
View File

@ -7,10 +7,8 @@
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_efuse.h"
@ -51,11 +49,11 @@ static cy_en_efuse_status_t ProcessOpcode(void);
*
* The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g
* \e \<PDL_DIR\>/devices/psoc6/psoc63/include/psoc63_config.\e h
*
* \param bitVal
*
* \param bitVal
* The pointer to the location to store the bit value.
*
* \return
* \return
* \ref cy_en_efuse_status_t
*
* \funcusage
@ -67,16 +65,16 @@ static cy_en_efuse_status_t ProcessOpcode(void);
cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal)
{
cy_en_efuse_status_t result = CY_EFUSE_BAD_PARAM;
if (bitVal != NULL)
{
uint32_t offset = bitNum / CY_EFUSE_BITS_PER_BYTE;
uint8_t byteVal;
*bitVal = false;
/* Read the eFuse byte */
result = Cy_EFUSE_GetEfuseByte(offset, &byteVal);
if (result == CY_EFUSE_SUCCESS)
{
uint32_t bitPos = bitNum % CY_EFUSE_BITS_PER_BYTE;
@ -112,7 +110,7 @@ cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal)
* \param byteVal
* The pointer to the location to store eFuse data.
*
* \return
* \return
* \ref cy_en_efuse_status_t
*
* \funcusage
@ -124,20 +122,20 @@ cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal)
cy_en_efuse_status_t Cy_EFUSE_GetEfuseByte(uint32_t offset, uint8_t *byteVal)
{
cy_en_efuse_status_t result = CY_EFUSE_BAD_PARAM;
if (byteVal != NULL)
{
/* Prepare opcode before calling the SROM API */
opcode = CY_EFUSE_OPCODE_READ_FUSE_BYTE | (offset << CY_EFUSE_OPCODE_OFFSET_Pos);
/* Send the IPC message */
if (Cy_IPC_Drv_SendMsgPtr(CY_EFUSE_IPC_STRUCT, CY_EFUSE_IPC_NOTIFY_STRUCT0, (void*)&opcode) == CY_IPC_DRV_SUCCESS)
{
{
/* Wait until the IPC structure is locked */
while(Cy_IPC_Drv_IsLockAcquired(CY_EFUSE_IPC_STRUCT) != false)
{
}
/* The result of the SROM API call is returned to the opcode variable */
if ((opcode & CY_EFUSE_OPCODE_STS_Msk) == CY_EFUSE_OPCODE_SUCCESS)
{
@ -187,7 +185,7 @@ uint32_t Cy_EFUSE_GetExternalStatus(void)
* Function Name: ProcessOpcode
****************************************************************************//**
*
* Converts System Call returns to the eFuse driver return defines. If
* Converts System Call returns to the eFuse driver return defines. If
* an unknown error was returned, the error code can be accessed via the
* Cy_EFUSE_GetExternalStatus() function.
*

14
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/efuse/cy_efuse.h
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#if !defined(CY_EFUSE_H)
@ -18,7 +16,7 @@
/**
* \defgroup group_efuse Electronic Fuses (eFuse)
* \{
*
*
* Electronic Fuses (eFuses) - non-volatile memory whose
* each bit is one-time programmable (OTP). One eFuse macro consists of
* 256 bits (32 * 8). The PSoC devices have up to 16 eFuse macros; consult the
@ -28,7 +26,7 @@
* - eFuses are used to control the device life-cycle stage (NORMAL, SECURE,
* and SECURE_WITH_DEBUG) and the protection settings;
* - eFuse memory can be programmed (eFuse bit value changed from '0' to '1')
* only once; if an eFuse bit is blown, it cannot be cleared again;
* only once; if an eFuse bit is blown, it cannot be cleared again;
* - programming fuses requires the associated I/O supply to be at a specific
* level: the VDDIO0 (or VDDIO if only one VDDIO is present in the package)
* supply of the device should be set to 2.5 V (&plusmn;5%);
@ -62,7 +60,7 @@
* conditions from the PSoC 6 Programming Specification are met.
*
* The code below shows an example of the efuse data structure
* definition to blow SECURE bit of the life-cycle stage register.
* definition to blow SECURE bit of the life-cycle stage register.
* The bits to blow are set to the EFUSE_STATE_SET value.
* \snippet eFuse_v1_0_sut_00.cydsn/main_cm0p.c SNIPPET_EFUSE_DATA_STC
*
@ -139,7 +137,7 @@
* \{
*/
/** This enum has the return values of the eFuse driver */
typedef enum
typedef enum
{
CY_EFUSE_SUCCESS = 0x00UL, /**< Success */
CY_EFUSE_INVALID_PROTECTION = CY_EFUSE_ID | CY_PDL_STATUS_ERROR | 0x01UL, /**< Invalid access in the current protection state */

6
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/flash/cy_flash.c
View File

@ -7,10 +7,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "flash/cy_flash.h"
#include "sysclk/cy_sysclk.h"

6
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/flash/cy_flash.h
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#if !defined(CY_FLASH_H)

30
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/gpio/cy_gpio.c
View File

@ -7,10 +7,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_gpio.h"
@ -38,7 +36,7 @@ extern "C" {
* \return
* Initialization status
*
* \note
* \note
* This function modifies port registers in read-modify-write operations. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -57,8 +55,8 @@ cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->outVal));
CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(config->driveMode));
CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(config->hsiom));
CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(config->intEdge));
CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(config->hsiom));
CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(config->intEdge));
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->intMask));
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtrip));
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->slewRate));
@ -68,7 +66,7 @@ cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const
CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtripSel));
CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(config->vrefSel));
CY_ASSERT_L2(CY_GPIO_IS_VOH_SEL_VALID(config->vohSel));
Cy_GPIO_Write(base, pinNum, config->outVal);
Cy_GPIO_SetDrivemode(base, pinNum, config->driveMode);
Cy_GPIO_SetHSIOM(base, pinNum, config->hsiom);
@ -78,7 +76,7 @@ cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const
Cy_GPIO_SetVtrip(base, pinNum, config->vtrip);
/* Slew rate and Driver strength */
maskCfgOut = (CY_GPIO_CFG_OUT_SLOW_MASK << pinNum)
maskCfgOut = (CY_GPIO_CFG_OUT_SLOW_MASK << pinNum)
| (CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET));
tempReg = base->CFG_OUT & ~(maskCfgOut);
base->CFG_OUT = tempReg | ((config->slewRate & CY_GPIO_CFG_OUT_SLOW_MASK) << pinNum)
@ -97,7 +95,7 @@ cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const
{
status = CY_GPIO_BAD_PARAM;
}
return(status);
}
@ -121,9 +119,9 @@ cy_en_gpio_status_t Cy_GPIO_Pin_Init(GPIO_PRT_Type *base, uint32_t pinNum, const
* \return
* Initialization status
*
* \note
* If using the PSoC Creator IDE, there is no need to initialize the pins when
* using the GPIO component on the schematic. Ports are configured in
* \note
* If using the PSoC Creator IDE, there is no need to initialize the pins when
* using the GPIO component on the schematic. Ports are configured in
* Cy_SystemInit() before main() entry.
*
* \funcusage
@ -144,7 +142,7 @@ cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt
CY_ASSERT_L2(CY_GPIO_IS_INTR_MASK_VALID(config->intrMask));
CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel0Active));
CY_ASSERT_L2(CY_GPIO_IS_SEL_ACT_VALID(config->sel1Active));
portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
baseHSIOM = (HSIOM_PRT_Type*)(HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum));
@ -162,7 +160,7 @@ cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt
{
status = CY_GPIO_BAD_PARAM;
}
return(status);
}
@ -193,7 +191,7 @@ cy_en_gpio_status_t Cy_GPIO_Port_Init(GPIO_PRT_Type* base, const cy_stc_gpio_prt
* \return
* void
*
* \note
* \note
* This function modifies port registers in read-modify-write operations. It is
* not thread safe as the resource is shared among multiple pins on a port.
*

108
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/gpio/cy_gpio.h
View File

@ -7,10 +7,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
@ -22,21 +20,21 @@
*
* Initialization can be performed either at the port level or by configuring the
* individual pins. For efficient use of code space, port
* configuration should be used in the field. Refer to the product device header files
* configuration should be used in the field. Refer to the product device header files
* for the list of supported ports and pins.
*
* - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit
*
* - Single pin configuration is performed by using \ref Cy_GPIO_Pin_FastInit
* (provide specific values) or \ref Cy_GPIO_Pin_Init (provide a filled
* cy_stc_gpio_pin_config_t structure).
* - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled
* cy_stc_gpio_prt_config_t structure. The values in the structure are
* - An entire port can be configured using \ref Cy_GPIO_Port_Init. Provide a filled
* cy_stc_gpio_prt_config_t structure. The values in the structure are
* bitfields representing the desired value for each pin in the port.
* - Pin configuration and management is based on the port address and pin number.
* \ref Cy_GPIO_PortToAddr function can optionally be used to calculate the port
* address from the port number at run-time.
*
* Once the pin/port initialization is complete, each pin can be accessed by
* specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API
* Once the pin/port initialization is complete, each pin can be accessed by
* specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API
* functions.
*
* \section group_gpio_configuration Configuration Considerations
@ -51,9 +49,9 @@
* called by the application.
*
* Multiple pins on a port can be updated using direct port register writes with an
* appropriate port mask. An example is shown below, highlighting the different ways of
* appropriate port mask. An example is shown below, highlighting the different ways of
* configuring Port 1 pins using,
*
*
* - Port output data register
* - Port output data set register
* - Port output data clear register
@ -75,7 +73,7 @@
* <tr>
* <td>16.7</td>
* <td>A</td>
* <td>A pointer parameter in a function prototype should be declared as pointer
* <td>A pointer parameter in a function prototype should be declared as pointer
* to const if the pointer is not used to modify the addressed object.</td>
* <td>The objects pointed to by the base addresses of the GPIO port are not always modified.
* While a const qualifier can be used in select scenarios, it brings little benefit
@ -88,7 +86,7 @@
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr>
* <td>1.10.1</td>
* <td>Updated description for the functions: \ref Cy_GPIO_GetInterruptStatus,
* <td>Updated description for the functions: \ref Cy_GPIO_GetInterruptStatus,
* \ref Cy_GPIO_GetInterruptMask, \ref Cy_GPIO_GetInterruptStatusMasked.
* Minor documentation edits.
* </td>
@ -156,7 +154,7 @@ extern "C" {
/**
* GPIO Driver error codes
*/
typedef enum
typedef enum
{
CY_GPIO_SUCCESS = 0x00u, /**< Returned successful */
CY_GPIO_BAD_PARAM = CY_GPIO_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */
@ -265,7 +263,7 @@ typedef struct {
GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk | \
GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk | \
GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk | \
GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk)
GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk)
#define CY_GPIO_PRT_INTR_CFG_RANGE_MASK (CY_GPIO_PRT_INTR_CFG_EDGE_SEL_MASK | \
GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk | \
GPIO_PRT_INTR_CFG_FLT_SEL_Msk)
@ -303,8 +301,8 @@ typedef struct {
(CY_SIO_VOH_2_50 == (vrefSel)) || \
(CY_SIO_VOH_2_78 == (vrefSel)) || \
(CY_SIO_VOH_4_16 == (vrefSel)))
#define CY_GPIO_IS_PIN_BIT_VALID(pinBit) (0U == ((pinBit) & (uint32_t)~CY_GPIO_PRT_PINS_MASK))
#define CY_GPIO_IS_PIN_BIT_VALID(pinBit) (0U == ((pinBit) & (uint32_t)~CY_GPIO_PRT_PINS_MASK))
#define CY_GPIO_IS_INTR_CFG_VALID(intrCfg) (0U == ((intrCfg) & (uint32_t)~CY_GPIO_PRT_INTR_CFG_RANGE_MASK))
#define CY_GPIO_IS_INTR_MASK_VALID(intrMask) (0U == ((intrMask) & (uint32_t)~CY_GPIO_PRT_INT_MASK_MASK))
#define CY_GPIO_IS_SEL_ACT_VALID(selActive) (0U == ((selActive) & (uint32_t)~CY_GPIO_PRT_SEL_ACTIVE_MASK))
@ -564,7 +562,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptCause3(void);
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -622,7 +620,7 @@ __STATIC_INLINE en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pi
uint32_t returnValue;
uint32_t portNum;
HSIOM_PRT_Type* portAddrHSIOM;
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
portNum = ((uint32_t)(base) - GPIO_BASE) / GPIO_PRT_SECTION_SIZE;
@ -664,7 +662,7 @@ __STATIC_INLINE en_hsiom_sel_t Cy_GPIO_GetHSIOM(GPIO_PRT_Type* base, uint32_t pi
__STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum)
{
GPIO_PRT_Type* base;
if(portNum < (uint32_t)IOSS_GPIO_GPIO_PORT_NR)
{
base = (GPIO_PRT_Type *)(GPIO_BASE + (GPIO_PRT_SECTION_SIZE * portNum));
@ -708,7 +706,7 @@ __STATIC_INLINE GPIO_PRT_Type* Cy_GPIO_PortToAddr(uint32_t portNum)
__STATIC_INLINE uint32_t Cy_GPIO_Read(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
return (base->IN >> (pinNum)) & CY_GPIO_IN_MASK;
}
@ -807,7 +805,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type* base, uint32_t pinNum)
__STATIC_INLINE void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
base->OUT_SET = CY_GPIO_OUT_MASK << pinNum;
}
@ -837,7 +835,7 @@ __STATIC_INLINE void Cy_GPIO_Set(GPIO_PRT_Type* base, uint32_t pinNum)
__STATIC_INLINE void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
base->OUT_CLR = CY_GPIO_OUT_MASK << pinNum;
}
@ -868,7 +866,7 @@ __STATIC_INLINE void Cy_GPIO_Clr(GPIO_PRT_Type* base, uint32_t pinNum)
__STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
base->OUT_INV = CY_GPIO_OUT_MASK << pinNum;
}
@ -896,7 +894,7 @@ __STATIC_INLINE void Cy_GPIO_Inv(GPIO_PRT_Type* base, uint32_t pinNum)
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -940,7 +938,7 @@ __STATIC_INLINE void Cy_GPIO_SetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum,
__STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
return (base->CFG >> (pinNum << CY_GPIO_DRIVE_MODE_OFFSET)) & CY_GPIO_CFG_DM_MASK;
}
@ -963,7 +961,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type* base, uint32_t pinN
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -1005,7 +1003,7 @@ __STATIC_INLINE void Cy_GPIO_SetVtrip(GPIO_PRT_Type* base, uint32_t pinNum, uint
__STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
return (base->CFG_IN >> pinNum) & CY_GPIO_CFG_IN_VTRIP_SEL_MASK;
}
@ -1028,7 +1026,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type* base, uint32_t pinNum)
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -1093,7 +1091,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type* base, uint32_t pinNu
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -1108,7 +1106,7 @@ __STATIC_INLINE void Cy_GPIO_SetDriveSel(GPIO_PRT_Type* base, uint32_t pinNum, u
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
CY_ASSERT_L2(CY_GPIO_IS_DRIVE_SEL_VALID(value));
pinLoc = (uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET;
tempReg = base->CFG_OUT & ~(CY_GPIO_CFG_OUT_DRIVE_SEL_MASK << pinLoc);
base->CFG_OUT = tempReg | ((value & CY_GPIO_CFG_OUT_DRIVE_SEL_MASK) << pinLoc);
@ -1138,7 +1136,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNu
{
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
return ((base->CFG_OUT >> ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET))
return ((base->CFG_OUT >> ((uint32_t)(pinNum << 1u) + CY_GPIO_CFG_OUT_DRIVE_OFFSET))
& CY_GPIO_CFG_OUT_DRIVE_SEL_MASK);
}
@ -1169,7 +1167,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type* base, uint32_t pinNu
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -1215,7 +1213,7 @@ __STATIC_INLINE void Cy_GPIO_SetVregEn(GPIO_PRT_Type* base, uint32_t pinNum, uin
__STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
return (base->CFG_SIO >> ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET)) & CY_GPIO_VREG_EN_MASK;
}
@ -1240,7 +1238,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVregEn(GPIO_PRT_Type* base, uint32_t pinNum)
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -1286,7 +1284,7 @@ __STATIC_INLINE void Cy_GPIO_SetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum, u
__STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_IBUF_SHIFT)) & CY_GPIO_IBUF_MASK;
}
@ -1311,7 +1309,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode(GPIO_PRT_Type* base, uint32_t pinNu
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -1382,7 +1380,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVtripSel(GPIO_PRT_Type* base, uint32_t pinNu
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -1397,7 +1395,7 @@ __STATIC_INLINE void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, ui
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
CY_ASSERT_L2(CY_GPIO_IS_VREF_SEL_VALID(value));
pinLoc = ((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT;
tempReg = (base->CFG_SIO & ~(CY_GPIO_VREF_SEL_MASK << pinLoc));
base->CFG_SIO = tempReg | ((value & CY_GPIO_VREF_SEL_MASK) << pinLoc);
@ -1428,7 +1426,7 @@ __STATIC_INLINE void Cy_GPIO_SetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum, ui
__STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VREF_SEL_SHIFT)) & CY_GPIO_VREF_SEL_MASK;
}
@ -1456,7 +1454,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel(GPIO_PRT_Type* base, uint32_t pinNum
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -1502,7 +1500,7 @@ __STATIC_INLINE void Cy_GPIO_SetVohSel(GPIO_PRT_Type* base, uint32_t pinNum, uin
__STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum));
return (base->CFG_SIO >> (((pinNum & CY_GPIO_SIO_ODD_PIN_MASK) << CY_GPIO_CFG_SIO_OFFSET) + CY_GPIO_VOH_SEL_SHIFT)) & CY_GPIO_VOH_SEL_MASK;
}
@ -1519,7 +1517,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum)
*
* \brief Returns the current unmasked interrupt state of the pin.
*
* The core processor's NVIC is triggered by the masked interrupt bits. This
* The core processor's NVIC is triggered by the masked interrupt bits. This
* function allows reading the unmasked interrupt state. Whether the bit
* positions actually trigger the interrupt are defined by the interrupt mask bits.
*
@ -1541,7 +1539,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetVohSel(GPIO_PRT_Type* base, uint32_t pinNum)
__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
return (base->INTR >> pinNum) & CY_GPIO_INTR_STATUS_MASK;
}
@ -1569,7 +1567,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatus(GPIO_PRT_Type* base, uint32_
__STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
/* Any INTR MMIO registers AHB clearing must be preceded with an AHB read access */
(void)base->INTR;
@ -1600,7 +1598,7 @@ __STATIC_INLINE void Cy_GPIO_ClearInterrupt(GPIO_PRT_Type* base, uint32_t pinNum
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -1647,7 +1645,7 @@ __STATIC_INLINE void Cy_GPIO_SetInterruptMask(GPIO_PRT_Type* base, uint32_t pinN
__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
return (base->INTR_MASK >> pinNum) & CY_GPIO_INTR_EN_MASK;
}
@ -1658,7 +1656,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t
*
* \brief Return the pin's current interrupt state after being masked.
*
* The core processor's NVIC is triggered by the masked interrupt bits. This
* The core processor's NVIC is triggered by the masked interrupt bits. This
* function allows reading this masked interrupt state. Note that the bits that
* are not masked will not be forwarded to the NVIC.
*
@ -1680,7 +1678,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptMask(GPIO_PRT_Type* base, uint32_t
__STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
return (base->INTR_MASKED >> pinNum) & CY_GPIO_INTR_MASKED_MASK;
}
@ -1708,7 +1706,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptStatusMasked(GPIO_PRT_Type* base, u
__STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum)
{
CY_ASSERT_L2(CY_GPIO_IS_FILTER_PIN_VALID(pinNum));
base->INTR_SET = CY_GPIO_INTR_SET_MASK << pinNum;
}
@ -1732,7 +1730,7 @@ __STATIC_INLINE void Cy_GPIO_SetSwInterrupt(GPIO_PRT_Type* base, uint32_t pinNum
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -1802,7 +1800,7 @@ __STATIC_INLINE uint32_t Cy_GPIO_GetInterruptEdge(GPIO_PRT_Type* base, uint32_t
* \return
* void
*
* \note
* \note
* This function modifies a port register in a read-modify-write operation. It is
* not thread safe as the resource is shared among multiple pins on a port.
*
@ -1819,7 +1817,7 @@ __STATIC_INLINE void Cy_GPIO_SetFilter(GPIO_PRT_Type* base, uint32_t value)
uint32_t tempReg;
CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(value));
tempReg = base->INTR_CFG & ~(CY_GPIO_INTR_FLT_EDGE_MASK << CY_GPIO_INTR_FILT_OFFSET);
base->INTR_CFG = tempReg | ((value & CY_GPIO_INTR_FLT_EDGE_MASK) << CY_GPIO_INTR_FILT_OFFSET);
}

54
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/i2s/cy_i2s.c
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_i2s.h"
@ -41,16 +39,16 @@ extern "C" {
cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config)
{
cy_en_i2s_status_t ret = CY_I2S_BAD_PARAM;
if((NULL != base) && (NULL != config))
{
cy_en_i2s_ws_pw_t wsPulseWidth;
cy_en_i2s_len_t channelLength;
uint32_t channels;
uint32_t clockDiv = (uint32_t)config->clkDiv - 1U;
CY_ASSERT_L2(CY_I2S_IS_CLK_DIV_VALID(clockDiv));
/* The clock setting */
base->CLOCK_CTL = _VAL2FLD(I2S_CLOCK_CTL_CLOCK_DIV, clockDiv) |
_BOOL2FLD(I2S_CLOCK_CTL_CLOCK_SEL, config->extClk);
@ -60,13 +58,13 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf
{
CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->txAlignment));
CY_ASSERT_L3(CY_I2S_IS_OVHDATA_VALID(config->txOverheadValue));
if ((CY_I2S_TDM_MODE_A == config->txAlignment) || (CY_I2S_TDM_MODE_B == config->txAlignment))
{
channels = (uint32_t)config->txChannels - 1UL;
wsPulseWidth = config->txWsPulseWidth;
channelLength = CY_I2S_LEN32;
CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels));
CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth));
CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->txWordLength));
@ -76,12 +74,12 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf
channels = 1UL;
wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH;
channelLength = config->txChannelLength;
CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->txWordLength));
}
CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->txFifoTriggerLevel, channels));
base->TX_WATCHDOG = config->txWatchdogValue;
base->TX_CTL = _VAL2FLD(I2S_TX_CTL_I2S_MODE, config->txAlignment) |
@ -101,13 +99,13 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf
if (config->rxEnabled)
{
CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->rxAlignment));
if ((CY_I2S_TDM_MODE_A == config->rxAlignment) || (CY_I2S_TDM_MODE_B == config->rxAlignment))
{
channels = (uint32_t)config->rxChannels - 1UL;
wsPulseWidth = config->rxWsPulseWidth;
channelLength = CY_I2S_LEN32;
CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels));
CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth));
CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->rxWordLength));
@ -117,10 +115,10 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf
channels = 1UL;
wsPulseWidth = CY_I2S_WS_ONE_CHANNEL_LENGTH;
channelLength = config->rxChannelLength;
CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->rxWordLength));
}
CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->rxFifoTriggerLevel, channels));
base->RX_WATCHDOG = config->rxWatchdogValue;
@ -163,7 +161,7 @@ cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * conf
base->TR_CTL |= _BOOL2FLD(I2S_TR_CTL_RX_REQ_EN, config->rxDmaTrigger);
}
ret = CY_I2S_SUCCESS;
}
@ -204,18 +202,18 @@ void Cy_I2S_DeInit(I2S_Type * base)
****************************************************************************//**
*
* This is a callback function to be used at the application layer to
* manage an I2S operation during the Deep-Sleep cycle. It stores the I2S state
* (Tx/Rx enabled/disabled/paused) into the context structure and stops the
* manage an I2S operation during the Deep-Sleep cycle. It stores the I2S state
* (Tx/Rx enabled/disabled/paused) into the context structure and stops the
* communication before entering into Deep-Sleep power mode and restores the I2S
* state after waking up.
*
* \param
* callbackParams - The pointer to the callback parameters structure,
* \param
* callbackParams - The pointer to the callback parameters structure,
* see \ref cy_stc_syspm_callback_params_t.
*
* \return the SysPm callback status \ref cy_en_syspm_status_t.
*
* \note Use the \ref cy_stc_i2s_context_t data type for definition of the
* \note Use the \ref cy_stc_i2s_context_t data type for definition of the
* *context element of the \ref cy_stc_syspm_callback_params_t strusture.
*
* \funcusage
@ -229,13 +227,13 @@ cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * c
I2S_Type * locBase = (I2S_Type*) callbackParams->base;
uint32_t * locInterruptMask = (uint32_t*) &(((cy_stc_i2s_context_t*)(callbackParams->context))->interruptMask);
uint32_t * locState = (uint32_t*) &(((cy_stc_i2s_context_t*)(callbackParams->context))->enableState);
switch(callbackParams->mode)
{
case CY_SYSPM_CHECK_READY:
case CY_SYSPM_CHECK_READY:
case CY_SYSPM_CHECK_FAIL:
break;
case CY_SYSPM_BEFORE_TRANSITION:
*locInterruptMask = Cy_I2S_GetInterruptMask(locBase); /* Store I2S interrupts */
*locState = Cy_I2S_GetCurrentState(locBase); /* Store I2S state */
@ -250,7 +248,7 @@ cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * c
Cy_I2S_SetInterruptMask(locBase, 0UL); /* Disable I2S interrupts */
/* Unload FIFOs in order not to lose data (if needed) */
break;
case CY_SYSPM_AFTER_TRANSITION:
if (0UL != (*locState & I2S_CMD_RX_START_Msk))
{
@ -271,12 +269,12 @@ cy_en_syspm_status_t Cy_I2S_DeepSleepCallback(cy_stc_syspm_callback_params_t * c
Cy_I2S_ClearInterrupt(locBase, *locInterruptMask); /* Clear possible pending I2S interrupts */
Cy_I2S_SetInterruptMask(locBase, *locInterruptMask); /* Restore I2S interrupts */
break;
default:
ret = CY_SYSPM_FAIL;
break;
}
return(ret);
}

50
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/i2s/cy_i2s.h
View File

@ -1,22 +1,20 @@
/***************************************************************************//**
* \file cy_i2s.h
* \version 2.0.1
*
*
* The header file of the I2S driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
* \defgroup group_i2s Inter-IC Sound (I2S)
* \{
* The I2S driver provides a function API to manage Inter-IC Sound. I2S is used
* to send digital audio streaming data to external I2S devices, such as audio
* The I2S driver provides a function API to manage Inter-IC Sound. I2S is used
* to send digital audio streaming data to external I2S devices, such as audio
* codecs or simple DACs. It can also receive digital audio streaming data.
*
* Features:
@ -25,14 +23,14 @@
* * Programmable Channel/Word Lengths.
* * Supports External Clock operation.
*
* The I2S bus is an industry standard. The hardware interface was
* developed by Philips Semiconductors (now NXP Semiconductors).
* The I2S bus is an industry standard. The hardware interface was
* developed by Philips Semiconductors (now NXP Semiconductors).
*
* \section group_i2s_configuration_considerations Configuration Considerations
*
* To set up an I2S, provide the configuration parameters in the
* \ref cy_stc_i2s_config_t structure.
*
* \ref cy_stc_i2s_config_t structure.
*
* For example, for Tx configuration, set txEnabled to true, configure
* txDmaTrigger (depending on whether DMA is going to be used or not), set
* extClk (if an external clock is used), provide clkDiv, txMasterMode,
@ -56,13 +54,13 @@
*
* For example:
* \snippet i2s/i2s_v2_0_sut_00.cydsn/main_cm4.c snippet_Cy_I2S_Init
*
* If you use a DMA, the DMA channel should be previously configured. The I2S interrupts
*
* If you use a DMA, the DMA channel should be previously configured. The I2S interrupts
* (if applicable) can be enabled by calling \ref Cy_I2S_SetInterruptMask.
*
* For example, if the trigger interrupt is used, during operation the ISR
* should call the \ref Cy_I2S_WriteTxData as many times as required for your
* FIFO payload, but not more than the FIFO size. Then call \ref Cy_I2S_ClearInterrupt
* should call the \ref Cy_I2S_WriteTxData as many times as required for your
* FIFO payload, but not more than the FIFO size. Then call \ref Cy_I2S_ClearInterrupt
* with appropriate parameters.
*
* The I2S/Left Justified data formats always contains two data channels.
@ -72,7 +70,7 @@
* or combined with zeroes: sample1-zero-sample2-zero (in this case only the
* left channel will finally sound, for right-only case zero should go first).
* The TDM frame word order in FIFOs is similar, one-by-one.
*
*
* If a DMA is used and the DMA channel is properly configured - no CPU activity
* (or any application code) is needed for I2S operation.
*
@ -207,7 +205,7 @@ extern "C" {
* \{
*/
/** Transmission is active */
/** Transmission is active */
#define CY_I2S_TX_START (I2S_CMD_TX_START_Msk)
/** Transmission is paused */
#define CY_I2S_TX_PAUSE (I2S_CMD_TX_PAUSE_Msk)
@ -227,7 +225,7 @@ extern "C" {
* I2S status definitions.
*/
typedef enum
typedef enum
{
CY_I2S_SUCCESS = 0x00UL, /**< Successful. */
CY_I2S_BAD_PARAM = CY_I2S_ID | CY_PDL_STATUS_ERROR | 0x01UL /**< One or more invalid parameters. */
@ -306,7 +304,7 @@ typedef struct
'true': SDO bit starts at rising edge which goes before the above
mentioned falling edge, i.e. the SDO signal is advanced by 0.5 SCK
period (if txSckoInversion is false).
If txSckoInversion is true - the rising/falling edges just swaps
If txSckoInversion is true - the rising/falling edges just swaps
in above explanations.
Effective only in slave mode, must be false in master mode.*/
bool txSckoInversion; /**< TX SCKO polarity:
@ -346,7 +344,7 @@ typedef struct
'true': SDI bit starts at rising edge which goes after the above
mentioned falling edge, i.e. the SDI signal is delayed by 0.5 SCK
period (if rxSckoInversion is false).
If rxSckoInversion is true - the rising/falling edges just swaps
If rxSckoInversion is true - the rising/falling edges just swaps
in above explanations.
Effective only in master mode, must be false in slave mode. */
bool rxSckoInversion; /**< RX SCKO polarity:
@ -372,7 +370,7 @@ typedef struct
cy_en_i2s_len_t rxWordLength; /**< RX word length, see #cy_en_i2s_len_t,
must be less or equal to rxChannelLength. */
bool rxSignExtension; /**< RX value sign extension (when the word length is less than 32 bits),
'false': all MSB are filled by zeroes,
'false': all MSB are filled by zeroes,
'true': all MSB are filled by the original sign bit value. */
uint8_t rxFifoTriggerLevel; /**< RX FIFO interrupt trigger level
(0, 1, ..., (255 - (number of channels))). */
@ -476,7 +474,7 @@ typedef struct
cy_en_i2s_status_t Cy_I2S_Init(I2S_Type * base, cy_stc_i2s_config_t const * config);
void Cy_I2S_DeInit(I2S_Type * base);
/** \addtogroup group_i2s_functions_syspm_callback
* The driver supports SysPm callback for Deep Sleep transition.
* \{
@ -520,7 +518,7 @@ __STATIC_INLINE uint32_t Cy_I2S_GetInterruptStatusMasked(I2S_Type const * base);
* Function Name: Cy_I2S_EnableTx
****************************************************************************//**
*
* Starts an I2S transmission. Interrupts enabling (by the
* Starts an I2S transmission. Interrupts enabling (by the
* \ref Cy_I2S_SetInterruptMask) is required after this function call, in case
* if any I2S interrupts are used in the application.
*
@ -578,7 +576,7 @@ __STATIC_INLINE void Cy_I2S_ResumeTx(I2S_Type * base)
* Function Name: Cy_I2S_DisableTx
****************************************************************************//**
*
* Stops an I2S transmission.
* Stops an I2S transmission.
*
* \pre TX interrupts disabling (by the \ref Cy_I2S_SetInterruptMask) is required
* prior to this function call, in case if any TX I2S interrupts are used.
@ -599,7 +597,7 @@ __STATIC_INLINE void Cy_I2S_DisableTx(I2S_Type * base)
* Function Name: Cy_I2S_EnableRx
****************************************************************************//**
*
* Starts an I2S reception. Interrupts enabling (by the
* Starts an I2S reception. Interrupts enabling (by the
* \ref Cy_I2S_SetInterruptMask) is required after this function call, in case
* if any I2S interrupts are used in the application.
*
@ -693,7 +691,7 @@ __STATIC_INLINE void Cy_I2S_ClearTxFifo(I2S_Type * base)
*
*******************************************************************************/
__STATIC_INLINE uint32_t Cy_I2S_GetNumInTxFifo(I2S_Type const * base)
{
{
return (_FLD2VAL(I2S_TX_FIFO_STATUS_USED, base->TX_FIFO_STATUS));
}

5
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_drv.c
View File

@ -7,10 +7,9 @@
* the IPC hardware.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_ipc_drv.h"

8
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_drv.h
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef CY_IPC_DRV_H
@ -239,7 +237,7 @@
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr>
* <td>1.10.1</td>
* <td>Updated description of the \ref Cy_IPC_Pipe_Init,
* <td>Updated description of the \ref Cy_IPC_Pipe_Init,
* \ref Cy_IPC_Pipe_EndpointInit, \ref Cy_IPC_Sema_Set functions.
* Added / updated code snippets.
* </td>

5
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_pipe.c
View File

@ -7,10 +7,9 @@
* of the IPC driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_ipc_pipe.h"

5
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_pipe.h
View File

@ -7,10 +7,9 @@
* structure definitions, pipe constants, and pipe endpoint address definitions.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef CY_IPC_PIPE_H
#define CY_IPC_PIPE_H

5
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_sema.c
View File

@ -7,10 +7,9 @@
* semaphore level APIs for the IPC interface.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "ipc/cy_ipc_drv.h"

6
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/ipc/cy_ipc_sema.h
View File

@ -7,10 +7,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#ifndef CY_IPC_SEMA_H

154
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lpcomp/cy_lpcomp.c
View File

@ -9,9 +9,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_lpcomp.h"
@ -43,7 +41,7 @@ static cy_stc_lpcomp_context_t cy_lpcomp_context;
cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, const cy_stc_lpcomp_config_t* config)
{
cy_en_lpcomp_status_t ret = CY_LPCOMP_BAD_PARAM;
CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
CY_ASSERT_L3(CY_LPCOMP_IS_OUT_MODE_VALID(config->outputMode));
CY_ASSERT_L3(CY_LPCOMP_IS_HYSTERESIS_VALID(config->hysteresis));
@ -55,7 +53,7 @@ cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t c
Cy_LPComp_GlobalEnable(base);
if (CY_LPCOMP_CHANNEL_0 == channel)
{
{
base->CMP0_CTRL = _VAL2FLD(LPCOMP_CMP0_CTRL_HYST0, (uint32_t)config->hysteresis) |
_VAL2FLD(LPCOMP_CMP0_CTRL_DSI_BYPASS0, (uint32_t)config->outputMode) |
_VAL2FLD(LPCOMP_CMP0_CTRL_DSI_LEVEL0, (uint32_t)config->outputMode >> 1u);
@ -66,16 +64,16 @@ cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t c
_VAL2FLD(LPCOMP_CMP1_CTRL_DSI_BYPASS1, (uint32_t)config->outputMode) |
_VAL2FLD(LPCOMP_CMP1_CTRL_DSI_LEVEL1, (uint32_t)config->outputMode >> 1u);
}
/* Save intType to use it in the Cy_LPComp_Enable() function */
cy_lpcomp_context.intType[(uint8_t)channel - 1u] = config->intType;
/* Save power to use it in the Cy_LPComp_Enable() function */
cy_lpcomp_context.power[(uint8_t)channel - 1u] = config->power;
ret = CY_LPCOMP_SUCCESS;
}
return (ret);
}
@ -98,14 +96,14 @@ cy_en_lpcomp_status_t Cy_LPComp_Init(LPCOMP_Type* base, cy_en_lpcomp_channel_t c
void Cy_LPComp_Enable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel)
{
cy_en_lpcomp_pwr_t powerSpeed;
CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
powerSpeed = cy_lpcomp_context.power[(uint8_t)channel - 1u];
/* Set power */
Cy_LPComp_SetPower(base, channel, powerSpeed);
/* Make delay before enabling the comparator interrupt to prevent false triggering */
if (CY_LPCOMP_MODE_ULP == powerSpeed)
{
@ -117,9 +115,9 @@ void Cy_LPComp_Enable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel)
}
else
{
Cy_SysLib_DelayUs(CY_LPCOMP_NORMAL_POWER_DELAY);
Cy_SysLib_DelayUs(CY_LPCOMP_NORMAL_POWER_DELAY);
}
/* Enable the comparator interrupt */
Cy_LPComp_SetInterruptTriggerMode(base, channel, cy_lpcomp_context.intType[(uint8_t)channel - 1u]);
}
@ -141,12 +139,12 @@ void Cy_LPComp_Enable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel)
*
*******************************************************************************/
void Cy_LPComp_Disable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel)
{
{
CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
/* Disable the comparator interrupt */
Cy_LPComp_SetInterruptTriggerMode(base, channel, CY_LPCOMP_INTR_DISABLE);
/* Set power off */
Cy_LPComp_SetPower(base, channel, CY_LPCOMP_MODE_OFF);
}
@ -156,9 +154,9 @@ void Cy_LPComp_Disable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel)
* Function Name: Cy_LPComp_SetInterruptTriggerMode
****************************************************************************//**
*
* Sets the interrupt edge-detect mode.
* Sets the interrupt edge-detect mode.
* This also controls the value provided on the output.
* \note Interrupts can be enabled after the block is enabled and the appropriate
* \note Interrupts can be enabled after the block is enabled and the appropriate
* start-up time has elapsed:
* 3 us for the normal power mode;
* 6 us for the LP mode;
@ -171,17 +169,17 @@ void Cy_LPComp_Disable(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel)
* The LPCOMP channel index.
*
* \param intType
* Interrupt edge trigger selection
* CY_LPCOMP_INTR_DISABLE (=0) - Disabled, no interrupt will be detected
* CY_LPCOMP_INTR_RISING (=1) - Rising edge
* CY_LPCOMP_INTR_FALLING (=2) - Falling edge
* Interrupt edge trigger selection
* CY_LPCOMP_INTR_DISABLE (=0) - Disabled, no interrupt will be detected
* CY_LPCOMP_INTR_RISING (=1) - Rising edge
* CY_LPCOMP_INTR_FALLING (=2) - Falling edge
* CY_LPCOMP_INTR_BOTH (=3) - Both rising and falling edges.
*
* \return None
*
*******************************************************************************/
void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en_lpcomp_int_t intType)
{
{
CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
CY_ASSERT_L3(CY_LPCOMP_IS_INTR_MODE_VALID(intType));
@ -204,11 +202,11 @@ void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t
****************************************************************************//**
*
* Sets the drive power and speeds to one of the four settings.
* \note Interrupts can be enabled after the block is enabled and the appropriate
* \note Interrupts can be enabled after the block is enabled and the appropriate
* start-up time has elapsed:
* 3 us for the normal power mode;
* 6 us for the LP mode;
* 50 us for the ULP mode.
* 50 us for the ULP mode.
* Otherwise, unexpected interrupts events can occur.
*
* \param *base
@ -219,9 +217,9 @@ void Cy_LPComp_SetInterruptTriggerMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t
*
* \param power
* The power setting sets an operation mode of the component:
* CY_LPCOMP_OFF_POWER (=0) - Off power
* CY_LPCOMP_MODE_ULP (=1) - Slow/ultra low power
* CY_LPCOMP_MODE_LP (=2) - Medium/low power
* CY_LPCOMP_OFF_POWER (=0) - Off power
* CY_LPCOMP_MODE_ULP (=1) - Slow/ultra low power
* CY_LPCOMP_MODE_LP (=2) - Medium/low power
* CY_LPCOMP_MODE_NORMAL(=3) - Fast/normal power
*
* \return None
@ -256,8 +254,8 @@ void Cy_LPComp_SetPower(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_en
* The LPCOMP channel index.
*
* \param hysteresis
* Sets an operation mode of the component
* CY_LPCOMP_HYST_ENABLE (=1) - Enables HYST
* Sets an operation mode of the component
* CY_LPCOMP_HYST_ENABLE (=1) - Enables HYST
* CY_LPCOMP_HYST_DISABLE(=0) - Disable HYST.
*
* \return None
@ -283,15 +281,15 @@ void Cy_LPComp_SetHysteresis(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel,
* Function Name: Cy_LPComp_SetInputs
****************************************************************************//**
*
* Sets the comparator input sources. The comparator inputs can be connected
* to the dedicated GPIO pins or AMUXBUSA/AMUXBUSB. Additionally, the negative
* comparator input can be connected to the local VREF.
* Sets the comparator input sources. The comparator inputs can be connected
* to the dedicated GPIO pins or AMUXBUSA/AMUXBUSB. Additionally, the negative
* comparator input can be connected to the local VREF.
* At least one unconnected input causes a comparator undefined output.
*
* \note Connection to AMUXBUSA/AMUXBUSB requires closing the additional
* switches which are a part of the IO system. These switches can be configured
* using the HSIOM->AMUX_SPLIT_CTL[3] register.
* Refer to the appropriate Technical Reference Manual (TRM) of a device
* switches which are a part of the IO system. These switches can be configured
* using the HSIOM->AMUX_SPLIT_CTL[3] register.
* Refer to the appropriate Technical Reference Manual (TRM) of a device
* for a detailed description.
*
* \param *base
@ -301,16 +299,16 @@ void Cy_LPComp_SetHysteresis(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel,
* The LPCOMP channel index.
*
* \param inputP
* Positive input selection
* CY_LPCOMP_SW_GPIO (0x01u)
* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode
* Positive input selection
* CY_LPCOMP_SW_GPIO (0x01u)
* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode
* CY_LPCOMP_SW_AMUXBUSB (0x04u) - Hi-Z in the hibernate mode.
*
* \param inputN
* Negative input selection
* CY_LPCOMP_SW_GPIO (0x01u)
* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode
* CY_LPCOMP_SW_AMUXBUSB (0x04u) - Hi-Z in hibernate mode
* Negative input selection
* CY_LPCOMP_SW_GPIO (0x01u)
* CY_LPCOMP_SW_AMUXBUSA (0x02u) - Hi-Z in hibernate mode
* CY_LPCOMP_SW_AMUXBUSB (0x04u) - Hi-Z in hibernate mode
* CY_LPCOMP_SW_LOCAL_VREF (0x08u) - the negative input only for a crude REF.
*
* \return None
@ -344,7 +342,7 @@ void Cy_LPComp_SetInputs(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_e
break;
}
}
switch(inputN)
{
case CY_LPCOMP_SW_AMUXBUSA:
@ -397,14 +395,14 @@ void Cy_LPComp_SetInputs(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel, cy_e
* The LPCOMP channel index.
*
* \param outType
* Interrupt edge trigger selection
* CY_LPCOMP_OUT_PULSE (=0) - the DSI output with the pulse option, no bypass
* CY_LPCOMP_OUT_DIRECT (=1) - the bypass mode, the direct output of the comparator
* Interrupt edge trigger selection
* CY_LPCOMP_OUT_PULSE (=0) - the DSI output with the pulse option, no bypass
* CY_LPCOMP_OUT_DIRECT (=1) - the bypass mode, the direct output of the comparator
* CY_LPCOMP_OUT_SYNC (=2) - DSI output with the level option, it is similar to the
* bypass mode but it is 1 cycle slow than the bypass.
* [DSI_LEVELx : DSI_BYPASSx] = [Bit11 : Bit10]
* 0 : 0 = 0x00 -> Pulse (PULSE)
* 1 : 0 = 0x02 -> Level (SYNC)
* bypass mode but it is 1 cycle slow than the bypass.
* [DSI_LEVELx : DSI_BYPASSx] = [Bit11 : Bit10]
* 0 : 0 = 0x00 -> Pulse (PULSE)
* 1 : 0 = 0x02 -> Level (SYNC)
* x : 1 = 0x01 -> Bypass (Direct).
*
* \return None
@ -430,26 +428,26 @@ void Cy_LPComp_SetOutputMode(LPCOMP_Type* base, cy_en_lpcomp_channel_t channel,
* Function Name: Cy_LPComp_DeepSleepCallback
****************************************************************************//**
*
* This function checks the current power mode of LPComp and then disables the
* LPComp block if there is no wake-up source from LPComp in the deep-sleep mode.
* It stores the state of the LPComp enable and then disables the LPComp block
* This function checks the current power mode of LPComp and then disables the
* LPComp block if there is no wake-up source from LPComp in the deep-sleep mode.
* It stores the state of the LPComp enable and then disables the LPComp block
* before going to the low power modes, and recovers the LPComp power state after
* wake-up using the stored value.
*
* \param *callbackParams
* The \ref cy_stc_syspm_callback_params_t structure with the callback
* The \ref cy_stc_syspm_callback_params_t structure with the callback
* parameters which consists of mode, base and context fields:
* *base - LPComp register structure pointer;
* *context - Context for the call-back function;
* mode
* CY_SYSPM_CHECK_READY - No action for this state.
* CY_SYSPM_CHECK_FAIL - No action for this state.
* CY_SYSPM_BEFORE_TRANSITION - Checks the LPComp interrupt mask and the power
* mode, and then disables or enables the LPComp block
* CY_SYSPM_BEFORE_TRANSITION - Checks the LPComp interrupt mask and the power
* mode, and then disables or enables the LPComp block
* according to the condition.
* Stores the LPComp state to recover the state after
* wake up.
* CY_SYSPM_AFTER_TRANSITION - Enables the LPComp block, if it was disabled
* CY_SYSPM_AFTER_TRANSITION - Enables the LPComp block, if it was disabled
* before the sleep mode.
*
* \return
@ -471,7 +469,7 @@ cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t
break;
case CY_SYSPM_CHECK_FAIL:
{
{
ret = CY_SYSPM_SUCCESS;
}
break;
@ -484,11 +482,11 @@ cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t
if (0u != enabled_status)
{
/* Disable the LPComp block when there is no wake-up source from any channel. */
if( !(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, locBase->CMP0_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) &&
if( !(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, locBase->CMP0_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) &&
_FLD2BOOL(LPCOMP_INTR_MASK_COMP0_MASK, locBase->INTR_MASK)) ||
((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, locBase->CMP1_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) &&
((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, locBase->CMP1_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) &&
_FLD2BOOL(LPCOMP_INTR_MASK_COMP1_MASK, locBase->INTR_MASK))) )
{
/* Disable the LPComp block to avoid leakage. */
Cy_LPComp_GlobalDisable(locBase);
@ -501,7 +499,7 @@ cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t
}
else
{
/* The LPComp block was already disabled and
/* The LPComp block was already disabled and
* the system is allowed to go to the low power mode.
*/
}
@ -512,8 +510,8 @@ cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t
case CY_SYSPM_AFTER_TRANSITION:
{
/* Enable LPComp to operate if it was enabled
* before entering to the low power mode.
/* Enable LPComp to operate if it was enabled
* before entering to the low power mode.
*/
if (0u != enabled_status)
{
@ -521,7 +519,7 @@ cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t
}
else
{
/* The LPComp block was disabled before calling this API
/* The LPComp block was disabled before calling this API
* with mode = CY_SYSPM_CHECK_READY.
*/
}
@ -542,19 +540,19 @@ cy_en_syspm_status_t Cy_LPComp_DeepSleepCallback(cy_stc_syspm_callback_params_t
* Function Name: Cy_LPComp_HibernateCallback
****************************************************************************//**
*
* This function checks the current power mode of LPComp and then disable the
* LPComp block, if there is no wake-up source from LPComp in the hibernate mode.
* This function checks the current power mode of LPComp and then disable the
* LPComp block, if there is no wake-up source from LPComp in the hibernate mode.
*
* \param *callbackParams
* The \ref cy_stc_syspm_callback_params_t structure with the callback
* The \ref cy_stc_syspm_callback_params_t structure with the callback
* parameters which consists of mode, base and context fields:
* *base - LPComp register structure pointer;
* *context - Context for the call-back function;
* mode
* CY_SYSPM_CHECK_READY - No action for this state.
* CY_SYSPM_CHECK_FAIL - No action for this state.
* CY_SYSPM_BEFORE_TRANSITION - Checks the wake-up source from the hibernate mode
* of the LPComp block, and then disables or enables
* CY_SYSPM_BEFORE_TRANSITION - Checks the wake-up source from the hibernate mode
* of the LPComp block, and then disables or enables
* the LPComp block according to the condition.
*
* \return
@ -576,7 +574,7 @@ cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t
break;
case CY_SYSPM_CHECK_FAIL:
{
{
ret = CY_SYSPM_SUCCESS;
}
break;
@ -589,11 +587,11 @@ cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t
if (0u != enabled_status)
{
/* Disable the LPComp block when there is no wake-up source from any channel. */
if( !(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, locBase->CMP0_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) &&
if( !(((_FLD2VAL(LPCOMP_CMP0_CTRL_MODE0, locBase->CMP0_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) &&
_FLD2BOOL(CY_LPCOMP_WAKEUP_PIN0, SRSS->PWR_HIBERNATE)) ||
((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, locBase->CMP1_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) &&
((_FLD2VAL(LPCOMP_CMP1_CTRL_MODE1, locBase->CMP1_CTRL) == (uint32_t)CY_LPCOMP_MODE_ULP) &&
_FLD2BOOL(CY_LPCOMP_WAKEUP_PIN1, SRSS->PWR_HIBERNATE))) )
{
/* Disable the LPComp block to avoid leakage. */
Cy_LPComp_GlobalDisable(locBase);
@ -606,7 +604,7 @@ cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t
}
else
{
/* The LPComp block was already disabled and
/* The LPComp block was already disabled and
* the system is allowed to go to the low power mode.
*/
}
@ -618,7 +616,7 @@ cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t
default:
break;
}
return (ret);
}

166
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lpcomp/cy_lpcomp.h
View File

@ -7,9 +7,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
@ -18,72 +16,72 @@
* Provides access to the low-power comparators implemented using the fixed-function
* LP comparator block that is present in PSoC 6.
*
* These comparators can perform fast analog signal comparison of internal
* and external analog signals in all system power modes. Low-power comparator
* output can be inspected by the CPU, used as an interrupt/wakeup source to the
* CPU when in low-power mode (Sleep, Low-Power Sleep, or Deep-Sleep), used as
* a wakeup source to system resources when in Hibernate mode, or fed to DSI as
* These comparators can perform fast analog signal comparison of internal
* and external analog signals in all system power modes. Low-power comparator
* output can be inspected by the CPU, used as an interrupt/wakeup source to the
* CPU when in low-power mode (Sleep, Low-Power Sleep, or Deep-Sleep), used as
* a wakeup source to system resources when in Hibernate mode, or fed to DSI as
* an asynchronous or synchronous signal (level or pulse).
*
* \section group_lpcomp_section_Configuration_Considerations Configuration Considerations
* To set up an LPComp, the inputs, the output, the mode, the interrupts and
* To set up an LPComp, the inputs, the output, the mode, the interrupts and
* other configuration parameters should be configured. Power the LPComp to operate.
*
* The sequence recommended for the LPComp operation:
*
* 1) To initialize the driver, call the Cy_LPComp_Init() function providing
* the filled cy_stc_lpcomp_config_t structure, the LPComp channel number,
* 1) To initialize the driver, call the Cy_LPComp_Init() function providing
* the filled cy_stc_lpcomp_config_t structure, the LPComp channel number,
* and the LPCOMP registers structure pointer.
*
* 2) Optionally, configure the interrupt requests if the interrupt event
* triggering is needed. Use the Cy_LPComp_SetInterruptMask() function with
* the parameter for the mask available in the configuration file.
* Additionally, enable the Global interrupts and initialize the referenced
* interrupt by setting the priority and the interrupt vector using
* 2) Optionally, configure the interrupt requests if the interrupt event
* triggering is needed. Use the Cy_LPComp_SetInterruptMask() function with
* the parameter for the mask available in the configuration file.
* Additionally, enable the Global interrupts and initialize the referenced
* interrupt by setting the priority and the interrupt vector using
* the \ref Cy_SysInt_Init() function of the sysint driver.
*
* 3) Configure the inputs and the output using the \ref Cy_GPIO_Pin_Init()
* functions of the GPIO driver.
* The High Impedance Analog drive mode is for the inputs and
* the Strong drive mode is for the output.
* Use the Cy_LPComp_SetInputs() function to connect the comparator inputs
* 3) Configure the inputs and the output using the \ref Cy_GPIO_Pin_Init()
* functions of the GPIO driver.
* The High Impedance Analog drive mode is for the inputs and
* the Strong drive mode is for the output.
* Use the Cy_LPComp_SetInputs() function to connect the comparator inputs
* to the dedicated IO pins, AMUXBUSA/AMUXBUSB or Vref:
* \image html lpcomp_inputs.png
*
* 4) Power on the comparator using the Cy_LPComp_Enable() function.
*
* 5) The comparator output can be monitored using
* the Cy_LPComp_GetCompare() function or using the LPComp interrupt
* 5) The comparator output can be monitored using
* the Cy_LPComp_GetCompare() function or using the LPComp interrupt
* (if the interrupt is enabled).
*
* \note The interrupt is not cleared automatically.
* It is the user's responsibility to do that.
* The interrupt is cleared by writing a 1 in the corresponding interrupt
* register bit position. The preferred way to clear interrupt sources
* \note The interrupt is not cleared automatically.
* It is the user's responsibility to do that.
* The interrupt is cleared by writing a 1 in the corresponding interrupt
* register bit position. The preferred way to clear interrupt sources
* is using the Cy_LPComp_ClearInterrupt() function.
*
* \note Individual comparator interrupt outputs are ORed together
* as a single asynchronous interrupt source before it is sent out and
* used to wake up the system in the low-power mode.
* For PSoC 6 devices, the individual comparator interrupt is masked
* \note Individual comparator interrupt outputs are ORed together
* as a single asynchronous interrupt source before it is sent out and
* used to wake up the system in the low-power mode.
* For PSoC 6 devices, the individual comparator interrupt is masked
* by the INTR_MASK register. The masked result is captured in
* the INTR_MASKED register.
* Writing a 1 to the INTR register bit will clear the interrupt.
* Writing a 1 to the INTR register bit will clear the interrupt.
*
* \section group_lpcomp_lp Low Power Support
* The LPComp provides the callback functions to facilitate
* the low-power mode transition. The callback
* \ref Cy_LPComp_DeepSleepCallback must be called during execution
* of \ref Cy_SysPm_DeepSleep; \ref Cy_LPComp_HibernateCallback must be
* called during execution of \ref Cy_SysPm_Hibernate.
* To trigger the callback execution, the callback must be registered
* before calling the mode transition function.
* Refer to \ref group_syspm driver for more
* The LPComp provides the callback functions to facilitate
* the low-power mode transition. The callback
* \ref Cy_LPComp_DeepSleepCallback must be called during execution
* of \ref Cy_SysPm_DeepSleep; \ref Cy_LPComp_HibernateCallback must be
* called during execution of \ref Cy_SysPm_Hibernate.
* To trigger the callback execution, the callback must be registered
* before calling the mode transition function.
* Refer to \ref group_syspm driver for more
* information about low-power mode transitions.
*
* \section group_lpcomp_more_information More Information
*
* Refer to the appropriate device technical reference manual (TRM) for
* Refer to the appropriate device technical reference manual (TRM) for
* a detailed description of the registers.
*
* \section group_lpcomp_MISRA MISRA-C Compliance
@ -101,12 +99,12 @@
* a different pointer to object type.</td>
* <td>
* The pointer to the buffer memory is void to allow handling different
* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits).
* The cast operation is safe because the configuration is verified
* different data types: uint8_t (4-8 bits) or uint16_t (9-16 bits).
* The cast operation is safe because the configuration is verified
* before operation is performed.
* The function \ref Cy_LPComp_DeepSleepCallback is a callback of
* The function \ref Cy_LPComp_DeepSleepCallback is a callback of
* the \ref cy_en_syspm_status_t type. The cast operation safety in this
* function becomes the user's responsibility because the pointers are
* function becomes the user's responsibility because the pointers are
* initialized when a callback is registered in the SysPm driver.</td>
* </tr>
* </table>
@ -121,7 +119,7 @@
* </tr>
* <tr>
* <td>1.10</td>
* <td>The CY_WEAK keyword is removed from Cy_LPComp_DeepSleepCallback()
* <td>The CY_WEAK keyword is removed from Cy_LPComp_DeepSleepCallback()
* and Cy_LPComp_HibernateCallback() functions<br>
* Added input parameter validation to the API functions.</td>
* <td></td>
@ -181,7 +179,7 @@ extern "C"
******************************************************************************/
/**< LPCOMP PDL ID */
#define CY_LPCOMP_ID CY_PDL_DRV_ID(0x23u)
#define CY_LPCOMP_ID CY_PDL_DRV_ID(0x23u)
/** The LPCOMP's number of channels. */
#define CY_LPCOMP_MAX_CHANNEL_NUM (2u)
@ -221,20 +219,20 @@ extern "C"
#define CY_LPCOMP_CMP0_OUTPUT_CONFIG_Pos LPCOMP_CMP0_CTRL_DSI_BYPASS0_Pos
#define CY_LPCOMP_CMP1_OUTPUT_CONFIG_Pos LPCOMP_CMP1_CTRL_DSI_BYPASS1_Pos
#define CY_LPCOMP_CMP0_OUTPUT_CONFIG_Msk (LPCOMP_CMP0_CTRL_DSI_BYPASS0_Msk | \
LPCOMP_CMP0_CTRL_DSI_LEVEL0_Msk)
#define CY_LPCOMP_CMP1_OUTPUT_CONFIG_Msk (LPCOMP_CMP1_CTRL_DSI_BYPASS1_Msk | \
LPCOMP_CMP1_CTRL_DSI_LEVEL1_Msk)
#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR_Pos HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos
#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_SR_Msk (HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk | \
HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk)
HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk)
#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR_Pos HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos
#define CY_HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_SR_Msk (HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk | \
HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk)
@ -264,7 +262,7 @@ typedef enum
{
CY_LPCOMP_OUT_PULSE = 0u, /**< The LPCOMP DSI output with the pulse option, no bypass. */
CY_LPCOMP_OUT_DIRECT = 1u, /**< The LPCOMP bypass mode, the direct output of a comparator. */
CY_LPCOMP_OUT_SYNC = 2u /**< The LPCOMP DSI output with the level option, it is similar
CY_LPCOMP_OUT_SYNC = 2u /**< The LPCOMP DSI output with the level option, it is similar
to the bypass mode but it is 1 cycle slow than the bypass. */
} cy_en_lpcomp_out_t;
@ -310,7 +308,7 @@ typedef enum
} cy_en_lpcomp_inputs_t;
/** The LPCOMP error codes. */
typedef enum
typedef enum
{
CY_LPCOMP_SUCCESS = 0x00u, /**< Successful */
CY_LPCOMP_BAD_PARAM = CY_LPCOMP_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */
@ -332,7 +330,7 @@ typedef enum
/** The LPCOMP configuration structure. */
typedef struct {
cy_en_lpcomp_out_t outputMode; /**< The LPCOMP's outputMode: Direct output,
cy_en_lpcomp_out_t outputMode; /**< The LPCOMP's outputMode: Direct output,
Synchronized output or Pulse output */
cy_en_lpcomp_hyst_t hysteresis; /**< Enables or disables the LPCOMP's hysteresis */
cy_en_lpcomp_pwr_t power; /**< Sets the LPCOMP power mode */
@ -380,7 +378,7 @@ typedef struct {
((input) == CY_LPCOMP_SW_AMUXBUSA) || \
((input) == CY_LPCOMP_SW_AMUXBUSB) || \
((input) == CY_LPCOMP_SW_LOCAL_VREF))
/** \endcond */
/**
@ -425,16 +423,16 @@ cy_en_syspm_status_t Cy_LPComp_HibernateCallback(cy_stc_syspm_callback_params_t
* Function Name: Cy_LPComp_GlobalEnable
****************************************************************************//**
*
* Activates the IP of the LPCOMP hardware block. This API should be enabled
* Activates the IP of the LPCOMP hardware block. This API should be enabled
* before operating any channel of comparators.
* Note: Interrupts can be enabled after the block is enabled and the appropriate
* Note: Interrupts can be enabled after the block is enabled and the appropriate
* start-up time has elapsed:
* 3 us for the normal power mode;
* 6 us for the LP mode;
* 50 us for the ULP mode.
*
* \param *base
* The structure of the channel pointer.
* The structure of the channel pointer.
*
* \return None
*
@ -449,7 +447,7 @@ __STATIC_INLINE void Cy_LPComp_GlobalEnable(LPCOMP_Type* base)
* Function Name: Cy_LPComp_GlobalDisable
****************************************************************************//**
*
* Deactivates the IP of the LPCOMP hardware block.
* Deactivates the IP of the LPCOMP hardware block.
* (Analog in power down, open all switches, all clocks off).
*
* \param *base
@ -468,7 +466,7 @@ __STATIC_INLINE void Cy_LPComp_GlobalDisable(LPCOMP_Type *base)
* Function Name: Cy_LPComp_UlpReferenceEnable
****************************************************************************//**
*
* Enables the local reference-generator circuit.
* Enables the local reference-generator circuit.
*
* \param *base
* The structure of the channel pointer.
@ -486,7 +484,7 @@ __STATIC_INLINE void Cy_LPComp_UlpReferenceEnable(LPCOMP_Type *base)
* Function Name: Cy_LPComp_UlpReferenceDisable
****************************************************************************//**
*
* Disables the local reference-generator circuit.
* Disables the local reference-generator circuit.
*
* \param *base
* The structure of the channel pointer.
@ -504,8 +502,8 @@ __STATIC_INLINE void Cy_LPComp_UlpReferenceDisable(LPCOMP_Type *base)
* Function Name: Cy_LPComp_GetCompare
****************************************************************************//**
*
* This function returns a nonzero value when the voltage connected to the
* positive input is greater than the negative input voltage.
* This function returns a nonzero value when the voltage connected to the
* positive input is greater than the negative input voltage.
*
* \param *base
* The LPComp register structure pointer.
@ -521,7 +519,7 @@ __STATIC_INLINE void Cy_LPComp_UlpReferenceDisable(LPCOMP_Type *base)
__STATIC_INLINE uint32_t Cy_LPComp_GetCompare(LPCOMP_Type const * base, cy_en_lpcomp_channel_t channel)
{
uint32_t result;
CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
if (CY_LPCOMP_CHANNEL_0 == channel)
@ -532,7 +530,7 @@ __STATIC_INLINE uint32_t Cy_LPComp_GetCompare(LPCOMP_Type const * base, cy_en_lp
{
result = _FLD2VAL(LPCOMP_STATUS_OUT1, base->STATUS);
}
return (result);
}
@ -541,15 +539,15 @@ __STATIC_INLINE uint32_t Cy_LPComp_GetCompare(LPCOMP_Type const * base, cy_en_lp
* Function Name: Cy_LPComp_SetInterruptMask
****************************************************************************//**
*
* Configures which bits of the interrupt request register will trigger an
* Configures which bits of the interrupt request register will trigger an
* interrupt event.
*
* \param *base
* The LPCOMP register structure pointer.
*
* \param interrupt
* uint32_t interruptMask: Bit Mask of interrupts to set.
* Bit 0: COMP0 Interrupt Mask
* uint32_t interruptMask: Bit Mask of interrupts to set.
* Bit 0: COMP0 Interrupt Mask
* Bit 1: COMP1 Interrupt Mask
*
* \return None
@ -579,7 +577,7 @@ __STATIC_INLINE void Cy_LPComp_SetInterruptMask(LPCOMP_Type* base, uint32_t inte
*******************************************************************************/
__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptMask(LPCOMP_Type const * base)
{
return (base->INTR_MASK);
return (base->INTR_MASK);
}
@ -587,8 +585,8 @@ __STATIC_INLINE uint32_t Cy_LPComp_GetInterruptMask(LPCOMP_Type const * base)
* Function Name: Cy_LPComp_GetInterruptStatusMasked
****************************************************************************//**
*
* Returns an interrupt request register masked by an interrupt mask.
* Returns the result of the bitwise AND operation between the corresponding
* Returns an interrupt request register masked by an interrupt mask.
* Returns the result of the bitwise AND operation between the corresponding
* interrupt request and mask bits.
*
* \param *base
@ -601,7 +599,7 @@ __STATIC_INLINE uint32_t Cy_LPComp_GetInterruptMask(LPCOMP_Type const * base)
*******************************************************************************/
__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatusMasked(LPCOMP_Type const * base)
{
return (base->INTR_MASKED);
return (base->INTR_MASKED);
}
@ -614,14 +612,14 @@ __STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatusMasked(LPCOMP_Type const *
* \param *base
* The LPCOMP register structure pointer.
*
* \return bit mapping information
* Bit 0: COMP0 Interrupt status
* \return bit mapping information
* Bit 0: COMP0 Interrupt status
* Bit 1: COMP1 Interrupt status
*
*******************************************************************************/
__STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatus(LPCOMP_Type const * base)
{
return (_FLD2VAL(CY_LPCOMP_INTR, base->INTR));
return (_FLD2VAL(CY_LPCOMP_INTR, base->INTR));
}
@ -629,13 +627,13 @@ __STATIC_INLINE uint32_t Cy_LPComp_GetInterruptStatus(LPCOMP_Type const * base)
* Function Name: Cy_LPComp_ClearInterrupt
****************************************************************************//**
*
* Clears LPCOMP interrupts by setting each bit.
* Clears LPCOMP interrupts by setting each bit.
*
* \param *base
* The LPCOMP register structure pointer.
*
* \param interrupt
* Bit 0: COMP0 Interrupt status
* Bit 0: COMP0 Interrupt status
* Bit 1: COMP1 Interrupt status
*
* \return None
@ -653,16 +651,16 @@ __STATIC_INLINE void Cy_LPComp_ClearInterrupt(LPCOMP_Type* base, uint32_t interr
* Function Name: Cy_LPComp_SetInterrupt
****************************************************************************//**
*
* Sets a software interrupt request.
* Sets a software interrupt request.
* This function is used in the case of combined interrupt signal from the global
* signal reference. This function from either component instance can be used
* signal reference. This function from either component instance can be used
* to trigger either or both software interrupts. It sets the INTR_SET interrupt mask.
*
* \param *base
* The LPCOMP register structure pointer.
*
* \param interrupt
* Bit 0: COMP0 Interrupt status
* Bit 0: COMP0 Interrupt status
* Bit 1: COMP1 Interrupt status
*
* \return None
@ -693,10 +691,10 @@ __STATIC_INLINE void Cy_LPComp_SetInterrupt(LPCOMP_Type* base, uint32_t interrup
__STATIC_INLINE void Cy_LPComp_ConnectULPReference(LPCOMP_Type *base, cy_en_lpcomp_channel_t channel)
{
CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel));
if (CY_LPCOMP_CHANNEL_0 == channel)
{
base->CMP0_SW_CLEAR = CY_LPCOMP_CMP0_SW_NEG_Msk;
base->CMP0_SW_CLEAR = CY_LPCOMP_CMP0_SW_NEG_Msk;
base->CMP0_SW = _CLR_SET_FLD32U(base->CMP0_SW, LPCOMP_CMP0_SW_CMP0_VN0, CY_LPCOMP_REF_CONNECTED);
}
else

16
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lvd/cy_lvd.c
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_lvd.h"
@ -26,7 +24,7 @@ extern "C" {
* When this function is registered by \ref Cy_SysPm_RegisterCallback - it
* automatically enables the LVD after wake up from Deep-Sleep mode.
*
* \param callbackParams The pointer to the callback parameters structure,
* \param callbackParams The pointer to the callback parameters structure,
* see \ref cy_stc_syspm_callback_params_t.
*
* \return the SysPm callback status \ref cy_en_syspm_status_t.
@ -35,23 +33,23 @@ extern "C" {
cy_en_syspm_status_t Cy_LVD_DeepSleepCallback(cy_stc_syspm_callback_params_t * callbackParams)
{
cy_en_syspm_status_t ret = CY_SYSPM_SUCCESS;
switch(callbackParams->mode)
{
case CY_SYSPM_CHECK_READY:
case CY_SYSPM_CHECK_FAIL:
case CY_SYSPM_BEFORE_TRANSITION:
break;
case CY_SYSPM_AFTER_TRANSITION:
Cy_LVD_Enable();
break;
default:
ret = CY_SYSPM_FAIL;
break;
}
return(ret);
}

82
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/lvd/cy_lvd.h
View File

@ -1,33 +1,31 @@
/***************************************************************************//**
* \file cy_lvd.h
* \version 1.0.1
*
*
* The header file of the LVD driver.
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
* \addtogroup group_lvd
* \{
* The LVD driver provides an API to manage the Low Voltage Detection block.
* The LVD block provides a status of currently observed VDDD voltage
* The LVD driver provides an API to manage the Low Voltage Detection block.
* The LVD block provides a status of currently observed VDDD voltage
* and triggers an interrupt when the observed voltage crosses an adjusted
* threshold.
*
* \section group_lvd_configuration_considerations Configuration Considerations
* To set up an LVD, configure the voltage threshold by the
* \ref Cy_LVD_SetThreshold function, ensure that the LVD block itself and LVD
* interrupt are disabled (by the \ref Cy_LVD_Disable and
* To set up an LVD, configure the voltage threshold by the
* \ref Cy_LVD_SetThreshold function, ensure that the LVD block itself and LVD
* interrupt are disabled (by the \ref Cy_LVD_Disable and
* \ref Cy_LVD_ClearInterruptMask functions correspondingly) before changing the
* threshold to prevent propagating a false interrupt.
* threshold to prevent propagating a false interrupt.
* Then configure interrupts by the \ref Cy_LVD_SetInterruptConfig function, do
* not forget to initialise an interrupt handler (the interrupt source number
* not forget to initialise an interrupt handler (the interrupt source number
* is srss_interrupt_IRQn).
* Then enable LVD by the \ref Cy_LVD_Enable function, then wait for at least 20us
* to get the circuit stabilized and clear the possible false interrupts by the
@ -68,14 +66,14 @@
* <td>A</td>
* <td>The object addressed by the pointer parameter '%s' is not modified and
* so the pointer could be of type 'pointer to const'.</td>
* <td>The pointer parameter is not used or modified, as there is no need
* to do any actions with it. However, such parameter is
* required to be presented in the function, because the
* \ref Cy_LVD_DeepSleepCallback is a callback
* <td>The pointer parameter is not used or modified, as there is no need
* to do any actions with it. However, such parameter is
* required to be presented in the function, because the
* \ref Cy_LVD_DeepSleepCallback is a callback
* of \ref cy_en_syspm_status_t type.
* The SysPM driver callback function type requires implementing the
* The SysPM driver callback function type requires implementing the
* function with the next parameters and return value: <br>
* cy_en_syspm_status_t (*Cy_SysPmCallback)
* cy_en_syspm_status_t (*Cy_SysPmCallback)
* (cy_stc_syspm_callback_params_t *callbackParams);</td>
* </tr>
* </table>
@ -106,7 +104,7 @@
#if !defined CY_LVD_H
#define CY_LVD_H
#include "syspm/cy_syspm.h"
#ifdef __cplusplus
@ -127,7 +125,7 @@ extern "C" {
#define CY_LVD_ID (CY_PDL_DRV_ID(0x39U))
/** Interrupt mask for \ref Cy_LVD_GetInterruptStatus(),
\ref Cy_LVD_GetInterruptMask() and
\ref Cy_LVD_GetInterruptMask() and
\ref Cy_LVD_GetInterruptStatusMasked() */
#define CY_LVD_INTR (SRSS_SRSS_INTR_HVLVD1_Msk)
@ -202,11 +200,11 @@ typedef enum
((threshold) == CY_LVD_THRESHOLD_2_9_V) || \
((threshold) == CY_LVD_THRESHOLD_3_0_V) || \
((threshold) == CY_LVD_THRESHOLD_3_1_V))
#define CY_LVD_CHECK_INTR_CFG(intrCfg) (((intrCfg) == CY_LVD_INTR_DISABLE) || \
((intrCfg) == CY_LVD_INTR_RISING) || \
((intrCfg) == CY_LVD_INTR_FALLING) || \
((intrCfg) == CY_LVD_INTR_BOTH))
((intrCfg) == CY_LVD_INTR_BOTH))
/** \endcond */
/**
@ -236,7 +234,7 @@ cy_en_syspm_status_t Cy_LVD_DeepSleepCallback(cy_stc_syspm_callback_params_t * c
* Function Name: Cy_LVD_Enable
****************************************************************************//**
*
* Enables the output of the LVD block when the VDDD voltage is
* Enables the output of the LVD block when the VDDD voltage is
* at or below the threshold.
* See the Configuration Considerations section for details.
*
@ -265,12 +263,12 @@ __STATIC_INLINE void Cy_LVD_Disable(void)
****************************************************************************//**
*
* Sets a threshold for monitoring the VDDD voltage.
* To prevent propagating a false interrupt, before changing the threshold
* ensure that the LVD block itself and LVD interrupt are disabled by the
* \ref Cy_LVD_Disable and \ref Cy_LVD_ClearInterruptMask functions
* To prevent propagating a false interrupt, before changing the threshold
* ensure that the LVD block itself and LVD interrupt are disabled by the
* \ref Cy_LVD_Disable and \ref Cy_LVD_ClearInterruptMask functions
* correspondingly.
*
* \param threshold
* \param threshold
* Threshold selection for Low Voltage Detect circuit, \ref cy_en_lvd_tripsel_t.
*
*******************************************************************************/
@ -287,9 +285,9 @@ __STATIC_INLINE void Cy_LVD_SetThreshold(cy_en_lvd_tripsel_t threshold)
*
* Returns the status of LVD.
* SRSS LVD Status Register (PWR_LVD_STATUS).
*
*
* \return LVD status, \ref cy_en_lvd_status_t.
*
*
*******************************************************************************/
__STATIC_INLINE cy_en_lvd_status_t Cy_LVD_GetStatus(void)
{
@ -301,11 +299,11 @@ __STATIC_INLINE cy_en_lvd_status_t Cy_LVD_GetStatus(void)
* Function Name: Cy_LVD_GetInterruptStatus
****************************************************************************//**
*
* Returns the status of LVD interrupt.
* Returns the status of LVD interrupt.
* SRSS Interrupt Register (SRSS_INTR).
*
*
* \return SRSS Interrupt status, \ref CY_LVD_INTR.
*
*
*******************************************************************************/
__STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatus(void)
{
@ -317,7 +315,7 @@ __STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatus(void)
* Function Name: Cy_LVD_ClearInterrupt
****************************************************************************//**
*
* Clears LVD interrupt.
* Clears LVD interrupt.
* SRSS Interrupt Register (SRSS_INTR).
*
*******************************************************************************/
@ -334,7 +332,7 @@ __STATIC_INLINE void Cy_LVD_ClearInterrupt(void)
*
* Triggers the device to generate interrupt for LVD.
* SRSS Interrupt Set Register (SRSS_INTR_SET).
*
*
*******************************************************************************/
__STATIC_INLINE void Cy_LVD_SetInterrupt(void)
{
@ -353,7 +351,7 @@ __STATIC_INLINE void Cy_LVD_SetInterrupt(void)
*
*******************************************************************************/
__STATIC_INLINE uint32_t Cy_LVD_GetInterruptMask(void)
{
{
return (SRSS->SRSS_INTR_MASK & SRSS_SRSS_INTR_MASK_HVLVD1_Msk);
}
@ -362,7 +360,7 @@ __STATIC_INLINE uint32_t Cy_LVD_GetInterruptMask(void)
* Function Name: Cy_LVD_SetInterruptMask
****************************************************************************//**
*
* Enables LVD interrupts.
* Enables LVD interrupts.
* Sets the LVD interrupt mask in the SRSS_INTR_MASK register.
*
*******************************************************************************/
@ -376,7 +374,7 @@ __STATIC_INLINE void Cy_LVD_SetInterruptMask(void)
* Function Name: Cy_LVD_ClearInterruptMask
****************************************************************************//**
*
* Disables LVD interrupts.
* Disables LVD interrupts.
* Clears the LVD interrupt mask in the SRSS_INTR_MASK register.
*
*******************************************************************************/
@ -390,12 +388,12 @@ __STATIC_INLINE void Cy_LVD_ClearInterruptMask(void)
* Function Name: Cy_LVD_GetInterruptStatusMasked
****************************************************************************//**
*
* Returns the masked interrupt status which is a bitwise AND between the
* Returns the masked interrupt status which is a bitwise AND between the
* interrupt status and interrupt mask registers.
* SRSS Interrupt Masked Register (SRSS_INTR_MASKED).
*
*
* \return SRSS Interrupt Masked value, \ref CY_LVD_INTR.
*
*
*******************************************************************************/
__STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatusMasked(void)
{
@ -407,9 +405,9 @@ __STATIC_INLINE uint32_t Cy_LVD_GetInterruptStatusMasked(void)
* Function Name: Cy_LVD_SetInterruptConfig
****************************************************************************//**
*
* Sets a configuration for LVD interrupt.
* Sets a configuration for LVD interrupt.
* SRSS Interrupt Configuration Register (SRSS_INTR_CFG).
*
*
* \param lvdInterruptConfig \ref cy_en_lvd_intr_config_t.
*
*******************************************************************************/

55
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/mcwdt/cy_mcwdt.c
View File

@ -6,10 +6,9 @@
* Provides a system API for the MCWDT driver.
*
********************************************************************************
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_mcwdt.h"
@ -62,10 +61,10 @@ cy_en_mcwdt_status_t Cy_MCWDT_Init(MCWDT_STRUCT_Type *base, cy_stc_mcwdt_config_
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1, config->c1Mode) |
(config->c0c1Cascade ? MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk : 0UL) |
_VAL2FLD(MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0, config->c0Mode);
ret = CY_MCWDT_SUCCESS;
}
return (ret);
}
@ -109,14 +108,14 @@ void Cy_MCWDT_DeInit(MCWDT_STRUCT_Type *base)
* The base pointer to a structure that describes the registers.
*
* \note
* The user must enable both counters, and cascade C0 to C1,
* before calling this function. C2 is not reported.
* The user must enable both counters, and cascade C0 to C1,
* before calling this function. C2 is not reported.
* Instead, to get a 64-bit C2-C1-C0 cascaded value, the
* user must call this function followed by
* Cy_MCWDT_GetCount(base, CY_MCWDT_COUNTER2), and then combine the results.
* \note This function does not return the correct result when it is called
* after the Cy_MCWDT_Enable() or Cy_MCWDT_ResetCounters() function with
* a delay less than two lf_clk cycles. The recommended waitUs parameter
* \note This function does not return the correct result when it is called
* after the Cy_MCWDT_Enable() or Cy_MCWDT_ResetCounters() function with
* a delay less than two lf_clk cycles. The recommended waitUs parameter
* value is 100 us.
*
*******************************************************************************/
@ -127,15 +126,15 @@ uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base)
uint32_t counter0 = countVal & MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk;
uint32_t match0 = _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0, base->MCWDT_MATCH);
uint32_t match1 = _FLD2VAL(MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1, base->MCWDT_MATCH);
/*
* The counter counter0 goes to zero when it reaches the match0
* value (c0ClearOnMatch = 1) or reaches the maximum
* value (c0ClearOnMatch = 0). The counter counter1 increments on
* the next rising edge of the MCWDT clock after
* the Clear On Match event takes place.
* The software increments counter1 to eliminate the case
* when the both counter0 and counter1 counters have zeros.
/*
* The counter counter0 goes to zero when it reaches the match0
* value (c0ClearOnMatch = 1) or reaches the maximum
* value (c0ClearOnMatch = 0). The counter counter1 increments on
* the next rising edge of the MCWDT clock after
* the Clear On Match event takes place.
* The software increments counter1 to eliminate the case
* when the both counter0 and counter1 counters have zeros.
*/
if (0u == counter0)
{
@ -144,19 +143,19 @@ uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base)
/* Check if the counter0 is Free running */
if (0u == _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0, base->MCWDT_CONFIG))
{
{
/* Save match0 value with the correction when counter0
* goes to zero when it reaches the match0 value.
* goes to zero when it reaches the match0 value.
*/
countVal = match0 + 1u;
if (0u < counter1)
if (0u < counter1)
{
/* Set match to the maximum value */
match0 = MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk;
match0 = MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk;
}
if (countVal < counter0)
if (countVal < counter0)
{
/* Decrement counter1 when the counter0 is great than match0 value */
counter1--;
@ -165,7 +164,7 @@ uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base)
/* Add the correction to counter0 */
counter0 += counter1;
/* Set counter1 match value to 65535 when the counter1 is free running */
if (0u == _FLD2VAL(MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1, base->MCWDT_CONFIG))
{

188
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/mcwdt/cy_mcwdt.h
View File

@ -7,15 +7,13 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
* \defgroup group_mcwdt Multi-Counter Watchdog (MCWDT)
* \{
* A MCWDT has two 16-bit counters and one 32-bit counter.
* A MCWDT has two 16-bit counters and one 32-bit counter.
* You can use this driver to create a free-running
* timer or generate periodic interrupts. The driver also
* includes support for the watchdog function to recover from CPU or
@ -32,45 +30,45 @@
*
* An additional use case is to implement a watchdog used for recovering from a CPU or
* firmware failure.
*
*
* \section group_mcwdt_configuration Configuration Considerations
*
* Each MCWDT may be configured for a particular product.
* One MCWDT block can be associated with only one CPU during runtime.
* A single MCWDT is not intended to be used by multiple CPUs simultaneously.
* Each block contains three sub-counters, each of which can be configured for
* various system utility functions - free running counter, periodic interrupts,
* Each MCWDT may be configured for a particular product.
* One MCWDT block can be associated with only one CPU during runtime.
* A single MCWDT is not intended to be used by multiple CPUs simultaneously.
* Each block contains three sub-counters, each of which can be configured for
* various system utility functions - free running counter, periodic interrupts,
* watchdog reset, or three interrupts followed by a watchdog reset.
* All counters are clocked by either LFCLK (nominal 32 kHz) or by a cascaded
* All counters are clocked by either LFCLK (nominal 32 kHz) or by a cascaded
* counter.
* A simplified diagram of the MCWDT hardware is shown below:
* \image html mcwdt.png
* The frequency of the periodic interrupts can be configured using the Match
* value with combining Clear on match option, which can be set individually
* for each counter using Cy_MCWDT_SetClearOnMatch(). When the Clear on match option
* is not set, the periodic interrupts of the C0 and C1 16-bit sub-counters occur
* after 65535 counts and the match value defines the shift between interrupts
* (see the figure below). The enabled Clear on match option
* The frequency of the periodic interrupts can be configured using the Match
* value with combining Clear on match option, which can be set individually
* for each counter using Cy_MCWDT_SetClearOnMatch(). When the Clear on match option
* is not set, the periodic interrupts of the C0 and C1 16-bit sub-counters occur
* after 65535 counts and the match value defines the shift between interrupts
* (see the figure below). The enabled Clear on match option
* resets the counter when the interrupt occurs.
* \image html mcwdt_counters.png
* 32-bit sub-counter C2 does not have Clear on match option.
* The interrupt of counter C2 occurs when the counts equal
* 32-bit sub-counter C2 does not have Clear on match option.
* The interrupt of counter C2 occurs when the counts equal
* 2<sup>Toggle bit</sup> value.
* \image html mcwdt_subcounters.png
* To set up an MCWDT, provide the configuration parameters in the
* cy_stc_mcwdt_config_t structure. Then call
* Cy_MCWDT_Init() to initialize the driver.
* To set up an MCWDT, provide the configuration parameters in the
* cy_stc_mcwdt_config_t structure. Then call
* Cy_MCWDT_Init() to initialize the driver.
* Call Cy_MCWDT_Enable() to enable all specified counters.
*
* You can also set the mode of operation for any counter. If you choose
* interrupt mode, use Cy_MCWDT_SetInterruptMask() with the
* parameter for the masks described in Macro Section. All counter interrupts
* interrupt mode, use Cy_MCWDT_SetInterruptMask() with the
* parameter for the masks described in Macro Section. All counter interrupts
* are OR'd together to from a single combined MCWDT interrupt.
* Additionally, enable the Global interrupts and initialize the referenced
* interrupt by setting the priority and the interrupt vector using
* Additionally, enable the Global interrupts and initialize the referenced
* interrupt by setting the priority and the interrupt vector using
* \ref Cy_SysInt_Init() of the sysint driver.
*
* The values of the MCWDT counters can be monitored using
*
* The values of the MCWDT counters can be monitored using
* Cy_MCWDT_GetCount().
*
* \note In addition to the MCWDTs, each device has a separate watchdog timer
@ -80,7 +78,7 @@
*
* \section group_mcwdt_more_information More Information
*
* For more information on the MCWDT peripheral, refer to
* For more information on the MCWDT peripheral, refer to
* the technical reference manual (TRM).
*
* \section group_mcwdt_MISRA MISRA-C Compliance]
@ -137,19 +135,19 @@ extern "C" {
/** The MCWDT component configuration structure. */
typedef struct
{
uint16_t c0Match; /**< The sub-counter#0 match comparison value, for interrupt or watchdog timeout.
Range: 0 - 65535 for c0ClearOnMatch = 0 and 1 - 65535 for
uint16_t c0Match; /**< The sub-counter#0 match comparison value, for interrupt or watchdog timeout.
Range: 0 - 65535 for c0ClearOnMatch = 0 and 1 - 65535 for
c0ClearOnMatch = 1. */
uint16_t c1Match; /**< The sub-counter#1 match comparison value, for interrupt or watchdog timeout.
Range: 0 - 65535 for c1ClearOnMatch = 0 and 1 - 65535 for
Range: 0 - 65535 for c1ClearOnMatch = 0 and 1 - 65535 for
c1ClearOnMatch = 1. */
uint8_t c0Mode; /**< The sub-counter#0 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
uint8_t c0Mode; /**< The sub-counter#0 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
\ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET. */
uint8_t c1Mode; /**< The sub-counter#1 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
uint8_t c1Mode; /**< The sub-counter#1 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE,
\ref CY_MCWDT_MODE_INT, \ref CY_MCWDT_MODE_RESET and \ref CY_MCWDT_MODE_INT_RESET. */
uint8_t c2ToggleBit; /**< The sub-counter#2 Period / Toggle Bit value.
uint8_t c2ToggleBit; /**< The sub-counter#2 Period / Toggle Bit value.
Range: 0 - 31. */
uint8_t c2Mode; /**< The sub-counter#2 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE
uint8_t c2Mode; /**< The sub-counter#2 mode. It can have the following values: \ref CY_MCWDT_MODE_NONE
and \ref CY_MCWDT_MODE_INT. */
bool c0ClearOnMatch; /**< The sub-counter#0 Clear On Match parameter enabled/disabled. */
bool c1ClearOnMatch; /**< The sub-counter#1 Clear On Match parameter enabled/disabled. */
@ -191,28 +189,28 @@ typedef struct
#define CY_MCWDT_ALL_WDT_ENABLE_Msk (MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk | MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk | \
MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk)
#define CY_MCWDT_CTR0_Pos (0u)
#define CY_MCWDT_CTR1_Pos (1u)
#define CY_MCWDT_CTR2_Pos (2u)
#define CY_MCWDT_CTR_Pos (0UL)
#define CY_MCWDT_C2_MODE_MASK (1u)
#define CY_MCWDT_C2_MODE_MASK (1u)
/** \endcond */
#define CY_MCWDT_ID CY_PDL_DRV_ID(0x35u) /**< MCWDT PDL ID */
#define CY_MCWDT_CTR0 (1UL << CY_MCWDT_CTR0_Pos) /**< The sub-counter#0 mask. This macro is used with functions
#define CY_MCWDT_CTR0 (1UL << CY_MCWDT_CTR0_Pos) /**< The sub-counter#0 mask. This macro is used with functions
that handle multiple counters, including Cy_MCWDT_Enable(),
Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
#define CY_MCWDT_CTR1 (1UL << CY_MCWDT_CTR1_Pos) /**< The sub-counter#1 mask. This macro is used with functions
#define CY_MCWDT_CTR1 (1UL << CY_MCWDT_CTR1_Pos) /**< The sub-counter#1 mask. This macro is used with functions
that handle multiple counters, including Cy_MCWDT_Enable(),
Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
#define CY_MCWDT_CTR2 (1UL << CY_MCWDT_CTR2_Pos) /**< The sub-counter#2 mask. This macro is used with functions
#define CY_MCWDT_CTR2 (1UL << CY_MCWDT_CTR2_Pos) /**< The sub-counter#2 mask. This macro is used with functions
that handle multiple counters, including Cy_MCWDT_Enable(),
Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
#define CY_MCWDT_CTR_Msk (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2) /**< The mask for all sub-counters. This macro is used with functions
#define CY_MCWDT_CTR_Msk (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2) /**< The mask for all sub-counters. This macro is used with functions
that handle multiple counters, including Cy_MCWDT_Enable(),
Cy_MCWDT_Disable(), Cy_MCWDT_ClearInterrupt() and Cy_MCWDT_ResetCounters(). */
@ -238,7 +236,7 @@ typedef enum
CY_MCWDT_MODE_NONE, /**< The No action mode. It is used for Set/GetMode functions. */
CY_MCWDT_MODE_INT, /**< The Interrupt mode. It is used for Set/GetMode functions. */
CY_MCWDT_MODE_RESET, /**< The Reset mode. It is used for Set/GetMode functions. */
CY_MCWDT_MODE_INT_RESET /**< The Three interrupts then watchdog reset mode. It is used for
CY_MCWDT_MODE_INT_RESET /**< The Three interrupts then watchdog reset mode. It is used for
Set/GetMode functions. */
} cy_en_mcwdtmode_t;
@ -246,17 +244,17 @@ typedef enum
typedef enum
{
CY_MCWDT_CASCADE_NONE, /**< The cascading is disabled. It is used for Set/GetCascade functions. */
CY_MCWDT_CASCADE_C0C1, /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade.
CY_MCWDT_CASCADE_C0C1, /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade.
It is used for Set/GetCascade functions. */
CY_MCWDT_CASCADE_C1C2, /**< The sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
It is used for Set/GetCascade functions. */
CY_MCWDT_CASCADE_BOTH /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade
and the sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
CY_MCWDT_CASCADE_BOTH /**< The sub-counter#1 is clocked by LFCLK or from sub-counter#0 cascade
and the sub-counter#2 is clocked by LFCLK or from sub-counter#1 cascade.
It is used for Set/GetCascade functions. */
} cy_en_mcwdtcascade_t;
/** The MCWDT error codes. */
typedef enum
typedef enum
{
CY_MCWDT_SUCCESS = 0x00u, /**< Successful */
CY_MCWDT_BAD_PARAM = CY_MCWDT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< One or more invalid parameters */
@ -267,9 +265,9 @@ typedef enum
/** \cond PARAM_CHECK_MACROS */
/** Parameter check macros */
#define CY_MCWDT_IS_CNTS_MASK_VALID(counters) (0U == ((counters) & (uint32_t)~CY_MCWDT_CTR_Msk))
/** Parameter check macros */
#define CY_MCWDT_IS_CNTS_MASK_VALID(counters) (0U == ((counters) & (uint32_t)~CY_MCWDT_CTR_Msk))
#define CY_MCWDT_IS_CNT_NUM_VALID(counter) ((CY_MCWDT_COUNTER0 == (counter)) || \
(CY_MCWDT_COUNTER1 == (counter)) || \
(CY_MCWDT_COUNTER2 == (counter)))
@ -286,12 +284,12 @@ typedef enum
(CY_MCWDT_CASCADE_C0C1 == (cascade)) || \
(CY_MCWDT_CASCADE_C1C2 == (cascade)) || \
(CY_MCWDT_CASCADE_BOTH == (cascade)))
#define CY_MCWDT_IS_MATCH_VALID(clearOnMatch, match) ((clearOnMatch) ? (1UL <= (match)) : true)
#define CY_MCWDT_IS_BIT_VALID(bit) (31UL >= (bit))
#define CY_MCWDT_IS_BIT_VALID(bit) (31UL >= (bit))
/** \endcond */
@ -346,13 +344,13 @@ uint32_t Cy_MCWDT_GetCountCascaded(MCWDT_STRUCT_Type const *base);
* CY_MCWDT_CTR2 macros.
*
* \param waitUs
* The function waits for some delay in microseconds before returning,
* because the counter begins counting after two lf_clk cycles pass.
* The function waits for some delay in microseconds before returning,
* because the counter begins counting after two lf_clk cycles pass.
* The recommended value is 93 us.
* \note
* Setting this parameter to a zero means No wait. In this case, it is
* the user's responsibility to check whether the selected counters were enabled
* immediately after the function call. This can be done by the
* the user's responsibility to check whether the selected counters were enabled
* immediately after the function call. This can be done by the
* Cy_MCWDT_GetEnabledStatus() API.
*
*******************************************************************************/
@ -361,7 +359,7 @@ __STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters,
uint32_t enableCounters;
CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
/* Extract particular counters for enable */
enableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
@ -387,13 +385,13 @@ __STATIC_INLINE void Cy_MCWDT_Enable(MCWDT_STRUCT_Type *base, uint32_t counters,
* CY_MCWDT_CTR2 macros.
*
* \param waitUs
* The function waits for some delay in microseconds before returning,
* because the counter stops counting after two lf_clk cycles pass.
* The function waits for some delay in microseconds before returning,
* because the counter stops counting after two lf_clk cycles pass.
* The recommended value is 93 us.
* \note
* Setting this parameter to a zero means No wait. In this case, it is
* the user's responsibility to check whether the selected counters were disabled
* immediately after the function call. This can be done by the
* Setting this parameter to a zero means No wait. In this case, it is
* the user's responsibility to check whether the selected counters were disabled
* immediately after the function call. This can be done by the
* Cy_MCWDT_GetEnabledStatus() API.
*
*******************************************************************************/
@ -402,7 +400,7 @@ __STATIC_INLINE void Cy_MCWDT_Disable(MCWDT_STRUCT_Type *base, uint32_t counters
uint32_t disableCounters;
CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
/* Extract particular counters for disable */
disableCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk : 0UL) |
((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk : 0UL) |
@ -435,7 +433,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetEnabledStatus(MCWDT_STRUCT_Type const *base
uint32_t status = 0u;
CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
switch (counter)
{
case CY_MCWDT_COUNTER0:
@ -540,7 +538,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetLockedStatus(MCWDT_STRUCT_Type const *base)
* The mode for Counter 2 can be set only to CY_MCWDT_MODE_NONE or CY_MCWDT_MODE_INT.
*
* \note
* This API must not be called while the counters are running.
* This API must not be called while the counters are running.
* Prior to calling this API, the counter must be disabled.
*
*******************************************************************************/
@ -607,7 +605,7 @@ __STATIC_INLINE cy_en_mcwdtmode_t Cy_MCWDT_GetMode(MCWDT_STRUCT_Type const *base
* Set 0 to disable; 1 to enable.
*
* \note
* This API must not be called while the counters are running.
* This API must not be called while the counters are running.
* Prior to calling this API, the counter must be disabled.
*
*******************************************************************************/
@ -678,17 +676,17 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetClearOnMatch(MCWDT_STRUCT_Type const *base,
* Sets or clears each of the cascade options.
*
* \note
* This API must not be called when the counters are running.
* This API must not be called when the counters are running.
* Prior to calling this API, the counter must be disabled.
*
*******************************************************************************/
__STATIC_INLINE void Cy_MCWDT_SetCascade(MCWDT_STRUCT_Type *base, cy_en_mcwdtcascade_t cascade)
{
CY_ASSERT_L3(CY_MCWDT_IS_CASCADE_VALID(cascade));
base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1,
(uint32_t) cascade);
base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2,
base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2,
((uint32_t) cascade >> 1u));
}
@ -730,20 +728,20 @@ __STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const
* The number of the WDT counter. The valid range is [0-1].
*
* \param match
* The value to match against the counter.
* The valid range is [0-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 0
* The value to match against the counter.
* The valid range is [0-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 0
* and [1-65535] for c0ClearOnMatch (or c1ClearOnMatch) = 1.
*
* \note
* The match value is not supported by Counter 2.
*
* \note
* Action on match is taken on the next increment after the counter value
* Action on match is taken on the next increment after the counter value
* equal to match value.
*
* \param waitUs
* The function waits for some delay in microseconds before returning,
* because the match affects after two lf_clk cycles pass. The recommended
* The function waits for some delay in microseconds before returning,
* because the match affects after two lf_clk cycles pass. The recommended
* value is 93 us.
* \note
* Setting this parameter to a zero means No wait. This must be taken
@ -753,8 +751,8 @@ __STATIC_INLINE cy_en_mcwdtcascade_t Cy_MCWDT_GetCascade(MCWDT_STRUCT_Type const
__STATIC_INLINE void Cy_MCWDT_SetMatch(MCWDT_STRUCT_Type *base, cy_en_mcwdtctr_t counter, uint32_t match, uint16_t waitUs)
{
CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID((CY_MCWDT_COUNTER0 == counter) ?
((base->MCWDT_CONFIG & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk) > 0U) :
CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID((CY_MCWDT_COUNTER0 == counter) ?
((base->MCWDT_CONFIG & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk) > 0U) :
((base->MCWDT_CONFIG & MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk) > 0U),
match));
@ -820,7 +818,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetMatch(MCWDT_STRUCT_Type const *base, cy_en_
__STATIC_INLINE void Cy_MCWDT_SetToggleBit(MCWDT_STRUCT_Type *base, uint32_t bit)
{
CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(bit));
base->MCWDT_CONFIG = _CLR_SET_FLD32U(base->MCWDT_CONFIG, MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2, bit);
}
@ -866,7 +864,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_
uint32_t countVal = 0u;
CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter));
switch (counter)
{
case CY_MCWDT_COUNTER0:
@ -902,17 +900,17 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetCount(MCWDT_STRUCT_Type const *base, cy_en_
* CY_MCWDT_CTR2 macros.
*
* \param waitUs
* The function waits for some delay in microseconds before returning, because
* The function waits for some delay in microseconds before returning, because
* a reset occurs after one lf_clk cycle passes. The recommended value is 62 us.
* \note This function resets the counters two times to prevent the case when
* \note This function resets the counters two times to prevent the case when
* the Counter 1 is not reset when the counters are cascaded. The delay waitUs
* must be greater than 100 us when the counters are cascaded.
* The total delay is greater than 2*waitUs because the function has
* must be greater than 100 us when the counters are cascaded.
* The total delay is greater than 2*waitUs because the function has
* the delay after the first reset.
* \note
* Setting this parameter to a zero means No wait. In this case, it is the
* user's responsibility to check whether the selected counters were reset
* immediately after the function call. This can be done by the
* Setting this parameter to a zero means No wait. In this case, it is the
* user's responsibility to check whether the selected counters were reset
* immediately after the function call. This can be done by the
* Cy_MCWDT_GetCount() API.
*
*******************************************************************************/
@ -921,18 +919,18 @@ __STATIC_INLINE void Cy_MCWDT_ResetCounters(MCWDT_STRUCT_Type *base, uint32_t co
uint32_t resetCounters;
CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
/* Extract particular counters for reset */
resetCounters = ((0UL != (counters & CY_MCWDT_CTR0)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk : 0UL) |
((0UL != (counters & CY_MCWDT_CTR1)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk : 0UL) |
((0UL != (counters & CY_MCWDT_CTR2)) ? MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk : 0UL);
base->MCWDT_CTL |= resetCounters;
Cy_SysLib_DelayUs(waitUs);
base->MCWDT_CTL |= resetCounters;
Cy_SysLib_DelayUs(waitUs);
}
@ -977,7 +975,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptStatus(MCWDT_STRUCT_Type const *ba
__STATIC_INLINE void Cy_MCWDT_ClearInterrupt(MCWDT_STRUCT_Type *base, uint32_t counters)
{
CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
base->MCWDT_INTR = counters;
(void) base->MCWDT_INTR;
}
@ -1044,7 +1042,7 @@ __STATIC_INLINE uint32_t Cy_MCWDT_GetInterruptMask(MCWDT_STRUCT_Type const *base
__STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t counters)
{
CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters));
base->MCWDT_INTR_MASK = counters;
}
@ -1054,9 +1052,9 @@ __STATIC_INLINE void Cy_MCWDT_SetInterruptMask(MCWDT_STRUCT_Type *base, uint32_t
****************************************************************************//**
*
* Returns the MCWDT interrupt masked request register. This register contains
* the logical AND of corresponding bits from the MCWDT interrupt request and
* the logical AND of corresponding bits from the MCWDT interrupt request and
* mask registers.
* In the interrupt service routine, this function identifies which of the
* In the interrupt service routine, this function identifies which of the
* enabled MCWDT interrupt sources caused an interrupt event.
*
* \param base

14
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/pdm_pcm/cy_pdm_pcm.c
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_pdm_pcm.h"
@ -61,11 +59,11 @@ cy_en_pdm_pcm_status_t Cy_PDM_PCM_Init(PDM_Type * base, cy_stc_pdm_pcm_config_t
CY_ASSERT_L3(CY_PDM_PCM_IS_HPF_GAIN_VALID(config->highPassFilterGain));
CY_ASSERT_L3(CY_PDM_PCM_IS_WORD_LEN_VALID(config->wordLen));
CY_ASSERT_L3(CY_PDM_PCM_IS_TRIG_LEVEL(config->rxFifoTriggerLevel, config->chanSelect));
ret = CY_PDM_PCM_SUCCESS;
base->CTL &= (uint32_t) ~PDM_CTL_ENABLED_Msk; /* Disable the PDM_PCM block */
/* The clock setting */
base->CLOCK_CTL = _VAL2FLD(PDM_CLOCK_CTL_CLK_CLOCK_DIV, config->clkDiv) |
_VAL2FLD(PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV, config->mclkDiv) |
@ -141,7 +139,7 @@ void Cy_PDM_PCM_SetGain(PDM_Type * base, cy_en_pdm_pcm_chan_select_t chan, cy_en
{
CY_ASSERT_L3(CY_PDM_PCM_IS_CHAN_VALID(chan));
CY_ASSERT_L3(CY_PDM_PCM_IS_GAIN_VALID(gain));
if (chan == CY_PDM_PCM_CHAN_LEFT)
{
base->CTL = _CLR_SET_FLD32U(base->CTL, PDM_CTL_PGA_L, ((uint32_t) gain));
@ -171,7 +169,7 @@ void Cy_PDM_PCM_SetGain(PDM_Type * base, cy_en_pdm_pcm_chan_select_t chan, cy_en
cy_en_pdm_pcm_gain_t Cy_PDM_PCM_GetGain(PDM_Type const * base, cy_en_pdm_pcm_chan_select_t chan)
{
cy_en_pdm_pcm_gain_t ret;
CY_ASSERT_L3(CY_PDM_PCM_IS_CHAN_VALID(chan));
if (chan == CY_PDM_PCM_CHAN_LEFT)

18
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/pdm_pcm/cy_pdm_pcm.h
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
@ -102,7 +100,7 @@
* <tr><th>Version</th><th>Changes</th><th>Reason for Change</th></tr>
* <tr>
* <td>2.10</td>
* <td>The gain values in range +4.5...+10.5dB (5 items) of /ref cy_en_pdm_pcm_gain_t are corrected.
* <td>The gain values in range +4.5...+10.5dB (5 items) of /ref cy_en_pdm_pcm_gain_t are corrected.
* Added Low Power Callback section.</td>
* <td>Incorrect setting of gain values in limited range.
* Documentation update and clarification.</td>
@ -110,7 +108,7 @@
* <tr>
* <td>2.0</td>
* <td>Enumeration types for gain and soft mute cycles are added.<br>
* Function parameter checks are added.<br>
* Function parameter checks are added.<br>
* The next functions are removed:
* * Cy_PDM_PCM_EnterLowPowerCallback
* * Cy_PDM_PCM_ExitLowPowerCallback
@ -345,7 +343,7 @@ typedef struct
- 1: extension by sign bits */
cy_en_pdm_pcm_gain_t gainLeft; /**< Gain for left channel, see #cy_en_pdm_pcm_gain_t */
cy_en_pdm_pcm_gain_t gainRight; /**< Gain for right channel, see #cy_en_pdm_pcm_gain_t */
uint8_t rxFifoTriggerLevel; /**< Fifo interrupt trigger level (in words),
uint8_t rxFifoTriggerLevel; /**< Fifo interrupt trigger level (in words),
range: 0 - 253 for stereo and 0 - 254 for mono mode */
bool dmaTriggerEnable; /**< DMA trigger enable */
uint32_t interruptMask; /**< Interrupts enable mask */
@ -425,7 +423,7 @@ typedef struct
#define CY_PDM_PCM_IS_CHAN_VALID(chan) (((chan) == CY_PDM_PCM_CHAN_LEFT) || \
((chan) == CY_PDM_PCM_CHAN_RIGHT))
#define CY_PDM_PCM_IS_S_CYCLES_VALID(sCycles) (((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_64) || \
((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_96) || \
((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_128) || \
@ -434,7 +432,7 @@ typedef struct
((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_256) || \
((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_384) || \
((sCycles) == CY_PDM_PCM_SOFT_MUTE_CYCLES_512))
#define CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt) (0UL == ((interrupt) & ((uint32_t) ~CY_PDM_PCM_INTR_MASK)))
#define CY_PDM_PCM_IS_SINC_RATE_VALID(sincRate) ((sincRate) <= 127U)
#define CY_PDM_PCM_IS_STEP_SEL_VALID(stepSel) ((stepSel) <= 1UL)
@ -604,7 +602,7 @@ __STATIC_INLINE uint32_t Cy_PDM_PCM_GetInterruptStatus(PDM_Type const * base)
* Clears one or more PDM-PCM interrupt statuses (sets an INTR register's bits).
*
* \param base The pointer to the PDM-PCM instance address
* \param interrupt
* \param interrupt
* The interrupt bit mask \ref group_pdm_pcm_macros_intrerrupt_masks.
*
******************************************************************************/

62
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/profile/cy_profile.c
View File

@ -1,15 +1,13 @@
/***************************************************************************//**
/***************************************************************************//**
* \file cy_profile.c
* \version 1.0
*
* Provides an API declaration of the energy profiler (EP) driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Provides an API declaration of the energy profiler (EP) driver.
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_profile.h"
@ -39,7 +37,7 @@ static cy_stc_profile_ctr_t cy_ep_ctrs[PROFILE_PRFL_CNT_NR];
* the cy_ep_ctrs[] array, and (2) whether the counter has been assigned.
*
* \param ctrAddr The handle to (address of) the assigned counter
*
*
* \return CY_PROFILE_SUCCESS, or CY_PROFILE_BAD_PARAM for invalid ctrAddr or counter not
* in use.
*
@ -71,12 +69,12 @@ static cy_en_profile_status_t Cy_Profile_IsPtrValid(const cy_stc_profile_ctr_ptr
* EP interrupt handler: Increments the overflow member of the counter structure,
* for each counter that is in use and has an overflow.
*
* This handler is not configured or used automatically. You must configure the
* interrupt handler for the EP, using Cy_SysInt_Init(). Typically you configure
* This handler is not configured or used automatically. You must configure the
* interrupt handler for the EP, using Cy_SysInt_Init(). Typically you configure
* the system to use \ref Cy_Profile_ISR() as the overflow interrupt handler. You
* can provide a custom interrupt handler to perform additional operations if
* required. Your handler can call \ref Cy_Profile_ISR() to handle counter
* overflow.
* overflow.
*
*******************************************************************************/
void Cy_Profile_ISR(void)
@ -139,7 +137,7 @@ void Cy_Profile_StartProfiling(void)
* Function Name: Cy_Profile_ClearConfiguration
****************************************************************************//**
*
* Clears all counter configurations and sets all counters and overflow counters
* Clears all counter configurations and sets all counters and overflow counters
* to 0. Calls Cy_Profile_ClearCounters() to clear counter registers.
*
* \funcusage
@ -159,12 +157,12 @@ void Cy_Profile_ClearConfiguration(void)
*
* Configures and assigns a hardware profile counter to the list of used counters.
*
* This function assigns an available profile counter to a slot in the internal
* This function assigns an available profile counter to a slot in the internal
* software data structure and returns the handle for that slot location. The data
* structure is used to keep track of the counter status and to implement a 64-bit
* profile counter. If no counter slots are available, the function returns a
* NULL pointer.
*
*
* \param monitor The monitor source number
*
* \param duration Events are monitored (0), or duration is monitored (1)
@ -172,7 +170,7 @@ void Cy_Profile_ClearConfiguration(void)
* \param refClk Counter reference clock
*
* \param weight Weighting factor for the counter value
*
*
* \return A pointer to the counter data structure. NULL if no counter is
* available.
*
@ -199,7 +197,7 @@ cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy
cy_ep_ctrs[i].weight = weight;
/* pass back the handle to (address of) the counter data structure */
retVal = &cy_ep_ctrs[i];
/* Load the CTL register bitfields of the assigned counter. */
retVal->cntAddr->CTL =
_VAL2FLD(PROFILE_CNT_STRUCT_CTL_CNT_DURATION, retVal->ctlRegVals.cntDuration) |
@ -222,8 +220,8 @@ cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy
*
* \param ctrAddr The handle to the assigned counter (returned by calling
* \ref Cy_Profile_ConfigureCounter()).
*
* \return
*
* \return
* Status of the operation.
*
* \note The counter is not disabled by this function.
@ -235,7 +233,7 @@ cy_stc_profile_ctr_ptr_t Cy_Profile_ConfigureCounter(en_ep_mon_sel_t monitor, cy
cy_en_profile_status_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr)
{
cy_en_profile_status_t retStatus = CY_PROFILE_BAD_PARAM;
retStatus = Cy_Profile_IsPtrValid(ctrAddr);
if (retStatus == CY_PROFILE_SUCCESS)
{
@ -249,15 +247,15 @@ cy_en_profile_status_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr)
* Function Name: Cy_Profile_EnableCounter
****************************************************************************//**
*
* Enables an assigned counter.
* Enables an assigned counter.
*
* \ref Cy_Profile_ConfigureCounter() must have been called for this counter
* before calling this function.
*
* \param ctrAddr The handle to the assigned counter, (returned by calling
* \ref Cy_Profile_ConfigureCounter()).
*
* \return
*
* \return
* Status of the operation.
*
* \funcusage
@ -267,7 +265,7 @@ cy_en_profile_status_t Cy_Profile_FreeCounter(cy_stc_profile_ctr_ptr_t ctrAddr)
cy_en_profile_status_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr)
{
cy_en_profile_status_t retStatus = CY_PROFILE_BAD_PARAM;
retStatus = Cy_Profile_IsPtrValid(ctrAddr);
if (retStatus == CY_PROFILE_SUCCESS)
{
@ -291,8 +289,8 @@ cy_en_profile_status_t Cy_Profile_EnableCounter(cy_stc_profile_ctr_ptr_t ctrAddr
*
* \param ctrAddr The handle to the assigned counter, (returned by calling
* \ref Cy_Profile_ConfigureCounter()).
*
* \return
*
* \return
* Status of the operation.
*
* \funcusage
@ -326,8 +324,8 @@ cy_en_profile_status_t Cy_Profile_DisableCounter(cy_stc_profile_ctr_ptr_t ctrAdd
* \ref Cy_Profile_ConfigureCounter()).
*
* \param result Output parameter used to write in the result.
*
* \return
*
* \return
* Status of the operation.
*
* \funcusage
@ -360,8 +358,8 @@ cy_en_profile_status_t Cy_Profile_GetRawCount(cy_stc_profile_ctr_ptr_t ctrAddr,
* \ref Cy_Profile_ConfigureCounter()).
*
* \param result Output parameter used to write in the result.
*
* \return
*
* \return
* Status of the operation.
*
* \funcusage
@ -416,7 +414,7 @@ uint64_t Cy_Profile_GetSumWeightedCounts(cy_stc_profile_ctr_ptr_t ptrsArray[],
daSum += num;
}
}
return (daSum);
}

72
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/profile/cy_profile.h
View File

@ -6,17 +6,15 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
* \defgroup group_energy_profiler Energy Profiler (Profile)
* \{
*
* The energy profiler driver is an API for configuring and using the profile
*
* The energy profiler driver is an API for configuring and using the profile
* hardware block. The profile block enables measurement of the signal activity
* of select peripherals and monitor sources during a measurement window. Using
* these measurements, it is possible to construct a profile of the energy consumed
@ -30,17 +28,17 @@
* \subsection group_profile_hardware Profile Hardware
*
* The profile hardware consists of a number of profile counters that accept specific
* triggers for incrementing the count value. This allows the events of the source
* triggers for incrementing the count value. This allows the events of the source
* (such as the number of SCB0 bus accesses or the duration of time the BLE RX radio
* is active) to be counted during the measurement window. The available monitor
* sources in the device can be found in the en_ep_mon_sel_t enum in the device
* is active) to be counted during the measurement window. The available monitor
* sources in the device can be found in the en_ep_mon_sel_t enum in the device
* configuration file (e.g. psoc62_config.h). These can be sourced to any of the
* profile counters as triggers. There are two methods of using the monitor sources
* in a profile counter.
*
* - Event: The count value is incremented when a pulse event signal is seen by the
* counter. This type of monitoring is suitable when the monitoring source of
* interest needs to count the discrete events (such as the number of Flash read
* counter. This type of monitoring is suitable when the monitoring source of
* interest needs to count the discrete events (such as the number of Flash read
* accesses) happening in the measurement window.
*
* - Duration: The count value is incremented at every clock edge while the monitor
@ -49,7 +47,7 @@
* duration needs to be expressed as number of clock cycles in the measurement window.
*
* Many of the available monitor sources are suitable for event type monitoring.
* Using a duration type on these signals may not give valuable information. Review
* Using a duration type on these signals may not give valuable information. Review
* the device TRM for more information on the monitor sources and details on how they
* should be used.
*
@ -66,20 +64,20 @@
* toggled. When the measurement window ends, the energy contribution caused by the
* GPIO toggle can be incorporated into the final calculation.
*
* - Event measurement: Monitored events happening in a measurement window can be
* - Event measurement: Monitored events happening in a measurement window can be
* used to increment a profile counter. This gives the activity numbers, which can
* then be multiplied by the instantaneous power numbers associated with the source
* to give the average energy consumption (Energy = Power x time). For example, the
* to give the average energy consumption (Energy = Power x time). For example, the
* energy consumped by an Operating System (OS) task can be estimated by monitoring
* the processor's active cycle count (E.g. CPUSS_MONITOR_CM4) and the Flash read
* accesses (CPUSS_MONITOR_FLASH). Note that these activity numbers can also be
* accesses (CPUSS_MONITOR_FLASH). Note that these activity numbers can also be
* timestamped using the continuous measurement method to differentiate between the
* different task switches. The activity numbers are then multiplied by the associated
* processor and flash access power numbers to give the average energy consumed by
* that task.
*
* - Duration measurement: A peripheral event such as the SMIF select signal can be
* used by a profile counter to measure the time spent on XIP communication through the
* - Duration measurement: A peripheral event such as the SMIF select signal can be
* used by a profile counter to measure the time spent on XIP communication through the
* SPI interface. This activity number can then be multiplied by the power associated
* with that activity to give the average energy consumed by that block during the
* measurement window. This type of monitoring should only be performed for signals
@ -88,16 +86,16 @@
* monitoring model. However tracking the activity of signals such the BLE radio
* should be done using the duration measurement method.
*
* - Low power measurement: The profile counters do not support measurement during chip
* - Low power measurement: The profile counters do not support measurement during chip
* deep-sleep, hibernate and off states. i.e. the profile counters are meant for active
* run-time measurements only. In order to measure the time spent in low power modes (LPM),
* a real-time clock (RTC) should be used. Take a timestamp before LPM entry and a
* a real-time clock (RTC) should be used. Take a timestamp before LPM entry and a
* timestamp upon LPM exit in a continuous measurement model. Then multiply the difference
* by the appropriate LPM power numbers.
*
* \subsection group_profile_usage Driver Usage
*
* At the highest level, the energy profiler must perform the following steps to
* At the highest level, the energy profiler must perform the following steps to
* obtain a measurement:
*
* 1. Initialize the profile hardware block.
@ -117,15 +115,15 @@
* Configuration Considerations for more information.
*
* \section group_profile_configuration Configuration Considerations
*
* Each counter is a 32-bit register that counts either a number of clock cycles,
*
* Each counter is a 32-bit register that counts either a number of clock cycles,
* or a number of events. It is possible to overflow the 32-bit register. To address
* this issue, the driver implements a 32-bit overflow counter. Combined with the 32-bit
* register, this gives a 64-bit counter for each monitored source.
* register, this gives a 64-bit counter for each monitored source.
*
* When an overflow occurs, the profile hardware generates an interrupt. The interrupt is
* When an overflow occurs, the profile hardware generates an interrupt. The interrupt is
* configured using the SysInt driver, where the sample interrupt handler Cy_Profile_ISR()
* can be used as the ISR. The ISR increments the overflow counter for each profiling counter
* can be used as the ISR. The ISR increments the overflow counter for each profiling counter
* and clears the interrupt.
*
* \section group_profile_more_information More Information
@ -205,10 +203,10 @@ extern "C" {
#define CY_PROFILE_ID CY_PDL_DRV_ID(0x1EU)
/** Start profiling command for the CMD register */
#define CY_PROFILE_START_TR 1UL
#define CY_PROFILE_START_TR 1UL
/** Stop profiling command for the CMD register */
#define CY_PROFILE_STOP_TR 2UL
#define CY_PROFILE_STOP_TR 2UL
/** Command to clear all counter registers to 0 */
#define CY_PROFILE_CLR_ALL_CNT 0x100UL
@ -223,7 +221,7 @@ extern "C" {
/**
* Profile counter reference clock source. Used when duration monitoring.
*/
typedef enum
typedef enum
{
CY_PROFILE_CLK_TIMER = 0, /**< Timer clock (TimerClk) */
CY_PROFILE_CLK_IMO = 1, /**< Internal main oscillator (IMO) */
@ -236,14 +234,14 @@ typedef enum
/**
* Monitor method type.
*/
typedef enum
typedef enum
{
CY_PROFILE_EVENT = 0, /**< Count (edge-detected) module events */
CY_PROFILE_DURATION = 1, /**< Count (level) duration in clock cycles */
} cy_en_profile_duration_t;
/** Profiler status codes */
typedef enum
typedef enum
{
CY_PROFILE_SUCCESS = 0x00U, /**< Operation completed successfully */
CY_PROFILE_BAD_PARAM = CY_PROFILE_ID | CY_PDL_STATUS_ERROR | 1UL /**< Invalid input parameters */
@ -265,14 +263,14 @@ typedef struct
cy_en_profile_duration_t cntDuration; /**< 0 = event; 1 = duration */
cy_en_profile_ref_clk_t refClkSel; /**< The reference clock used by the counter */
en_ep_mon_sel_t monSel; /**< The monitor signal to be observed by the counter */
} cy_stc_profile_ctr_ctl_t;
} cy_stc_profile_ctr_ctl_t;
/**
* Software structure for holding a profile counter status and configuration information.
*/
typedef struct
{
uint8_t ctrNum; /**< Profile counter number */
uint8_t ctrNum; /**< Profile counter number */
uint8_t used; /**< 0 = available; 1 = used */
cy_stc_profile_ctr_ctl_t ctlRegVals; /**< Initial counter CTL register settings */
PROFILE_CNT_STRUCT_Type * cntAddr; /**< Base address of the counter instance registers */
@ -322,12 +320,12 @@ __STATIC_INLINE uint32_t Cy_Profile_IsProfiling(void);
* Function Name: Cy_Profile_Init
****************************************************************************//**
*
* Initializes and enables the profile hardware.
* Initializes and enables the profile hardware.
*
* This function must be called once when energy profiling is desired. The
* This function must be called once when energy profiling is desired. The
* operation does not start a profiling session.
*
* \note The profile interrupt must also be configured. \ref Cy_Profile_ISR()
* \note The profile interrupt must also be configured. \ref Cy_Profile_ISR()
* can be used as its handler.
*
* \funcusage
@ -336,7 +334,7 @@ __STATIC_INLINE uint32_t Cy_Profile_IsProfiling(void);
*******************************************************************************/
__STATIC_INLINE void Cy_Profile_Init(void)
{
PROFILE->CTL = _VAL2FLD(PROFILE_CTL_ENABLED, 1UL/*enabled */) |
PROFILE->CTL = _VAL2FLD(PROFILE_CTL_ENABLED, 1UL/*enabled */) |
_VAL2FLD(PROFILE_CTL_WIN_MODE, 0UL/*start/stop mode*/);
PROFILE->INTR_MASK = 0UL; /* clear all counter interrupt mask bits */
}
@ -346,7 +344,7 @@ __STATIC_INLINE void Cy_Profile_Init(void)
* Function Name: Cy_Profile_DeInit
****************************************************************************//**
*
* Clears the interrupt mask and disables the profile hardware.
* Clears the interrupt mask and disables the profile hardware.
*
* This function should be called when energy profiling is no longer desired.
*

462
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/prot/cy_prot.c
View File

File diff suppressed because it is too large Load Diff

132
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/prot/cy_prot.h
View File

@ -7,10 +7,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
@ -20,18 +18,18 @@
* The Protection Unit driver provides an API to configure the Memory Protection
* Units (MPU), Shared Memory Protection Units (SMPU), and Peripheral Protection
* Units (PPU). These are separate from the ARM Core MPUs and provide additional
* mechanisms for securing resource accesses. The Protection units address the
* mechanisms for securing resource accesses. The Protection units address the
* following concerns in an embedded design:
* - <b>Security requirements:</b> This includes the prevention of malicious attacks
* to access secure memory or peripherals.
* - <b>Safety requirements:</b> This includes detection of accidental (non-malicious)
* SW errors and random HW errors. It is important to enable failure analysis
* to investigate the root cause of a safety violation.
*
*
* \section group_prot_protection_type Protection Types
*
* Protection units are hardware configuration structures that control bus accesses
* to the resources that they protect. By combining these individual configuration
* Protection units are hardware configuration structures that control bus accesses
* to the resources that they protect. By combining these individual configuration
* structures, a system is built to allow strict restrictions on the capabilities
* of individual bus masters (e.g. CM0+, CM4, Crypt) and their operating modes.
* This architecture can then be integrated into the overall security system
@ -40,16 +38,16 @@
* it must pass the evaluation performed for each category. These access evaluations
* are prioritized, where MPU has the highest priority, followed by SMPU, followed
* by PPU. i.e. if an SMPU and a PPU protect the same resource and if access is
* denied by the SMPU, then the PPU access evaluation is skipped. This can lead to a
* denied by the SMPU, then the PPU access evaluation is skipped. This can lead to a
* denial-of-service scenario and the application should pay special attention in
* taking ownership of the protection unit configurations.
*
* \subsection group_prot_memory_protection Memory Protection
*
* Memory access control for a bus master is controlled using an MPU. These are
* most often used to distinguish user and privileged accesses from a single bus
* master such as task switching in an OS/kernel. For ARM cores (CM0+, CM4), the
* core MPUs are used to perform this task. For other non-ARM bus masters such
* most often used to distinguish user and privileged accesses from a single bus
* master such as task switching in an OS/kernel. For ARM cores (CM0+, CM4), the
* core MPUs are used to perform this task. For other non-ARM bus masters such
* as Crypto, MPU structs are available, which can be used in a similar manner
* as the ARM core MPUs. These MPUs however must be configured by the ARM cores.
* Other bus masters that do not have an MPU, such as DMA (DW), inherit the access
@ -67,10 +65,10 @@
* This protection effectively allows only those with correct bus master access
* settings to read/write/execute the memory region. This type of protection
* is used in general memory such as Flash and SRAM. Peripheral registers are
* best configured using the peripheral protection units instead. SMPU structs
* have a descending priority, where larger index struct has higher priority
* best configured using the peripheral protection units instead. SMPU structs
* have a descending priority, where larger index struct has higher priority
* access evaluation over lower index structs. E.g. SMPU_STRUCT15 has higher priority
* than SMPU_STRUCT14 and its access will be evaluated before SMPU_STRUCT14.
* than SMPU_STRUCT14 and its access will be evaluated before SMPU_STRUCT14.
* If both target the same memory, then the higher index (MPU_STRUCT15) will be
* used, and the lower index (SMPU_STRUCT14) will be ignored.
*
@ -80,7 +78,7 @@
* register accesses by bus masters. Four types of PPUs are available.
* - <b>Fixed Group (GR) PPUs</b> are used to protect an entire peripheral MMIO group
* from invalid bus master accesses. The MMIO grouping information and which
* resource belongs to which group is device specific and can be obtained
* resource belongs to which group is device specific and can be obtained
* from the device technical reference manual (TRM). Group PPUs have the highest
* priority in the PPU category. Therefore their access evaluations take precedence
* over the other types of PPUs.
@ -89,17 +87,17 @@
* type of peripheral protection unit. Programmable PPUs have the second highest
* priority and take precedence over Region PPUs and Slave PPUs. Similar to SMPUs,
* higher index PROG PPUs have higher priority than lower indexes PROG PPUs.
* - <b>Fixed Region (RG) PPUs</b> are used to protect an entire peripheral slave
* instance from invalid bus master accesses. For example, TCPWM0, TCPWM1,
* - <b>Fixed Region (RG) PPUs</b> are used to protect an entire peripheral slave
* instance from invalid bus master accesses. For example, TCPWM0, TCPWM1,
* SCB0, and SCB1, etc. Region PPUs have the third highest priority and take precedence
* over Slave PPUs.
* - <b>Fixed Slave (SL) PPUs</b> are used to protect specified regions of peripheral
* instances. For example, individual DW channel structs, SMPU structs, and
* instances. For example, individual DW channel structs, SMPU structs, and
* IPC structs, etc. Slave PPUs have the lowest priority in the PPU category and
* therefore are evaluated last.
*
* \section group_prot_protection_context Protection Context
*
*
* Protection context (PC) attribute is present in all bus masters and is evaluated
* when accessing memory protected by an SMPU or a PPU. There are no limitations
* to how the PC values are allocated to the bus masters and this makes it
@ -138,12 +136,12 @@
* user and privileged modes is handled by updating its Control register or
* by exception entries. Other bus masters such as Crypto have their own
* user/privileged settings bit in the bus master control register. This is
* then controlled by the ARM cores. Bus masters that do not have
* then controlled by the ARM cores. Bus masters that do not have
* user/privileged access controls, such as DMA, inherit their attributes
* from the bus master that configured it. The user/privileged distinction
* is used mainly in the MPUs for single bus master accesses but they can
* also be used in all other protection units.
* - <b>Secure/Non-secure access:</b> The secure/non-secure attribute is another
* - <b>Secure/Non-secure access:</b> The secure/non-secure attribute is another
* identifier to distinguish between two separate modes of operations. Much
* like the user/privileged access, the secure/non-secure mode flag is present
* in the bus master control register. The ARM core does not have this
@ -155,10 +153,10 @@
* both secure and non-secure regions, whereas a bus master with non-secure
* attribute can only access non-secure regions.
* - <b>Protection Context access:</b> Protection Context is an attribute
* that serves two purposes; To enter the hardware controlled secure PC=0
* that serves two purposes; To enter the hardware controlled secure PC=0
* mode of operation from non-secure modes and to provide finer granularity
* to the bus master access definitions. It is used in SMPU and PPU configuration
* to control which bus master protection context can access the resources
* to control which bus master protection context can access the resources
* that they protect.
*
* \section group_prot_protection_structure Protection Structure
@ -167,7 +165,7 @@
* The exception to this rule is MPU structs, which only have the slave struct
* equivalent. The protection units apply their access evaluations in a decreasing
* index order. For example, if SMPU1 and SMPU2 both protect a specific memory region,
* the the higher index (SMPU2) will be evaluated first. In a secure system, the
* the the higher index (SMPU2) will be evaluated first. In a secure system, the
* higher index protection structs would then provide the high level of security
* and the lower indexes would provide the lower level of security. Refer to the
* \ref group_prot_protection_type section for more information.
@ -182,41 +180,41 @@
* \subsubsection group_prot_slave_addr Slave Struct Address Definition
*
* - Address: For MPU, SMPU and PROG PPU, the address field is used to define
* the base memory region to apply the protection. This field has a dependency
* the base memory region to apply the protection. This field has a dependency
* on the region size, which dictates the alignment of the protection unit. E.g.
* if the region size is 64KB, the address field is aligned to 64KB. Hence
* the lowest bits [15:0] are ignored. For instance, if the address is defined
* the lowest bits [15:0] are ignored. For instance, if the address is defined
* at 0x0800FFFF, the protection unit would apply its protection settings from
* 0x08000000. Thus alignment must be checked before defining the protection
* address. The address field for other PPUs are not used, as they are bound
* to their respective peripheral memory locations.
* 0x08000000. Thus alignment must be checked before defining the protection
* address. The address field for other PPUs are not used, as they are bound
* to their respective peripheral memory locations.
* - Region Size: For MPU, SMPU and PROG PPU, the region size is used to define
* the memory block size to apply the protection settings, starting from the
* defined base address. It is also used to define the 8 sub-regions for the
* chosen memory block. E.g. If the region size is 64KB, each subregion would
* be 8KB. This information can then be used to disable the protection
* settings for select subregions, which gives finer granularity to the
* memory regions. PPUs do not have region size definitions as they are bound
* to their respective peripheral memory locations.
* settings for select subregions, which gives finer granularity to the
* memory regions. PPUs do not have region size definitions as they are bound
* to their respective peripheral memory locations.
* - Subregions: The memory block defined by the address and region size fields
* is divided into 8 (0 to 7) equally spaced subregions. The protection settings
* of the protection unit can be disabled for these subregions. E.g. for a
* given 64KB of memory block starting from address 0x08000000, disabling
* of the protection unit can be disabled for these subregions. E.g. for a
* given 64KB of memory block starting from address 0x08000000, disabling
* subregion 0 would result in the protection settings not affecting the memory
* located between 0x08000000 to 0x08001FFF. PPUs do not have subregion
* definitions as they are bound to their respective peripheral memory locations.
* located between 0x08000000 to 0x08001FFF. PPUs do not have subregion
* definitions as they are bound to their respective peripheral memory locations.
*
* \subsubsection group_prot_slave_attr Slave Struct Attribute Definition
*
* - User Permission: Protection units can control the access restrictions
* of the read (R), write (W) and execute (X) (subject to their availability
* depending on the type of protection unit) operations on the memory block
* of the read (R), write (W) and execute (X) (subject to their availability
* depending on the type of protection unit) operations on the memory block
* when the bus master is operating in user mode. PPU structs do not provide
* execute attributes.
* - Privileged Permission: Similar to the user permission, protection units can
* control the access restrictions of the read (R), write (W) and execute (X)
* (subject to their availability depending on the type of protection unit)
* operations on the memory block when the bus master is operating in
* control the access restrictions of the read (R), write (W) and execute (X)
* (subject to their availability depending on the type of protection unit)
* operations on the memory block when the bus master is operating in
* privileged mode. PPU structs do not provide execute attributes.
* - Secure/Non-secure: Applies the secure/non-secure protection settings to
* the defined memory region. Secure protection allows only bus masters that
@ -240,7 +238,7 @@
* protection context values allowed by the protection unit. E.g. If SMPU1 is
* configured to allow only PC=1 and PC=5, a bus master (such as CM4) must
* be operating at PC=1 or PC=5 when accessing the protected memory region.
*
*
* \subsection group_prot_master_struct Master Struct
*
* The master struct protects its slave struct in the protection unit. This
@ -258,10 +256,10 @@
*
* \subsubsection group_prot_master_attr Master Struct Attribute Definition
*
* - User Permission: Only the write (W) access attribute is allowed for
* - User Permission: Only the write (W) access attribute is allowed for
* master structs, which controls whether a bus master operating in user
* mode has the write access.
* - Privileged Permission: Only the write (W) access attribute is allowed for
* - Privileged Permission: Only the write (W) access attribute is allowed for
* master structs, which controls whether a bus master operating in privileged
* mode has the write access.
* - Secure/Non-Secure: Same behavior as slave struct.
@ -286,15 +284,15 @@
* the protected memory.
*
* For example, by configuring the CM0+ bus master configuration to allow
* only protection contexts 2 and 3, the bus master will be able to
* set its protection context only to 2 or 3. During runtime, the CM0+ core
* can set its protection context to 2 by calling Cy_Prot_SetActivePC()
* only protection contexts 2 and 3, the bus master will be able to
* set its protection context only to 2 or 3. During runtime, the CM0+ core
* can set its protection context to 2 by calling Cy_Prot_SetActivePC()
* and access all regions of protected memory that allow PC=2. A fault will
* be triggered if a resource is protected with different protection settings.
*
* Note that each protection unit is distinguished by its type (e.g.
* Note that each protection unit is distinguished by its type (e.g.
* PROT_MPU_MPU_STRUCT_Type). The list of supported protection units can be
* obtained from the device definition header file. Choose a protection unit
* obtained from the device definition header file. Choose a protection unit
* of interest, and call its corresponding Cy_Prot_Config<X>Struct() function
* with its software protection unit configuration structure populated. Then
* enable the protection unit by calling the Cy_Prot_Enable<X>Struct() function.
@ -307,17 +305,17 @@
* When a resource (memory/register) is accessed, it must pass evaluation of
* all three protection unit categories in the following order: MPU->SMPU->PPU.
* The application should ensure that a denial-of-service attack cannot be
* made on the PPU by the SMPU. For this reason, it is recommended that the
* made on the PPU by the SMPU. For this reason, it is recommended that the
* application's security policy limit the ability for the non-secure client
* from configuring the SMPUs.
*
*
* Within each category, the priority hierarchy must be carefully considered
* to ensure that a higher priority protection unit cannot be configured to
* override the security configuration of a lower index protection unit.
* Therefore if a lower index protection unit is configured, relevant higher
* priority indexes should be configured (or protected from unwanted
* priority indexes should be configured (or protected from unwanted
* reconfiguration). E.g. If a PPU_SL is configured, PPU_RG and PPU_GR that
* overlaps with the protected registers should also be configured. SImilar
* overlaps with the protected registers should also be configured. SImilar
* to SMPUs, it is recommended that the configuration of PPU_PROG be limited.
* Otherwise they can be used to override the protection settings of PPU_RG
* and PPU_SL structs.
@ -329,8 +327,8 @@
* exception entry in the CPUSS.CM0_PC0_HANDLER register.
*
* - SMPU 15 and 14 are configured and enabled to only allow PC=0 accesses at
* device boot.
* - PROG PPU 15, 14, 13 and 12 are configured to only allow PC=0 accesses at
* device boot.
* - PROG PPU 15, 14, 13 and 12 are configured to only allow PC=0 accesses at
* device boot.
* - GR PPU 0 and 2 are configured to only allow PC=0 accesses at device boot.
*
@ -347,7 +345,7 @@
* <tr>
* <td rowspan="2">1.10</td>
* <td>Added input parameter validation to the API functions.<br>
* cy_en_prot_pcmask_t, cy_en_prot_subreg_t and cy_en_prot_pc_t
* cy_en_prot_pcmask_t, cy_en_prot_subreg_t and cy_en_prot_pc_t
* types are set to typedef enum</td>
* <td>Improved debugging capability</td>
* </tr>
@ -412,7 +410,7 @@ extern "C" {
/**
* Prot Driver error codes
*/
typedef enum
typedef enum
{
CY_PROT_SUCCESS = 0x00u, /**< Returned successful */
CY_PROT_BAD_PARAM = CY_PROT_ID | CY_PDL_STATUS_ERROR | 0x01u, /**< Bad parameter was passed */
@ -422,7 +420,7 @@ typedef enum
/**
* User/Privileged permission
*/
typedef enum
typedef enum
{
CY_PROT_PERM_DISABLED = 0x00u, /**< Read, Write and Execute disabled */
CY_PROT_PERM_R = 0x01u, /**< Read enabled */
@ -437,7 +435,7 @@ typedef enum
/**
* Memory region size
*/
typedef enum
typedef enum
{
CY_PROT_SIZE_256B = 7u, /**< 256 bytes */
CY_PROT_SIZE_512B = 8u, /**< 512 bytes */
@ -504,7 +502,7 @@ enum cy_en_prot_subreg_t
};
/**
* Protection context mask (PC_MASK)
* Protection context mask (PC_MASK)
*/
enum cy_en_prot_pcmask_t
{
@ -715,7 +713,7 @@ enum cy_en_prot_pcmask_t
*/
/** Configuration structure for MPU Struct initialization */
typedef struct
typedef struct
{
uint32_t* address; /**< Base address of the memory region */
cy_en_prot_size_t regionSize; /**< Size of the memory region */
@ -726,7 +724,7 @@ typedef struct
} cy_stc_mpu_cfg_t;
/** Configuration structure for SMPU struct initialization */
typedef struct
typedef struct
{
uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */
cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */
@ -739,7 +737,7 @@ typedef struct
} cy_stc_smpu_cfg_t;
/** Configuration structure for Programmable (PROG) PPU (PPU_PR) struct initialization */
typedef struct
typedef struct
{
uint32_t* address; /**< Base address of the memory region (Only applicable to slave) */
cy_en_prot_size_t regionSize; /**< Size of the memory region (Only applicable to slave) */
@ -752,7 +750,7 @@ typedef struct
} cy_stc_ppu_prog_cfg_t;
/** Configuration structure for Fixed Group (GR) PPU (PPU_GR) struct initialization */
typedef struct
typedef struct
{
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
@ -762,7 +760,7 @@ typedef struct
} cy_stc_ppu_gr_cfg_t;
/** Configuration structure for Fixed Slave (SL) PPU (PPU_SL) struct initialization */
typedef struct
typedef struct
{
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */
@ -772,7 +770,7 @@ typedef struct
} cy_stc_ppu_sl_cfg_t;
/** Configuration structure for Fixed Region (RG) PPU (PPU_RG) struct initialization */
typedef struct
typedef struct
{
cy_en_prot_perm_t userPermission; /**< User permissions for the region */
cy_en_prot_perm_t privPermission; /**< Privileged permissions for the region */

385
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/rtc/cy_rtc.c
View File

File diff suppressed because it is too large Load Diff

348
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/rtc/cy_rtc.h
View File

@ -2,15 +2,13 @@
* \file cy_rtc.h
* \version 2.10
*
* This file provides constants and parameter values for the APIs for the
* This file provides constants and parameter values for the APIs for the
* Real-Time Clock (RTC).
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*
*******************************************************************************/
@ -18,13 +16,13 @@
* \defgroup group_rtc Real-Time Clock (RTC)
* \{
*
* The Real-time Clock (RTC) driver provides an application interface
* The Real-time Clock (RTC) driver provides an application interface
* for keeping track of time and date.
*
* Use the RTC driver when the system requires the current time or date. You
* can also use the RTC when you do not need the current time and date but you
* Use the RTC driver when the system requires the current time or date. You
* can also use the RTC when you do not need the current time and date but you
* do need accurate timing of events with one-second resolution.
*
*
* The RTC driver provides these features: <br>
* * Different hour format support <br>
* * Multiple alarm function (two-alarms) <br>
@ -32,122 +30,122 @@
* * Automatic leap year compensation <br>
* * Option to drive the RTC by an external 50 Hz or 60 Hz clock source
*
* The RTC driver provides access to the HW real-time clock. The HW RTC is
* located in the Backup domain. You need to choose the clock source for the
* Backup domain using the Cy_SysClk_ClkBakSetSource() function. If the clock
* for the Backup domain is set and enabled, the RTC automatically
* The RTC driver provides access to the HW real-time clock. The HW RTC is
* located in the Backup domain. You need to choose the clock source for the
* Backup domain using the Cy_SysClk_ClkBakSetSource() function. If the clock
* for the Backup domain is set and enabled, the RTC automatically
* starts counting.
*
* The RTC driver keeps track of second, minute, hour, day of the week, day of
* The RTC driver keeps track of second, minute, hour, day of the week, day of
* the month, month, and year.
*
* DST may be enabled and supports any start and end date. The start and end
* dates can be a fixed date (like 24 March) or a relative date (like the
* DST may be enabled and supports any start and end date. The start and end
* dates can be a fixed date (like 24 March) or a relative date (like the
* second Sunday in March).
*
* The RTC has two alarms that you can configure to generate an interrupt.
* The RTC has two alarms that you can configure to generate an interrupt.
* You specify the match value for the time when you want the alarm to occur.
* Your interrupt handler then handles the response. The alarm flexibility
* supports periodic alarms (such as every minute), or a single alarm
* Your interrupt handler then handles the response. The alarm flexibility
* supports periodic alarms (such as every minute), or a single alarm
* (13:45 on 28 September, 2043).
*
* <b> Clock Source </b> <br>
* The Backup domain can be driven by: <br>
* * Watch-crystal oscillator (WCO). This is a high-accuracy oscillator that is
* suitable for RTC applications and requires a 32.768 kHz external crystal
* populated on the application board. The WCO can be supplied by vddbak and
* suitable for RTC applications and requires a 32.768 kHz external crystal
* populated on the application board. The WCO can be supplied by vddbak and
* therefore can run without vddd/vccd present. This can be used to wake the chip
* from Hibernate mode.
*
* * The Internal Low-speed Oscillator (ILO) routed from Clk_LF or directly
* (as alternate backup domain clock source). Depending on the device power
* mode the alternate backup domain clock source is set. For example, for
* * The Internal Low-speed Oscillator (ILO) routed from Clk_LF or directly
* (as alternate backup domain clock source). Depending on the device power
* mode the alternate backup domain clock source is set. For example, for
* DeepSleep mode the ILO is routed through Clk_LF. But for Hibernate
* power mode the ILO is set directly. Note that, the ILO should be configured to
* work in the Hibernate mode. For more info refer to the \ref group_sysclk
* driver. The ILO is a low-accuracy RC-oscillator that does not require
* any external elements on the board. Its poor accuracy (+/- 30%) means it is
* any external elements on the board. Its poor accuracy (+/- 30%) means it is
* less useful for the RTC. However, current can be supplied by an internal
* power supply (Vback) and therefore it can run without Vddd/Vccd present.
* This also can be used to wake the chip from Hibernate mode using RTC alarm
* This also can be used to wake the chip from Hibernate mode using RTC alarm
* interrupt. For more details refer to Power Modes (syspm) driver description.
*
* * The Precision Internal Low-speed Oscillator (PILO), routed from Clk_LF
* * The Precision Internal Low-speed Oscillator (PILO), routed from Clk_LF
* (alternate backup domain clock source). This is an RC-oscillator (ILO) that
* can achieve accuracy of +/- 2% with periodic calibration. It is not expected
* to be accurate enough for good RTC capability. The PILO requires
* Vddd/Vccd present. It can be used in modes down to DeepSleep, but ceases to
* can achieve accuracy of +/- 2% with periodic calibration. It is not expected
* to be accurate enough for good RTC capability. The PILO requires
* Vddd/Vccd present. It can be used in modes down to DeepSleep, but ceases to
* function in Hibernate mode.
*
* * External 50 Hz or 60 Hz sine-wave clock source or 32.768kHz square clock
* * External 50 Hz or 60 Hz sine-wave clock source or 32.768kHz square clock
* source.
* For example, the wall AC frequency can be the clock source. Such a clock
* For example, the wall AC frequency can be the clock source. Such a clock
* source can be used if the external 32.768 kHz WCO is absent from the board.
* For more details, refer to the Cy_RTC_SelectFrequencyPrescaler() function
* For more details, refer to the Cy_RTC_SelectFrequencyPrescaler() function
* description.
*
* The WCO is the recommended clock source for the RTC, if it is present
* in design. For setting the Backup domain clock source, refer to the
* The WCO is the recommended clock source for the RTC, if it is present
* in design. For setting the Backup domain clock source, refer to the
* \ref group_sysclk driver.
*
* \note If the WCO is enabled, it should source the Backup domain directly.
* Do not route the WCO through the Clk_LF. This is because Clk_LF is not
* \note If the WCO is enabled, it should source the Backup domain directly.
* Do not route the WCO through the Clk_LF. This is because Clk_LF is not
* available in all low-power modes.
*
* \section group_rtc_section_configuration Configuration Considerations
*
* Before RTC set up, ensure that the Backup domain is clocked with the desired
* Before RTC set up, ensure that the Backup domain is clocked with the desired
* clock source.
*
* To set up an RTC, provide the configuration parameters in the
* cy_stc_rtc_config_t structure. Then call Cy_RTC_Init(). You can also set the
* date and time at runtime. Call Cy_RTC_SetDateAndTime() using the filled
* cy_stc_rtc_config_t structure, or call Cy_RTC_SetDateAndTimeDirect() with
* valid time and date values.
* To set up an RTC, provide the configuration parameters in the
* cy_stc_rtc_config_t structure. Then call Cy_RTC_Init(). You can also set the
* date and time at runtime. Call Cy_RTC_SetDateAndTime() using the filled
* cy_stc_rtc_config_t structure, or call Cy_RTC_SetDateAndTimeDirect() with
* valid time and date values.
*
* <b> RTC Interrupt Handling </b> <br>
* The RTC driver provides three interrupt handler functions:
* Cy_RTC_Alarm1Interrupt(), Cy_RTC_Alarm2Interrupt(), and
* Cy_RTC_CenturyInterrupt(). All three functions are blank functions with
* The RTC driver provides three interrupt handler functions:
* Cy_RTC_Alarm1Interrupt(), Cy_RTC_Alarm2Interrupt(), and
* Cy_RTC_CenturyInterrupt(). All three functions are blank functions with
* the WEAK attribute. For any interrupt you use, redefine the interrupt handler
* in your source code.
*
* When an interrupt occurs, call the Cy_RTC_Interrupt() function. The RTC
* hardware provides a single interrupt line to the NVIC for the three RTC
* interrupts. This function checks the interrupt register to determine which
* interrupt (out of the three) was generated. It then calls the
* When an interrupt occurs, call the Cy_RTC_Interrupt() function. The RTC
* hardware provides a single interrupt line to the NVIC for the three RTC
* interrupts. This function checks the interrupt register to determine which
* interrupt (out of the three) was generated. It then calls the
* appropriate handler.
*
* \warning The Cy_RTC_Alarm2Interrupt() is not called if the DST feature is
* enabled. If DST is enabled, the Cy_RTC_Interrupt() function redirects that
* \warning The Cy_RTC_Alarm2Interrupt() is not called if the DST feature is
* enabled. If DST is enabled, the Cy_RTC_Interrupt() function redirects that
* interrupt to manage daylight savings time using Cy_RTC_DstInterrupt().
* In general, the RTC interrupt handler function the Cy_RTC_DstInterrupt()
* In general, the RTC interrupt handler function the Cy_RTC_DstInterrupt()
* function is called instead of Cy_RTC_Alarm2Interrupt().
*
* For RTC interrupt handling, the user should: <br>
* 1) Implement strong interrupt handling function(s) for the required events
* (see above). If DST is enabled, then Alarm2 is not available. The DST handler
* 1) Implement strong interrupt handling function(s) for the required events
* (see above). If DST is enabled, then Alarm2 is not available. The DST handler
* is built into the PDL.<br>
* 2) Implement an RTC interrupt handler and call Cy_RTC_Interrupt()
* 2) Implement an RTC interrupt handler and call Cy_RTC_Interrupt()
* from there<br>
* 3) Configure the RTC interrupt: <br>
* a) Set the mask for RTC required interrupt using
* a) Set the mask for RTC required interrupt using
* Cy_RTC_SetInterruptMask()<br>
* b) Initialize the RTC interrupt by setting priority and the RTC interrupt
* b) Initialize the RTC interrupt by setting priority and the RTC interrupt
* vector using the Cy_SysInt_Init() function <br>
* c) Enable the RTC interrupt using the CMSIS core function NVIC_EnableIRQ().
*
* <b> Alarm functionality </b> <br>
* To set up an alarm, enable the required RTC interrupt. Then provide the
* configuration parameters in the cy_stc_rtc_alarm_t structure. You enable
* any item you want matched, and provide a match value. You disable any other.
* You do not need to set match values for disabled elements, as they are
* ignored.
* \note The alarm itself must be enabled in this structure. When a match
* To set up an alarm, enable the required RTC interrupt. Then provide the
* configuration parameters in the cy_stc_rtc_alarm_t structure. You enable
* any item you want matched, and provide a match value. You disable any other.
* You do not need to set match values for disabled elements, as they are
* ignored.
* \note The alarm itself must be enabled in this structure. When a match
* occurs, the alarm is triggered and your interrupt handler is called.
*
* An example is the best way to explain how this works. If you want an alarm
* on every hour, then in the cy_stc_rtc_alarm_t structure, you provide
* An example is the best way to explain how this works. If you want an alarm
* on every hour, then in the cy_stc_rtc_alarm_t structure, you provide
* these values:
*
* Alarm_1.sec = 0u <br>
@ -159,42 +157,42 @@
* Alarm_1.dateEn = CY_RTC_ALARM_DISABLE <br>
* Alarm_1.monthEn = CY_RTC_ALARM_DISABLE <br>
* Alarm_1.almEn = CY_RTC_ALARM_ENABLE <br>
*
* With this setup, every time both the second and minute are zero, Alarm1 is
* asserted. That happens once per hour. Note that, counterintuitively, to have
* an alarm every hour, Alarm_1.hourEn is disabled. This is disabled because
*
* With this setup, every time both the second and minute are zero, Alarm1 is
* asserted. That happens once per hour. Note that, counterintuitively, to have
* an alarm every hour, Alarm_1.hourEn is disabled. This is disabled because
* for an hourly alarm you do not match the value of the hour.
*
* After cy_stc_rtc_alarm_t structure is filled, call the
* Cy_RTC_SetAlarmDateAndTime(). The alarm can also be set without using the
* cy_stc_rtc_alarm_t structure. Call Cy_RTC_SetAlarmDateAndTimeDirect() with
* After cy_stc_rtc_alarm_t structure is filled, call the
* Cy_RTC_SetAlarmDateAndTime(). The alarm can also be set without using the
* cy_stc_rtc_alarm_t structure. Call Cy_RTC_SetAlarmDateAndTimeDirect() with
* valid values.
*
* <b> The DST Feature </b> <br>
* The DST feature is managed by the PDL using the RTC Alarm2 interrupt.
* Therefore, you cannot have both DST enabled and use the Alarm2 interrupt.
* The DST feature is managed by the PDL using the RTC Alarm2 interrupt.
* Therefore, you cannot have both DST enabled and use the Alarm2 interrupt.
*
* To set up the DST, route the RTC interrupt to NVIC:<br>
* 1) Initialize the RTC interrupt by setting priority and the RTC interrupt
* 1) Initialize the RTC interrupt by setting priority and the RTC interrupt
* vector using Cy_SysInt_Init() <br>
* 2) Enable the RTC interrupt using the CMSIS core function NVIC_EnableIRQ().
*
* After this, provide the configuration parameters in the
* cy_stc_rtc_dst_t structure. This structure consists of two
* cy_stc_rtc_dst_format_t structures, one for DST Start time and one for
*
* After this, provide the configuration parameters in the
* cy_stc_rtc_dst_t structure. This structure consists of two
* cy_stc_rtc_dst_format_t structures, one for DST Start time and one for
* DST Stop time. You also specify whether these times are absolute or relative.
*
* After the cy_stc_rtc_dst_t structure is filled, call Cy_RTC_EnableDstTime()
*
* After the cy_stc_rtc_dst_t structure is filled, call Cy_RTC_EnableDstTime()
*
* \section group_rtc_lp Low Power Support
* The RTC provides the callback functions to facilitate
* the low-power mode transition. The callback
* \ref Cy_RTC_DeepSleepCallback must be called during execution
* of \ref Cy_SysPm_DeepSleep; \ref Cy_RTC_HibernateCallback must be
* called during execution of \ref Cy_SysPm_Hibernate.
* To trigger the callback execution, the callback must be registered
* before calling the mode transition function.
* Refer to \ref group_syspm driver for more
* The RTC provides the callback functions to facilitate
* the low-power mode transition. The callback
* \ref Cy_RTC_DeepSleepCallback must be called during execution
* of \ref Cy_SysPm_DeepSleep; \ref Cy_RTC_HibernateCallback must be
* called during execution of \ref Cy_SysPm_Hibernate.
* To trigger the callback execution, the callback must be registered
* before calling the mode transition function.
* Refer to \ref group_syspm driver for more
* information about low-power mode transitions.
*
* \section group_rtc_section_more_information More Information
@ -216,14 +214,14 @@
* <td>The object addressed by the pointer parameter '%s' is not modified and
* so the pointer could be of type 'pointer to const'.</td>
* <td>
* The pointer parameter is not used or modified, as there is no need
* to do any actions with it. However, such parameter is
* required to be presented in the function, because the
* \ref Cy_RTC_DeepSleepCallback and \ref Cy_RTC_HibernateCallback are
* The pointer parameter is not used or modified, as there is no need
* to do any actions with it. However, such parameter is
* required to be presented in the function, because the
* \ref Cy_RTC_DeepSleepCallback and \ref Cy_RTC_HibernateCallback are
* callbacks of \ref cy_en_syspm_status_t type.
* The SysPm driver callback function type requires implementing the
* The SysPm driver callback function type requires implementing the
* function with the next parameter and return value: <br>
* cy_en_syspm_status_t (*Cy_SysPmCallback)
* cy_en_syspm_status_t (*Cy_SysPmCallback)
* (cy_stc_syspm_callback_params_t *callbackParams);
* </td>
* </tr>
@ -238,9 +236,9 @@
* function <br>
* Corrected internal macro <br>
* Documentation updates</td>
* <td> Incorrect behavior of \ref Cy_RTC_SetDateAndTimeDirect() and
* <td> Incorrect behavior of \ref Cy_RTC_SetDateAndTimeDirect() and
* \ref Cy_RTC_SetNextDstTime() work in debug mode <br>
* Debug assert correction in \ref Cy_RTC_ConvertDayOfWeek,
* Debug assert correction in \ref Cy_RTC_ConvertDayOfWeek,
* \ref Cy_RTC_IsLeapYear, \ref Cy_RTC_DaysInMonth </td>
* </tr>
* <tr>
@ -249,7 +247,7 @@
* * Added input parameter(s) validation to all public functions. <br>
* * Removed "Cy_RTC_" prefixes from the internal functions names. <br>
* * Renamed the elements in the cy_stc_rtc_alarm structure. <br>
* * Changed the type of elements with limited set of values, from
* * Changed the type of elements with limited set of values, from
* uint32_t to enumeration.
* </td>
* <td></td>
@ -344,28 +342,28 @@ typedef enum cy_en_rtc_alarm
} cy_en_rtc_alarm_t;
/** This enumeration is used to set/get hours format */
typedef enum
typedef enum
{
CY_RTC_24_HOURS, /**< The 24 hour format */
CY_RTC_12_HOURS /**< The 12 hour (AM/PM) format */
} cy_en_rtc_hours_format_t;
/** Enumeration to configure the RTC Write register */
typedef enum
typedef enum
{
CY_RTC_WRITE_DISABLED, /**< Writing the RTC is disabled */
CY_RTC_WRITE_ENABLED /**< Writing the RTC is enabled */
} cy_en_rtc_write_status_t;
/** Enumeration used to set/get DST format */
typedef enum
typedef enum
{
CY_RTC_DST_RELATIVE, /**< Relative DST format */
CY_RTC_DST_FIXED /**< Fixed DST format */
} cy_en_rtc_dst_format_t;
/** Enumeration to indicate the AM/PM period of day */
typedef enum
typedef enum
{
CY_RTC_AM, /**< AM period of day */
CY_RTC_PM /**< PM period of day */
@ -390,7 +388,7 @@ typedef enum
*/
/**
* This is the data structure that is used to configure the rtc time
* This is the data structure that is used to configure the rtc time
* and date values.
*/
typedef struct cy_stc_rtc_config
@ -399,14 +397,14 @@ typedef struct cy_stc_rtc_config
uint32_t sec; /**< Seconds value, range [0-59] */
uint32_t min; /**< Minutes value, range [0-59] */
uint32_t hour; /**< Hour, range depends on hrFormat, if hrFormat = CY_RTC_24_HOURS, range [0-23];
If hrFormat = CY_RTC_12_HOURS, range [1-12] and appropriate AM/PM day
If hrFormat = CY_RTC_12_HOURS, range [1-12] and appropriate AM/PM day
period should be set (amPm) */
cy_en_rtc_am_pm_t amPm; /**< AM/PM hour period, see \ref cy_en_rtc_am_pm_t.
This element is actual when hrFormat = CY_RTC_12_HOURS. The firmware
This element is actual when hrFormat = CY_RTC_12_HOURS. The firmware
ignores this element if hrFormat = CY_RTC_24_HOURS */
cy_en_rtc_hours_format_t hrFormat; /**< Hours format, see \ref cy_en_rtc_hours_format_t */
uint32_t dayOfWeek; /**< Day of the week, range [1-7], see \ref group_rtc_day_of_the_week */
/* Date information */
uint32_t date; /**< Date of month, range [1-31] */
uint32_t month; /**< Month, range [1-12]. See \ref group_rtc_month */
@ -417,34 +415,34 @@ typedef struct cy_stc_rtc_config
typedef struct cy_stc_rtc_alarm
{
/* Alarm time information */
uint32_t sec; /**< Alarm seconds, range [0-59].
The appropriate ALARMX interrupt is be asserted on matching with this
uint32_t sec; /**< Alarm seconds, range [0-59].
The appropriate ALARMX interrupt is be asserted on matching with this
value if secEn is previous enabled (secEn = 1) */
cy_en_rtc_alarm_enable_t secEn; /**< Enable alarm on seconds matching, see \ref cy_en_rtc_alarm_enable_t. */
uint32_t min; /**< Alarm minutes, range [0-59].
uint32_t min; /**< Alarm minutes, range [0-59].
The appropriate ALARMX interrupt is be asserted on matching with this
value if minEn is previous enabled (minEn = 1) */
cy_en_rtc_alarm_enable_t minEn; /**< Enable alarm on minutes matching, see \ref cy_en_rtc_alarm_enable_t. */
uint32_t hour; /**< Alarm hours, range [0-23]
The appropriate ALARMX interrupt is be asserted on matching with this
The appropriate ALARMX interrupt is be asserted on matching with this
value if hourEn is previous enabled (hourEn = 1) */
cy_en_rtc_alarm_enable_t hourEn; /**< Enable alarm on hours matching, see \ref cy_en_rtc_alarm_enable_t. */
uint32_t dayOfWeek; /**< Alarm day of the week, range [1-7]
The appropriate ALARMX interrupt is be asserted on matching with this
value if dayOfWeek is previous enabled (dayOfWeekEn = 1) */
cy_en_rtc_alarm_enable_t dayOfWeekEn; /**< Enable alarm on day of the week matching,
cy_en_rtc_alarm_enable_t dayOfWeekEn; /**< Enable alarm on day of the week matching,
see \ref cy_en_rtc_alarm_enable_t */
/* Alarm date information */
uint32_t date; /**< Alarm date, range [1-31].
The appropriate ALARMX interrupt is be asserted on matching with this
uint32_t date; /**< Alarm date, range [1-31].
The appropriate ALARMX interrupt is be asserted on matching with this
value if dateEn is previous enabled (dateEn = 1) */
cy_en_rtc_alarm_enable_t dateEn; /**< Enable alarm on date matching, see \ref cy_en_rtc_alarm_enable_t. */
uint32_t month; /**< Alarm Month, range [1-12].
uint32_t month; /**< Alarm Month, range [1-12].
The appropriate ALARMX interrupt is be asserted on matching with this
value if dateEn is previous enabled (dateEn = 1) */
cy_en_rtc_alarm_enable_t monthEn; /**< Enable alarm on month matching, see \ref cy_en_rtc_alarm_enable_t. */
@ -461,21 +459,21 @@ typedef struct cy_stc_rtc_alarm
*/
typedef struct
{
cy_en_rtc_dst_format_t format; /**< DST format. See /ref cy_en_rtc_dst_format_t.
cy_en_rtc_dst_format_t format; /**< DST format. See /ref cy_en_rtc_dst_format_t.
Based on this value other structure elements
should be filled or could be ignored */
uint32_t hour; /**< Should be filled for both format types.
Hour is always presented in 24hour format, range[0-23] */
uint32_t dayOfMonth; /**< Day of Month, range[1-31]. This element should be filled if
uint32_t dayOfMonth; /**< Day of Month, range[1-31]. This element should be filled if
format = CY_RTC_DST_FIXED. Firmware calculates this value in condition that
format = CY_RTC_DST_RELATIVE is selected */
uint32_t weekOfMonth; /**< Week of month, range[1-6]. This element should be filled if
uint32_t weekOfMonth; /**< Week of month, range[1-6]. This element should be filled if
format = CY_RTC_DST_RELATIVE.
Firmware calculates dayOfMonth value based on weekOfMonth
Firmware calculates dayOfMonth value based on weekOfMonth
and dayOfWeek values */
uint32_t dayOfWeek; /**< Day of the week, this element should be filled in condition that
format = CY_RTC_DST_RELATIVE. Range[1- 7],
see \ref group_rtc_day_of_the_week. Firmware calculates dayOfMonth value
uint32_t dayOfWeek; /**< Day of the week, this element should be filled in condition that
format = CY_RTC_DST_RELATIVE. Range[1- 7],
see \ref group_rtc_day_of_the_week. Firmware calculates dayOfMonth value
based on dayOfWeek and weekOfMonth values */
uint32_t month; /**< Month value, range[1-12], see \ref group_rtc_month.
This value should be filled for both format types */
@ -507,7 +505,7 @@ typedef struct
cy_en_rtc_status_t Cy_RTC_Init(cy_stc_rtc_config_t const *config);
cy_en_rtc_status_t Cy_RTC_SetDateAndTime(cy_stc_rtc_config_t const *dateTime);
void Cy_RTC_GetDateAndTime(cy_stc_rtc_config_t *dateTime);
cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour,
cy_en_rtc_status_t Cy_RTC_SetDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour,
uint32_t date, uint32_t month, uint32_t year);
cy_en_rtc_status_t Cy_RTC_SetHoursFormat(cy_en_rtc_hours_format_t hoursFormat);
void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel);
@ -519,7 +517,7 @@ void Cy_RTC_SelectFrequencyPrescaler(cy_en_rtc_clock_freq_t clkSel);
*/
cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTime(cy_stc_rtc_alarm_t const *alarmDateTime, cy_en_rtc_alarm_t alarmIndex);
void Cy_RTC_GetAlarmDateAndTime(cy_stc_rtc_alarm_t *alarmDateTime, cy_en_rtc_alarm_t alarmIndex);
cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour,
cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, uint32_t hour,
uint32_t date, uint32_t month, cy_en_rtc_alarm_t alarmIndex);
/** \} group_rtc_alarm_functions */
@ -673,7 +671,7 @@ __STATIC_INLINE void Cy_RTC_SyncToRtcAhbAlarm(uint32_t alarmTimeBcd, uint32_t al
/**
* \defgroup group_rtc_busy_status RTC Status definitions
* \{
* Definitions for indicating the RTC BUSY bit
* Definitions for indicating the RTC BUSY bit
*/
#define CY_RTC_BUSY (1UL) /**< RTC Busy bit is set, RTC is pending */
#define CY_RTC_AVAILABLE (0UL) /**< RTC Busy bit is cleared, RTC is available */
@ -793,7 +791,7 @@ extern uint8_t const cy_RTC_daysInMonthTbl[CY_RTC_MONTHS_PER_YEAR];
/* Internal macro to validate RTC day of the week parameter */
#define CY_RTC_IS_DOW_VALID(dayOfWeek) (((dayOfWeek) > 0U) && ((dayOfWeek) <= CY_RTC_DAYS_PER_WEEK))
/* Internal macro to validate RTC day parameter */
#define CY_RTC_IS_DAY_VALID(day) (((day) > 0U) && ((day) <= CY_RTC_MAX_DAYS_IN_MONTH))
@ -831,9 +829,9 @@ extern uint8_t const cy_RTC_daysInMonthTbl[CY_RTC_MONTHS_PER_YEAR];
*
* Returns a day of the week for a year, month, and day of month that are passed
* through parameters. Zeller's congruence is used to calculate the day of
* the week.
* RTC HW block does not provide the converting function for day of week. This
* function should be called before Cy_RTC_SetDateAndTime() to get the day of
* the week.
* RTC HW block does not provide the converting function for day of week. This
* function should be called before Cy_RTC_SetDateAndTime() to get the day of
* week.
*
* For the Georgian calendar, Zeller's congruence is:
@ -868,7 +866,7 @@ __STATIC_INLINE uint32_t Cy_RTC_ConvertDayOfWeek(uint32_t day, uint32_t month, u
CY_ASSERT_L3(CY_RTC_IS_DAY_VALID(day));
CY_ASSERT_L3(CY_RTC_IS_MONTH_VALID(month));
CY_ASSERT_L3(CY_RTC_IS_YEAR_LONG_VALID(year));
/* Converts month number from regular convention
* (1=January,..., 12=December) to convention required for this
* algorithm (January and February are counted as months 13 and 14 of
@ -881,7 +879,7 @@ __STATIC_INLINE uint32_t Cy_RTC_ConvertDayOfWeek(uint32_t day, uint32_t month, u
}
/* Calculates Day of Week using Zeller's congruence algorithms */
retVal =
retVal =
(day + (((month + 1UL) * 26UL) / 10UL) + year + (year / 4UL) + (6UL * (year / 100UL)) + (year / 400UL)) % 7UL;
/* Makes correction for Saturday. Saturday number should be 7 instead of 0*/
@ -901,9 +899,9 @@ __STATIC_INLINE uint32_t Cy_RTC_ConvertDayOfWeek(uint32_t day, uint32_t month, u
* Checks whether the year passed through the parameter is leap or not.
*
* This API is for checking an invalid value input for leap year.
* RTC HW block does not provide a validation checker against time/date values,
* RTC HW block does not provide a validation checker against time/date values,
* the valid range of days in Month should be checked before SetDateAndTime()
* function call. Leap year is identified as a year that is a multiple of 4
* function call. Leap year is identified as a year that is a multiple of 4
* or 400 but not 100.
*
* \param year The year to be checked. Valid range - 2000...2100.
@ -926,7 +924,7 @@ __STATIC_INLINE bool Cy_RTC_IsLeapYear(uint32_t year)
*
* Returns a number of days in a month passed through the parameters. This API
* is for checking an invalid value input for days.
* RTC HW block does not provide a validation checker against time/date values,
* RTC HW block does not provide a validation checker against time/date values,
* the valid range of days in Month should be checked before SetDateAndTime()
* function call.
*
@ -961,11 +959,11 @@ __STATIC_INLINE uint32_t Cy_RTC_DaysInMonth(uint32_t month, uint32_t year)
* Function Name: Cy_RTC_SyncFromRtc
****************************************************************************//**
*
* The Synchronizer updates RTC values into AHB RTC user registers from the
* actual RTC. By calling this function, the actual RTC register values is
* The Synchronizer updates RTC values into AHB RTC user registers from the
* actual RTC. By calling this function, the actual RTC register values is
* copied to AHB user registers.
*
* \note Only after calling Cy_RTC_SyncFromRtc(), the RTC time values can be
* \note Only after calling Cy_RTC_SyncFromRtc(), the RTC time values can be
* read.
* After Cy_RTC_SyncFromRtc() calling the snapshot of the actual RTC registers
* are copied to the user registers. Meanwhile the RTC continues to clock.
@ -974,10 +972,10 @@ __STATIC_INLINE uint32_t Cy_RTC_DaysInMonth(uint32_t month, uint32_t year)
__STATIC_INLINE void Cy_RTC_SyncFromRtc(void)
{
uint32_t interruptState;
interruptState = Cy_SysLib_EnterCriticalSection();
/* RTC Write is possible only in the condition that CY_RTC_BUSY bit = 0
interruptState = Cy_SysLib_EnterCriticalSection();
/* RTC Write is possible only in the condition that CY_RTC_BUSY bit = 0
* or RTC Write bit is not set.
*/
if((CY_RTC_BUSY != Cy_RTC_GetSyncStatus()) && (!_FLD2BOOL(BACKUP_RTC_RW_WRITE, BACKUP->RTC_RW)))
@ -999,12 +997,12 @@ __STATIC_INLINE void Cy_RTC_SyncFromRtc(void)
* Function Name: Cy_RTC_WriteEnable
****************************************************************************//**
*
* Set/Clear writeable option for RTC user registers. When the Write bit is set,
* data can be written into the RTC user registers. After all the RTC writes are
* Set/Clear writeable option for RTC user registers. When the Write bit is set,
* data can be written into the RTC user registers. After all the RTC writes are
* done, the firmware must clear (call Cy_RTC_WriteEnable(RTC_WRITE_DISABLED))
* the Write bit for the RTC update to take effect.
* the Write bit for the RTC update to take effect.
*
* Set/Clear cannot be done if the RTC is still busy with a previous update
* Set/Clear cannot be done if the RTC is still busy with a previous update
* (CY_RTC_BUSY = 1) or RTC Reading is executing.
*
* \param writeEnable write status, see \ref cy_en_rtc_write_status_t.
@ -1022,7 +1020,7 @@ __STATIC_INLINE cy_en_rtc_status_t Cy_RTC_WriteEnable(cy_en_rtc_write_status_t w
if(writeEnable == CY_RTC_WRITE_ENABLED)
{
/* RTC Write bit set is possible only in condition that CY_RTC_BUSY bit = 0
/* RTC Write bit set is possible only in condition that CY_RTC_BUSY bit = 0
* or RTC Read bit is not set
*/
if((CY_RTC_BUSY != Cy_RTC_GetSyncStatus()) && (!_FLD2BOOL(BACKUP_RTC_RW_READ, BACKUP->RTC_RW)))
@ -1050,8 +1048,8 @@ __STATIC_INLINE cy_en_rtc_status_t Cy_RTC_WriteEnable(cy_en_rtc_write_status_t w
****************************************************************************//**
*
* Return current status of CY_RTC_BUSY. The status indicates
* synchronization between the RTC user register and the actual RTC register.
* CY_RTC_BUSY bit is set if it is synchronizing. It is not possible to set
* synchronization between the RTC user register and the actual RTC register.
* CY_RTC_BUSY bit is set if it is synchronizing. It is not possible to set
* the Read or Write bit until CY_RTC_BUSY clears.
*
* \return
@ -1060,7 +1058,7 @@ __STATIC_INLINE cy_en_rtc_status_t Cy_RTC_WriteEnable(cy_en_rtc_write_status_t w
*
*******************************************************************************/
__STATIC_INLINE uint32_t Cy_RTC_GetSyncStatus(void)
{
{
return((_FLD2BOOL(BACKUP_STATUS_RTC_BUSY, BACKUP->STATUS)) ? CY_RTC_BUSY : CY_RTC_AVAILABLE);
}
@ -1079,7 +1077,7 @@ __STATIC_INLINE uint32_t Cy_RTC_GetSyncStatus(void)
* \return
* decNum An 8-bit hexadecimal equivalent number of the BCD number.
*
* For example, for 0x11223344 BCD number, the function returns
* For example, for 0x11223344 BCD number, the function returns
* 0x2C in hexadecimal format.
*
*******************************************************************************/
@ -1087,8 +1085,8 @@ __STATIC_INLINE uint32_t Cy_RTC_ConvertBcdToDec(uint32_t bcdNum)
{
uint32_t retVal;
retVal =
((bcdNum & (CY_RTC_BCD_ONE_DIGIT_MASK << CY_RTC_BCD_NUMBER_SIZE))
retVal =
((bcdNum & (CY_RTC_BCD_ONE_DIGIT_MASK << CY_RTC_BCD_NUMBER_SIZE))
>> CY_RTC_BCD_NUMBER_SIZE ) * CY_RTC_BCD_DOZED_DEGREE;
retVal += bcdNum & CY_RTC_BCD_ONE_DIGIT_MASK;
@ -1105,14 +1103,14 @@ __STATIC_INLINE uint32_t Cy_RTC_ConvertBcdToDec(uint32_t bcdNum)
* is converted individually and returned as an individual byte in the 32-bit
* variable.
*
* \param
* \param
* decNum An 8-bit hexadecimal number. Each byte is represented in hex.
* 0x11223344 -> 0x20 hex format.
*
* \return
* bcdNum - An 8-bit BCD equivalent of the passed hexadecimal number.
*
* For example, for 0x11223344 hexadecimal number, the function returns
* For example, for 0x11223344 hexadecimal number, the function returns
* 0x20 BCD number.
*
*******************************************************************************/
@ -1159,8 +1157,8 @@ __STATIC_INLINE cy_en_rtc_hours_format_t Cy_RTC_GetHoursFormat(void)
* True if the reset reason is the power cycle and the XRES (external reset) <br>
* False if the reset reason is other than power cycle and the XRES.
*
* \note Based on a return value the RTC time and date can be updated or skipped
* after the device reset. For example, you should skip the
* \note Based on a return value the RTC time and date can be updated or skipped
* after the device reset. For example, you should skip the
* Cy_RTC_SetAlarmDateAndTime() call function if internal WDT reset occurs.
*
*******************************************************************************/
@ -1174,11 +1172,11 @@ __STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void)
* Function Name: Cy_RTC_SyncToRtcAhbDateAndTime
****************************************************************************//**
*
* This function updates new time and date into the time and date RTC AHB
* This function updates new time and date into the time and date RTC AHB
* registers.
*
* \param timeBcd
* The BCD-formatted time variable which has the same bit masks as the
* The BCD-formatted time variable which has the same bit masks as the
* RTC_TIME register: <br>
* [0:6] - Calendar seconds in BCD, the range 0-59. <br>
* [14:8] - Calendar minutes in BCD, the range 0-59. <br>
@ -1189,7 +1187,7 @@ __STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void)
* [26:24] - A calendar day of the week, the range 1 - 7, where 1 - Sunday. <br>
*
* \param dateBcd
* The BCD-formatted time variable which has the same bit masks as the
* The BCD-formatted time variable which has the same bit masks as the
* RTC_DATE register: <br>
* [5:0] - A calendar day of a month in BCD, the range 1-31. <br>
* [12:8] - A calendar month in BCD, the range 1-12. <br>
@ -1197,15 +1195,15 @@ __STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void)
*
* \note Ensure that the parameters are presented in the BCD format. Use the
* ConstructTimeDate() function to construct BCD time and date values.
* Refer to ConstructTimeDate() function description for more details
* about the RTC_TIME and RTC_DATE bit fields format.
* Refer to ConstructTimeDate() function description for more details
* about the RTC_TIME and RTC_DATE bit fields format.
*
* The RTC AHB registers can be updated only under condition that the
* Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). Call the
* Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). Call the
* Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED) and ensure that Cy_RTC_WriteEnable()
* returned CY_RTC_SUCCESS. Then you can call Cy_RTC_SyncToRtcAhbDateAndTime().
* Do not forget to clear the RTC Write bit to finish an RTC register update by
* calling Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED) after you executed
* Do not forget to clear the RTC Write bit to finish an RTC register update by
* calling Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED) after you executed
* Cy_RTC_SyncToRtcAhbDateAndTime(). Ensure that Cy_RTC_WriteEnable()
* retuned CY_RTC_SUCCESS.
*
@ -1221,17 +1219,17 @@ __STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t d
* Function Name: Cy_RTC_SyncToRtcAhbAlarm
****************************************************************************//**
*
* This function updates new alarm time and date into the alarm tire and date
* This function updates new alarm time and date into the alarm tire and date
* RTC AHB registers.
*
* \param alarmTimeBcd
* The BCD-formatted time variable which has the same bit masks as the
* The BCD-formatted time variable which has the same bit masks as the
* ALMx_TIME register time fields: <br>
* [0:6] - Alarm seconds in BCD, the range 0-59. <br>
* [7] - Alarm seconds Enable: 0 - ignore, 1 - match. <br>
* [14:8] - Alarm minutes in BCD, the range 0-59. <br>
* [15] - Alarm minutes Enable: 0 - ignore, 1 - match. <br>
* [21:16] - Alarm hours in BCD, value depending on the 12/24-hour mode
* [21:16] - Alarm hours in BCD, value depending on the 12/24-hour mode
* (RTC_CTRL_12HR) <br>
* 12HR: [21]:0 = AM, 1 = PM, [20:16] = 1 - 12; <br>
* 24HR: [21:16] = the range 0-23. <br>
@ -1240,7 +1238,7 @@ __STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t d
* [31] - An alarm day of the week Enable: 0 - ignore, 1 - match. <br>
*
* \param alarmDateBcd
* The BCD-formatted date variable which has the same bit masks as the
* The BCD-formatted date variable which has the same bit masks as the
* ALMx_DATE register date fields: <br>
* [5:0] - An alarm day of a month in BCD, the range 1-31. <br>
* [7] - An alarm day of a month Enable: 0 - ignore, 1 - match. <br>
@ -1251,17 +1249,17 @@ __STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t d
* \param alarmIndex
* The alarm index to be configured, see \ref cy_en_rtc_alarm_t.
*
* \note Ensure that the parameters are presented in the BCD format. Use the
* \note Ensure that the parameters are presented in the BCD format. Use the
* ConstructTimeDate() function to construct BCD time and date values.
* Refer to ConstructTimeDate() function description for more details
* about the RTC ALMx_TIME and ALMx_DATE bit-fields format.
* Refer to ConstructTimeDate() function description for more details
* about the RTC ALMx_TIME and ALMx_DATE bit-fields format.
*
* The RTC AHB registers can be updated only under condition that the
* Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). Call the
* Write bit is set and the RTC busy bit is cleared (RTC_BUSY = 0). Call the
* Cy_RTC_WriteEnable(CY_RTC_WRITE_ENABLED) and ensure that Cy_RTC_WriteEnable()
* returned CY_RTC_SUCCESS. Then you can call Cy_RTC_SyncToRtcAhbDateAndTime().
* Do not forget to clear the RTC Write bit to finish an RTC register update by
* calling the Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED) after you executed
* Do not forget to clear the RTC Write bit to finish an RTC register update by
* calling the Cy_RTC_WriteEnable(CY_RTC_WRITE_DISABLED) after you executed
* Cy_RTC_SyncToRtcAhbDateAndTime(). Ensure that Cy_RTC_WriteEnable()
* retuned CY_RTC_SUCCESS.
*
@ -1269,7 +1267,7 @@ __STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t d
__STATIC_INLINE void Cy_RTC_SyncToRtcAhbAlarm(uint32_t alarmTimeBcd, uint32_t alarmDateBcd, cy_en_rtc_alarm_t alarmIndex)
{
CY_ASSERT_L3(CY_RTC_IS_ALARM_IDX_VALID(alarmIndex));
if(alarmIndex != CY_RTC_ALARM_2)
{
BACKUP->ALM1_TIME = alarmTimeBcd;
@ -1279,7 +1277,7 @@ __STATIC_INLINE void Cy_RTC_SyncToRtcAhbAlarm(uint32_t alarmTimeBcd, uint32_t al
{
BACKUP->ALM2_TIME = alarmTimeBcd;
BACKUP->ALM2_DATE = alarmDateBcd;
}
}
}
#if defined(__cplusplus)

8
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sar/cy_sar.c
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_sar.h"
@ -135,7 +133,7 @@ cy_en_sar_status_t Cy_SAR_Init(SAR_Type *base, const cy_stc_sar_config_t *config
{
base->ANA_TRIM0 = CY_SAR_CAP_TRIM;
}
/* Set the REFBUF_EN bit as this is required for proper operation. */
base->CTRL = config->ctrl | SAR_CTRL_REFBUF_EN_Msk;

10
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sar/cy_sar.h
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
@ -537,8 +535,8 @@
* <td> Correct CAP_TRIM is necessary achieving specified SAR ADC linearity</td>
* </tr>
* <tr>
* <td> Turn off the entire hardware block only if the SARMUX is not enabled
* for Deep Sleep operation.
* <td> Turn off the entire hardware block only if the SARMUX is not enabled
* for Deep Sleep operation.
* </td>
* <td> Improvement of the \ref Cy_SAR_Sleep flow</td>
* </tr>

6
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_common.c
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_scb_common.h"

4
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_common.h
View File

@ -7,9 +7,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**

34
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_ezi2c.c
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_scb_ezi2c.h"
@ -210,7 +208,7 @@ void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
****************************************************************************//**
*
* This function handles the transition of the EZI2C SCB into and out of
* Deep Sleep mode. It prevents the device from entering Deep Sleep mode if
* Deep Sleep mode. It prevents the device from entering Deep Sleep mode if
* the EZI2C slave is actively communicating.
* The following behavior of the EZI2C depends on whether the SCB block is
* wakeup-capable:
@ -218,7 +216,7 @@ void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
* receives the address and stretches the clock until the device is woken from
* Deep Sleep mode. If the slave address occurs before the device enters
* Deep Sleep mode, the device will not enter Deep Sleep mode.
* * The SCB is <b>not wakeup-capable</b>: the EZI2C is disabled. It is enabled
* * The SCB is <b>not wakeup-capable</b>: the EZI2C is disabled. It is enabled
* when the device fails to enter Deep Sleep mode or it is woken from Deep Sleep
* mode. While the EZI2C is disabled, it stops driving the outputs and
* ignores the input lines. The slave NACKs all incoming addresses.
@ -240,7 +238,7 @@ void Cy_SCB_EZI2C_Disable(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *context)
* For proper operation, when the EZI2C slave is configured to be a wakeup source
* from Deep Sleep mode, this function must be copied and modified by the user.
* The EZI2C clock disable code must be inserted in the
* \ref CY_SYSPM_BEFORE_TRANSITION and clock enable code in the
* \ref CY_SYSPM_BEFORE_TRANSITION and clock enable code in the
* \ref CY_SYSPM_AFTER_TRANSITION mode processing.
*
*******************************************************************************/
@ -340,10 +338,10 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params
/* Disable SCB clock */
locBase->I2C_CFG &= (uint32_t) ~CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
/* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
* for proper entering Deep Sleep mode the I2C clock must be disabled.
* This code must be inserted by the user because the driver
/* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
* for proper entering Deep Sleep mode the I2C clock must be disabled.
* This code must be inserted by the user because the driver
* does not have access to the clock.
*/
}
@ -358,10 +356,10 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params
{
/* Enable SCB clock */
locBase->I2C_CFG |= CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
/* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
* for proper exiting Deep Sleep mode, the I2C clock must be enabled.
* This code must be inserted by the user because the driver
/* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
* for proper exiting Deep Sleep mode, the I2C clock must be enabled.
* This code must be inserted by the user because the driver
* does not have access to the clock.
*/
@ -394,7 +392,7 @@ cy_en_syspm_status_t Cy_SCB_EZI2C_DeepSleepCallback(cy_stc_syspm_callback_params
****************************************************************************//**
*
* This function handles the transition of the EZI2C SCB block into Hibernate
* mode. It prevents the device from entering Hibernate mode if the EZI2C slave
* mode. It prevents the device from entering Hibernate mode if the EZI2C slave
* is actively communicating.
* If the EZI2C is ready to enter Hibernate mode, it is disabled. If the device
* fails to enter Hibernate mode, the EZI2C is enabled. While the EZI2C
@ -761,11 +759,11 @@ void Cy_SCB_EZI2C_Interrupt(CySCB_Type *base, cy_stc_scb_ezi2c_context_t *contex
/* Handle an I2C wake-up event */
if (0UL != (CY_SCB_I2C_INTR_WAKEUP & Cy_SCB_GetI2CInterruptStatusMasked(base)))
{
/* Move from IDLE state, the slave was addressed. Following address match
/* Move from IDLE state, the slave was addressed. Following address match
* interrupt continue transfer.
*/
context->state = CY_SCB_EZI2C_STATE_ADDR;
Cy_SCB_ClearI2CInterrupt(base, CY_SCB_I2C_INTR_WAKEUP);
}

104
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_ezi2c.h
View File

@ -7,9 +7,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
@ -40,89 +38,89 @@
* at run time.
*
* \section group_scb_ezi2c_configuration Configuration Considerations
* The EZI2C slave driver configuration can be divided to number of sequential
* steps listed below:
* The EZI2C slave driver configuration can be divided to number of sequential
* steps listed below:
* * \ref group_scb_ezi2c_config
* * \ref group_scb_ezi2c_pins
* * \ref group_scb_ezi2c_clock
* * \ref group_scb_ezi2c_data_rate
* * \ref group_scb_ezi2c_intr
* * \ref group_scb_ezi2c_enable
*
* \note
* EZI2C slave driver is built on top of the SCB hardware block. The SCB3
* instance is used as an example for all code snippets. Modify the code to
*
* \note
* EZI2C slave driver is built on top of the SCB hardware block. The SCB3
* instance is used as an example for all code snippets. Modify the code to
* match your design.
*
* \subsection group_scb_ezi2c_config Configure EZI2C slave
* To set up the EZI2C slave driver, provide the configuration parameters in the
* \ref cy_stc_scb_ezi2c_config_t structure. The primary slave address
* slaveAddress1 must be provided. The other parameters are optional for
* operation. To initialize the driver, call \ref Cy_SCB_EZI2C_Init
* function providing a pointer to the filled \ref cy_stc_scb_ezi2c_config_t
* To set up the EZI2C slave driver, provide the configuration parameters in the
* \ref cy_stc_scb_ezi2c_config_t structure. The primary slave address
* slaveAddress1 must be provided. The other parameters are optional for
* operation. To initialize the driver, call \ref Cy_SCB_EZI2C_Init
* function providing a pointer to the filled \ref cy_stc_scb_ezi2c_config_t
* structure and allocated \ref cy_stc_scb_ezi2c_context_t.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG
*
* Set up the EZI2C slave buffer before enabling its
* operation by using \ref Cy_SCB_EZI2C_SetBuffer1 for the primary slave address
* Set up the EZI2C slave buffer before enabling its
* operation by using \ref Cy_SCB_EZI2C_SetBuffer1 for the primary slave address
* and \ref Cy_SCB_EZI2C_SetBuffer2 for the secondary (if the secondary is enabled).
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG_BUFFER
*
* \subsection group_scb_ezi2c_pins Assign and Configure Pins
* Only dedicated SCB pins can be used for I2C operation. The HSIOM
* register must be configured to connect the block to the pins. Also the I2C pins
* must be configured in Open-Drain, Drives Low mode (this pin configuration
* Only dedicated SCB pins can be used for I2C operation. The HSIOM
* register must be configured to connect the block to the pins. Also the I2C pins
* must be configured in Open-Drain, Drives Low mode (this pin configuration
* implies usage of external pull-up resistors):
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG_PINS
*
* \note
* The alternative pins configuration is Resistive Pull-ups which implies usage
* internal pull-up resistors. This configuration is not recommended because
* resistor value is fixed and cannot be used for all supported data rates.
* The alternative pins configuration is Resistive Pull-ups which implies usage
* internal pull-up resistors. This configuration is not recommended because
* resistor value is fixed and cannot be used for all supported data rates.
* Refer to device datasheet parameter RPULLUP for resistor value specifications.
*
* \subsection group_scb_ezi2c_clock Assign Clock Divider
* The clock source must be connected to the SCB block to oversample input and
* output signals. You must use one of the 8-bit or 16-bit dividers <em><b>(the
* source clock of this divider must be Clk_Peri)</b></em>. Use the
* The clock source must be connected to the SCB block to oversample input and
* output signals. You must use one of the 8-bit or 16-bit dividers <em><b>(the
* source clock of this divider must be Clk_Peri)</b></em>. Use the
* \ref group_sysclk driver API to do that.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG_ASSIGN_CLOCK
*
* \subsection group_scb_ezi2c_data_rate Configure Data Rate
* To get EZI2C slave to operate at the desired data rate, the source clock must be
* fast enough to provide sufficient oversampling. Therefore, the clock divider
* must be configured to provide desired clock frequency. Use the
* \ref group_sysclk driver API to do that.
* Refer to the technical reference manual (TRM) section I2C sub-section
* Oversampling and Bit Rate to get information about how to configure the I2C to run
* To get EZI2C slave to operate at the desired data rate, the source clock must be
* fast enough to provide sufficient oversampling. Therefore, the clock divider
* must be configured to provide desired clock frequency. Use the
* \ref group_sysclk driver API to do that.
* Refer to the technical reference manual (TRM) section I2C sub-section
* Oversampling and Bit Rate to get information about how to configure the I2C to run
* at the desired data rate.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_CFG_DATA_RATE
*
* \subsection group_scb_ezi2c_intr Configure Interrupt
* The interrupt is mandatory for the EZI2C slave operation.
* The \ref Cy_SCB_EZI2C_Interrupt function must be called in the interrupt
* handler for the selected SCB instance. Also, this interrupt must be enabled
* The interrupt is mandatory for the EZI2C slave operation.
* The \ref Cy_SCB_EZI2C_Interrupt function must be called in the interrupt
* handler for the selected SCB instance. Also, this interrupt must be enabled
* in the NVIC or it will not work.
*
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_INTR_A
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_INTR_B
*
* \subsection group_scb_ezi2c_enable Enable EZI2C slave
* Finally, enable the EZI2C slave operation by calling \ref Cy_SCB_EZI2C_Enable.
* Finally, enable the EZI2C slave operation by calling \ref Cy_SCB_EZI2C_Enable.
* Now the I2C device responds to the assigned address.
* \snippet SCB_CompDatasheet_sut_01_revA.cydsn\ezi2c_snippets.c EZI2C_ENABLE
*
* \section group_scb_ezi2c_use_cases Common Use Cases
* \section group_scb_ezi2c_use_cases Common Use Cases
* The EZI2C slave operation might not require calling any EZI2C slave function
* because the I2C master is able to access the slave buffer. The application
* can directly access it as well. Note that this is an application-level task
* to ensure the buffer content integrity.
*
*
* \subsection group_scb_ezi2c_master_wr Master Write operation
* This operation starts with sending a base address that is one
* or two bytes, depending on the sub-address size configuration. This base
@ -134,9 +132,9 @@
* read/write region size.\n
* When a master attempts to write outside the read/write region or past the
* end of the buffer, the last byte is NACKed.
*
*
* \image html scb_ezi2c_write.png
*
*
* \subsection group_scb_ezi2c_master_rd Master Read operation
* This operation always starts from the base address set by the most
* recent write operation. The buffer index is incremented for each read byte.
@ -150,26 +148,26 @@
*
* \image html scb_ezi2c_read.png
*
* The I2C master may use the ReStart or Stop/Start conditions to combine the
* The I2C master may use the ReStart or Stop/Start conditions to combine the
* operations. The write operation sets only the base address and the following
* read operation will start from the new base address. In cases where the base
* address remains the same, there is no need for a write operation.
* \image html scb_ezi2c_set_ba_read.png
*
* \section group_scb_ezi2c_lp Low Power Support
* The EZI2C slave provides the callback functions to handle power mode
* transition. The callback \ref Cy_SCB_EZI2C_DeepSleepCallback must be called
* during execution of \ref Cy_SysPm_DeepSleep;
* \ref Cy_SCB_EZI2C_HibernateCallback must be called during execution of
* \ref Cy_SysPm_Hibernate. To trigger the callback execution, the callback must
* be registered before calling the power mode transition function. Refer to
* \ref group_syspm driver for more information about power mode transitions and
* The EZI2C slave provides the callback functions to handle power mode
* transition. The callback \ref Cy_SCB_EZI2C_DeepSleepCallback must be called
* during execution of \ref Cy_SysPm_DeepSleep;
* \ref Cy_SCB_EZI2C_HibernateCallback must be called during execution of
* \ref Cy_SysPm_Hibernate. To trigger the callback execution, the callback must
* be registered before calling the power mode transition function. Refer to
* \ref group_syspm driver for more information about power mode transitions and
* callback registration.
*
* \note
* Only applicable for <b>rev-08 of the CY8CKIT-062-BLE</b>.
* For proper operation, when the EZI2C slave is configured to be a wakeup
* source from Deep Sleep mode, the \ref Cy_SCB_EZI2C_DeepSleepCallback must
* For proper operation, when the EZI2C slave is configured to be a wakeup
* source from Deep Sleep mode, the \ref Cy_SCB_EZI2C_DeepSleepCallback must
* be copied and modified. Refer to the function description to get the details.
*
* \section group_scb_ezi2c_more_information More Information
@ -349,10 +347,10 @@ typedef struct cy_stc_scb_ezi2c_config
} cy_stc_scb_ezi2c_config_t;
/** EZI2C slave context structure.
* All fields for the context structure are internal. Firmware never reads or
* writes these values. Firmware allocates the structure and provides the
* address of the structure to the driver in function calls. Firmware must
* ensure that the defined instance of this structure remains in scope
* All fields for the context structure are internal. Firmware never reads or
* writes these values. Firmware allocates the structure and provides the
* address of the structure to the driver in function calls. Firmware must
* ensure that the defined instance of this structure remains in scope
* while the drive is in use.
*/
typedef struct cy_stc_scb_ezi2c_context

36
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_i2c.c
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_scb_i2c.h"
@ -1219,8 +1217,8 @@ cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterRead(CySCB_Type *base,
if (CY_SCB_I2C_IDLE == context->state)
{
/* Put the address in the TX FIFO, then generate a Start condition.
* This sequence ensures that after the Start condition generation
/* Put the address in the TX FIFO, then generate a Start condition.
* This sequence ensures that after the Start condition generation
* the address is available to be sent onto the bus.
*/
Cy_SCB_WriteTxFifo(base, address);
@ -1444,8 +1442,8 @@ cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWrite(CySCB_Type *base,
if (CY_SCB_I2C_IDLE == context->state)
{
/* Put the address in the TX FIFO, then generate a Start condition.
* This sequence ensures that after the Start condition generation
/* Put the address in the TX FIFO, then generate a Start condition.
* This sequence ensures that after the Start condition generation
* the address is available to be sent onto the bus.
*/
Cy_SCB_WriteTxFifo (base, address);
@ -1464,9 +1462,9 @@ cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterWrite(CySCB_Type *base,
if (0U == context->masterBufferSize)
{
/* The address is the last byte to transfer.
* Put the address byte in the TX FIFO and clear the TX
* Underflow interrupt source inside the critical section
* to ensure that the TX Underflow interrupt will trigger
* Put the address byte in the TX FIFO and clear the TX
* Underflow interrupt source inside the critical section
* to ensure that the TX Underflow interrupt will trigger
* after the address byte is sent onto the bus.
*/
intrState = Cy_SysLib_EnterCriticalSection();
@ -1808,8 +1806,8 @@ cy_en_scb_i2c_status_t Cy_SCB_I2C_MasterSendReStart(CySCB_Type *base,
if (false == _FLD2BOOL(SCB_I2C_STATUS_M_READ, base->I2C_STATUS))
{
/* Cypress ID #295908: Wait until ReStart is generated to complete
* the previous write transfer. This ensures that the address byte
* will not be interpreted as the data byte of the previous
* the previous write transfer. This ensures that the address byte
* will not be interpreted as the data byte of the previous
* transfer.
*/
while ((0U == locStatus) &&
@ -2493,9 +2491,9 @@ static void SlaveHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t *
{
uint32_t intrStatus;
/* Put the last data byte in the TX FIFO and clear the TX Underflow
* interrupt source inside the critical section to ensure that the
* TX Underflow interrupt will trigger after all data bytes from the
/* Put the last data byte in the TX FIFO and clear the TX Underflow
* interrupt source inside the critical section to ensure that the
* TX Underflow interrupt will trigger after all data bytes from the
* TX FIFO are transferred onto the bus.
*/
intrStatus = Cy_SysLib_EnterCriticalSection();
@ -2887,9 +2885,9 @@ static void MasterHandleDataTransmit(CySCB_Type *base, cy_stc_scb_i2c_context_t
{
uint32_t intrStatus;
/* Put the last data byte in the TX FIFO and clear the TX Underflow
* interrupt source inside the critical section to ensure that the
* TX Underflow interrupt will trigger after all data bytes from the
/* Put the last data byte in the TX FIFO and clear the TX Underflow
* interrupt source inside the critical section to ensure that the
* TX Underflow interrupt will trigger after all data bytes from the
* TX FIFO are transferred onto the bus.
*/
intrStatus = Cy_SysLib_EnterCriticalSection();

22
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_i2c.h
View File

@ -7,9 +7,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
@ -305,9 +303,9 @@
* <td rowspan="4"> 2.10</td>
* <td>Fixed the ReStart condition generation sequence for a write
* transaction in the \ref Cy_SCB_I2C_MasterWrite function.</td>
* <td>The driver can notify about a zero length write transaction completion
* before the address byte is sent if the \ref Cy_SCB_I2C_MasterWrite
* function execution was interrupted between setting the restart
* <td>The driver can notify about a zero length write transaction completion
* before the address byte is sent if the \ref Cy_SCB_I2C_MasterWrite
* function execution was interrupted between setting the restart
* generation command and writing the address byte into the TX FIFO.</td>
* </tr>
* <tr>
@ -318,7 +316,7 @@
* master mode configurations.</td>
* </tr>
* <tr>
* <td>Updated the Start condition generation sequence in the \ref
* <td>Updated the Start condition generation sequence in the \ref
* Cy_SCB_I2C_MasterWrite and \ref Cy_SCB_I2C_MasterRead.</td>
* <td></td>
* </tr>
@ -329,8 +327,8 @@
* </tr>
* <tr>
* <td rowspan="5"> 2.0</td>
* <td>Fixed the \ref Cy_SCB_I2C_MasterSendReStart function to properly
* generate the ReStart condition when the previous transaction was
* <td>Fixed the \ref Cy_SCB_I2C_MasterSendReStart function to properly
* generate the ReStart condition when the previous transaction was
* a write.</td>
* <td>The master interpreted the address byte written into the TX FIFO as a
* data byte and continued a write transaction. The ReStart condition was
@ -345,10 +343,10 @@
* firmware.</td>
* <td>The observed slave operation failure depends on whether Level 2 assert
* is enabled or not. Enabled: the device stuck in the fault handler due
* to the assert assignment in the \ref Cy_SCB_I2C_Interrupt. Disabled:
* the slave sets the transaction completion status and notifies on the
* to the assert assignment in the \ref Cy_SCB_I2C_Interrupt. Disabled:
* the slave sets the transaction completion status and notifies on the
* transaction completion event after the address was NACKed. The failure
* is observed only when the slave is configured to accept an address in
* is observed only when the slave is configured to accept an address in
* the RX FIFO.</td>
* </tr>
* <tr>

56
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_spi.c
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_scb_spi.h"
@ -248,28 +246,28 @@ void Cy_SCB_SPI_Disable(CySCB_Type *base, cy_stc_scb_spi_context_t *context)
*
* This function handles the transition of the SCB SPI into and out of
* Deep Sleep mode. It prevents the device from entering Deep Sleep mode
* if the SPI slave or master is actively communicating, or there is any data
* if the SPI slave or master is actively communicating, or there is any data
* in the TX or RX FIFOs.
* The following behavior of the SPI SCB depends on whether the SCB block is
* wakeup-capable or not:
* * The SCB is <b>wakeup-capable</b>: any transfer intended to the slave wakes up
* the device from Deep Sleep mode. The slave responds with 0xFF to the transfer
* and incoming data is ignored.
* * The SCB is <b>wakeup-capable</b>: any transfer intended to the slave wakes up
* the device from Deep Sleep mode. The slave responds with 0xFF to the transfer
* and incoming data is ignored.
* If the transfer occurs before the device enters Deep Sleep mode, the device
* will not enter Deep Sleep mode and incoming data is stored in the RX FIFO.
* The SCB clock is disabled before entering Deep Sleep and enabled after the
* device exits Deep Sleep mode. The SCB clock must be enabled after exiting
* Deep Sleep mode and after the source of hf_clk[0] gets stable, this includes
* the FLL/PLL. The SysClk callback ensures that hf_clk[0] gets stable and
* it must be called before Cy_SCB_SPI_DeepSleepCallback. The SCB clock
* disabling may lead to corrupted data in the RX FIFO. Clear the RX FIFO
* after this callback is executed. If the transfer occurs before the device
* enters Deep Sleep mode, the device will not enter Deep Sleep mode and
* The SCB clock is disabled before entering Deep Sleep and enabled after the
* device exits Deep Sleep mode. The SCB clock must be enabled after exiting
* Deep Sleep mode and after the source of hf_clk[0] gets stable, this includes
* the FLL/PLL. The SysClk callback ensures that hf_clk[0] gets stable and
* it must be called before Cy_SCB_SPI_DeepSleepCallback. The SCB clock
* disabling may lead to corrupted data in the RX FIFO. Clear the RX FIFO
* after this callback is executed. If the transfer occurs before the device
* enters Deep Sleep mode, the device will not enter Deep Sleep mode and
* incoming data will be stored in the RX FIFO. \n
* Only the SPI slave can be configured to be a wakeup source from Deep Sleep
* mode.
* * The SCB is not <b>wakeup-capable</b>: the SPI is disabled. It is enabled when
* the device fails to enter Deep Sleep mode or it is awakened from Deep Sleep
* * The SCB is not <b>wakeup-capable</b>: the SPI is disabled. It is enabled when
* the device fails to enter Deep Sleep mode or it is awakened from Deep Sleep
* mode. While the SPI is disabled, it stops driving the outputs and ignores the
* inputs. Any incoming data is ignored.
*
@ -385,13 +383,13 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t
* becomes pending and prevents entering Deep Sleep mode.
*/
Cy_SCB_SetSpiInterruptMask(locBase, CY_SCB_I2C_INTR_WAKEUP);
/* Disable SCB clock */
locBase->I2C_CFG &= (uint32_t) ~CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
/* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
* for proper entering Deep Sleep mode the SPI clock must be disabled.
* This code must be inserted by the user because the driver
/* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
* for proper entering Deep Sleep mode the SPI clock must be disabled.
* This code must be inserted by the user because the driver
* does not have access to the clock.
*/
}
@ -406,13 +404,13 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t
{
/* Enable SCB clock */
locBase->I2C_CFG |= CY_SCB_I2C_CFG_CLK_ENABLE_Msk;
/* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
* for proper exiting Deep Sleep mode, the SPI clock must be enabled.
* This code must be inserted by the user because the driver
/* IMPORTANT (replace line above for the CY8CKIT-062 rev-08):
* for proper exiting Deep Sleep mode, the SPI clock must be enabled.
* This code must be inserted by the user because the driver
* does not have access to the clock.
*/
/* The SCB is wakeup-capable: disable the SPI wakeup interrupt
* source
*/
@ -441,7 +439,7 @@ cy_en_syspm_status_t Cy_SCB_SPI_DeepSleepCallback(cy_stc_syspm_callback_params_t
****************************************************************************//**
*
* This function handles the transition of the SCB SPI into Hibernate mode.
* It prevents the device from entering Hibernate mode if the SPI slave or
* It prevents the device from entering Hibernate mode if the SPI slave or
* master is actively communicating, or there is any data in the TX or RX FIFOs.
* If the SPI is ready to enter Hibernate mode, it is disabled. If the device
* failed to enter Hibernate mode, the SPI is enabled. While the SPI is

38
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_spi.h
View File

@ -7,9 +7,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
@ -184,7 +182,7 @@
* parameter to configure TX FIFO level value. \n
* <em>For example, the TX FIFO has 0 data elements (empty) and the TX FIFO level
* is 7. The TX trigger signal remains active until DMA does not load TX FIFO
* with 7 data elements (note that after the first TX load operation, the data
* with 7 data elements (note that after the first TX load operation, the data
* element goes to the shift register and TX FIFO remains empty).</em>
*
* To route SCB TX or RX trigger signals to the DMA controller, use \ref group_trigmux
@ -203,23 +201,23 @@
* callback execution, the callback must be registered before calling the
* power mode transition function. Refer to \ref group_syspm driver for more
* information about power mode transitions and callback registration.
*
* The SPI master is disabled during Deep Sleep and Hibernate and stops driving
* the output pins. The state of the SPI master output pins SCLK, SS, and MOSI is
* High-Z, which can cause unexpected behavior of the SPI Slave due to possible
* glitches on these lines. These pins must be set to the inactive state before
* entering Deep Sleep or Hibernate mode. To do that, configure the SPI master
* pins output to drive the inactive state and High-Speed Input Output
* Multiplexer (HSIOM) to control output by GPIO (use \ref group_gpio
* driver API). The pins configuration must be restored after exiting Deep Sleep
* mode to return the SPI master control of the pins (after exiting Hibernate
* mode, the system init code does the same).
* Note that the SPI master must be enabled to drive the pins during
* configuration change not to cause glitches on the lines. Copy either or
* both \ref Cy_SCB_SPI_DeepSleepCallback and \ref Cy_SCB_SPI_HibernateCallback
*
* The SPI master is disabled during Deep Sleep and Hibernate and stops driving
* the output pins. The state of the SPI master output pins SCLK, SS, and MOSI is
* High-Z, which can cause unexpected behavior of the SPI Slave due to possible
* glitches on these lines. These pins must be set to the inactive state before
* entering Deep Sleep or Hibernate mode. To do that, configure the SPI master
* pins output to drive the inactive state and High-Speed Input Output
* Multiplexer (HSIOM) to control output by GPIO (use \ref group_gpio
* driver API). The pins configuration must be restored after exiting Deep Sleep
* mode to return the SPI master control of the pins (after exiting Hibernate
* mode, the system init code does the same).
* Note that the SPI master must be enabled to drive the pins during
* configuration change not to cause glitches on the lines. Copy either or
* both \ref Cy_SCB_SPI_DeepSleepCallback and \ref Cy_SCB_SPI_HibernateCallback
* as appropriate, and make the changes described above inside the function.
* Alternately, external pull-up or pull-down resistors can be connected
* to the appropriate SPI lines to keep them inactive during Deep-Sleep or
* Alternately, external pull-up or pull-down resistors can be connected
* to the appropriate SPI lines to keep them inactive during Deep-Sleep or
* Hibernate.
*
* \note

10
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_uart.c
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_scb_uart.h"
@ -265,7 +263,7 @@ void Cy_SCB_UART_Disable(CySCB_Type *base, cy_stc_scb_uart_context_t *context)
****************************************************************************//**
*
* This function handles the transition of the SCB UART into and out of
* Deep Sleep mode. It prevents the device from entering Deep Sleep
* Deep Sleep mode. It prevents the device from entering Deep Sleep
* mode if the UART is transmitting data or has any data in the RX FIFO. If the
* UART is ready to enter Deep Sleep mode, it is disabled. The UART is enabled
* when the device fails to enter Deep Sleep mode or it is awakened from
@ -365,7 +363,7 @@ cy_en_syspm_status_t Cy_SCB_UART_DeepSleepCallback(cy_stc_syspm_callback_params_
* Function Name: Cy_SCB_UART_HibernateCallback
****************************************************************************//**
*
* This function handles the transition of the SCB UART into Hibernate mode.
* This function handles the transition of the SCB UART into Hibernate mode.
* It prevents the device from entering Hibernate mode if the UART is
* transmitting data or has any data in the RX FIFO. If the UART is ready
* to enter Hibernate mode, it is disabled. If the device fails to enter

34
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/scb/cy_scb_uart.h
View File

@ -7,9 +7,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
@ -191,7 +189,7 @@
* parameter to configure TX FIFO level value. \n
* <em>For example, the TX FIFO has 0 data elements (empty) and the TX FIFO level
* is 7. The TX trigger signal remains active until DMA does not load TX FIFO
* with 7 data elements (note that after the first TX load operation, the data
* with 7 data elements (note that after the first TX load operation, the data
* element goes to the shift register and TX FIFO remains empty).</em>
*
* To route SCB TX or RX trigger signals to DMA controller use \ref group_trigmux
@ -211,22 +209,22 @@
* power mode transition function. Refer to \ref group_syspm driver for more
* information about power mode transitions and callback registration.
*
* The UART is disabled during Deep Sleep and Hibernate and stops driving
* the output pins. The state of the UART output pins TX and RTS is High-Z,
* The UART is disabled during Deep Sleep and Hibernate and stops driving
* the output pins. The state of the UART output pins TX and RTS is High-Z,
* which can cause unexpected behavior of the UART receiver due to possible
* glitches on these lines. These pins must be set to the inactive state before
* entering Deep Sleep or Hibernate mode. To do that, configure the UART
* pins output to drive the inactive state and High-Speed Input Output
* Multiplexer (HSIOM) to control output by GPIO (use \ref group_gpio
* driver API). The pins configuration must be restored after exiting Deep Sleep
* mode to return the UART control of the pins (after exiting Hibernate mode,
* the system init code does the same).
* Note that the UART must be enabled to drive the pins during configuration
* change not to cause glitches on the lines. Copy either or both
* \ref Cy_SCB_UART_DeepSleepCallback and \ref Cy_SCB_UART_HibernateCallback as
* glitches on these lines. These pins must be set to the inactive state before
* entering Deep Sleep or Hibernate mode. To do that, configure the UART
* pins output to drive the inactive state and High-Speed Input Output
* Multiplexer (HSIOM) to control output by GPIO (use \ref group_gpio
* driver API). The pins configuration must be restored after exiting Deep Sleep
* mode to return the UART control of the pins (after exiting Hibernate mode,
* the system init code does the same).
* Note that the UART must be enabled to drive the pins during configuration
* change not to cause glitches on the lines. Copy either or both
* \ref Cy_SCB_UART_DeepSleepCallback and \ref Cy_SCB_UART_HibernateCallback as
* appropriate, and make the changes described above inside the function.
* Alternately, external pull-up or pull-down resistors can be connected
* to the appropriate UART lines to keep them inactive during Deep-Sleep or
* Alternately, external pull-up or pull-down resistors can be connected
* to the appropriate UART lines to keep them inactive during Deep-Sleep or
* Hibernate.
*
* \section group_scb_uart_more_information More Information

102
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/smif/cy_smif.c
View File

@ -10,9 +10,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_smif.h"
@ -57,7 +55,7 @@ extern "C" {
* - \ref CY_SMIF_SUCCESS
*
*******************************************************************************/
cy_en_smif_status_t Cy_SMIF_Init(SMIF_Type *base,
cy_en_smif_status_t Cy_SMIF_Init(SMIF_Type *base,
cy_stc_smif_config_t const *config,
uint32_t timeout,
cy_stc_smif_context_t *context)
@ -66,14 +64,14 @@ cy_en_smif_status_t Cy_SMIF_Init(SMIF_Type *base,
if((NULL != base) && (NULL != config) && (NULL != context))
{
/* Copy the base address of the SMIF and the SMIF Device block
* registers to the context.
/* Copy the base address of the SMIF and the SMIF Device block
* registers to the context.
*/
context->timeout = timeout;
/* Configure the initial interrupt mask */
/* Disable the TR_TX_REQ and TR_RX_REQ interrupts */
Cy_SMIF_SetInterruptMask(base, Cy_SMIF_GetInterruptMask(base)
Cy_SMIF_SetInterruptMask(base, Cy_SMIF_GetInterruptMask(base)
& ~(SMIF_INTR_TR_TX_REQ_Msk | SMIF_INTR_TR_RX_REQ_Msk));
/* Check config structure */
@ -81,7 +79,7 @@ cy_en_smif_status_t Cy_SMIF_Init(SMIF_Type *base,
CY_ASSERT_L3(CY_SMIF_CLOCK_SEL_VALID(config->rxClockSel));
CY_ASSERT_L2(CY_SMIF_DESELECT_DELAY_VALID(config->deselectDelay));
CY_ASSERT_L3(CY_SMIF_BLOCK_EVENT_VALID(config->blockEvent));
/* Configure the SMIF interface */
base->CTL = (uint32_t)(_VAL2FLD(SMIF_CTL_XIP_MODE, config->mode) |
_VAL2FLD(SMIF_CTL_CLOCK_IF_RX_SEL, config->rxClockSel) |
@ -115,8 +113,8 @@ void Cy_SMIF_DeInit(SMIF_Type *base)
{
uint32_t idx;
/* Configure the SMIF interface to default values.
* The default value is 0.
/* Configure the SMIF interface to default values.
* The default value is 0.
*/
base->CTL = CY_SMIF_CTL_REG_DEFAULT;
base->TX_DATA_FIFO_CTL = 0U;
@ -153,7 +151,7 @@ void Cy_SMIF_DeInit(SMIF_Type *base)
void Cy_SMIF_SetMode(SMIF_Type *base, cy_en_smif_mode_t mode)
{
CY_ASSERT_L3(CY_SMIF_MODE_VALID(mode));
/* Set the register SMIF.CTL.XIP_MODE = TRUE */
if (CY_SMIF_NORMAL == mode)
{
@ -223,10 +221,10 @@ void Cy_SMIF_SetDataSelect(SMIF_Type *base, cy_en_smif_slave_select_t slaveSelec
cy_en_smif_data_select_t dataSelect)
{
SMIF_DEVICE_Type volatile *device;
CY_ASSERT_L3(CY_SMIF_SLAVE_SEL_VALID(slaveSelect));
CY_ASSERT_L3(CY_SMIF_DATA_SEL_VALID(dataSelect));
/* Connect the slave to its data lines */
device = Cy_SMIF_GetDeviceBySlot(base, slaveSelect);
@ -252,7 +250,7 @@ void Cy_SMIF_SetDataSelect(SMIF_Type *base, cy_en_smif_slave_select_t slaveSelec
* transmission. This function sets up the slave lines for the rest of the
* command structure. The \ref Cy_SMIF_TransmitCommand is called before \ref
* Cy_SMIF_TransmitData or \ref Cy_SMIF_ReceiveData is called. When enabled, the
* cmpltTxfr parameter in the function will de-assert the slave select line at
* cmpltTxfr parameter in the function will de-assert the slave select line at
* the end of the function execution.
*
* \note This function blocks until all the command and associated parameters
@ -310,7 +308,7 @@ cy_en_smif_status_t Cy_SMIF_TransmitCommand(SMIF_Type *base,
{
/* The return variable */
cy_en_smif_status_t result = CY_SMIF_SUCCESS;
/* Check input values */
CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(cmdTxfrWidth));
CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(paramTxfrWidth));
@ -340,10 +338,10 @@ cy_en_smif_status_t Cy_SMIF_TransmitCommand(SMIF_Type *base,
base->TX_CMD_FIFO_WR = constCmdPart|
_VAL2FLD(CY_SMIF_CMD_FIFO_WR_TXDATA,
(uint32_t) cmdParam[bufIndex]) |
_VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH,
_VAL2FLD(CY_SMIF_CMD_FIFO_WR_WIDTH,
(uint32_t) paramTxfrWidth) |
_VAL2FLD(CY_SMIF_CMD_FIFO_WR_LAST_BYTE,
((((uint32_t)bufIndex + 1UL) < paramSize) ?
((((uint32_t)bufIndex + 1UL) < paramSize) ?
0UL : cmpltTxfr));
bufIndex++;
@ -383,14 +381,14 @@ cy_en_smif_status_t Cy_SMIF_TransmitCommand(SMIF_Type *base,
*
* \param txBuffer
* The pointer to the data to be transferred. If this pointer is a NULL, then the
* function does not enable the interrupt. This use case is typically used when
* the FIFO is handled outside the interrupt and is managed in either a
* function does not enable the interrupt. This use case is typically used when
* the FIFO is handled outside the interrupt and is managed in either a
* polling-based code or a DMA. The user would handle the FIFO management in a
* DMA or a polling-based code.
*
*
* \note If the user provides a NULL pointer in this function and does not handle
* the FIFO transaction, this could either stall or timeout the operation.
* The transfer statuses returned by \ref Cy_SMIF_GetTxfrStatus are no longer
* The transfer statuses returned by \ref Cy_SMIF_GetTxfrStatus are no longer
* valid.
*
* \param size
@ -418,7 +416,7 @@ cy_en_smif_status_t Cy_SMIF_TransmitData(SMIF_Type *base,
{
/* The return variable */
cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
/* Check input values */
CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(transferWidth));
@ -506,7 +504,7 @@ cy_en_smif_status_t Cy_SMIF_TransmitDataBlocking(SMIF_Type *base,
{
/* The return variable */
cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
/* Check input values */
CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(transferWidth));
@ -555,8 +553,8 @@ cy_en_smif_status_t Cy_SMIF_TransmitDataBlocking(SMIF_Type *base,
*
* This function implements the receive data phase in the memory command. The
* data is received into the RX Data FIFO using the RX_COUNT command. This
* function sets up the interrupt to trigger on the RX Data FIFO level, and the
* data is fetched from the RX Data FIFO to the rxBuffer as it gets filled. This
* function sets up the interrupt to trigger on the RX Data FIFO level, and the
* data is fetched from the RX Data FIFO to the rxBuffer as it gets filled. This
* function does not block until completion. The completion will trigger the call
* back function.
*
@ -579,14 +577,14 @@ cy_en_smif_status_t Cy_SMIF_TransmitDataBlocking(SMIF_Type *base,
*
* \param rxBuffer
* The pointer to the variable where the receive data is stored. If this pointer
* is a NULL, then the function does not enable the interrupt. This use case is
* typically used when the FIFO is handled outside the interrupt and is managed
* in either a polling-based code or a DMA. The user would handle the FIFO
* is a NULL, then the function does not enable the interrupt. This use case is
* typically used when the FIFO is handled outside the interrupt and is managed
* in either a polling-based code or a DMA. The user would handle the FIFO
* management in a DMA or a polling-based code.
*
* \note If the user provides a NULL pointer in this function and does not handle
* the FIFO transaction, this could either stall or timeout the operation.
* The transfer statuses returned by \ref Cy_SMIF_GetTxfrStatus are no longer
* The transfer statuses returned by \ref Cy_SMIF_GetTxfrStatus are no longer
* valid.
*
* \param size
@ -614,7 +612,7 @@ cy_en_smif_status_t Cy_SMIF_ReceiveData(SMIF_Type *base,
{
/* The return variable */
cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
/* Check input values */
CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(transferWidth));
@ -705,7 +703,7 @@ cy_en_smif_status_t Cy_SMIF_ReceiveDataBlocking(SMIF_Type *base,
{
/* The return variable */
cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
/* Check input values */
CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(transferWidth));
@ -773,7 +771,7 @@ cy_en_smif_status_t Cy_SMIF_SendDummyCycles(SMIF_Type *base,
{
/* The return variable */
cy_en_smif_status_t result = CY_SMIF_BAD_PARAM;
if (cycles > 0U)
{
result = CY_SMIF_CMD_FIFO_FULL;
@ -782,7 +780,7 @@ cy_en_smif_status_t Cy_SMIF_SendDummyCycles(SMIF_Type *base,
{
/* Send the dummy bytes */
base->TX_CMD_FIFO_WR =
_VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE,
_VAL2FLD(CY_SMIF_CMD_FIFO_WR_MODE,
CY_SMIF_CMD_FIFO_DUMMY_COUNT_MODE) |
_VAL2FLD(CY_SMIF_CMD_FIFO_WR_DUMMY, ((uint32_t)(cycles-1U)));
@ -806,7 +804,7 @@ cy_en_smif_status_t Cy_SMIF_SendDummyCycles(SMIF_Type *base,
* is only valid if the functions passed a non-NULL buffer to transmit or
* receive respectively. If the pointer passed to \ref Cy_SMIF_ReceiveData()
* or \ref Cy_SMIF_TransmitData() is a NULL, then the code/DMA outside this
* driver will take care of the transfer and the Cy_GetTxfrStatus() will return
* driver will take care of the transfer and the Cy_GetTxfrStatus() will return
* an erroneous result.
*
* \param base
@ -819,7 +817,7 @@ cy_en_smif_status_t Cy_SMIF_SendDummyCycles(SMIF_Type *base,
* \return Returns the transfer status. \ref cy_en_smif_txfr_status_t
*
*******************************************************************************/
uint32_t Cy_SMIF_GetTxfrStatus(SMIF_Type *base,
uint32_t Cy_SMIF_GetTxfrStatus(SMIF_Type *base,
cy_stc_smif_context_t const *context)
{
return (context->transferStatus);
@ -929,7 +927,7 @@ cy_en_smif_status_t Cy_SMIF_Encrypt(SMIF_Type *base,
uint32_t bufIndex;
cy_en_smif_status_t status = CY_SMIF_BAD_PARAM;
uint32_t timeoutUnits = context->timeout;
CY_ASSERT_L2(size > 0U);
if((NULL != data) && ((address & (~CY_SMIF_CRYPTO_ADDR_MASK)) == 0UL) )
@ -948,15 +946,15 @@ cy_en_smif_status_t Cy_SMIF_Encrypt(SMIF_Type *base,
/* Start the encryption */
base->CRYPTO_CMD &= ~SMIF_CRYPTO_CMD_START_Msk;
base->CRYPTO_CMD = (uint32_t)(_VAL2FLD(SMIF_CRYPTO_CMD_START,
base->CRYPTO_CMD = (uint32_t)(_VAL2FLD(SMIF_CRYPTO_CMD_START,
CY_SMIF_CRYPTO_START));
while((CY_SMIF_CRYPTO_COMPLETED != _FLD2VAL(SMIF_CRYPTO_CMD_START,
while((CY_SMIF_CRYPTO_COMPLETED != _FLD2VAL(SMIF_CRYPTO_CMD_START,
base->CRYPTO_CMD)) &&
(CY_SMIF_EXCEED_TIMEOUT != status))
{
/* Wait until the encryption is completed and check the
* timeout
/* Wait until the encryption is completed and check the
* timeout
*/
status = Cy_SMIF_TimeoutRun(&timeoutUnits);
}
@ -966,13 +964,13 @@ cy_en_smif_status_t Cy_SMIF_Encrypt(SMIF_Type *base,
break;
}
Cy_SMIF_UnPackByteArray(base->CRYPTO_OUTPUT0,
Cy_SMIF_UnPackByteArray(base->CRYPTO_OUTPUT0,
&cryptoOut[CY_SMIF_CRYPTO_FIRST_WORD] , true);
Cy_SMIF_UnPackByteArray(base->CRYPTO_OUTPUT1,
Cy_SMIF_UnPackByteArray(base->CRYPTO_OUTPUT1,
&cryptoOut[CY_SMIF_CRYPTO_SECOND_WORD], true);
Cy_SMIF_UnPackByteArray(base->CRYPTO_OUTPUT2,
Cy_SMIF_UnPackByteArray(base->CRYPTO_OUTPUT2,
&cryptoOut[CY_SMIF_CRYPTO_THIRD_WORD] , true);
Cy_SMIF_UnPackByteArray(base->CRYPTO_OUTPUT3,
Cy_SMIF_UnPackByteArray(base->CRYPTO_OUTPUT3,
&cryptoOut[CY_SMIF_CRYPTO_FOURTH_WORD], true);
for(outIndex = 0U; outIndex < CY_SMIF_AES128_BYTES; outIndex++)
@ -1002,7 +1000,7 @@ cy_en_smif_status_t Cy_SMIF_Encrypt(SMIF_Type *base,
* - \ref CY_SMIF_BAD_PARAM
*
*******************************************************************************/
cy_en_smif_status_t Cy_SMIF_CacheEnable(SMIF_Type *base,
cy_en_smif_status_t Cy_SMIF_CacheEnable(SMIF_Type *base,
cy_en_smif_cache_en_t cacheType)
{
cy_en_smif_status_t status = CY_SMIF_SUCCESS;
@ -1022,7 +1020,7 @@ cy_en_smif_status_t Cy_SMIF_CacheEnable(SMIF_Type *base,
/* A user error*/
status = CY_SMIF_BAD_PARAM;
break;
}
}
return (status);
}
@ -1044,7 +1042,7 @@ cy_en_smif_status_t Cy_SMIF_CacheEnable(SMIF_Type *base,
* - \ref CY_SMIF_BAD_PARAM
*
*******************************************************************************/
cy_en_smif_status_t Cy_SMIF_CacheDisable(SMIF_Type *base,
cy_en_smif_status_t Cy_SMIF_CacheDisable(SMIF_Type *base,
cy_en_smif_cache_en_t cacheType)
{
cy_en_smif_status_t status = CY_SMIF_SUCCESS;
@ -1130,7 +1128,7 @@ cy_en_smif_status_t Cy_SMIF_CachePrefetchingEnable(SMIF_Type *base,
* - \ref CY_SMIF_BAD_PARAM
*
*******************************************************************************/
cy_en_smif_status_t Cy_SMIF_CachePrefetchingDisable(SMIF_Type *base,
cy_en_smif_status_t Cy_SMIF_CachePrefetchingDisable(SMIF_Type *base,
cy_en_smif_cache_en_t cacheType)
{
cy_en_smif_status_t status = CY_SMIF_SUCCESS;
@ -1173,7 +1171,7 @@ cy_en_smif_status_t Cy_SMIF_CachePrefetchingDisable(SMIF_Type *base,
* - \ref CY_SMIF_BAD_PARAM
*
*******************************************************************************/
cy_en_smif_status_t Cy_SMIF_CacheInvalidate(SMIF_Type *base,
cy_en_smif_status_t Cy_SMIF_CacheInvalidate(SMIF_Type *base,
cy_en_smif_cache_en_t cacheType)
{
cy_en_smif_status_t status = CY_SMIF_SUCCESS;
@ -1230,7 +1228,7 @@ cy_en_smif_status_t Cy_SMIF_CacheInvalidate(SMIF_Type *base,
cy_en_syspm_status_t Cy_SMIF_DeepSleepCallback(cy_stc_syspm_callback_params_t *callbackParams)
{
cy_en_syspm_status_t retStatus = CY_SYSPM_SUCCESS;
CY_ASSERT_L1(NULL != callbackParams);
SMIF_Type *locBase = (SMIF_Type *) callbackParams->base;
@ -1336,7 +1334,7 @@ cy_en_syspm_status_t Cy_SMIF_HibernateCallback(cy_stc_syspm_callback_params_t *c
cy_en_syspm_status_t retStatus = CY_SYSPM_SUCCESS;
CY_ASSERT_L1(NULL != callbackParams);
SMIF_Type *locBase = (SMIF_Type *) callbackParams->base;
cy_stc_smif_context_t *locContext = (cy_stc_smif_context_t *) callbackParams->context;
@ -1344,7 +1342,7 @@ cy_en_syspm_status_t Cy_SMIF_HibernateCallback(cy_stc_syspm_callback_params_t *c
{
case CY_SYSPM_CHECK_READY:
{
/* Check if API is not busy executing transfer operation
/* Check if API is not busy executing transfer operation
* If SPI bus is not busy, all data elements are transferred on
* the bus from the TX FIFO and shifter and the RX FIFIOs is
* empty - the SPI is ready enter Deep Sleep.

64
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/smif/cy_smif.h
View File

@ -7,9 +7,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/**
@ -44,11 +42,11 @@
* - SMIF configuration structures
*
* The SMIF API is divided into the low-level functions and memory-slot functions. Use
* the low level API for the SMIF block initialization and for implementing a generic
* the low level API for the SMIF block initialization and for implementing a generic
* SPI communication interface using the SMIF block.
*
* The memory slot API has functions to implement the basic memory operations such as
* program, read, erase etc. These functions are implemented using the memory
* The memory slot API has functions to implement the basic memory operations such as
* program, read, erase etc. These functions are implemented using the memory
* parameters in the memory device configuration data structure. The memory-slot
* initialization API initializes all the memory slots based on the settings in the
* array.
@ -62,14 +60,14 @@
* structures are input parameters for cy_smif_memslot API level
*
* \warning The driver is not responsible for external memory persistence. You cannot edit
* a buffer during the Read/Write operations. If there is a memory error, the SMIF ip block
* can require a reset. To determine if this has happened, check the SMIF
* busy status using Cy_SMIF_BusyCheck() and implement a timeout. Reset the SMIF
* a buffer during the Read/Write operations. If there is a memory error, the SMIF ip block
* can require a reset. To determine if this has happened, check the SMIF
* busy status using Cy_SMIF_BusyCheck() and implement a timeout. Reset the SMIF
* block by toggling CTL.ENABLED. Then reconfigure the SMIF block.
*
* For the Write operation, check that the SMIF driver has completed
* transferring by calling Cy_SMIF_BusyCheck(). Also, check that the memory is
* available with Cy_SMIF_Memslot_IsBusy() before proceeding.
* For the Write operation, check that the SMIF driver has completed
* transferring by calling Cy_SMIF_BusyCheck(). Also, check that the memory is
* available with Cy_SMIF_Memslot_IsBusy() before proceeding.
*
* Simple example of external flash memory programming using low level SMIF API.
* All steps mentioned in example below are incorporated in
@ -94,7 +92,7 @@
*
* \snippet smif/smif_sut_01.cydsn/main_cm4.c SMIF_API: Read example
*
* The user should invalidate the cache by calling Cy_SMIF_CacheInvalidate() when
* The user should invalidate the cache by calling Cy_SMIF_CacheInvalidate() when
* switching from the MMIO mode to XIP mode.
*
* \section group_smif_configuration Configuration Considerations
@ -103,7 +101,7 @@
* \ref page_getting_started_pdl_design "PDL Design" section.
*
* See the documentation for Cy_SMIF_Init() and Cy_SMIF_Memslot_Init() for details
* on the required configuration structures and other initialization topics.
* on the required configuration structures and other initialization topics.
*
* The normal (MMIO) mode is used for implementing a generic SPI/DSPI/QSPI/Dual
* Quad-SPI/Octal-SPI communication interface using the SMIF block. This
@ -137,21 +135,21 @@
* memslot level API usage.
*
* \subsection group_smif_xip_init SMIF XIP Initialization
* The eXecute In Place (XIP) is a mode of operation where read or write commands
* to the memory device are directed through the SMIF without any use of API
* function calls. In this mode the SMIF block maps the AHB bus-accesses to
* external memory device addresses to make it behave similar to internal memory.
* This allows the CPU to execute code directly from external memory. This mode
* is not limited to code and is suitable also for data read and write accesses.
* The eXecute In Place (XIP) is a mode of operation where read or write commands
* to the memory device are directed through the SMIF without any use of API
* function calls. In this mode the SMIF block maps the AHB bus-accesses to
* external memory device addresses to make it behave similar to internal memory.
* This allows the CPU to execute code directly from external memory. This mode
* is not limited to code and is suitable also for data read and write accesses.
* \snippet smif/smif_sut_01.cydsn/main_cm4.c SMIF_INIT: XIP
* \note Example of input parameters initialization is in \ref group_smif_init
* \note Example of input parameters initialization is in \ref group_smif_init
* section.
* \warning Functions that called from external memory should be declared with
* long call attribute.
* \warning Functions that called from external memory should be declared with
* long call attribute.
*
* \section group_smif_more_information More Information
*
* More information regarding the Serial Memory Interface can be found in the component
* More information regarding the Serial Memory Interface can be found in the component
* datasheet and the Technical Reference Manual (TRM).
* More information regarding the SMIF Configuration Tool are in SMIF
* Configuration Tool User Guide located in \<PDL_DIR\>/tools/\<OS_DIR\>/SMIFConfigurationTool/
@ -198,7 +196,7 @@
* </tr>
* <tr>
* <td>1.10</td>
* <td>Fix write to external memory from CM0+ core. Add checks of API input parameters.
* <td>Fix write to external memory from CM0+ core. Add checks of API input parameters.
* Minor documentation updates</td>
* <td></td>
* </tr>
@ -354,7 +352,7 @@ extern "C" {
(CY_SMIF_SEL_INV_INTERNAL_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
(CY_SMIF_SEL_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)) || \
(CY_SMIF_SEL_INV_FEEDBACK_CLK == (cy_en_smif_clk_select_t)(clkSel)))
#define CY_SMIF_DESELECT_DELAY_VALID(delay) ((delay) <= CY_SMIF_MAX_DESELECT_DELAY)
#define CY_SMIF_SLAVE_SEL_VALID(ss) ((CY_SMIF_SLAVE_SELECT_0 == (ss)) || \
(CY_SMIF_SLAVE_SELECT_1 == (ss)) || \
@ -396,7 +394,7 @@ extern "C" {
#define CY_SMIF_CMD_FIFO_WR_SS_Pos (8UL) /* [11:8] Slave select */
#define CY_SMIF_CMD_FIFO_WR_SS_Msk (0x00000F00UL) /* DATA[11:8] Slave select */
#define CY_SMIF_CMD_FIFO_WR_TXDATA_Pos (0UL) /* [0] Transmitted byte */
#define CY_SMIF_CMD_FIFO_WR_TXDATA_Msk (0x000000FFUL) /* DATA[7:0] Transmitted byte */
#define CY_SMIF_CMD_FIFO_WR_DUMMY_Pos (0UL) /* [0] Dummy count */
@ -429,8 +427,8 @@ typedef enum
{
/**< Generates a bus error. */
CY_SMIF_BUS_ERROR = 0UL,
/** Stalls the bus with the wait states. This option will increase the
* interrupt latency.
/** Stalls the bus with the wait states. This option will increase the
* interrupt latency.
*/
CY_SMIF_WAIT_STATES = 1UL
} cy_en_smif_error_event_t;
@ -511,7 +509,7 @@ typedef enum
} cy_en_smif_status_t;
/** The SMIF slave select definitions for the driver API. Each slave select is
* represented by an enumeration that has the bit corresponding to the slave
* represented by an enumeration that has the bit corresponding to the slave
* select number set. */
typedef enum
{
@ -570,10 +568,10 @@ typedef struct
* - "5": 6 clock cycles.
* - "6": 7 clock cycles.
* - "7": 8 clock cycles. */
uint32_t rxClockSel; /**< Specifies the clock source for the receiver
uint32_t rxClockSel; /**< Specifies the clock source for the receiver
* clock \ref cy_en_smif_clk_select_t. */
uint32_t blockEvent; /**< Specifies what happens when there is a Read
* from an empty RX FIFO or a Write to a full
uint32_t blockEvent; /**< Specifies what happens when there is a Read
* from an empty RX FIFO or a Write to a full
* TX FIFO. \ref cy_en_smif_error_event_t. */
} cy_stc_smif_config_t;

72
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/smif/cy_smif_memslot.c
View File

@ -10,9 +10,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_smif_memslot.h"
@ -43,7 +41,7 @@ static void Cy_SMIF_Memslot_XipRegInit(SMIF_DEVICE_Type volatile *dev,
* achieved using Cy_SMIF_Init(). The cy_stc_smif_context_t context structure
* returned from Cy_SMIF_Init() is passed as a parameter to this function.
* This function calls the \ref Cy_SMIF_Memslot_SfdpDetect() function for each
* element of the \ref cy_stc_smif_mem_config_t memConfig array and fills the memory
* element of the \ref cy_stc_smif_mem_config_t memConfig array and fills the memory
* parameters if the autoDetectSfdp field is enabled in \ref cy_stc_smif_mem_config_t.
* The filled memConfig is a part of the \ref cy_stc_smif_block_config_t * blockConfig
* structure. The function expects that all the requirements of
@ -74,7 +72,7 @@ cy_en_smif_status_t Cy_SMIF_Memslot_Init(SMIF_Type *base,
uint32_t sfdpRes =(uint32_t)CY_SMIF_SUCCESS;
uint32_t idx;
if ((NULL != base) && (NULL != blockConfig) && (NULL != blockConfig->memConfig)
if ((NULL != base) && (NULL != blockConfig) && (NULL != blockConfig->memConfig)
&& (NULL != context) && (0U != blockConfig->memCount))
{
uint32_t size = blockConfig->memCount;
@ -91,7 +89,7 @@ cy_en_smif_status_t Cy_SMIF_Memslot_Init(SMIF_Type *base,
CY_ASSERT_L3(CY_SMIF_DATA_SEL_VALID(memCfg->dataSelect));
CY_ASSERT_L1(NULL != memCfg->deviceCfg);
CY_ASSERT_L2(CY_SMIF_MEM_ADDR_SIZE_VALID(memCfg->deviceCfg->numOfAddrBytes));
device = Cy_SMIF_GetDeviceBySlot(base, memCfg->slaveSelect);
if (NULL != device)
{
@ -119,7 +117,7 @@ cy_en_smif_status_t Cy_SMIF_Memslot_Init(SMIF_Type *base,
/* Check valid parameters for XIP */
CY_ASSERT_L3(CY_SMIF_MEM_ADDR_VALID( memCfg->baseAddress, memCfg->memMappedSize));
CY_ASSERT_L3(CY_SMIF_MEM_MAPPED_SIZE_VALID( memCfg->memMappedSize));
Cy_SMIF_Memslot_XipRegInit(device, memCfg);
/* The device control register initialization */
@ -291,8 +289,8 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdWriteEnable(SMIF_Type *base,
{
/* The memory Write Enable */
cy_stc_smif_mem_cmd_t* writeEn = memDevice->deviceCfg->writeEnCmd;
CY_ASSERT_L1(NULL != writeEn);
CY_ASSERT_L1(NULL != writeEn);
return Cy_SMIF_TransmitCommand( base, (uint8_t) writeEn->command,
writeEn->cmdWidth,
@ -335,8 +333,8 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdWriteDisable(SMIF_Type *base,
{
cy_stc_smif_mem_cmd_t* writeDis = memDevice->deviceCfg->writeDisCmd;
CY_ASSERT_L1(NULL != writeDis);
CY_ASSERT_L1(NULL != writeDis);
/* The memory write disable */
return Cy_SMIF_TransmitCommand( base, (uint8_t)writeDis->command,
writeDis->cmdWidth,
@ -381,8 +379,8 @@ bool Cy_SMIF_Memslot_IsBusy(SMIF_Type *base, cy_stc_smif_mem_config_t *memDevice
cy_en_smif_status_t readStsResult;
cy_stc_smif_mem_device_cfg_t* device = memDevice->deviceCfg;
CY_ASSERT_L1(NULL != device->readStsRegWipCmd);
CY_ASSERT_L1(NULL != device->readStsRegWipCmd);
readStsResult = Cy_SMIF_Memslot_CmdReadSts(base, memDevice, &status,
(uint8_t)device->readStsRegWipCmd->command,
context);
@ -428,14 +426,14 @@ cy_en_smif_status_t Cy_SMIF_Memslot_QuadEnable(SMIF_Type *base,
cy_stc_smif_context_t const *context)
{
cy_en_smif_status_t result;
uint8_t statusReg[CY_SMIF_QE_BIT_STS_REG2_T1] = {0U};
uint8_t statusReg[CY_SMIF_QE_BIT_STS_REG2_T1] = {0U};
cy_stc_smif_mem_device_cfg_t* device = memDevice->deviceCfg;
/* Check that command exists */
CY_ASSERT_L1(NULL != device->readStsRegQeCmd);
CY_ASSERT_L1(NULL != device->writeStsRegQeCmd);
CY_ASSERT_L1(NULL != device->readStsRegWipCmd);
uint8_t readQeCmd = (uint8_t)device->readStsRegQeCmd->command;
uint8_t writeQeCmd = (uint8_t)device->writeStsRegQeCmd->command;
uint8_t readWipCmd = (uint8_t)device->readStsRegWipCmd->command;
@ -572,7 +570,7 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdReadSts(SMIF_Type *base,
* The status to write into the status register.
*
* \param command
* The command to write into the status/configuration register.
* The command to write into the status/configuration register.
*
* \return A status of the command transmission.
* - \ref CY_SMIF_SUCCESS
@ -692,7 +690,7 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdSectorErase(SMIF_Type *base,
cy_stc_smif_mem_device_cfg_t *device = memDevice->deviceCfg;
cy_stc_smif_mem_cmd_t *cmdErase = device->eraseCmd;
CY_ASSERT_L1(NULL != cmdErase);
result = Cy_SMIF_TransmitCommand( base, (uint8_t)cmdErase->command,
@ -709,7 +707,7 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdSectorErase(SMIF_Type *base,
* Function Name: Cy_SMIF_Memslot_CmdProgram
****************************************************************************//**
*
* This function performs the Program operation.
* This function performs the Program operation.
*
* \note This function uses the Cy_SMIF_TransmitCommand() API.
* The Cy_SMIF_TransmitCommand() API works in the blocking mode. In the dual quad mode,
@ -730,11 +728,11 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdSectorErase(SMIF_Type *base,
* \param writeBuff
* The pointer to the data to program. If this pointer is a NULL, then the
* function does not enable the interrupt. This use case is typically used when
* the FIFO is handled outside the interrupt and is managed in either a
* polling-based code or a DMA. The user would handle the FIFO management
* in a DMA or a polling-based code.
* If the user provides a NULL pointer in this function and does not handle
* the FIFO transaction, this could either stall or timeout the operation
* the FIFO is handled outside the interrupt and is managed in either a
* polling-based code or a DMA. The user would handle the FIFO management
* in a DMA or a polling-based code.
* If the user provides a NULL pointer in this function and does not handle
* the FIFO transaction, this could either stall or timeout the operation
* \ref Cy_SMIF_TransmitData().
*
*
@ -766,7 +764,7 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdProgram(SMIF_Type *base,
cy_stc_smif_mem_device_cfg_t *device = memDevice->deviceCfg;
cy_stc_smif_mem_cmd_t *cmdProg = device->programCmd;
CY_ASSERT_L1(NULL != cmdProg);
if ((NULL != addr) && (size <= device->programSize))
@ -818,13 +816,13 @@ cy_en_smif_status_t Cy_SMIF_Memslot_CmdProgram(SMIF_Type *base,
* The address to read.
*
* \param readBuff
* The pointer to the variable where the read data is stored. If this pointer is
* a NULL, then the function does not enable the interrupt. This use case is
* The pointer to the variable where the read data is stored. If this pointer is
* a NULL, then the function does not enable the interrupt. This use case is
* typically used when the FIFO is handled outside the interrupt and is managed
* in either a polling-based code or a DMA. The user would handle the FIFO
* management in a DMA or a polling-based code.
* If the user provides a NULL pointer in this function and does not handle
* the FIFO transaction, this could either stall or timeout the operation
* management in a DMA or a polling-based code.
* If the user provides a NULL pointer in this function and does not handle
* the FIFO transaction, this could either stall or timeout the operation
* \ref Cy_SMIF_TransmitData().
*
* \param size
@ -944,7 +942,7 @@ cy_en_smif_status_t Cy_SMIF_Memslot_SfdpDetect(SMIF_Type *base,
/* Check input parameters */
CY_ASSERT_L1(NULL != device);
CY_ASSERT_L1(NULL != device->readSfdpCmd);
uint8_t sfdpBuffer[CY_SMIF_SFDP_LENGTH];
uint8_t sfdpAddress[CY_SMIF_SFDP_ADDRESS_LENGTH] = {0x00U, 0x00U, 0x00U};
cy_en_smif_status_t result;
@ -1101,13 +1099,13 @@ cy_en_smif_status_t Cy_SMIF_Memslot_SfdpDetect(SMIF_Type *base,
device->memSize = (locSize - CY_SMIF_BITS_IN_BYTE_ABOVE_4GB) |
CY_SMIF_SFDP_SIZE_ABOVE_4GB_Msk;
}
/* The page size */
device->programSize = 0x01UL << _FLD2VAL(CY_SMIF_SFDP_PAGE_SIZE,
(uint32_t) sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_28 + offset]);
(uint32_t) sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_28 + offset]);
/* The size of the Erase sector */
device->eraseSize = (0x01UL << (uint32_t)sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_1C + offset]);
device->eraseSize = (0x01UL << (uint32_t)sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_1C + offset]);
/* This specifies the Read command. The preference order Quad>Dual>SPI */
if ((_FLD2VAL(CY_SMIF_SFDP_FAST_READ_1_4_4,
@ -1276,7 +1274,7 @@ cy_en_smif_status_t Cy_SMIF_Memslot_SfdpDetect(SMIF_Type *base,
device->writeDisCmd->command = CY_SMIF_WR_DISABLE_CMD;
/* The width of the command transfer */
device->writeDisCmd->cmdWidth = CY_SMIF_WIDTH_SINGLE;
/* The chip Erase command */
/* The 8-bit command. Chip Erase */
device->chipEraseCmd->command = CY_SMIF_CHIP_ERASE_CMD;
@ -1308,7 +1306,7 @@ cy_en_smif_status_t Cy_SMIF_Memslot_SfdpDetect(SMIF_Type *base,
/* The busy mask for the status registers */
device->stsRegBusyMask = CY_SMIF_STS_REG_BUSY_MASK;
/* The command to read the WIP-containing status register */
/* The 8-bit command. WIP RDSR */
device->readStsRegWipCmd->command = CY_SMIF_RD_STS_REG1_CMD;

12
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/smif/cy_smif_memslot.h
View File

@ -11,9 +11,7 @@
********************************************************************************
* \copyright
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#if !defined(CY_SMIF_MEMORYSLOT_H)
@ -129,15 +127,15 @@ extern "C" {
#define CY_SMIF_SFDP_ERASE_TIME_16MS (16U) /**< Units of Erase Typical Time in ms */
#define CY_SMIF_SFDP_ERASE_TIME_128MS (128U) /**< Units of Erase Typical Time in ms */
#define CY_SMIF_SFDP_ERASE_TIME_1S (1000U) /**< Units of Erase Typical Time in ms */
#define CY_SMIF_SFDP_CHIP_ERASE_TIME_16MS (16U) /**< Units of Chip Erase Typical Time in ms */
#define CY_SMIF_SFDP_CHIP_ERASE_TIME_256MS (256U) /**< Units of Chip Erase Typical Time in ms */
#define CY_SMIF_SFDP_CHIP_ERASE_TIME_4S (4000U) /**< Units of Chip Erase Typical Time in ms */
#define CY_SMIF_SFDP_CHIP_ERASE_TIME_64S (64000U) /**< Units of Chip Erase Typical Time in ms */
#define CY_SMIF_SFDP_PROG_TIME_8US (8U) /**< Units of Page Program Typical Time in us */
#define CY_SMIF_SFDP_PROG_TIME_64US (64U) /**< Units of Page Program Typical Time in us */
#define CY_SMIF_SFDP_UNIT_0 (0U) /**< Units of Basic Flash Parameter Table Time Parameters */
#define CY_SMIF_SFDP_UNIT_1 (1U) /**< Units of Basic Flash Parameter Table Time Parameters */
#define CY_SMIF_SFDP_UNIT_2 (2U) /**< Units of Basic Flash Parameter Table Time Parameters */
@ -280,7 +278,7 @@ typedef struct
*/
typedef struct
{
uint32_t numOfAddrBytes; /**< This specifies the number of address bytes used by the
uint32_t numOfAddrBytes; /**< This specifies the number of address bytes used by the
* memory slave device, valid values 1-4 */
uint32_t memSize; /**< The size of the memory */
cy_stc_smif_mem_cmd_t* readCmd; /**< This specifies the Read command */

6
targets/TARGET_Cypress/TARGET_PSOC6/device/drivers/peripheral/sysanalog/cy_sysanalog.c
View File

@ -6,10 +6,8 @@
*
********************************************************************************
* \copyright
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
#include "cy_sysanalog.h"

Some files were not shown because too many files have changed in this diff Show More