mirror of https://github.com/ARMmbed/mbed-os.git
STM32F429/STM32F439 alignment
jeromecoutant
parent
c0108b1b48
commit
a8c87c0804
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@ -0,0 +1,49 @@
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Permissive Binary License
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Version 1.0, September 2015
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Redistribution. Redistribution and use in binary form, without
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modification, are permitted provided that the following conditions are
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met:
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1) Redistributions must reproduce the above copyright notice and the
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following disclaimer in the documentation and/or other materials
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provided with the distribution.
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2) Unless to the extent explicitly permitted by law, no reverse
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engineering, decompilation, or disassembly of this software is
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permitted.
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3) Redistribution as part of a software development kit must include the
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accompanying file named "DEPENDENCIES" and any dependencies listed in
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that file.
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4) Neither the name of the copyright holder nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
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this software without specific prior written permission.
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Limited patent license. The copyright holders (and contributors) grant a
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worldwide, non-exclusive, no-charge, royalty-free patent license to
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make, have made, use, offer to sell, sell, import, and otherwise
|
||||
transfer this software, where such license applies only to those patent
|
||||
claims licensable by the copyright holders (and contributors) that are
|
||||
necessarily infringed by this software. This patent license shall not
|
||||
apply to any combinations that include this software. No hardware is
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licensed hereunder.
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If you institute patent litigation against any entity (including a
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cross-claim or counterclaim in a lawsuit) alleging that the software
|
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itself infringes your patent(s), then your rights granted under this
|
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license shall terminate as of the date such litigation is filed.
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DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
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NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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||||
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Binary file not shown.
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@ -0,0 +1,10 @@
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{
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"name": "bootloader_NUCLEO_F439ZI",
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"target_overrides": {
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"*": {
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"target.app_offset": "0x10400",
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"target.header_offset": "0x10000",
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"target.bootloader_img": "mbed-bootloader-nucleo_f439zi-block_device-sotp-v3_4_0.bin"
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}
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}
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}
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@ -30,7 +30,7 @@
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**/
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#include "stm32f4xx.h"
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#include "nvic_addr.h"
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#include "mbed_error.h"
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// clock source is selected with CLOCK_SOURCE in json config
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@ -56,6 +56,10 @@ uint8_t SetSysClock_PLL_HSI(void);
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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@ -79,6 +83,13 @@ void SystemInit(void)
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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@ -30,7 +30,7 @@
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**/
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#include "stm32f4xx.h"
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#include "nvic_addr.h"
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#include "mbed_error.h"
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// clock source is selected with CLOCK_SOURCE in json config
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@ -56,6 +56,10 @@ uint8_t SetSysClock_PLL_HSI(void);
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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@ -79,6 +83,13 @@ void SystemInit(void)
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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@ -168,15 +168,9 @@ __Vectors_Size EQU __Vectors_End - __Vectors
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInitPre
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IMPORT HAL_InitPre
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInitPre
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BLX R0
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LDR R0, =HAL_InitPre
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BLX R0
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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@ -45,7 +45,7 @@
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#define MBED_RAM0_START (MBED_CRASH_REPORT_RAM_START + MBED_CRASH_REPORT_RAM_SIZE)
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#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE - MBED_CRASH_REPORT_RAM_SIZE)
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; 2 MB FLASH (0x200000) + 192 KB SRAM (0x30000)
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; 2 MB FLASH (0x200000) + 256 KB SRAM (0x30000 + 0x10000)
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
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@ -61,6 +61,9 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE) { ; RW data
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.ANY (+RW +ZI)
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}
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RW_IRAM2 (0x10000000) (0x10000) { ; RW data
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.ANY (+RW +ZI)
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}
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}
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@ -1,11 +1,3 @@
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M_VECTOR_RAM_SIZE = 0x400;
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/* With the RTOS in use, this does not affect the main stack size. The size of
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* the stack where main runs is determined via the RTOS. */
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STACK_SIZE = 0x400;
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HEAP_SIZE = 0x6000;
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#if !defined(MBED_APP_START)
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#define MBED_APP_START 0x08000000
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#endif
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@ -16,13 +8,13 @@ HEAP_SIZE = 0x6000;
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M_CRASH_DATA_RAM_SIZE = 0x100;
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/* Specify the memory areas */
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/* Linker script to configure memory regions. */
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/* 0x1AC resevered for vectors; 8-byte aligned = 0x1B0 (0x1AC + 0x4)*/
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MEMORY
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{
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VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x400
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FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400
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CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 192k
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{
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FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
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CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
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RAM (rwx) : ORIGIN = 0x200001B0, LENGTH = 192k - (0x1AC+0x4)
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}
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/* Linker script to place sections and symbol values. Should be used together
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@ -56,18 +48,10 @@ ENTRY(Reset_Handler)
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SECTIONS
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{
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.isr_vector :
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{
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__vector_table = .;
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KEEP(*(.isr_vector))
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. = ALIGN(8);
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} > VECTORS
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.text :
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{
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KEEP(*(.isr_vector))
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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@ -96,7 +80,6 @@ SECTIONS
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} > FLASH
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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@ -105,17 +88,6 @@ SECTIONS
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__etext = .;
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_sidata = .;
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.interrupts_ram :
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{
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. = ALIGN(8);
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__VECTOR_RAM__ = .;
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__interrupts_ram_start__ = .; /* Create a global symbol at data start */
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*(.m_interrupts_ram) /* This is a user defined section */
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. += M_VECTOR_RAM_SIZE;
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. = ALIGN(8);
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__interrupts_ram_end__ = .; /* Define a global symbol at data end */
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} > RAM
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.crash_data_ram :
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{
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@ -127,12 +99,10 @@ SECTIONS
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. += M_CRASH_DATA_RAM_SIZE;
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. = ALIGN(8);
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__CRASH_DATA_RAM_END__ = .; /* Define a global symbol at data end */
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} > RAM
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} > RAM
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.data :
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.data : AT (__etext)
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{
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PROVIDE( __etext = LOADADDR(.data) );
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__data_start__ = .;
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_sdata = .;
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*(vtable)
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@ -165,23 +135,9 @@ SECTIONS
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__data_end__ = .;
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_edata = .;
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} > RAM AT > FLASH
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/* Uninitialized data section
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* This region is not initialized by the C/C++ library and can be used to
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* store state across soft reboots. */
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.uninitialized (NOLOAD):
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{
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. = ALIGN(32);
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__uninitialized_start = .;
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*(.uninitialized)
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KEEP(*(.keep.uninitialized))
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. = ALIGN(32);
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__uninitialized_end = .;
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} > RAM
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.bss (NOLOAD):
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.bss :
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{
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. = ALIGN(8);
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__bss_start__ = .;
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@ -193,18 +149,29 @@ SECTIONS
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_ebss = .;
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} > RAM
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.heap (NOLOAD):
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.heap (COPY):
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{
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__end__ = .;
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end = __end__;
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. += HEAP_SIZE;
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*(.heap*)
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__HeapLimit = .;
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} > RAM
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/* .stack_dummy section doesn't contains any symbols. It is only
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* used for linker to calculate size of stack sections, and assign
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* values to stack symbols later */
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.stack_dummy (COPY):
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{
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*(.stack*)
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} > RAM
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/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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__StackTop = ORIGIN(RAM) + LENGTH(RAM);
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__stack = __StackTop;
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__StackLimit = __StackTop - STACK_SIZE;
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ASSERT(__StackLimit >= __HeapLimit, "Region RAM overflowed with stack and heap")
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_estack = __StackTop;
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__StackLimit = __StackTop - SIZEOF(.stack_dummy);
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PROVIDE(__stack = __StackTop);
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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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}
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@ -74,10 +74,10 @@ defined in linker script */
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr sp, =__stack /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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Reset_Handler:
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ldr sp, =_estack /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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@ -106,8 +106,6 @@ LoopFillZerobss:
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInitPre
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bl HAL_InitPre
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bl SystemInit
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/* Call static constructors */
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//bl __libc_init_array
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@ -142,10 +140,10 @@ Infinite_Loop:
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word __stack
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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@ -212,7 +210,7 @@ g_pfnVectors:
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.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
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.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
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.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
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.word FMC_IRQHandler /* FMC */
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.word FMC_IRQHandler /* FMC */
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.word SDIO_IRQHandler /* SDIO */
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.word TIM5_IRQHandler /* TIM5 */
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.word SPI3_IRQHandler /* SPI3 */
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@ -252,8 +250,8 @@ g_pfnVectors:
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.word SPI5_IRQHandler /* SPI5 */
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.word SPI6_IRQHandler /* SPI6 */
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.word SAI1_IRQHandler /* SAI1 */
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.word LTDC_IRQHandler /* LTDC_IRQHandler */
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.word LTDC_ER_IRQHandler /* LTDC_ER_IRQHandler */
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.word LTDC_IRQHandler /* LTDC */
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.word LTDC_ER_IRQHandler /* LTDC error */
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.word DMA2D_IRQHandler /* DMA2D */
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/*******************************************************************************
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@ -61,8 +61,6 @@
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInitPre
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EXTERN HAL_InitPre
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EXTERN SystemInit
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PUBLIC __vector_table
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@ -188,10 +186,6 @@ __vector_table
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SECTION .text:CODE:REORDER:NOROOT(2)
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Reset_Handler
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LDR R0, =SystemInitPre
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BLX R0
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LDR R0, =HAL_InitPre
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BLX R0
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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@ -648,13 +642,13 @@ FPU_IRQHandler
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B FPU_IRQHandler
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PUBWEAK UART7_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SECTION .text:CODE:REORDER:NOROOT(1)
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UART7_IRQHandler
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B UART7_IRQHandler
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PUBWEAK UART8_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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UART8_IRQHandler
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UART8_IRQHandler
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B UART8_IRQHandler
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PUBWEAK SPI4_IRQHandler
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@ -664,7 +658,7 @@ SPI4_IRQHandler
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PUBWEAK SPI5_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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SPI5_IRQHandler
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SPI5_IRQHandler
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B SPI5_IRQHandler
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PUBWEAK SPI6_IRQHandler
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|
|
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@ -17,16 +17,16 @@ define symbol __ICFEDIT_region_RAM_end__ = 0x2002FFFF;
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define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000;
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define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF;
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/*-Sizes-*/
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/*Heap 64K and stack 4K */
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define symbol __ICFEDIT_size_cstack__ = 0x1000;
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define symbol __ICFEDIT_size_heap__ = 0x10000;
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/*Heap 89kB and stack 1kB */
|
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define symbol __ICFEDIT_size_cstack__ = 0x400;
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define symbol __ICFEDIT_size_heap__ = 0x15C00;
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/**** End of ICF editor section. ###ICF###*/
|
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|
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
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define region CRASH_DATA_RAM_region = mem:[from __region_CRASH_DATA_RAM_start__ to __region_CRASH_DATA_RAM_end__];
|
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
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define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__];
|
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|
||||
/* Define Crash Data Symbols */
|
||||
|
|
|
|||
|
|
@ -259,7 +259,7 @@ typedef enum {
|
|||
LED2 = PB_7, // Blue
|
||||
LED3 = PB_14, // Red
|
||||
LED4 = PB_0,
|
||||
LED_RED = LED2,
|
||||
LED_RED = LED3,
|
||||
USER_BUTTON = PC_13,
|
||||
// Standardized button names
|
||||
BUTTON1 = USER_BUTTON,
|
||||
|
|
|
|||
|
|
@ -17,20 +17,15 @@
|
|||
/**
|
||||
* This file configures the system clock as follows:
|
||||
*-----------------------------------------------------------------------------------
|
||||
* System clock source | 1- USE_PLL_HSE_EXTC (CLOCK_SOURCE_USB=1) | 3- USE_PLL_HSI (CLOCK_SOURCE_USB=1)
|
||||
* | (external 8 MHz clock) | (internal 16 MHz clock)
|
||||
* | 2- USE_PLL_HSE_XTAL |
|
||||
* | (external 8 MHz xtal) |
|
||||
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) |
|
||||
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) | CLOCK_SOURCE_USB=1
|
||||
* | 3- USE_PLL_HSI (internal 16 MHz clock) |
|
||||
*-----------------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 180 (168)
|
||||
*-----------------------------------------------------------------------------------
|
||||
* AHBCLK (MHz) | 180 (168)
|
||||
*-----------------------------------------------------------------------------------
|
||||
* APB1CLK (MHz) | 45 (42)
|
||||
*-----------------------------------------------------------------------------------
|
||||
* APB2CLK (MHz) | 90 (84)
|
||||
*-----------------------------------------------------------------------------------
|
||||
* USB capable (48 MHz) | YES (HSI calibration needed)
|
||||
* SYSCLK(MHz) | 180 | 168
|
||||
* AHBCLK (MHz) | 180 | 168
|
||||
* APB1CLK (MHz) | 45 | 42
|
||||
* APB2CLK (MHz) | 90 | 84
|
||||
* USB capable (48 MHz) | NO | YES (HSI calibration needed)
|
||||
*-----------------------------------------------------------------------------------
|
||||
**/
|
||||
|
||||
|
|
@ -40,7 +35,7 @@
|
|||
|
||||
// clock source is selected with CLOCK_SOURCE in json config
|
||||
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
|
||||
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
|
||||
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
|
||||
#define USE_PLL_HSI 0x2 // Use HSI internal clock
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
|
|
@ -51,6 +46,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
|||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the FPU setting, vector table location and External memory
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
|
|||
RW_m_crash_data MBED_CRASH_REPORT_RAM_START EMPTY MBED_CRASH_REPORT_RAM_SIZE { ; RW data
|
||||
}
|
||||
|
||||
; Total: 107 vectors = 428 bytes(0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM
|
||||
; Total: 107 vectors = 428 bytes (0x1AC) 8-byte aligned = 0x1B0 (0x1AC + 0x4) to be reserved in RAM
|
||||
RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE) { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ MEMORY
|
|||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
|
|
|
|||
|
|
@ -254,8 +254,6 @@ Infinite_Loop:
|
|||
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
|
|
@ -567,7 +565,3 @@ Infinite_Loop:
|
|||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Flash Size */
|
||||
/* FLASH SIZE */
|
||||
#define FLASH_SIZE (uint32_t) 0x200000
|
||||
|
||||
/* Base address of the Flash sectors Bank 1 */
|
||||
|
|
|
|||
|
|
@ -186,10 +186,7 @@ HAL_StatusTypeDef HAL_Init(void)
|
|||
#endif /* PREFETCH_ENABLE */
|
||||
|
||||
/* Set Interrupt Group Priority */
|
||||
/* MBED : moved to HAL_InitPre() */
|
||||
#if !defined (TARGET_STM32F429xI)
|
||||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
#endif
|
||||
|
||||
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
|
||||
HAL_InitTick(TICK_INT_PRIORITY);
|
||||
|
|
|
|||
|
|
@ -1,28 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2015, ARM Limited, All Rights Reserved
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "stm32f4xx_hal.h"
|
||||
|
||||
HAL_StatusTypeDef HAL_InitPre(void);
|
||||
|
||||
HAL_StatusTypeDef HAL_InitPre(void)
|
||||
{
|
||||
/* Set Interrupt Group Priority */
|
||||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
||||
|
||||
/* Return function status */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
|
@ -2603,7 +2603,10 @@
|
|||
"STM32F429xI",
|
||||
"STM_EMAC"
|
||||
],
|
||||
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
|
||||
"macros_add": [
|
||||
"USB_STM_HAL",
|
||||
"USBHOST_OTHER"
|
||||
],
|
||||
"device_has_add": [
|
||||
"ANALOGOUT",
|
||||
"CAN",
|
||||
|
|
@ -2660,6 +2663,7 @@
|
|||
"ANALOGOUT",
|
||||
"CAN",
|
||||
"EMAC",
|
||||
"SERIAL_ASYNCH",
|
||||
"SERIAL_FC",
|
||||
"TRNG",
|
||||
"FLASH",
|
||||
|
|
|
|||
Loading…
Reference in New Issue