ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'master' of https://github.com/kyliuxing/mbed-os into dev_rollup

pull/8753/head
Martin Kojtal 2018-11-15 13:58:04 +00:00
parent 4d07bcbd6e 627064297e
commit 88ef552d1a
43 changed files with 4747 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
platform/mbed_lib.json
View File

@ -110,6 +110,9 @@
},
"EFR32": {
"stdio-baud-rate": 115200
},
"UNO_91H": {
"stdio-baud-rate": 115200
}
}
}

87
targets/TARGET_RDA/TARGET_UNO_91H/PeripheralNames.h Normal file
View File

@ -0,0 +1,87 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)RDA_UART0_BASE,
UART_1 = (int)RDA_UART1_BASE
} UARTName;
typedef enum {
// Make sure GPIO_BASE & 0x1F == 0, store GPIO index at this field when mapping pins
GPIO_0 = (int)RDA_GPIO_BASE
} GPIOName;
typedef enum {
I2C_0 = (int)RDA_I2C0_BASE
} I2CName;
typedef enum {
SPI_0 = (int)RDA_SPI0_BASE
} SPIName;
typedef enum {
I2S_0 = (int)RDA_I2S_BASE
} I2SName;
typedef enum {
WDT_0 = (int)RDA_WDT_BASE
} WDTName;
typedef enum {
PWM_0 = 0,
PWM_1,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7
} PWMName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2
} ADCName;
typedef enum {
GPADC0_0 = 0,
GPADC0_1
} GPADCName;
#define STDIO_UART_TX UART0_TX
#define STDIO_UART_RX UART0_RX
#define STDIO_UART UART_0
// Default peripherals
#define MBED_UART0 PA_0, PA_1
#define MBED_UART1 PB_1, PB_2
#define MBED_UARTUSB USBTX, USBRX
#ifdef __cplusplus
}
#endif
#endif

180
targets/TARGET_RDA/TARGET_UNO_91H/PinNames.h Normal file
View File

@ -0,0 +1,180 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 8
typedef enum {
PA_0 = (0 << PORT_SHIFT | 0 ),
PA_1 = (0 << PORT_SHIFT | 1 ),
PA_2 = (0 << PORT_SHIFT | 2 ),
PA_3 = (0 << PORT_SHIFT | 3 ),
PA_4 = (0 << PORT_SHIFT | 4 ),
PA_5 = (0 << PORT_SHIFT | 5 ),
PA_6 = (0 << PORT_SHIFT | 6 ),
PA_7 = (0 << PORT_SHIFT | 7 ),
PA_8 = (0 << PORT_SHIFT | 8 ),
PA_9 = (0 << PORT_SHIFT | 9 ),
PB_0 = (1 << PORT_SHIFT | 0 ),
PB_1 = (1 << PORT_SHIFT | 1 ),
PB_2 = (1 << PORT_SHIFT | 2 ),
PB_3 = (1 << PORT_SHIFT | 3 ),
PB_4 = (1 << PORT_SHIFT | 4 ),
PB_5 = (1 << PORT_SHIFT | 5 ),
PB_6 = (1 << PORT_SHIFT | 6 ),
PB_7 = (1 << PORT_SHIFT | 7 ),
PB_8 = (1 << PORT_SHIFT | 8 ),
PB_9 = (1 << PORT_SHIFT | 9 ),
PC_0 = (4 << PORT_SHIFT | 0 ),
PC_1 = (4 << PORT_SHIFT | 1 ),
PC_2 = (4 << PORT_SHIFT | 2 ),
PC_3 = (4 << PORT_SHIFT | 3 ),
PC_4 = (4 << PORT_SHIFT | 4 ),
PC_5 = (4 << PORT_SHIFT | 5 ),
PC_6 = (4 << PORT_SHIFT | 6 ),
PC_7 = (4 << PORT_SHIFT | 7 ),
PC_8 = (4 << PORT_SHIFT | 8 ),
PC_9 = (4 << PORT_SHIFT | 9 ),
PD_0 = (5 << PORT_SHIFT | 0 ),
PD_1 = (5 << PORT_SHIFT | 1 ),
PD_2 = (5 << PORT_SHIFT | 2 ),
PD_3 = (5 << PORT_SHIFT | 3 ),
PD_9 = (5 << PORT_SHIFT | 9 ), // Fake pin for GPADC_VBAT
UART0_RX = PA_0,
UART0_TX = PA_1,
UART1_RX = PB_1,
UART1_TX = PB_2,
USBRX = UART0_RX,
USBTX = UART0_TX,
I2C_SCL = PC_0,
I2C_SDA = PC_1,
I2S_TX_SD = PB_1,
I2S_TX_WS = PB_2,
I2S_TX_BCLK = PB_3,
I2S_RX_SD = PB_4,
I2S_RX_WS = PB_5,
I2S_RX_BCLK = PB_8,
GPIO_PIN0 = PB_0,
GPIO_PIN1 = PB_1,
GPIO_PIN2 = PB_2,
GPIO_PIN3 = PB_3,
GPIO_PIN4 = PB_4,
GPIO_PIN5 = PB_5,
GPIO_PIN6 = PB_6,
GPIO_PIN7 = PB_7,
GPIO_PIN8 = PB_8,
GPIO_PIN9 = PB_9,
GPIO_PIN10 = PA_8,
GPIO_PIN11 = PA_9,
GPIO_PIN12 = PC_0,
GPIO_PIN13 = PC_1,
GPIO_PIN14 = PC_2,
GPIO_PIN15 = PC_3,
GPIO_PIN16 = PC_4,
GPIO_PIN17 = PC_5,
GPIO_PIN18 = PC_6,
GPIO_PIN19 = PC_7,
GPIO_PIN20 = PC_8,
GPIO_PIN21 = PC_9,
GPIO_PIN22 = PD_0,
GPIO_PIN23 = PD_1,
GPIO_PIN24 = PD_2,
GPIO_PIN25 = PD_3,
GPIO_PIN26 = PA_0,
GPIO_PIN27 = PA_1,
// Another pin names for GPIO 14 - 19
GPIO_PIN14A = PA_2,
GPIO_PIN15A = PA_3,
GPIO_PIN16A = PA_4,
GPIO_PIN17A = PA_5,
GPIO_PIN18A = PA_6,
GPIO_PIN19A = PA_7,
ADC_PIN0 = PB_6,
ADC_PIN1 = PB_7,
ADC_PIN1A = PB_8, // Another pin name for ADC 1
ADC_PIN2 = PD_9,
LED1 = GPIO_PIN21,
LED2 = GPIO_PIN1,
// Arduino Pin Names
// Analog Ports (A0-A1)
A0 = PB_6,
A1 = PB_8,
// A2
// A3
// Digital Pins with "An" name
A4 = PB_2,
A5 = PB_3,
// Digital Port (D0-D7)
D0 = PB_1,
D1 = PB_2,
D2 = PB_3,
D3 = PB_4,
D4 = PB_5,
D5 = PB_7,
D6 = PB_9,
D7 = PC_9,
// Digital Port (D8-D13)
D8 = PB_0,
// D9
D10 = PD_1, // CS0
D11 = PD_2, // MOSI
D12 = PD_3, // MISO
D13 = PD_0, // CLK
// GND
// AREF
SDA = PC_1,
D14 = SDA,
SCL = PC_0,
D15 = SCL,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 2,
Repeater = 3,
PullDefault = Repeater,
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

33
targets/TARGET_RDA/TARGET_UNO_91H/PortNames.h Normal file
View File

@ -0,0 +1,33 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 4,
PortD = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

92
targets/TARGET_RDA/TARGET_UNO_91H/analogin_api.c Normal file
View File

@ -0,0 +1,92 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#include "pinmap.h"
#include "rda_ccfg_api.h"
#define ANALOGIN_MEDIAN_FILTER 1
#define RDA_ADC_RANGE (0x03FFU)
#if DEVICE_ANALOGIN
static const PinMap PinMap_ADC[] = {
{PB_6, ADC0_0, 0},
{PB_7, ADC0_1, 0},
{PB_8, ADC0_1, 0},
{PD_9, ADC0_2, 0},
{NC, NC, 0}
};
static unsigned char adc1_gp = 0U;
static int adc_inited_cnt = 0;
void analogin_init(analogin_t *obj, PinName pin)
{
unsigned char gp = (unsigned char)(pin & 0x00FFU);
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
/* Init ADC */
if (0 == adc_inited_cnt) {
rda_ccfg_adc_init();
}
adc_inited_cnt++;
if (ADC0_2 == obj->adc) {
return;
}
if ((ADC0_1 == obj->adc) && (0U == adc1_gp)) {
adc1_gp = (2 >= rda_ccfg_hwver()) ? 7U : 8U;
MBED_ASSERT(gp == adc1_gp);
}
rda_ccfg_gp(gp, 0x00U);
rda_ccfg_adc_gp(gp, 0x00U);
rda_ccfg_adc_oenb(obj->adc, 0x01U);
pinmap_pinout(pin, PinMap_ADC);
}
uint16_t analogin_read_u16(analogin_t *obj)
{
uint16_t value = rda_ccfg_adc_read((unsigned char)(obj->adc));
return (value); // 10 bit
}
float analogin_read(analogin_t *obj)
{
uint16_t value = rda_ccfg_adc_read((unsigned char)(obj->adc));
return (float)value * (1.0f / (float)RDA_ADC_RANGE);
}
void analogin_free(analogin_t *obj)
{
unsigned char gp = 6U;
adc_inited_cnt--;
if (0 == adc_inited_cnt) {
rda_ccfg_adc_free();
}
if (ADC0_2 == obj->adc) {
return;
}
if (ADC0_1 == obj->adc) {
if (0U == adc1_gp) {
return;
}
gp = adc1_gp;
}
rda_ccfg_adc_gp(gp, 0x01U);
rda_ccfg_gp(gp, 0x01U);
}
#endif /* DEVICE_ANALOGIN */

40
targets/TARGET_RDA/TARGET_UNO_91H/device.h Normal file
View File

@ -0,0 +1,40 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#endif

78
targets/TARGET_RDA/TARGET_UNO_91H/device/RDA5981_nvic_virtual.h Normal file
View File

@ -0,0 +1,78 @@
/**************************************************************************//**
* @file RDA5981_nvic_virtual.h
* @brief
* @version
* @date
******************************************************************************/
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __RDA5981_NVIC
#define __RDA5981_NVIC
//#include "cmsis.h"
//#include <stdint.h>
extern void rda_ccfg_ckrst(void);
extern void rda_wdt_softreset(void);
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __RDA5981_SystemReset(void)
{
rda_ccfg_ckrst () ;
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_VECTRESET_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
#define NVIC_GetActive __NVIC_GetActive
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __RDA5981_SystemReset
#ifdef __cplusplus
}
#endif
#endif

527
targets/TARGET_RDA/TARGET_UNO_91H/device/RDA5991H.h Normal file
View File

@ -0,0 +1,527 @@
/******************************************************************************
* @file RDA5991H.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
* RDA RDA5991H Device Series
* @version: V1.09
* @date: 07. June 2018
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __RDA5991H_H__
#define __RDA5991H_H__
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** RDA5991H Specific Interrupt Numbers ******************************************************/
SPIFLASH_IRQn = 0, /*!< SPI Flash Interrupt */
PTA_IRQn = 1, /*!< PTA Interrupt */
SDIO_IRQn = 2, /*!< SDIO Interrupt */
USBDMA_IRQn = 3, /*!< USBDMA Interrupt */
USB_IRQn = 4, /*!< USB Interrupt */
GPIO_IRQn = 5, /*!< GPIO Interrupt */
TIMER_IRQn = 6, /*!< Timer Interrupt */
UART0_IRQn = 7, /*!< UART0 Interrupt */
MACHW_IRQn = 8, /*!< MAC Hardware Interrupt */
UART1_IRQn = 9, /*!< UART1 Interrupt */
AHBDMA_IRQn = 10, /*!< AHBDMA Interrupt */
PSRAM_IRQn = 11, /*!< PSRAM Interrupt */
SDMMC_IRQn = 12, /*!< SDMMC Interrupt */
EXIF_IRQn = 13, /*!< EXIF Interrupt */
I2C_IRQn = 14 /*!< I2C Interrupt */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M4 Processor and Core Peripherals */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_RDA5991H.h" /* System Header */
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*------------- System Control Unit (SCU) ------------------------------------*/
typedef struct
{
__IO uint32_t CLKGATE0; /* 0x00 : Clock Gating 0 */
__IO uint32_t PWRCTRL; /* 0x04 : Power Control */
__IO uint32_t CLKGATE1; /* 0x08 : Clock Gating 1 */
__IO uint32_t CLKGATE2; /* 0x0C : Clock Gating 2 */
__IO uint32_t RESETCTRL; /* 0x10 : Power Control */
__IO uint32_t CLKGATE3; /* 0x14 : Clock Gating 3 */
__IO uint32_t CORECFG; /* 0x18 : Core Config */
__IO uint32_t CPUCFG; /* 0x1C : CPU Config */
__IO uint32_t FTMRINITVAL; /* 0x20 : Free Timer Initial Value */
__IO uint32_t FTMRTS; /* 0x24 : Free Timer Timestamp */
__IO uint32_t CLKGATEBP; /* 0x28 : Clock Gating Bypass */
uint32_t RESERVED0[2];
__IO uint32_t PWMCFG; /* 0x34 : PWM Config */
__IO uint32_t FUN0WAKEVAL; /* 0x38 : SDIO Func0 Wake Val */
__IO uint32_t FUN1WAKEVAL; /* 0x3C : SDIO Func1 Wake Val */
__IO uint32_t BOOTJUMPADDR; /* 0x40 : Boot Jump Addr */
__IO uint32_t SDIOINTVAL; /* 0x44 : SDIO Int Val */
__IO uint32_t I2SCLKDIV; /* 0x48 : I2S Clock Divider */
__IO uint32_t BOOTJUMPADDRCFG; /* 0x4C : Boot Jump Addr Config */
__IO uint32_t FTMRPREVAL; /* 0x50 : Free Timer Prescale Init Val*/
__IO uint32_t PWROPENCFG; /* 0x54 : Power Open Config */
__IO uint32_t PWRCLOSECFG; /* 0x58 : Power Close Config */
} RDA_SCU_TypeDef;
/*------------- Timer0 (TIM0) ------------------------------------------------*/
typedef struct
{
__IO uint32_t LDCNT; /* 0x00 : Timer Load Count Register */
__I uint32_t CVAL; /* 0x04 : Current Timer Value Register*/
__IO uint32_t TCTRL; /* 0x08 : Timer Control Register */
__I uint32_t INTCLR; /* 0x0C : Interrupt Clear Register */
} RDA_TIM0_TypeDef;
/*------------- Timer1 (TIM1) ------------------------------------------------*/
typedef struct
{
__IO uint32_t TCTRL; /* 0x00 : Timer Control Register */
uint32_t RESERVED0[2];
__IO uint32_t LDCNT; /* 0x0C : Timer Load Count Register */
__I uint32_t CVAL; /* 0x10 : Current Timer Value Register*/
uint32_t RESERVED1;
__I uint32_t INTCLR; /* 0x18 : Interrupt Clear Register */
} RDA_TIM1_TypeDef;
/*------------- Timer Interrupt Status (TIMINTST) ----------------------------*/
typedef struct
{
__I uint32_t INTST; /* 0x00 : Timer Int Stat Register */
} RDA_TIMINTST_TypeDef;
/*------------- General Purpose Input/Output (GPIO) --------------------------*/
typedef struct
{
__IO uint32_t CTRL; /* 0x00 : GPIO Control */
uint32_t RESERVED0;
__IO uint32_t DOUT; /* 0x08 : GPIO Data Output */
__IO uint32_t DIN; /* 0x0C : GPIO Data Input */
__IO uint32_t DIR; /* 0x10 : GPIO Direction */
__IO uint32_t SLEW0; /* 0x14 : GPIO Slew Config 0 */
__IO uint32_t SLEWIOMUX; /* 0x18 : GPIO IOMUX Slew Config */
__IO uint32_t INTCTRL; /* 0x1C : GPIO Interrupt Control */
__IO uint32_t IFCTRL; /* 0x20 : Interface Control */
__IO uint32_t SLEW1; /* 0x24 : GPIO Slew Config 1 */
__IO uint32_t REVID; /* 0x28 : ASIC Reversion ID */
__IO uint32_t LPOSEL; /* 0x2C : LPO Select */
uint32_t RESERVED1;
__IO uint32_t INTSEL; /* 0x34 : GPIO Interrupt Select */
uint32_t RESERVED2;
__IO uint32_t SDIOCFG; /* 0x3C : SDIO Config */
__IO uint32_t MEMCFG; /* 0x40 : Memory Config */
__IO uint32_t IOMUXCTRL[8]; /* 0x44 - 0x60 : IOMUX Control */
__IO uint32_t PCCTRL; /* 0x64 : Pulse Counter Control */
} RDA_GPIO_TypeDef;
/*------------- Inter-Integrated Circuit 0 (I2C0) ----------------------------*/
typedef struct
{
__IO uint32_t CR0; /* 0x00 : Control Register 0 */
__I uint32_t SR; /* 0x04 : Status Register */
__IO uint32_t DR; /* 0x08 : TX/RX Data Register */
__O uint32_t CMD; /* 0x0C : Command Register */
__O uint32_t ICR; /* 0x10 : Interrupt Clear Register */
__IO uint32_t CR1; /* 0x14 : Control Register 1 */
} RDA_I2C0_TypeDef;
/*------------- Pulse Width Modulator (PWM) ----------------------------------*/
typedef struct
{
__IO uint32_t PWTCFG; /* 0x00 : PWT Config Register */
__IO uint32_t LPGCFG; /* 0x04 : LPG Config Register */
__IO uint32_t PWL0CFG; /* 0x08 : PWL0 Config Register */
__IO uint32_t PWL1CFG; /* 0x0C : PWL1 Config Register */
__IO uint32_t CLKR; /* 0x10 : Clock Config Register */
} RDA_PWM_TypeDef;
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct
{
union {
__I uint32_t RBR; /* 0x00 : UART Receive buffer register */
__O uint32_t THR; /* 0x00 : UART Transmit holding register */
__IO uint32_t DLL; /* 0x00 : UART Divisor latch(low) */
};
union {
__IO uint32_t DLH; /* 0x04 : UART Divisor latch(high) */
__IO uint32_t IER; /* 0x04 : UART Interrupt enable register */
};
union {
__I uint32_t IIR; /* 0x08 : UART Interrupt id register */
__O uint32_t FCR; /* 0x08 : UART Fifo control register */
};
__IO uint32_t LCR; /* 0x0C : UART Line control register */
__IO uint32_t MCR; /* 0x10 : UART Moderm control register */
__I uint32_t LSR; /* 0x14 : UART Line status register */
__I uint32_t MSR; /* 0x18 : UART Moderm status register */
__IO uint32_t SCR; /* 0x1C : UART Scratchpad register */
__I uint32_t FSR; /* 0x20 : UART FIFO status register */
__IO uint32_t FRR; /* 0x24 : UART FIFO tx/rx trigger resiger */
__IO uint32_t DL2; /* 0x28 : UART Baud rate adjust register */
__I uint32_t RESERVED0[4];
__I uint32_t BAUD; /* 0x3C : UART Auto baud counter */
__I uint32_t DL_SLOW; /* 0x40 : UART Divisor Adjust when slow clk */
__I uint32_t DL_FAST; /* 0x44 : UART Divisor Adjust when fast clk */
} RDA_UART_TypeDef;
/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
typedef struct
{
__IO uint32_t CFG;
__IO uint32_t D0CMD;
__IO uint32_t D1CMD;
} RDA_SPI_TypeDef;
/*------------- Integrated Interchip Sound (I2S) -----------------------------*/
typedef struct
{
__IO uint32_t CFG;
__IO uint32_t DOUTWR;
__I uint32_t DINRD;
} RDA_I2S_TypeDef;
/*------------- External Interface (EXIF) ------------------------------------*/
typedef struct
{
RDA_SPI_TypeDef SPI0; /* 0x00 - 0x08 : SPI0 registers group */
RDA_I2S_TypeDef I2S; /* 0x0C - 0x14 : I2S registers group */
__IO uint32_t MISCSTCFG; /* 0x18 : Misc status config register */
__IO uint32_t SPI1CTRL; /* 0x1C : SPI1 Control register */
uint32_t RESERVED0[4];
__IO uint32_t MISCINTCFG; /* 0x30 : Misc int config register */
__IO uint32_t MBB2W; /* 0x34 : BT to WiFi mailbox register */
__IO uint32_t MBW2B; /* 0x38 : WiFi to BT mailbox register */
__IO uint32_t MISCCFG; /* 0x3C : Misc configure register */
__IO uint32_t PWM0CFG; /* 0x40 : PWM0 configure register */
__IO uint32_t PWM1CFG; /* 0x44 : PWM1 configure register */
__IO uint32_t PWM2CFG; /* 0x48 : PWM2 configure register */
__IO uint32_t PWM3CFG; /* 0x4C : PWM3 configure register */
} RDA_EXIF_TypeDef;
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
typedef struct
{
__IO uint32_t WDTCFG;
} RDA_WDT_TypeDef;
/*------------- Pin Configure (PINCFG) ---------------------------------------*/
typedef struct
{
union {
__IO uint32_t IOMUXCTRL[8];
struct {
__IO uint32_t MUX0;
__IO uint32_t MUX1;
__IO uint32_t MODE0;
__IO uint32_t MODE1;
__IO uint32_t MUX2;
__IO uint32_t MUX3;
__IO uint32_t MODE2;
__IO uint32_t MODE3;
};
};
} RDA_PINCFG_TypeDef;
/*------------- AHB Direct Memory Access (DMA) -------------------------------*/
typedef struct
{
__IO uint32_t dma_ctrl; /* 0x00 : DMA ctrl */
__IO uint32_t dma_src; /* 0x04 : DMA src */
__IO uint32_t dma_dst; /* 0x08 : DMA dst */
__IO uint32_t dma_len; /* 0x0c : DMA len */
__IO uint32_t crc_gen; /* 0x10 : CRC gen */
__IO uint32_t dma_func_ctrl; /* 0x14 : DMA func ctrl */
__IO uint32_t aes_key0; /* 0x18 : AES key 0 */
__IO uint32_t aes_key1; /* 0x1c : AES key 1 */
__IO uint32_t aes_key2; /* 0x20 : AES key 2 */
__IO uint32_t aes_key3; /* 0x24 : AES key 2 */
__IO uint32_t aes_iv0; /* 0x28 : AES iv 0 */
__IO uint32_t aes_iv1; /* 0x2c : AES iv 1 */
__IO uint32_t aes_iv2; /* 0x30 : AES iv 2 */
__IO uint32_t aes_iv3; /* 0x34 : AES iv 2 */
__IO uint32_t aes_mode; /* 0x38 : AES mode */
__IO uint32_t cios_ctrl; /* 0x3c : cios ctrl */
__IO uint32_t cios_reg0; /* 0x40 : cios reg 0 */
__IO uint32_t crc_init_val; /* 0x44 : CRC init val */
__IO uint32_t crc_out_xorval; /* 0x48 : CRC out xorval */
__I uint32_t crc_out_val; /* 0x4c : CRC out val */
uint32_t RESERVED0[12];
__IO uint32_t dma_int_out; /* 0x80 : DMA int out */
__IO uint32_t dma_int_mask; /* 0x84 : DMA int mask */
uint32_t RESERVED1[478];
__IO uint32_t cios_data_base; /* 0x800 : CIOS data base */
} RDA_DMACFG_TypeDef;
/*------------- Random Number Generator (RNG) --------------------------------*/
typedef struct
{
__IO uint32_t TCTRL; /* 0x00 : TRNG ctrl */
__IO uint32_t PCTRL; /* 0x04 : PRNG ctrl */
__IO uint32_t PSEED; /* 0x08 : PRNG seed */
__IO uint32_t PTMRINIT; /* 0x0C : PRNG timer init */
__I uint32_t PTMR; /* 0x10 : PRNG timer */
__I uint32_t TD0; /* 0x14 : TRNG data 0 */
__I uint32_t TD0MSK; /* 0x18 : TRNG data 0 mask */
__I uint32_t TD1; /* 0x1C : TRNG data 1 */
__I uint32_t TD1MSK; /* 0x20 : TRNG data 1 mask */
__I uint32_t PD; /* 0x24 : PRNG data */
__I uint32_t THC; /* 0x28 : TRNG h/c value */
} RDA_RNG_TypeDef;
/*------------- Universal Serial Bus (USB) -------------------------------------------*/
typedef struct
{
struct {
__IO uint8_t FUNC_ADDR; /* 0x00: Function Address */
__IO uint8_t POWER; /* 0x01: Power */
__IO uint16_t INTRTX; /* 0x02-0x03: IntrTx */
};
struct {
__IO uint16_t INTRRX; /* 0x04-0x05: IntrRx */
__IO uint16_t INTRTXEN; /* 0x06-0x07: IntrTx Enable */
};
struct {
__IO uint16_t INTRRXEN; /* 0x08-0x09: IntrRx Enable */
__IO uint8_t INTR; /* 0x0a: Interrupt */
__IO uint8_t INTREN; /* 0x0b: Intr Enable */
};
struct {
__IO uint16_t FRAMENUM; /* 0x0c-0x0d: Frame Number */
__IO uint8_t EPIDX; /* 0x0e: Endpoint Index */
__IO uint8_t TESTMODE; /* 0x0f: Test Mode */
};
struct {
__IO uint16_t TXMAXPKTSIZE; /* 0x10-0x11: Tx Max Packet Size */
union {
__IO uint16_t CSR0; /* 0x12-0x13: CSR0 */
__IO uint16_t TXCSR; /* 0x12-0x13: CSR0 */
};
};
struct {
__IO uint16_t RXMAXPKTSIZE; /* 0x14-0x15: Rx Max Packet Size */
__IO uint16_t RXCSR; /* 0x16-0x17: Rx CSR */
};
struct {
union {
__IO uint16_t RXCOUNT0; /* 0x18-0x19: Rx Counter of EP0 */
__IO uint16_t RXCOUNT; /* 0x18-0x19: Rx Counter of Rx EP */
};
#if 0
uint16_t RESERVED0; /* 0x1a-0x1b: reserved */
#else
/* host mode only */
__IO uint8_t TXTYPE; /* 0x1a: TxType */
__IO uint8_t TXINTERVAL; /* 0x1B: TxInterval */
#endif
};
struct {
__IO uint8_t RXTYPE; /* 0x1c: rxtype */
__IO uint8_t RXINTERVAL; /* 0x1d: rxInterval */
uint8_t RESERVED1[1]; /* 0x1e: reserved */
union {
__IO uint8_t CONFIGDATA; /* 0x1f: Data of Core Configuration */
__IO uint8_t FIFOSIZE; /* 0x1f: Size of Selected TX/RX Fifo */
};
};
__IO uint32_t FIFOs[16]; /* 0x20-0x5F: fifos for Endpoint */
struct {
__IO uint8_t DEVCTL; /* 0x60: OTG device control */
uint8_t RESERVED2; /* 0x61: unused */
__IO uint8_t TXFIFOSZ; /* 0x62: Tx Endpoint FIFO Size */
__IO uint8_t RXFIFOSZ; /* 0x63: Rx Endpoint FIFO Size */
};
struct {
__IO uint16_t TXFIFOADDR; /* 0x64-0x65: Tx Endpoint FIFO Address */
__IO uint16_t RXFIFOADDR; /* 0x66-0x67: Rx Endpoint FIFO Address */
};
union {
__IO uint32_t VCONTROL; /* 0x68-0x6b: UTMI+PHY Vendor Register */
__IO uint32_t VSTATUS; /* 0x68-0x6b: UTMI+PHY Vendor Register */
};
struct {
__IO uint16_t HWVERSION; /* 0x6c-0x6d: Hardware Version Number Register */
uint16_t RESERVED3; /* 0x6e-0x6f: Unused */
};
__IO uint8_t ULPIREG[8]; /* 0x70-0x77: ulpi register, not used */
struct {
__IO uint8_t EPINFO; /* 0x78: numbers of tx/rx ep */
__IO uint8_t RAMINFO; /* 0x79: width of RAM and number of DMA channels */
__IO uint8_t LINKINFO; /* 0x7a: delays to be applied */
__IO uint8_t VPLEN; /* 0x7b: Duration of the VBus pulsing charge */
};
struct {
__IO uint8_t HSEOF; /* 0x7c: Timer buffer available on HS transaction */
__IO uint8_t FSEOF; /* 0x7d: Timer buffer available on HS transaction */
__IO uint8_t LSEOF; /* 0x7e: Timer buffer available on HS transaction */
uint8_t RESERVED4; /* 0x7f: unused */
};
uint32_t RESERVED5[3]; /* 0x80-0x8b: unused */
__IO uint32_t FIFO_CTRL; /* 0x8c: FIFO Control */
__IO uint32_t ANAREG2; /* 0x90-0x93 */
uint32_t RESERVED6[91]; /* 0x94-0x1ff: unused */
struct {
__IO uint8_t DMAINTR; /* 0x200: DMA Interrrupt */
__IO uint8_t RESERVED7[3]; /* 0x201-0x203: unused; */
};
__IO uint32_t DMACTRL0; /* 0x204: channel 0 */
__IO uint32_t DMAADDR0; /* 0x208: AHB Memory Address channel 0 */
__IO uint32_t COUNT0; /* 0x20c: DMA Counter for channel 0 */
uint32_t RESERVED8; /* 0x210-0x213: unused */
__IO uint32_t DMACTRL1; /* 0x214: channel 1 */
__IO uint32_t DMAADDR1; /* 0x218: AHB Memory Address channel 1 */
__IO uint32_t COUNT1; /* 0x21c: DMA Counter for channel 1 */
uint8_t RESERVED9[224]; /* 0x220 - 0x2FF: unused */
__IO uint32_t PKCNT0; /* 0X300: packet count epnum 0 */
__IO uint32_t PKCNT1; /* 0X304: packet count epnum 1 */
__IO uint32_t PKCNT2; /* 0X308:packet count epnum 1 */
}RDA_USB_TypeDef;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
//#define RDA_ICACHE_DISABLE
#define RDA_PARTITION_INDEX 0
/* Base addresses */
#define RDA_ROM_BASE (0x00000000UL)
#define RDA_IRAM_BASE (0x00100000UL)
#define RDA_DRAM_BASE (0x00180000UL)
#define RDA_PSRAM_BASE (0x10000000UL)
#define RDA_FLASH_BASE (0x14000000UL)
#define RDA_ICACHE_BASE (0x18000000UL)
#if (0 == RDA_PARTITION_INDEX)
#define RDA_PADDR_OFST (0x00001000UL)
#elif (1 == RDA_PARTITION_INDEX)
#define RDA_PADDR_OFST (0x0007E000UL)
#else
#error "Not supported"
#endif
#if defined(RDA_ICACHE_DISABLE)
#define RDA_CODE_BASE (RDA_FLASH_BASE + RDA_PADDR_OFST)
#else /* RDA_ICACHE_DISABLE */
#define RDA_CODE_BASE (RDA_ICACHE_BASE + RDA_PADDR_OFST)
#endif /* RDA_ICACHE_DISABLE */
#define RDA_PER_BASE (0x40000000UL)
#define RDA_AHB0_BASE (0x40000000UL)
#define RDA_APB_BASE (RDA_AHB0_BASE)
#define RDA_AHB1_BASE (0x40100000UL)
#define RDA_PERBTBND_BASE (0x42000000UL)
#define RDA_CM4_BASE (0xE0000000UL)
/* APB peripherals */
#define RDA_SCU_BASE (RDA_APB_BASE + 0x00000)
#define RDA_GPIO_BASE (RDA_APB_BASE + 0x01000)
#define RDA_TIM0_BASE (RDA_APB_BASE + 0x02000)
#define RDA_TIM1_BASE (RDA_APB_BASE + 0x02008)
#define RDA_TIMINTST_BASE (RDA_APB_BASE + 0x02010)
#define RDA_I2C0_BASE (RDA_APB_BASE + 0x03000)
/* AHB0 peripherals */
#define RDA_PWM_BASE (RDA_AHB0_BASE + 0x04000)
#define RDA_PSRAMCFG_BASE (RDA_AHB0_BASE + 0x05000)
#define RDA_SDMMC_BASE (RDA_AHB0_BASE + 0x06000)
#define RDA_I2C_BASE (RDA_AHB0_BASE + 0x10000)
#define RDA_TRAP_BASE (RDA_AHB0_BASE + 0x11000)
#define RDA_UART0_BASE (RDA_AHB0_BASE + 0x12000)
#define RDA_EXIF_BASE (RDA_AHB0_BASE + 0x13000)
#define RDA_PA_BASE (RDA_AHB0_BASE + 0x20000)
#define RDA_CE_BASE (RDA_AHB0_BASE + 0x22000)
#define RDA_MON_BASE (RDA_AHB0_BASE + 0x24000)
#define RDA_SDIO_BASE (RDA_AHB0_BASE + 0x30000)
#define RDA_USB_BASE (RDA_AHB0_BASE + 0x31000)
/* AHB1 peripherals */
#define RDA_MEMC_BASE (RDA_AHB1_BASE + 0x00000)
#define RDA_UART1_BASE (RDA_AHB1_BASE + 0x80000)
#define RDA_DMACFG_BASE (RDA_AHB1_BASE + 0x81000)
#define RDA_RNG_BASE (RDA_AHB1_BASE + 0x81100)
/* EXIF peripherals */
#define RDA_SPI0_BASE (RDA_EXIF_BASE + 0x00000)
#define RDA_I2S_BASE (RDA_EXIF_BASE + 0x0000C)
/* MISC peripherals */
#define RDA_WDT_BASE (RDA_SCU_BASE + 0x0000C)
#define RDA_PINCFG_BASE (RDA_GPIO_BASE + 0x00044)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define RDA_SCU ((RDA_SCU_TypeDef *) RDA_SCU_BASE )
#define RDA_GPIO ((RDA_GPIO_TypeDef *) RDA_GPIO_BASE )
#define RDA_TIM0 ((RDA_TIM0_TypeDef *) RDA_TIM0_BASE )
#define RDA_TIM1 ((RDA_TIM1_TypeDef *) RDA_TIM1_BASE )
#define RDA_TIMINTST ((RDA_TIMINTST_TypeDef *) RDA_TIMINTST_BASE )
#define RDA_I2C0 ((RDA_I2C0_TypeDef *) RDA_I2C0_BASE )
#define RDA_PWM ((RDA_PWM_TypeDef *) RDA_PWM_BASE )
#define RDA_UART0 ((RDA_UART_TypeDef *) RDA_UART0_BASE )
#define RDA_UART1 ((RDA_UART_TypeDef *) RDA_UART1_BASE )
#define RDA_SPI0 ((RDA_SPI_TypeDef *) RDA_SPI0_BASE )
#define RDA_I2S ((RDA_I2S_TypeDef *) RDA_I2S_BASE )
#define RDA_EXIF ((RDA_EXIF_TypeDef *) RDA_EXIF_BASE )
#define RDA_WDT ((RDA_WDT_TypeDef *) RDA_WDT_BASE )
#define RDA_PINCFG ((RDA_PINCFG_TypeDef *) RDA_PINCFG_BASE )
#define RDA_DMACFG ((RDA_DMACFG_TypeDef *) RDA_DMACFG_BASE )
#define RDA_RNG ((RDA_RNG_TypeDef *) RDA_RNG_BASE )
#define RDA_USB ((RDA_USB_TypeDef *) RDA_USB_BASE )
#endif /* __RDA5991H_H__ */

57
targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_ARM_STD/TARGET_UNO_91H/RDA5981C.sct Normal file
View File

@ -0,0 +1,57 @@
#! armcc -E
//#define RDA_ICACHE_DISABLE
#define RDA_PARTITION_INDEX 0
#define RDA_ROM_BASE (0x00000000)
#define RDA_IRAM_BASE (0x00100000)
#define RDA_IRAM_SIZE (0x00020000)
#define RDA_DRAM_BASE (0x00180000)
#define RDA_DRAM_SIZE (0x00028000)
#define RDA_PSRAM_BASE (0x10000000)
#define RDA_FLASH_BASE (0x14000000)
#define RDA_ICACHE_BASE (0x18000000)
#if (0 == RDA_PARTITION_INDEX)
#define RDA_PADDR_OFST (0x00001000)
#elif (1 == RDA_PARTITION_INDEX)
#define RDA_PADDR_OFST (0x001F5000)
#else
#error "Not supported"
#endif
#if defined(RDA_ICACHE_DISABLE)
#define RDA_CODE_BASE (RDA_FLASH_BASE + RDA_PADDR_OFST)
#else /* RDA_ICACHE_DISABLE */
#define RDA_CODE_BASE (RDA_ICACHE_BASE + RDA_PADDR_OFST)
#endif /* RDA_ICACHE_DISABLE */
#define RDA_CODE_SIZE (0x001F4000)
#define RDA_AHB1_BASE (0x40100000)
#define RDA_MEMC_BASE (RDA_AHB1_BASE + 0x00000)
; max code size: RDA_CODE_SIZE
LR_IROM1 RDA_CODE_BASE RDA_CODE_SIZE { ; load region size_region
ER_IROM0 RDA_CODE_BASE RDA_CODE_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 8_byte_aligned(31 vect * 4 bytes) = 8_byte_aligned(0x7C) = 0x80
ER_IRAMVEC RDA_IRAM_BASE EMPTY 0x80 { ; Reserved for vectors
}
; IRAM Size: Total(128KB) - Vector(128B) - Stack(2KB)
RW_IRAM1 AlignExpr(+0, 8) (0x20000 - 0x80 - 0x800) {
.ANY (+RW +ZI)
}
ARM_LIB_STACK AlignExpr(+0, 8) EMPTY (RDA_IRAM_BASE + RDA_IRAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 8)) {
}
ARM_LIB_HEAP RDA_DRAM_BASE EMPTY RDA_DRAM_SIZE {
}
RW_IRAM2 RDA_MEMC_BASE 0x18C00 { ; RW data, MACLIB_RAM
.ANY (SECTIONRESERVED1)
}
RW_IRAM3 (RDA_MEMC_BASE + 0x18C00) 0x0C00 { ; RW data, AES_RAM
.ANY (AHB1SMEM0)
}
RW_IRAM4 (RDA_MEMC_BASE + 0x19800) 0x6800 { ; RW data, WLAN RAM
.ANY (AHB1SMEM1)
}
}

180
targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_ARM_STD/startup_RDA5991H.S Normal file
View File

@ -0,0 +1,180 @@
;/*****************************************************************************
; * @file: startup_RDA5991H.s
; * @purpose: CMSIS Cortex-M4 Core Device Startup File
; * for the RDA RDA5991H Device Series
; * @version: V1.02, modified for mbed
; * @date: 07. June 2018
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2009 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| [WEAK]
EXPORT __Vectors
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD SPIFLASH_IRQHandler ; 16: SPI Flash
DCD PTA_IRQHandler ; 17: PTA
DCD SDIO_IRQHandler ; 18: SDIO
DCD USBDMA_IRQHandler ; 19: USB DMA
DCD USB_IRQHandler ; 20: USB
DCD GPIO_IRQHandler ; 21: GPIO
DCD TIMER0_IRQHandler ; 22: Timer0
DCD UART0_IRQHandler ; 23: UART0
DCD MACHW_IRQHandler ; 24: MAC Hardware
DCD UART1_IRQHandler ; 25: UART1
DCD AHBDMA_IRQHandler ; 26: AHB DMA
DCD PSRAM_IRQHandler ; 27: PSRAM
DCD SDMMC_IRQHandler ; 28: SDMMC
DCD EXIF_IRQHandler ; 29: EXIF
DCD I2C_IRQHandler ; 30: I2C
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT rda_ccfg_boot
IMPORT SystemInit
IMPORT __main
LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
MSR MSP, R0
LDR R0, =rda_ccfg_boot
BLX R0
CMP R0, #0x01
BNE Soft_Reset
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Soft Reset
Soft_Reset PROC
MOV R1, #0x04
LDR R0, [R1]
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SPIFLASH_IRQHandler [WEAK]
EXPORT PTA_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT USBDMA_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT GPIO_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT MACHW_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT AHBDMA_IRQHandler [WEAK]
EXPORT PSRAM_IRQHandler [WEAK]
EXPORT SDMMC_IRQHandler [WEAK]
EXPORT EXIF_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
SPIFLASH_IRQHandler
PTA_IRQHandler
SDIO_IRQHandler
USBDMA_IRQHandler
USB_IRQHandler
GPIO_IRQHandler
TIMER0_IRQHandler
UART0_IRQHandler
MACHW_IRQHandler
UART1_IRQHandler
AHBDMA_IRQHandler
PSRAM_IRQHandler
SDMMC_IRQHandler
EXIF_IRQHandler
I2C_IRQHandler
B .
ENDP
ALIGN
END

36
targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_ARM_STD/sys.cpp Normal file
View File

@ -0,0 +1,36 @@
/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2018 ARM Limited. All rights reserved.
*
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*/
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include <arm_compat.h>
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$ARM_LIB_HEAP$$ZI$$Base[];
extern char Image$$ARM_LIB_HEAP$$ZI$$Length[];
extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
{
uint32_t hp_base = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Base;
uint32_t hp_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Length + hp_base;
struct __initial_stackheap r;
hp_base = (hp_base + 7) & ~0x7; // ensure hp_base is 8-byte aligned
r.heap_base = hp_base;
r.heap_limit = hp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

192
targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_GCC_ARM/TARGET_UNO_91H/RDA5981C.ld Normal file
View File

@ -0,0 +1,192 @@
/* Linker script for mbed RDA5981C */
/* Linker script to configure memory regions. */
MEMORY
{
/* If ICache is enable, use virtual flash base address */
/* Use partition index: 0 */
FLASH (rx) : ORIGIN = 0x18001000, LENGTH = 2000K
/* Use partition index: 1 */
/* FLASH (rx) : ORIGIN = 0x181F5000, LENGTH = 2000K */
/* If ICache is disable, use real flash base address. Depends on macro: RDA_ICACHE_DISABLE */
/* Use partition index: 0 */
/* FLASH (rx) : ORIGIN = 0x14001000, LENGTH = 2000K */
/* Use partition index: 1 */
/* FLASH (rx) : ORIGIN = 0x141F5000, LENGTH = 2000K */
IRAM (rwx) : ORIGIN = 0x00100080, LENGTH = (128K - 0x80)
DRAM (rwx) : ORIGIN = 0x00180000, LENGTH = 160K
MACLIB_RAM(rwx) : ORIGIN = 0x40100000, LENGTH = 99K
AES_RAM(rwx) : ORIGIN = 0x40118C00, LENGTH = 1K
WLAN_RAM(rwx) : ORIGIN = 0x40119000, LENGTH = 28K
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
Image$$RW_IRAM1$$Base = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > IRAM
.bss :
{
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
Image$$RW_IRAM1$$ZI$$Limit = . ;
} > IRAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > IRAM
/* Set stack top to end of IRAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(IRAM) + LENGTH(IRAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + stack exceeds RAM limit */
ASSERT(__StackLimit >= __bss_end__, "region IRAM overflowed with stack")
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > DRAM
PROVIDE(__sbrk_start = ADDR(.heap));
PROVIDE(__krbs_start = ADDR(.heap) + SIZEOF(.heap));
/* Code can explicitly ask for data to be
placed in these higher RAM banks where
they will be left uninitialized.
*/
.SECTIONRESERVED1 (NOLOAD):
{
Image$$RW_IRAM2$$Base = . ;
*(SECTIONRESERVED1)
Image$$RW_IRAM2$$ZI$$Limit = .;
} > MACLIB_RAM
.AHB1SMEM0 (NOLOAD):
{
Image$$RW_IRAM3$$Base = . ;
*(AHB1SMEM0)
Image$$RW_IRAM3$$ZI$$Limit = .;
} > AES_RAM
.AHB1SMEM1 (NOLOAD):
{
Image$$RW_IRAM4$$Base = . ;
*(AHB1SMEM1)
Image$$RW_IRAM4$$ZI$$Limit = .;
} > WLAN_RAM
}

196
targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_GCC_ARM/TARGET_UNO_91H/startup_RDA5981C.S Normal file
View File

@ -0,0 +1,196 @@
/* File: startup_ARMCM4.s
* Purpose: startup file for Cortex-M3/M4 devices. Should use with
* GNU Tools for ARM Embedded Processors
* Version: V1.1
* Date: 17 June 2018
*
* Copyright (C) 2011 ARM Limited. All rights reserved.
* ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*/
.syntax unified
.arch armv7-m
/* Memory Model
The HEAP starts at the end of the DATA section and grows upward.
The STACK starts at the end of the RAM and grows downward.
The HEAP and stack STACK are only checked at compile time:
(DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
This is just a check for the bare minimum for the Heap+Stack area before
aborting compilation, it is not the run time limit:
Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
*/
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x800
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0x28000
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
.long SPIFLASH_IRQHandler /* 16: SPI Flash */
.long PTA_IRQHandler /* 17: PTA */
.long SDIO_IRQHandler /* 18: SDIO */
.long USBDMA_IRQHandler /* 19: USB DMA */
.long USB_IRQHandler /* 20: USB */
.long GPIO_IRQHandler /* 21: GPIO */
.long TIMER0_IRQHandler /* 22: Timer0 */
.long UART0_IRQHandler /* 23: UART0 */
.long MACHW_IRQHandler /* 24: MAC Hardware */
.long UART1_IRQHandler /* 25: UART1 */
.long AHBDMA_IRQHandler /* 26: AHB DMA */
.long PSRAM_IRQHandler /* 27: PSRAM */
.long SDMMC_IRQHandler /* 28: SDMMC */
.long EXIF_IRQHandler /* 29: EXIF */
.long I2C_IRQHandler /* 30: I2C */
.size __isr_vector, . - __isr_vector
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* _etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r0, =__StackTop
msr msp, r0
ldr r0, =rda_ccfg_boot
blx r0
cmp r0, #0x01
bne Soft_Reset
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.Lflash_to_ram_loop:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .Lflash_to_ram_loop
ldr r0, =SystemInit
blx r0
ldr r0, =_start
bx r0
Soft_Reset:
mov r1, #0x04
ldr r0, [r1]
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
def_default_handler Default_Handler
.macro def_irq_default_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_default_handler SPIFLASH_IRQHandler
def_irq_default_handler PTA_IRQHandler
def_irq_default_handler SDIO_IRQHandler
def_irq_default_handler USBDMA_IRQHandler
def_irq_default_handler USB_IRQHandler
def_irq_default_handler GPIO_IRQHandler
def_irq_default_handler TIMER0_IRQHandler
def_irq_default_handler UART0_IRQHandler
def_irq_default_handler MACHW_IRQHandler
def_irq_default_handler UART1_IRQHandler
def_irq_default_handler AHBDMA_IRQHandler
def_irq_default_handler PSRAM_IRQHandler
def_irq_default_handler SDMMC_IRQHandler
def_irq_default_handler EXIF_IRQHandler
def_irq_default_handler I2C_IRQHandler
.end

37
targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_GCC_ARM/rda_retarget.c Normal file
View File

@ -0,0 +1,37 @@
/* mbed Microcontroller Library
* Copyright (c) 2009-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined(TWO_RAM_REGIONS)
#include <stdint.h>
#include <errno.h>
extern uint32_t __sbrk_start;
extern uint32_t __krbs_start;
/* Overide _sbrk() to support two region model */
void *__wrap__sbrk(int incr)
{
static uint32_t heap_ind = (uint32_t)(&__sbrk_start);
uint32_t heap_ind_pre = heap_ind;
uint32_t heap_ind_new = (heap_ind_pre + incr + 0x07) & ~0x07;
if (heap_ind_new > (uint32_t)(&__krbs_start)) {
errno = ENOMEM;
return (void *)(-1);
}
heap_ind = heap_ind_new;
return (void *) heap_ind_pre;
}
#endif

64
targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_IAR/TARGET_UNO_91H/RDA5981C.icf Normal file
View File

@ -0,0 +1,64 @@
/* Linker file for the IAR Compiler for ARM */
/* Specials */
define symbol RDA_ICACHE_DISABLE = 0;
define symbol RDA_PARTITION_INDEX = 0;
/* Memory Regions */
define symbol RDA_IRAM_BASE = 0x00100000;
define symbol RDA_IRAM_END = 0x0011FFFF;
define symbol RDA_DRAM_BASE = 0x00180000;
define symbol RDA_DRAM_END = 0x001A7FFF;
define symbol RDA_FLASH_BASE = 0x14000000;
define symbol RDA_ICACHE_BASE = 0x18000000;
if (0 == RDA_PARTITION_INDEX) {
define symbol RDA_PADDR_OFST = 0x00001000;
} else {
define symbol RDA_PADDR_OFST = 0x001F5000;
}
if (1 == RDA_ICACHE_DISABLE) {
define symbol RDA_CODE_BASE = RDA_FLASH_BASE + RDA_PADDR_OFST;
} else {
define symbol RDA_CODE_BASE = RDA_ICACHE_BASE + RDA_PADDR_OFST;
}
define symbol RDA_CODE_END = RDA_CODE_BASE + 0x1F3FFF;
define symbol RDA_AHB1_BASE = 0x40100000;
define symbol RDA_MEMC_BASE = RDA_AHB1_BASE + 0x00000;
define symbol RDA_MEMC_END = RDA_AHB1_BASE + 0x1FFFF;
define symbol INTVEC_BASE = RDA_CODE_BASE;
define symbol INTVEC_RAM_BASE = RDA_IRAM_BASE;
define symbol I_DATA_BASE = RDA_IRAM_BASE + 0x80;
define symbol I_DATA_END = RDA_IRAM_END;
define symbol D_DATA_BASE = RDA_DRAM_BASE;
define symbol D_DATA_END = RDA_DRAM_END;
define symbol AES_BASE = RDA_MEMC_BASE + 0x18C00;
define symbol AES_END = RDA_MEMC_BASE + 0x197FF;
define symbol WLAN_BASE = RDA_MEMC_BASE + 0x19800;
define symbol WLAN_END = RDA_MEMC_END;
/* Stack Size & Heap Size*/
define symbol CSTACK_SIZE = 0x00400;
define symbol HEAP_SIZE = RDA_DRAM_END - RDA_DRAM_BASE + 1;
/*Memory regions*/
define memory mem with size = 4G;
define region ROM_REGION = mem:[from RDA_CODE_BASE to RDA_CODE_END];
define region IRAM_REGION = mem:[from I_DATA_BASE to I_DATA_END];
define region DRAM_REGION = mem:[from D_DATA_BASE to D_DATA_END];
define region AES_REGION = mem:[from AES_BASE to AES_END];
define region WLAN_REGION = mem:[from WLAN_BASE to WLAN_END];
define block CSTACK with alignment = 8, size = CSTACK_SIZE { };
define block HEAP with alignment = 8, size = HEAP_SIZE { };
define block RW { readwrite };
define block ZI { zi };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:INTVEC_BASE { readonly section .intvec };
place in ROM_REGION { readonly };
place in IRAM_REGION { block RW, block ZI, block CSTACK};
place in DRAM_REGION { block HEAP};
place in AES_REGION { section AHB1SMEM0 };
place in WLAN_REGION { section AHB1SMEM1 };

221
targets/TARGET_RDA/TARGET_UNO_91H/device/TOOLCHAIN_IAR/startup_RDA5991H.S Normal file
View File

@ -0,0 +1,221 @@
;/*****************************************************************************
; * @file: startup_RDA5991H.s
; * @purpose: CMSIS Cortex-M4 Core Device Startup File
; * for the RDA5981x Device Series
; * @version: V1.00
; * @date: 09. June 2018
; *----------------------------------------------------------------------------
; *
; * Copyright (C) 2010 ARM Limited. All rights reserved.
; *
; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
EXTERN rda_ccfg_boot
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler
DCD NMI_Handler
DCD HardFault_Handler
DCD MemManage_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
__vector_table_0x1c
DCD 0
DCD 0
DCD 0
DCD 0
DCD SVC_Handler
DCD DebugMon_Handler
DCD 0
DCD PendSV_Handler
DCD SysTick_Handler
; External Interrupts
DCD SPIFLASH_IRQHandler
DCD PTA_IRQHandler
DCD SDIO_IRQHandler
DCD USBDMA_IRQHandler
DCD USB_IRQHandler
DCD GPIO_IRQHandler
DCD TIMER0_IRQHandler
DCD UART0_IRQHandler
DCD MACHW_IRQHandler
DCD UART1_IRQHandler
DCD AHBDMA_IRQHandler
DCD PSRAM_IRQHandler
DCD SDMMC_IRQHandler
DCD EXIF_IRQHandler
DCD I2C_IRQHandler
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =sfe(CSTACK)
MSR MSP, R0
LDR R0, =rda_ccfg_boot
BLX R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK SPIFLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPIFLASH_IRQHandler
B SPIFLASH_IRQHandler
PUBWEAK PTA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PTA_IRQHandler
B PTA_IRQHandler
PUBWEAK SDIO_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK USBDMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USBDMA_IRQHandler
B USBDMA_IRQHandler
PUBWEAK USB_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USB_IRQHandler
B USB_IRQHandler
PUBWEAK GPIO_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
GPIO_IRQHandler
B GPIO_IRQHandler
PUBWEAK TIMER0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_IRQHandler
B TIMER0_IRQHandler
PUBWEAK UART0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART0_IRQHandler
B UART0_IRQHandler
PUBWEAK MACHW_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
MACHW_IRQHandler
B MACHW_IRQHandler
PUBWEAK UART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART1_IRQHandler
B UART1_IRQHandler
PUBWEAK AHBDMA_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
AHBDMA_IRQHandler
B AHBDMA_IRQHandler
PUBWEAK PSRAM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PSRAM_IRQHandler
B PSRAM_IRQHandler
PUBWEAK SDMMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC_IRQHandler
B SDMMC_IRQHandler
PUBWEAK EXIF_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXIF_IRQHandler
B EXIF_IRQHandler
PUBWEAK I2C_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C_IRQHandler
B I2C_IRQHandler
END

13
targets/TARGET_RDA/TARGET_UNO_91H/device/cmsis.h Normal file
View File

@ -0,0 +1,13 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2018 ARM Limited. All rights reserved.
*
* A generic CMSIS include header
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "RDA5991H.h"
#include "cmsis_nvic.h"
#endif

40
targets/TARGET_RDA/TARGET_UNO_91H/device/cmsis_nvic.h Normal file
View File

@ -0,0 +1,40 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2018 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 15)
#define NVIC_RAM_VECTOR_ADDRESS (RDA_IRAM_BASE)
#endif

188
targets/TARGET_RDA/TARGET_UNO_91H/device/system_RDA5991H.c Normal file
View File

@ -0,0 +1,188 @@
/**************************************************************************//**
* @file system_RDA5991H.c
* @brief CMSIS Cortex-M4 Device System Source File for
* RDA RDA5991H Device Series
* @version V1.11
* @date 12. June 2018
*
* @note
* Copyright (C) 2009-2016 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
#include "RDA5991H.h"
/** @addtogroup RDA5991H_System
* @{
*/
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <e> Clock Configuration
// <h> Clock Gating Control 0 Register (CLKGATE0)
// <o1.0> DEEPSLEEP: Deep sleep mode enable
// <o1.15> EXIF: EXIF clock gating enable
// </h>
//
// <h> Clock Gating Control 1 Register (CLKGATE1)
// <o2.0> GPIO: GPIO clock gating enable
// <o2.1> I2S: I2S clock gating enable
// <o2.2> PWM: PWM clock gating enable
// <o2.3> TIMER: APB Timer clock gating enable
// <o2.4> PSRAM_PCLK: PSRAM PCLK clock gating enable
// <o2.5> SDMMC: SDMMC clock gating enable
// <o2.6> I2C: I2C clock gating enable
// <o2.4> PSRAM_HCLK: PSRAM HCLK clock gating enable
// </h>
//
// <h> Clock Gating Control 2 Register (CLKGATE2)
// <o3.16> I2SIN: I2SIN clock gating enable
// <o3.17> I2SOUT: I2SOUT clock gating enable
// <o3.18> GSPI: General SPI clock gating enable
// <o3.19> RFSPI: RF SPI clock gating enable
// <o3.31> SLOWFLASH: Slow flash clock gating enable
// </h>
//
// <h> Clock Gating Control 3 Register (CLKGATE3)
// <o4.30> DOZEMODE: Doze mode enable
// <o4.31> CLKMODE: Clock mode enable
// </h>
//
// <h> Clock Core Configure Register (CORECFG)
// <o5.11> HCLK: HCLK config
// <o5.12..13> CPUCLK: CPU Clock config
// </h>
//
// </e>
*/
/** @addtogroup RDA5991H_System_Defines RDA5991H System Defines
@{
*/
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define RDA_SYS_CLK_FREQUENCY_40M ( 40000000UL)
#define RDA_SYS_CLK_FREQUENCY_80M ( 80000000UL)
#define RDA_SYS_CLK_FREQUENCY_160M (160000000UL)
#define RDA_BUS_CLK_FREQUENCY_40M ( 40000000UL)
#define RDA_BUS_CLK_FREQUENCY_80M ( 80000000UL)
/**
* @}
*/
/** @addtogroup RDA5991H_System_Public_Variables RDA5991H System Public Variables
@{
*/
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = RDA_SYS_CLK_FREQUENCY_160M; /*!< System Clock Frequency (Core Clock)*/
uint32_t AHBBusClock = RDA_BUS_CLK_FREQUENCY_80M; /*!< AHB Bus Clock Frequency (Bus Clock)*/
/**
* @}
*/
/** @addtogroup RDA5991H_System_Public_Functions RDA5991H System Public Functions
@{
*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate (void) /* Get Core/Bus Clock Frequency */
{
uint32_t val = RDA_SCU->CORECFG;
/* Determine clock frequency according to SCU core config register values */
switch ((val >> 12) & 0x03UL) {
case 0:
SystemCoreClock = RDA_SYS_CLK_FREQUENCY_40M;
break;
case 1:
SystemCoreClock = RDA_SYS_CLK_FREQUENCY_80M;
break;
case 2:
case 3:
SystemCoreClock = RDA_SYS_CLK_FREQUENCY_160M;
break;
}
/* Determine clock frequency according to SCU core config register values */
switch ((val >> 11) & 0x01UL) {
case 0:
AHBBusClock = RDA_BUS_CLK_FREQUENCY_40M;
break;
case 1:
AHBBusClock = RDA_BUS_CLK_FREQUENCY_80M;
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
SCB->VTOR = RDA_CODE_BASE; /* vector table in flash */
NVIC_SetPriorityGrouping(0x06); /* 1 bit for pre-emption pri */
__enable_irq();
}
/**
* @}
*/
/**
* @}
*/

61
targets/TARGET_RDA/TARGET_UNO_91H/device/system_RDA5991H.h Normal file
View File

@ -0,0 +1,61 @@
/******************************************************************************
* @file: system_RDA5991H.h
* @purpose: CMSIS Cortex-M4 Device Peripheral Access Layer Header File
* for the RDA RDA5991H Device Series
* @version: V1.02
* @date: 07. June 2018
*----------------------------------------------------------------------------
*
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-M3
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_RDA5991H_H
#define __SYSTEM_RDA5991H_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t AHBBusClock; /*!< AHB Bus Clock Frequency (Bus Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_RDA5991H_H */

80
targets/TARGET_RDA/TARGET_UNO_91H/flash_api.c Normal file
View File

@ -0,0 +1,80 @@
/* mbed Microcontroller Library
* Copyright (c) 2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "flash_api.h"
#include "flash_data.h"
#include "mbed_critical.h"
// This file is automagically generated
// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM
static uint32_t FLASH_ALGO[] = {
0x4df0e92d, 0x4180f04f, 0x68082400, 0xea322203, 0xbf1c62d0, 0x50c0f040, 0x49cc6008, 0xf0106808,
0xd1100f40, 0x00c0f040, 0x03086008, 0x68486088, 0x0001f040, 0x20006048, 0x28081c40, 0x6848d3fc,
0x0f01f010, 0x4dc2d1fb, 0x0835f04f, 0x8000f8c5, 0x1c402000, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01,
0xf0106928, 0xd17b0f02, 0x6c704eba, 0x007cf420, 0x1010f440, 0x68b06470, 0x2040f440, 0x209f60b0,
0x20006028, 0x28081c40, 0x68e8d3fc, 0x0f01f010, 0x6928d1fb, 0x69286929, 0x2102b2ca, 0xf04f2705,
0xf04f0a00, 0x2a400b01, 0xb2c0d123, 0xd9202815, 0xf36f6868, 0xf4402010, 0x60687080, 0xf00060a9,
0x2031f92b, 0x20006028, 0x28081c40, 0x68e8d3fc, 0x0f01f010, 0x602fd1fb, 0x1c402000, 0xd3fc2808,
0xf01068e8, 0xd1fb0f01, 0xf0106928, 0xd1f20f01, 0x6868e021, 0x2010f36f, 0x7000f440, 0xf8c56068,
0x60a9a008, 0xf908f000, 0xb000f8c5, 0x1c402000, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01, 0x2000602f,
0x28081c40, 0x68e8d3fc, 0x0f01f010, 0x6928d1fb, 0x0f01f010, 0x4a88d1f2, 0x444a2100, 0x8000f8c5,
0x1c402000, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01, 0x1c496928, 0x6f80f5b1, 0x2401d303, 0xa000f882,
0xf010e00d, 0xd0e90f02, 0x6968b94c, 0x0001f040, 0x6c706168, 0x00d8f440, 0xf8826470, 0x4620b000,
0x8df0e8bd, 0x47702000, 0x47702000, 0xf000b510, 0x496ff8c3, 0x60082060, 0x1c402000, 0xd3fc2808,
0xf01068c8, 0xd1fb0f01, 0x600a2205, 0x1c402000, 0xd3fc2808, 0xf01068c8, 0xd1fb0f01, 0xf0106908,
0xd1f20f01, 0x68484961, 0x0001f040, 0x20006048, 0x28081c40, 0x6848d3fc, 0x0001f010, 0xbd10d1fb,
0x4604b510, 0xf898f000, 0x20204959, 0x2004ea40, 0x20006008, 0x28081c40, 0x68c8d3fc, 0x0f01f010,
0x2205d1fb, 0x2000600a, 0x28081c40, 0x68c8d3fc, 0x0f01f010, 0x6908d1fb, 0x0f01f010, 0x494bd1f2,
0xf0406848, 0x60480001, 0x1c402000, 0xd3fc2808, 0xf0106848, 0xd1fb0001, 0xe92dbd10, 0xf02005f0,
0x4845437c, 0x78004448, 0xbf142800, 0x24022432, 0x2c11ea5f, 0x68684d3e, 0x2010f36f, 0x3080f440,
0xf04f6068, 0xbf1c0100, 0x26052706, 0xf04fd042, 0x20000800, 0xa000f812, 0xa008f8c5, 0x28041c40,
0x1d12dbf8, 0x0801f108, 0x0f40f1b8, 0x602fdbf1, 0x1c402000, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01,
0x2000602e, 0x28081c40, 0x68e8d3fc, 0x0f01f010, 0x6928d1fb, 0x0f02f010, 0xea44d0f2, 0x60282003,
0xf5032000, 0x1c407380, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01, 0x2000602e, 0x28081c40, 0x68e8d3fc,
0x0f01f010, 0x6928d1fb, 0x0f01f010, 0x1c49d1f2, 0xd3bc4561, 0x68484915, 0x0001f040, 0x20006048,
0x28081c40, 0x6848d3fc, 0x0001f010, 0xe8bdd1fb, 0x477005f0, 0x47704408, 0x2006490d, 0x20006008,
0x28081c40, 0x68c8d3fc, 0x0f01f010, 0x2205d1fb, 0x2000600a, 0x28081c40, 0x68c8d3fc, 0x0f01f010,
0x6908d1fb, 0x0f02f010, 0x4770d0f2, 0x40014000, 0x17fff000, 0x40001000, 0x00000004, 0x00000000,
0x00000000
};
static const flash_algo_t flash_algo_config = {
.init = 0x1,
.uninit = 0x185,
.erase_sector = 0x1e1,
.program_page = 0x23b,
.static_base = 0x35c,
.algo_blob = FLASH_ALGO
};
static const sector_info_t sectors_info[] = {
{0x18000000, 0x1000},
};
static const flash_target_config_t flash_target_config = {
.page_size = 0x100,
.flash_start = 0x18000000,
.flash_size = 0x100000,
.sectors = sectors_info,
.sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
};
void flash_set_target_config(flash_t *obj)
{
obj->flash_algo = &flash_algo_config;
obj->target_config = &flash_target_config;
}

121
targets/TARGET_RDA/TARGET_UNO_91H/gpio_api.c Normal file
View File

@ -0,0 +1,121 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "gpio_api.h"
#include "pinmap.h"
#include "rda_ccfg_api.h"
#define GPIO_PIN_NUM 28
static const PinMap PinMap_GPIO[] = {
{PB_0, (GPIO_0 | 0), 0},
{PB_1, (GPIO_0 | 1), 0},
{PB_2, (GPIO_0 | 2), 0},
{PB_3, (GPIO_0 | 3), 0},
{PB_4, (GPIO_0 | 4), 0},
{PB_5, (GPIO_0 | 5), 0},
{PB_6, (GPIO_0 | 6), 0},
{PB_7, (GPIO_0 | 7), 0},
{PB_8, (GPIO_0 | 8), 0},
{PB_9, (GPIO_0 | 9), 0},
{PA_8, (GPIO_0 | 10), 0},
{PA_9, (GPIO_0 | 11), 0},
{PC_0, (GPIO_0 | 12), 1},
{PC_1, (GPIO_0 | 13), 1},
{PC_2, (GPIO_0 | 14), 0},
{PC_3, (GPIO_0 | 15), 0},
{PC_4, (GPIO_0 | 16), 0},
{PC_5, (GPIO_0 | 17), 0},
{PC_6, (GPIO_0 | 18), 0},
{PC_7, (GPIO_0 | 19), 0},
{PC_8, (GPIO_0 | 20), 0},
{PC_9, (GPIO_0 | 21), 0},
{PD_0, (GPIO_0 | 22), 0},
{PD_1, (GPIO_0 | 23), 0},
{PD_2, (GPIO_0 | 24), 0},
{PD_3, (GPIO_0 | 25), 0},
{PA_0, (GPIO_0 | 26), 1},
{PA_1, (GPIO_0 | 27), 1},
{PA_2, (GPIO_0 | 14), 1},
{PA_3, (GPIO_0 | 15), 1},
{PA_4, (GPIO_0 | 16), 1},
{PA_5, (GPIO_0 | 17), 1},
{PA_6, (GPIO_0 | 18), 1},
{PA_7, (GPIO_0 | 19), 1},
{NC, NC, 0}
};
#define PER_BITBAND_ADDR(reg, bit) (uint32_t *)(RDA_PERBTBND_BASE + (((uint32_t)(reg)-RDA_PER_BASE)<<5U) + (((uint32_t)(bit))<<2U))
PinName gpio_pinname(int pin_n)
{
MBED_ASSERT(pin_n < GPIO_PIN_NUM);
return PinMap_GPIO[pin_n].pin;
}
uint32_t gpio_set(PinName pin)
{
MBED_ASSERT(pin != (PinName)NC);
uint32_t func = 0;
uint32_t idx = 0;
func = pinmap_function(pin, PinMap_GPIO);
idx = pinmap_peripheral(pin, PinMap_GPIO) & 0x001F;
pin_function(pin, func);
return idx;
}
void gpio_init(gpio_t *obj, PinName pin)
{
uint32_t gpio_idx = 0;
obj->pin = pin;
if (pin == (PinName)NC)
return;
gpio_idx = gpio_set(pin);
if ((6U <= gpio_idx) && (9U >= gpio_idx)) {
rda_ccfg_gp((unsigned char)gpio_idx, 0x01U);
}
obj->reg_out = PER_BITBAND_ADDR(&RDA_GPIO->DOUT, gpio_idx);
obj->reg_in = PER_BITBAND_ADDR(&RDA_GPIO->DIN, gpio_idx);
obj->reg_dir = PER_BITBAND_ADDR(&RDA_GPIO->DIR, gpio_idx);
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
{
uint32_t dir = 0x00UL;
MBED_ASSERT(obj->pin != (PinName)NC);
if (PIN_INPUT == direction) {
dir = 0x01UL;
}
if (rda_ccfg_hwver() >= 5) {
uint32_t gpio_idx = pinmap_peripheral(obj->pin, PinMap_GPIO) & 0x001F;
/* Since U05, for gpio 2/3/8/14/15/16/17/20/21, 1'b1 means output */
if (0x00UL != (0x0033C10CUL & (0x01UL << gpio_idx))) {
dir ^= 0x01UL;
}
}
*obj->reg_dir = dir;
}

195
targets/TARGET_RDA/TARGET_UNO_91H/gpio_irq_api.c Normal file
View File

@ -0,0 +1,195 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "gpio_irq_api.h"
#include "mbed_error.h"
#include "cmsis.h"
#if DEVICE_INTERRUPTIN
#if defined(GPIO_IRQ_DEBUG)
#include "mbed_interface.h"
#endif /* GPIO_IRQ_DEBUG */
#define GPIO_PINNUM 28
#define NONE (uint32_t)NC
#define GPIO_INT_CTRL_REG (RDA_GPIO->INTCTRL)
#define GPIO_INT_SEL_REG (RDA_GPIO->INTSEL)
#define GPIO_DATA_IN_REG (RDA_GPIO->DIN)
typedef enum {
GPIO_IRQ_CH0,
GPIO_IRQ_CH1,
CHANNEL_NUM
} GPIO_IRQ_IDX_T;
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static uint32_t channel_pinidxs[CHANNEL_NUM] = {0};
static uint8_t channel_bothedge_flag[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler[CHANNEL_NUM] = {NULL};
#if defined(GPIO_IRQ_DEBUG)
static uint32_t exception_cntr;
#endif /* GPIO_IRQ_DEBUG */
static GPIO_IRQ_IDX_T gpio_irq_ava_chidx(void)
{
GPIO_IRQ_IDX_T ret;
for (ret = GPIO_IRQ_CH0; ret < CHANNEL_NUM; ret++) {
if (0 == channel_ids[ret])
break;
}
return ret;
}
static uint32_t gpio_irq_pinidx(PinName pin)
{
uint8_t idx;
const uint32_t pinmap_gpio_irq[GPIO_PINNUM] = {
/* GPIO 0 ~ 13 */
PB_0, PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PA_8, PA_9, PC_0, PC_1,
/* GPIO 14 ~ 21, Not support interrupt */
NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,
/* GPIO 22 ~ 27 */
PD_0, PD_1, PD_2, PD_3, PA_0, PA_1
};
for (idx = 0; idx < GPIO_PINNUM; idx++) {
if (pinmap_gpio_irq[idx] == NONE) {
continue;
} else if (pinmap_gpio_irq[idx] == (uint32_t)pin) {
break;
}
}
if (GPIO_PINNUM == idx) {
error("The pin cannot generate interrupt");
}
return idx;
}
static void handle_interrupt_in(void)
{
/* Read current interrupt register */
uint32_t int_ctrl = GPIO_INT_CTRL_REG;
uint32_t din_val = GPIO_DATA_IN_REG;
uint32_t idx;
if (int_ctrl & (0x01UL << 16)) {
GPIO_INT_CTRL_REG |= (0x01UL << 16);
while (GPIO_INT_CTRL_REG & (0x01UL << 16));
}
for (idx = GPIO_IRQ_CH0; idx < CHANNEL_NUM; idx++) {
if (int_ctrl & (0x01UL << (21 + idx))) {
gpio_irq_event flagRiseFall_1, flagRiseFall_2;
GPIO_INT_CTRL_REG |= (0x01UL << (17 + idx)); // clear int flag
flagRiseFall_1 = (int_ctrl & (0x01UL << (2 + idx))) ? IRQ_RISE : IRQ_FALL;
flagRiseFall_2 = (din_val & (0x01UL << channel_pinidxs[idx])) ? IRQ_RISE : IRQ_FALL;
if (flagRiseFall_1 == flagRiseFall_2) {
if (channel_bothedge_flag[idx]) {
GPIO_INT_CTRL_REG ^= (0x01UL << (2 + idx));
}
irq_handler[idx](channel_ids[idx], flagRiseFall_1);
#if defined(GPIO_IRQ_DEBUG)
exception_cntr = 0;
#endif /* GPIO_IRQ_DEBUG */
}
#if defined(GPIO_IRQ_DEBUG)
else {
exception_cntr++;
if (exception_cntr >= 2) {
exception_cntr = 0;
mbed_error_printf("invalid gpio irq: %d,%d\r\n", (int)flagRiseFall_1, (int)flagRiseFall_2);
}
}
#endif /* GPIO_IRQ_DEBUG */
}
}
}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
uint32_t regval;
if (pin == NC) return -1;
obj->ch = (uint16_t)gpio_irq_ava_chidx();
MBED_ASSERT(CHANNEL_NUM != obj->ch);
irq_handler[obj->ch] = handler;
channel_ids[obj->ch] = id;
channel_pinidxs[obj->ch] = gpio_irq_pinidx(pin);
regval = RDA_GPIO->INTSEL & ~(0x3FFUL << 10);
RDA_GPIO->INTSEL = regval | (0x3FFUL << 10);
NVIC_SetVector(GPIO_IRQn, (uint32_t)handle_interrupt_in);
NVIC_SetPriority(GPIO_IRQn, 0x1FUL);
NVIC_EnableIRQ(GPIO_IRQn);
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
channel_ids[obj->ch] = 0;
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
uint32_t reg_val;
uint16_t intEn;
MBED_ASSERT(1 >= obj->ch);
if (IRQ_RISE == event) {
obj->flagR = (uint8_t)enable;
} else {
obj->flagF = (uint8_t)enable;
}
if (obj->flagR && obj->flagF)
channel_bothedge_flag[obj->ch] = 1U;
else
channel_bothedge_flag[obj->ch] = 0U;
if (obj->flagR || obj->flagF)
intEn = 1;
else
intEn = 0;
if (0 == intEn) {
GPIO_INT_CTRL_REG &= ~(0x01UL << (6 + obj->ch));
} else {
/* Set interrupt select reg */
reg_val = GPIO_INT_SEL_REG & ~(0x1FUL << (5 * obj->ch));
GPIO_INT_SEL_REG = reg_val | ((0x1FUL & ((channel_pinidxs[obj->ch] >= 22) ? (channel_pinidxs[obj->ch] - 8) : channel_pinidxs[obj->ch])) << (5 * obj->ch));
/* Set interrupt control reg */
reg_val = GPIO_INT_CTRL_REG & ~(0x01UL << (2 + obj->ch));
GPIO_INT_CTRL_REG = reg_val | (((0U == channel_bothedge_flag[obj->ch]) && (1U == obj->flagR)) ? (0x01UL << (2 + obj->ch)) : (0x00UL))
| (0x01UL << (6 + obj->ch));
}
}
void gpio_irq_enable(gpio_irq_t *obj)
{
NVIC_EnableIRQ(GPIO_IRQn);
}
void gpio_irq_disable(gpio_irq_t *obj)
{
NVIC_DisableIRQ(GPIO_IRQn);
}
#endif /* DEVICE_INTERRUPTIN */

53
targets/TARGET_RDA/TARGET_UNO_91H/gpio_object.h Normal file
View File

@ -0,0 +1,53 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
__IO uint32_t *reg_out;
__I uint32_t *reg_in;
__IO uint32_t *reg_dir;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value)
{
MBED_ASSERT(obj->pin != (PinName)NC);
*obj->reg_out = ((value) ? 1 : 0);
}
static inline int gpio_read(gpio_t *obj)
{
MBED_ASSERT(obj->pin != (PinName)NC);
return ((*obj->reg_in) ? 1 : 0);
}
static inline int gpio_is_connected(const gpio_t *obj)
{
return obj->pin != (PinName)NC;
}
#ifdef __cplusplus
}
#endif
#endif

49
targets/TARGET_RDA/TARGET_UNO_91H/lib/LICENSE-permissive-binary-license-1.0.txt Normal file
View File

@ -0,0 +1,49 @@
Permissive Binary License
Version 1.0, September 2018
Redistribution. Redistribution and use in binary form, without
modification, are permitted provided that the following conditions are
met:
1) Redistributions must reproduce the above copyright notice and the
following disclaimer in the documentation and/or other materials
provided with the distribution.
2) Unless to the extent explicitly permitted by law, no reverse
engineering, decompilation, or disassembly of this software is
permitted.
3) Redistribution as part of a software development kit must include the
accompanying file named “DEPENDENCIES” and any dependencies listed in
that file.
4) Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
Limited patent license. The copyright holders (and contributors) grant a
worldwide, non-exclusive, no-charge, royalty-free patent license to
make, have made, use, offer to sell, sell, import, and otherwise
transfer this software, where such license applies only to those patent
claims licensable by the copyright holders (and contributors) that are
necessarily infringed by this software. This patent license shall not
apply to any combinations that include this software. No hardware is
licensed hereunder.
If you institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the software
itself infringes your patent(s), then your rights granted under this
license shall terminate as of the date such litigation is filed.
DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

7
targets/TARGET_RDA/TARGET_UNO_91H/lib/README.md Normal file
View File

@ -0,0 +1,7 @@
This directory tree contains binaries build from RDA SDK modified for Mbed OS and released under Permissive Binary License.
libhal files in the subfolders are generated with toolchains:
Arm Compiler 5 - version 5.06u1
GNU Arm Embedded - version 6.3.1
IAR EWARM - version 7.80.2

BIN
targets/TARGET_RDA/TARGET_UNO_91H/lib/TOOLCHAIN_ARM_STD/libhal.ar Normal file
View File

Binary file not shown.

BIN
targets/TARGET_RDA/TARGET_UNO_91H/lib/TOOLCHAIN_GCC_ARM/libhal.a Normal file
View File

Binary file not shown.

BIN
targets/TARGET_RDA/TARGET_UNO_91H/lib/TOOLCHAIN_IAR/libhal.a Normal file
View File

Binary file not shown.

27
targets/TARGET_RDA/TARGET_UNO_91H/mbed_overrides.c Normal file
View File

@ -0,0 +1,27 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cmsis.h"
#include "mbed_error.h"
#include "rda_ccfg_api.h"
extern void sleep_cal_lpo(unsigned int calms);
/* This function is called after RAM initialization and before main. */
void mbed_sdk_init(void)
{
/* Update the SystemCoreClock variable. */
SystemCoreClockUpdate();
}

101
targets/TARGET_RDA/TARGET_UNO_91H/objects.h Normal file
View File

@ -0,0 +1,101 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#include "gpio_object.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
uint16_t ch;
uint8_t flagR;
uint8_t flagF;
};
struct port_s {
PortName port;
uint32_t mask;
__IO uint32_t *reg_out;
__I uint32_t *reg_in;
__IO uint32_t *reg_dir;
};
struct pwmout_s {
uint32_t channel;
uint32_t *base_clk_ptr;
uint32_t period_ticks;
uint32_t pulsewidth_ticks;
uint32_t period_ticks_max;
uint32_t period_ticks_min;
PinName pin;
__IO uint32_t *CFGR;
};
struct serial_s {
RDA_UART_TypeDef *uart;
int index;
};
struct i2s_s {
RDA_I2S_TypeDef *i2s;
};
struct wdt_s {
RDA_WDT_TypeDef *wdt;
};
struct analogin_s {
ADCName adc;
};
struct gpadc_s {
GPADCName ch;
PinName pin;
};
#if 0
struct dac_s {
DACName dac;
};
#endif
struct i2c_s {
RDA_I2C0_TypeDef *i2c;
};
struct spi_s {
RDA_SPI_TypeDef *spi;
uint8_t bit_ofst[2];
};
struct trng_s {
uint8_t dma_clk_flag;
uint8_t byte_idx;
uint32_t trng_data0;
};
#ifdef __cplusplus
}
#endif
#endif

62
targets/TARGET_RDA/TARGET_UNO_91H/pinmap.c Normal file
View File

@ -0,0 +1,62 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "rda_ccfg_api.h"
void pin_function(PinName pin, int function)
{
int index = pin >> PORT_SHIFT;
int raw_ofst = pin & 0x00FF;
int offset;
MBED_ASSERT(pin != (PinName)NC);
switch (index) {
case 1:
if ((8 == raw_ofst) && (rda_ccfg_hwver() >= 5)) {
function ^= 0x01;
}
break;
case 4:
if (1 < raw_ofst) {
offset = raw_ofst << 1;
RDA_PINCFG->MODE2 &= ~(0x03UL << offset);
}
break;
case 5:
if (2 > raw_ofst) {
offset = (raw_ofst << 1) + 20;
RDA_PINCFG->MODE2 &= ~(0x03UL << offset);
} else {
offset = (raw_ofst << 1) - 4;
RDA_PINCFG->MODE3 &= ~(0x03UL << offset);
}
break;
default:
break;
}
offset = raw_ofst * 3;
RDA_PINCFG->IOMUXCTRL[index] &= ~(0x07UL << offset);
RDA_PINCFG->IOMUXCTRL[index] |= ((function & 0x07UL) << offset);
}
void pin_mode(PinName pin, PinMode mode)
{
MBED_ASSERT(pin != (PinName)NC);
}

81
targets/TARGET_RDA/TARGET_UNO_91H/port_api.c Normal file
View File

@ -0,0 +1,81 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
extern PinName gpio_pinname(int pin_n);
PinName port_pin(PortName port, int pin_n)
{
return (PinName)((port << PORT_SHIFT) | pin_n);
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
uint32_t i;
obj->port = port;
obj->mask = mask;
obj->reg_out = &RDA_GPIO->DOUT;
obj->reg_in = &RDA_GPIO->DIN;
obj->reg_dir = &RDA_GPIO->DIR;
// The mode is set per pin: reuse gpio logic
for (i = 0; i < 32; i++) {
if (obj->mask & (1 << i)) {
// For RDA5991H, port0,1,4,5 is about IOMUX, not GPIO number, cannot use port_pin here
//gpio_set(port_pin(obj->port, i));
gpio_set(gpio_pinname(i));
}
}
port_dir(obj, dir);
}
void port_mode(port_t *obj, PinMode mode)
{
uint32_t i;
// The mode is set per pin: reuse pinmap logic
for (i = 0; i < 32; i++) {
if (obj->mask & (1 <<i )) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir)
{
switch (dir) {
case PIN_INPUT :
*obj->reg_dir |= obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir &= ~obj->mask;
break;
}
}
void port_write(port_t *obj, int value)
{
*obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
}
int port_read(port_t *obj)
{
return (*obj->reg_in & obj->mask);
}

394
targets/TARGET_RDA/TARGET_UNO_91H/pwmout_api.c Normal file
View File

@ -0,0 +1,394 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if DEVICE_PWMOUT
#include "mbed_assert.h"
#include "pwmout_api.h"
#include "gpio_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_interface.h"
#define PWM_CLK_SRC_20MHZ (20000000)
#define PWM_CLK_SRC_32KHZ (32768)
#define PWM_CLK_IDX_NUM (3)
#define PWM_CLKGATE_REG (RDA_SCU->CLKGATE1)
#define PWM_CLKSRC_REG (RDA_SCU->PWMCFG)
#define PWM_CLKDIV_REG (RDA_PWM->CLKR)
#define EXIF_PWM_EN_REG (RDA_EXIF->MISCCFG)
/* PORT ID, PWM ID, Pin function */
static const PinMap PinMap_PWM[] = {
{PA_0, PWM_6, 4},
{PA_1, PWM_3, 4},
{PB_0, PWM_2, 4},
{PB_1, PWM_7, 4},
{PB_2, PWM_5, 4},
{PB_3, PWM_4, 4},
{PB_8, PWM_0, 4},
{PC_1, PWM_1, 5},
{PD_0, PWM_0, 4},
{PD_1, PWM_1, 4},
{PD_2, PWM_2, 4},
{PD_3, PWM_3, 4},
{NC, NC, 0}
};
__IO uint32_t *PWM_MATCH[] = {
&(RDA_EXIF->PWM0CFG),
&(RDA_EXIF->PWM1CFG),
&(RDA_EXIF->PWM2CFG),
&(RDA_EXIF->PWM3CFG),
&( RDA_PWM->PWTCFG ),
&( RDA_PWM->LPGCFG ),
&( RDA_PWM->PWL0CFG),
&( RDA_PWM->PWL1CFG)
};
static uint32_t BaseClk_PWM[PWM_CLK_IDX_NUM] = {0UL};
static uint8_t is_pwmout_started(pwmout_t* obj);
static void pwmout_start(pwmout_t* obj);
static void pwmout_stop(pwmout_t* obj);
static void pwmout_update_cfgreg(pwmout_t* obj);
void pwmout_clk_set(pwmout_t *obj, int src, int div)
{
uint32_t reg_val = 0UL;
uint32_t clk_idx = 0UL, clk_hz = PWM_CLK_SRC_32KHZ >> 1;
PWMName pwm = (PWMName)(obj->channel);
uint32_t divider = (uint32_t)div;
MBED_ASSERT(PWM_7 >= pwm);
if (PWM_5 == pwm) {
clk_idx = 1;
} else if (PWM_6 <= pwm) {
clk_idx = 2;
}
if (divider > 0x80UL) { // max divider is 128
divider = 0x80UL;
}
reg_val = PWM_CLKSRC_REG & ~((0x00FFUL << (clk_idx * 8)) | (0x01UL << (24 + clk_idx)));
if (src) {
reg_val |= (0x01UL << (7 + (clk_idx * 8)));
clk_hz = PWM_CLK_SRC_20MHZ >> 1;
}
if (divider) {
reg_val |= ((divider - 0x01UL) << (clk_idx * 8));
BaseClk_PWM[clk_idx] = clk_hz / divider;
} else {
BaseClk_PWM[clk_idx] = clk_hz;
}
PWM_CLKSRC_REG = reg_val | (0x01UL << (24 + clk_idx));
}
void pwmout_init(pwmout_t* obj, PinName pin)
{
/* determine the channel */
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
obj->channel = pwm;
obj->CFGR = PWM_MATCH[pwm];
obj->pin = pin;
/* Enable PWM Clock-gating */
PWM_CLKGATE_REG |= (0x01UL << 2);
/* Init PWM clock source and divider */
if (PWM_4 >= pwm) {
/* default to 20MHz / 2 */
pwmout_clk_set(obj, 1, 0);
if (PWM_4 == pwm) {
obj->period_ticks_max = 0x1FF8UL;
obj->period_ticks_min = 0x0008UL;
} else {
obj->period_ticks_max = 0x20000UL;
obj->period_ticks_min = 0x00002UL;
}
obj->base_clk_ptr = &(BaseClk_PWM[0]);
} else if (PWM_5 == pwm) {
/* default to 32KHz / 2 */
pwmout_clk_set(obj, 0, 0);
obj->period_ticks_max = 0x7000UL;
obj->period_ticks_min = 0x0800UL;
obj->base_clk_ptr = &(BaseClk_PWM[1]);
} else {
/* default to 20MHz / 2 */
pwmout_clk_set(obj, 1, 0);
//do not need to div
obj->period_ticks_max = 0x0FFUL; // TBD
obj->period_ticks_min = 0x001UL;
obj->base_clk_ptr = &(BaseClk_PWM[2]);
}
// default to half of max period
if (PWM_5 >= pwm) {
pwmout_period_us(obj, (obj->period_ticks_max * 1e6) / (*(obj->base_clk_ptr)) / 2);
}
//PWM6 PWM7 has no period
pwmout_write (obj, 0.5f);
// Wire pinout
pinmap_pinout(pin, PinMap_PWM);
}
void pwmout_free(pwmout_t* obj)
{
/* Disable PWM Clock-gating */
PWM_CLKGATE_REG &= ~(0x01UL << 2);
}
void pwmout_write(pwmout_t* obj, float value)
{
uint32_t ticks;
/* Check if already started */
if (is_pwmout_started(obj))
pwmout_stop(obj);
if (value < 0.0f) {
value = 0.0;
} else if (value > 1.0f) {
value = 1.0;
}
/* Set channel match to percentage */
if (PWM_5 >= (PWMName)obj->channel) {
ticks = (uint32_t)((float)(obj->period_ticks) * value);
}
else if (PWM_6 <= (PWMName)obj->channel) {
obj->period_ticks = 0xFF;
ticks = (uint32_t)((float)(obj->period_ticks) * value);
}
if (0 == ticks) {
obj->pulsewidth_ticks = 0;
} else {
/* Update Hw reg */
if (ticks != obj->pulsewidth_ticks) {
obj->pulsewidth_ticks = ticks;
pwmout_update_cfgreg(obj);
}
}
/* Start PWM module */
pwmout_start(obj);
}
float pwmout_read(pwmout_t* obj)
{
float v = (float)(obj->pulsewidth_ticks) / (float)(obj->period_ticks);
return (v > 1.0f) ? (1.0f) : (v);
}
void pwmout_period(pwmout_t* obj, float seconds)
{
pwmout_period_us(obj, seconds * 1000000.0f);
}
void pwmout_period_ms(pwmout_t* obj, int ms)
{
pwmout_period_us(obj, ms * 1000);
}
/* Set the PWM period, keeping the duty cycle the same. */
void pwmout_period_us(pwmout_t* obj, int us)
{
uint32_t ticks;
MBED_ASSERT(PWM_5 >= (PWMName)(obj->channel));
/* Check if already started */
if (is_pwmout_started(obj))
pwmout_stop(obj);
/* Calculate number of ticks */
ticks = (uint64_t)(*(obj->base_clk_ptr)) * us / 1000000;
if (ticks != obj->period_ticks) {
float duty_ratio;
/* Preserve the duty ratio */
if (0 == obj->period_ticks)
duty_ratio = 0.5f;
else
duty_ratio = (float)obj->pulsewidth_ticks / (float)obj->period_ticks;
obj->period_ticks = ticks;
obj->pulsewidth_ticks = (uint32_t)(ticks * duty_ratio);
MBED_ASSERT(obj->period_ticks >= obj->pulsewidth_ticks);
pwmout_update_cfgreg(obj);
}
/* Start PWM module */
pwmout_start(obj);
}
void pwmout_pulsewidth(pwmout_t* obj, float seconds)
{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
{
pwmout_pulsewidth_us(obj, ms * 1000);
}
/* Set the PWM pulsewidth, keeping the period the same. */
void pwmout_pulsewidth_us(pwmout_t* obj, int us)
{
uint32_t ticks;
MBED_ASSERT(PWM_7 >= (PWMName)(obj->channel));
/* Check if already started */
if (is_pwmout_started(obj))
pwmout_stop(obj);
/* Calculate number of ticks */
ticks = (uint64_t)(*(obj->base_clk_ptr)) * us / 1000000;
if (ticks != obj->pulsewidth_ticks) {
obj->pulsewidth_ticks = ticks;
MBED_ASSERT(obj->period_ticks >= obj->pulsewidth_ticks);
pwmout_update_cfgreg(obj);
}
/* Start PWM module */
pwmout_start(obj);
}
static uint8_t is_pwmout_started(pwmout_t* obj)
{
uint8_t retVal = 0;
uint32_t reg_val;
MBED_ASSERT(PWM_7 >= (PWMName)(obj->channel));
if (PWM_3 >= (PWMName)obj->channel) {
reg_val = (EXIF_PWM_EN_REG >> 8) & 0x0FUL;
if (reg_val & (0x01UL << obj->channel))
retVal = 1;
} else if (PWM_4 == (PWMName)obj->channel) {
if (*(obj->CFGR) & (0x01UL << 1))
retVal = 1;
} else if (PWM_5 == (PWMName)obj->channel) {
retVal = 1;
} else {
if (*(obj->CFGR) & (0x01UL << 16))
retVal = 1;
}
return retVal;
}
static void pwmout_start(pwmout_t* obj)
{
MBED_ASSERT(PWM_7 >= (PWMName)(obj->channel));
if (obj->period_ticks == obj->pulsewidth_ticks) {
gpio_t gpio;
gpio_init_out(&gpio, obj->pin);
gpio_write(&gpio, 1);
//mbed_error_printf("100\n");
} else if (0 == obj->pulsewidth_ticks) {
gpio_t gpio;
gpio_init_out(&gpio, obj->pin);
gpio_write(&gpio, 0);
//mbed_error_printf("0\n");
} else {
pinmap_pinout(obj->pin, PinMap_PWM);
}
if (PWM_3 >= (PWMName)obj->channel) {
EXIF_PWM_EN_REG |= (0x01UL << (8 + obj->channel));
} else if (PWM_4 == (PWMName)obj->channel) {
*(obj->CFGR) |= 0x01UL;
} else if (PWM_5 == (PWMName)obj->channel) {
/* Nothing to be done */
} else {
*(obj->CFGR) |= (0x01UL << 16);
}
}
static void pwmout_stop(pwmout_t* obj)
{
MBED_ASSERT(PWM_7 >= (PWMName)(obj->channel));
if (obj->period_ticks == obj->pulsewidth_ticks) {
gpio_t gpio;
gpio_init_out(&gpio, obj->pin);
gpio_write(&gpio, 0);
}
if (PWM_3 >= (PWMName)obj->channel) {
EXIF_PWM_EN_REG &= ~(0x01UL << (8 + obj->channel));
} else if (PWM_4 == (PWMName)(obj->channel)) {
*(obj->CFGR) &= ~0x01UL;
} else if (PWM_5 == (PWMName)(obj->channel)) {
/* Nothing to be done */
} else {
*(obj->CFGR) &= ~(0x01UL << 16);
}
}
static void pwmout_update_cfgreg(pwmout_t* obj)
{
int err_code = 0;
if (obj->pulsewidth_ticks < obj->period_ticks_min) {
obj->pulsewidth_ticks = obj->period_ticks_min;
err_code = 1; // too small duty
if (obj->period_ticks < obj->period_ticks_min) {
obj->period_ticks = obj->period_ticks_min;
err_code = 2; // too small duty & period
}
}
if (obj->period_ticks > obj->period_ticks_max) {
obj->period_ticks = obj->period_ticks_max;
err_code = 3; // too large period
if (obj->pulsewidth_ticks > obj->period_ticks_max) {
obj->pulsewidth_ticks = obj->period_ticks_max;
err_code = 4; // too large period & duty
}
}
if (0 != err_code) {
mbed_error_printf("PwmCfgErr:%d\r\n",err_code);
}
if (PWM_3 >= (PWMName)(obj->channel)) {
if (obj->period_ticks == obj->pulsewidth_ticks) {
*(obj->CFGR) = ((obj->pulsewidth_ticks - 1) << 16);
} else {
*(obj->CFGR) = ((obj->period_ticks - obj->pulsewidth_ticks - 1) & 0xFFFFUL) |
((obj->pulsewidth_ticks - 1) << 16);
}
} else if (PWM_4 == (PWMName)(obj->channel)) {
*(obj->CFGR) = ((obj->pulsewidth_ticks & ~0x07UL) << ( 4 - 3)) |
((obj->period_ticks & ~0x07UL) << (16 - 3));
} else if (PWM_5 == (PWMName)(obj->channel)) {
/* TBD */
uint32_t reg_val = *(obj->CFGR) & ~(0xFUL << 4) & ~(0x7UL << 16);
uint32_t lpg_field_ontime = (0x01UL << 4) & (0xFUL << 4); // to be confirm
uint32_t lpg_field_period = (obj->period_ticks << 4) & (0x7UL << 16);
*(obj->CFGR) = reg_val | lpg_field_ontime | lpg_field_period;
} else if (PWM_6 == (PWMName)(obj->channel)) {
uint32_t reg_val = *(obj->CFGR) & ~(0xFF);
*(obj->CFGR) = reg_val | (obj->pulsewidth_ticks);//1~254
} else{
//PWM_7
uint32_t reg_val = *(obj->CFGR) & ~(0xFF);
*(obj->CFGR) = reg_val | (obj->pulsewidth_ticks);//1~254
}
}
#endif

44
targets/TARGET_RDA/TARGET_UNO_91H/rda_ccfg_api.h Normal file
View File

@ -0,0 +1,44 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef RDA_CCFG_API_H
#define RDA_CCFG_API_H
#ifdef __cplusplus
extern "C" {
#endif
void rda_ccfg_aontmr(void);
void rda_ccfg_gp6(unsigned short cfg);
void rda_ccfg_gp7(unsigned short cfg);
void rda_ccfg_gp(unsigned char gp, unsigned short cfg);
void rda_ccfg_ckrst(void);
void rda_ccfg_perrst(void);
void rda_ccfg_adc_init(void);
void rda_ccfg_adc_gp(unsigned char gp, unsigned short cfg);
void rda_ccfg_adc_oenb(unsigned char ch, unsigned short cfg);
unsigned short rda_ccfg_adc_read(unsigned char ch);
void rda_ccfg_adc_free(void);
int rda_ccfg_abort_flag(void);
void rda_ccfg_wdt_en(void);
int rda_ccfg_hwver(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

40
targets/TARGET_RDA/TARGET_UNO_91H/rda_timer_isr.c Normal file
View File

@ -0,0 +1,40 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "us_ticker_api.h"
#define rTIMER_INTSTATE (RDA_TIMINTST->INTST)
#define RDA_TIMER_IRQn (TIMER_IRQn)
#define TIMER0_CONTROL_ENABLE (0x01)
extern uint32_t us_ticker_soft_int_flag;
extern void us_ticker_irq_callback();
static void rda_timer_isr(void)
{
uint32_t int_status = rTIMER_INTSTATE & 0x000FUL;
if ((int_status == 0x05) ||((int_status == 0) && (us_ticker_soft_int_flag == 1))){
us_ticker_irq_callback();
us_ticker_irq_handler();
}
}
void rda_timer_irq_set(void)
{
NVIC_SetVector(RDA_TIMER_IRQn, (uint32_t)rda_timer_isr);
NVIC_SetPriority(RDA_TIMER_IRQn, 0x1FUL);
NVIC_EnableIRQ(RDA_TIMER_IRQn);
}

403
targets/TARGET_RDA/TARGET_UNO_91H/serial_api.c Normal file
View File

@ -0,0 +1,403 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// math.h required for floating point operations for baud rate calculation
#include "mbed_assert.h"
#include <math.h>
#include <string.h>
#include <stdlib.h>
#include "serial_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "gpio_api.h"
/******************************************************************************
* INITIALIZATION
******************************************************************************/
#define UART_NUM 2
#define UART_CLKGATE_REG (RDA_SCU->CLKGATE0)
#define UART1_CLKEN_MASK (0x01UL << 21)
#define RXFIFO_EMPTY_MASK (0x01UL << 0)
#define TXFIFO_FULL_MASK (0x01UL << 19)
#define AFCE_MASK (0x01UL << 5)
static const PinMap PinMap_UART_TX[] = {
{PA_1, UART_0, 0},
{PB_2, UART_1, 5},
{PD_3, UART_1, 2},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RX[] = {
{PA_0, UART_0, 0},
{PB_1, UART_1, 5},
{PD_2, UART_1, 2},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RTS[] = {
{PD_1, UART_1, 2},
{NC, NC, 0}
};
static const PinMap PinMap_UART_CTS[] = {
{PD_0, UART_1, 2},
{NC, NC, 0}
};
static uart_irq_handler irq_handler[UART_NUM];
int stdio_uart_inited = 0;
serial_t stdio_uart;
struct serial_global_data_s {
uint32_t serial_irq_id;
gpio_t sw_rts, sw_cts;
uint8_t count, rx_irq_set_flow, rx_irq_set_api;
};
static struct serial_global_data_s uart_data[UART_NUM];
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
int is_stdio_uart = 0;
// determine the UART to use
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart != NC);
switch (uart) {
case UART_0:
obj->index = 0;
break;
case UART_1:
obj->index = 1;
/* Enable clock-gating */
UART_CLKGATE_REG |= UART1_CLKEN_MASK;
break;
}
obj->uart = (RDA_UART_TypeDef *)uart;
// enable fifos and default rx trigger level
obj->uart->FCR = 0 << 0 //FIFO Enable - 0 = Disables, 1 = Enabled
| 0 << 1 // Rx Fifo Reset
| 0 << 2 // Tx Fifo Reset
| 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
// disable irqs
obj->uart->IER = 0 << 0 // Rx Data available irq enable
| 0 << 1 // Tx Fifo empty irq enable
| 0 << 2; // Rx Line Status irq enable
obj->uart->MCR = 1 << 8; //select clock
obj->uart->FRR = 0x2001; //tx_trigger = 0x10, rx_trigger = 0x01
serial_format(obj, 8, ParityNone, 1);
// pinout the chosen uart
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
// set rx/tx pins in PullUp mode
if (tx != NC) {
pin_mode(tx, PullUp);
}
if (rx != NC) {
pin_mode(rx, PullUp);
}
if ((rx != NC) && (tx != NC)) {
obj->uart->FCR |= 1 << 0; //enable fifo
}
uart_data[obj->index].sw_rts.pin = NC;
uart_data[obj->index].sw_cts.pin = NC;
serial_set_flow_control(obj, FlowControlNone, NC, NC);
is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
serial_clear(obj);
}
void serial_free(serial_t *obj)
{
uart_data[obj->index].serial_irq_id = 0;
}
// serial_baud
// set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate)
{
MBED_ASSERT((int)obj->uart <= UART_1);
uint32_t baud_divisor;
uint32_t baud_mod;
baud_divisor = (AHBBusClock / baudrate) >> 4;
baud_mod = (AHBBusClock / baudrate) & 0x0F;
obj->uart->LCR |= (1 << 7); //enable load devisor register
obj->uart->DLL = (baud_divisor >> 0) & 0xFF;
obj->uart->DLH = (baud_divisor >> 8) & 0xFF;
obj->uart->DL2 = (baud_mod>>1) + ((baud_mod - (baud_mod>>1))<<4);
obj->uart->LCR &= ~(1 << 7);// after loading, disable load devisor register
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
(parity == ParityForced1) || (parity == ParityForced0));
stop_bits -= 1;
data_bits -= 5;
int parity_enable, parity_select;
switch (parity) {
case ParityNone:
parity_enable = 0;
parity_select = 0;
break;
case ParityOdd:
parity_enable = 1;
parity_select = 0;
break;
case ParityEven:
parity_enable = 1;
parity_select = 1;
break;
case ParityForced1:
parity_enable = 1;
parity_select = 2;
break;
case ParityForced0:
parity_enable = 1;
parity_select = 3;
break;
default:
parity_enable = 0;
parity_select = 0;
break;
}
obj->uart->LCR = (obj->uart->LCR) &
((~0x3FUL) |
(data_bits << 0) |
(stop_bits << 2) |
(parity_enable << 3) |
(parity_select << 4));
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void uart_irq(uint32_t iir, uint32_t index, RDA_UART_TypeDef *puart)
{
SerialIrq irq_type;
switch (iir) {
case 0x02UL: irq_type = TxIrq; break;
case 0x04UL: irq_type = RxIrq; break;
case 0x00UL: iir = puart->MSR;
default: return;
}
if ((RxIrq == irq_type) && ((NC != uart_data[index].sw_rts.pin) && ((puart->MCR & AFCE_MASK) == 0x00UL))) {
gpio_write(&uart_data[index].sw_rts, 1);
// Disable interrupt if it wasn't enabled by other part of the application
if (!uart_data[index].rx_irq_set_api)
puart->IER &= ~(1 << RxIrq);
}
if (uart_data[index].serial_irq_id != 0)
if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
(irq_handler[index])(uart_data[index].serial_irq_id, irq_type);
}
void uart0_irq(void)
{
uart_irq((RDA_UART0->IIR & 0x0FUL), 0, (RDA_UART_TypeDef*)RDA_UART0);
}
void uart1_irq(void)
{
uart_irq((RDA_UART1->IIR & 0x0FUL), 1, (RDA_UART_TypeDef*)RDA_UART1);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler[obj->index] = handler;
uart_data[obj->index].serial_irq_id = id;
}
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable)
{
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
switch ((int)obj->uart) {
case UART_0:
irq_n=UART0_IRQn;
vector = (uint32_t)&uart0_irq;
break;
case UART_1:
irq_n=UART1_IRQn;
vector = (uint32_t)&uart1_irq;
break;
default:
break;
}
if (enable) {
obj->uart->IER |= 1 << irq;
NVIC_SetVector(irq_n, vector);
NVIC_SetPriority(irq_n, 0x1FUL);
NVIC_EnableIRQ(irq_n);
}
else if ((TxIrq == irq) ||
(uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
int all_disabled = 0;
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
obj->uart->IER &= ~(1 << irq);
all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
if (all_disabled)
NVIC_DisableIRQ(irq_n);
}
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
if (RxIrq == irq)
uart_data[obj->index].rx_irq_set_api = enable;
serial_irq_set_internal(obj, irq, enable);
}
static void serial_flow_irq_set(serial_t *obj, uint32_t enable)
{
uart_data[obj->index].rx_irq_set_flow = enable;
serial_irq_set_internal(obj, RxIrq, enable);
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj)
{
int data = 0;
while (!serial_readable(obj));
data = (int)(obj->uart->RBR & 0x00FFUL);
if (((obj->uart->MCR & AFCE_MASK) == 0x00UL) && (NC != uart_data[obj->index].sw_rts.pin)) { //enable flow control rx
gpio_write(&uart_data[obj->index].sw_rts, 0);
obj->uart->IER |= 1 << RxIrq;
}
return data;
}
void serial_putc(serial_t *obj, int c)
{
while (serial_writable(obj));
obj->uart->THR = c;
}
int serial_readable(serial_t *obj)
{
return (obj->uart->LSR & RXFIFO_EMPTY_MASK);
}
int serial_writable(serial_t *obj)
{
int isWritable = 1;
if (obj->index == 0) {
return (obj->uart->FSR & TXFIFO_FULL_MASK); // uart0 not have flow control
} else {
if (((obj->uart->MCR & AFCE_MASK) == 0x00UL) && (NC != uart_data[obj->index].sw_cts.pin)) //If flow control: writable if CTS low + UART done
isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && (obj->uart->FSR & TXFIFO_FULL_MASK);
else
isWritable = (obj->uart->FSR & TXFIFO_FULL_MASK);
return isWritable;
}
}
void serial_clear(serial_t *obj)
{
obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
| 1 << 1 // rx FIFO reset
| 1 << 2; // tx FIFO reset
}
void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj)
{
obj->uart->LCR |= (1 << 6);
}
void serial_break_clear(serial_t *obj)
{
obj->uart->LCR &= ~(1 << 6);
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
{
// Only UART1 has hardware flow control on RDA5991H
MBED_ASSERT((rxflow != UART0_RX) && (txflow != UART0_TX));
RDA_UART_TypeDef *uart1 = (uint32_t)obj->uart == (uint32_t)RDA_UART1 ? RDA_UART1 : NULL;
int index = obj->index;
// First, disable flow control completely
uart_data[index].sw_rts.pin = uart_data[index].sw_cts.pin = NC;
serial_flow_irq_set(obj, 0);
if (FlowControlNone == type) {
RDA_GPIO->IFCTRL &= ~(0x01UL << 2); //disable flow control
return;
}
// Check type(s) of flow control to use
UARTName uart_rts = (UARTName)pinmap_find_peripheral(rxflow, PinMap_UART_RTS);
UARTName uart_cts = (UARTName)pinmap_find_peripheral(txflow, PinMap_UART_CTS);
if ((UART_1 == uart_cts) && (NULL != uart1)) {
pinmap_pinout(txflow, PinMap_UART_CTS);
gpio_init_in(&uart_data[index].sw_cts, txflow);
}
if ((UART_1 == uart_rts) && (NULL != uart1)) {
pinmap_pinout(rxflow, PinMap_UART_RTS);
gpio_init_out(&uart_data[index].sw_rts, rxflow);
serial_flow_irq_set(obj, 1);
}
uart1->MCR = uart1->MCR | AFCE_MASK; //enable auto flow control, in this case we don't have to read and write sw_cts & sw_rts
uart1->FRR = (0x3EUL << 0) | (0x3EUL << 9); //rts/cts fifo trigger
RDA_GPIO->IFCTRL |= 0x01UL << 2; //enable flow control
}

54
targets/TARGET_RDA/TARGET_UNO_91H/sleep.c Normal file
View File

@ -0,0 +1,54 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "sleep_api.h"
#include "cmsis.h"
#include "mbed_interface.h"
#define DEFAULT_PD_BOOTJUMPADDR (0x18001004UL)
void hal_sleep(void)
{
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
// wait for interrupt
__DSB();
__WFI();
}
/*
* The mbed UNO_91H does not support the deepsleep mode
* as a debugger is connected to it (the mbed interface).
*
* We treat a deepsleep() as a normal sleep().
*/
void hal_deepsleep(void)
{
uint32_t regval, gpio_num = 4;
/* Set pd write_en */
RDA_SCU->PWRCTRL |= (0x01UL << 8);
regval = RDA_SCU->PWRCTRL | (0x01UL << 3); // gpio wakeup en
regval &= ~(0x0FUL << 9);
regval |= (gpio_num << 9); // set gpio number
RDA_SCU->PWRCTRL = regval & ~(0x01UL << 14); // posedge
RDA_SCU->BOOTJUMPADDRCFG = DEFAULT_PD_BOOTJUMPADDR;
/* Clr pd write_en */
RDA_SCU->PWRCTRL &= ~(0x01UL << 8);
osDelay(1);
rda_ccfg_ckrst();
osDelay(1);
RDA_SCU->PWRCTRL |= (0x01UL << 25); // goto low-power mode
}

285
targets/TARGET_RDA/TARGET_UNO_91H/spi_api.c Normal file
View File

@ -0,0 +1,285 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if DEVICE_SPI
#include "mbed_assert.h"
#include <math.h>
#include "spi_api.h"
#include "rda_ccfg_api.h"
#include "cmsis.h"
#include "pinmap.h"
/*------------- Wlan Monitor (WLANMON) ---------------------------------------*/
typedef struct
{
__IO uint32_t PHYSEL_3_0; /* 0x00 : PHY select register 0 - 3 */
} RDA_WLANMON_TypeDef;
/*
* Macros
*/
#define RDA_MON ((RDA_WLANMON_TypeDef *)RDA_MON_BASE)
#define ENABLE_RDA_SPI_MODE 0
#define SPI_CLKGATE_REG (RDA_SCU->CLKGATE2)
#define SPI_MODESEL_REG (RDA_GPIO->CTRL)
#define SPI_PINSEL_REG0 (RDA_GPIO->MEMCFG)
#define SPI_PINSEL_REG1 (RDA_MON->PHYSEL_3_0)
#define SPI_PINSEL_REG2 (RDA_EXIF->MISCCFG)
/*
* Global Variables
*/
static const PinMap PinMap_SPI_SCLK[] = {
{PB_4, SPI_0, 4},
{PD_0, SPI_0, 1},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{PB_6, SPI_0, 3},
{PC_0, SPI_0, 6},
{PD_2, SPI_0, 1},
{PB_3, SPI_0, 2},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{PB_7, SPI_0, 3},
{PC_1, SPI_0, 6},
{PD_3, SPI_0, 1},
{PB_8, SPI_0, 3},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{PD_1, SPI_0, 1},
{PB_5, SPI_0, 4},
{PA_0, SPI_0, 3},
{PA_1, SPI_0, 3},
{NC , NC , 0}
};
/*
* Inline Functions
*/
static inline int spi_pin_cs_num(PinName ssel);
static inline void spi_write(spi_t *obj, int value);
static inline int spi_read(spi_t *obj);
/*
* Functions
*/
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
uint32_t reg_val;
/* Determine the SPI to use */
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (RDA_SPI_TypeDef*)pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)obj->spi != NC);
/* Enable power and clocking */
SPI_CLKGATE_REG |= (0x01UL << 18);
/* Select 4-wire SPI mode */
SPI_MODESEL_REG &= ~(0x01UL << 14);
/* Set Config Reg */
reg_val = obj->spi->CFG;
#if ENABLE_RDA_SPI_MODE
/* RDA SPI mode */
reg_val |= (0x01UL << 2);
#else /* ENABLE_RDA_SPI_MODE */
/* Normal SPI mode */
reg_val &= ~(0x01UL << 2);
/* Set read flag */
reg_val |= (0x01UL << 3);
#endif /* ENABLE_RDA_SPI_MODE */
/* Set core cfg for mosi, miso */
if (PB_6 == mosi) {
rda_ccfg_gp(6U, 0x01U);
}
if (PB_7 == miso) {
rda_ccfg_gp(7U, 0x01U);
}
/* Config gpio/wlan_mon regs */
if (PB_3 == mosi) {
SPI_MODESEL_REG &= ~(0x0FUL);
SPI_PINSEL_REG1 &= ~(0x3FUL << 24);
SPI_PINSEL_REG2 &= ~(0x0FUL << 12);
SPI_MODESEL_REG |= (0x0BUL);
SPI_PINSEL_REG1 |= (0x02UL << 24);
SPI_PINSEL_REG2 |= (0x01UL << 12);
}
if (PB_8 == miso) {
SPI_PINSEL_REG0 &= ~(0x01UL << 11);
}
/* Pin out the SPI pins */
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
int cs_num = spi_pin_cs_num(ssel);
reg_val &= ~(0x03UL << 23);
reg_val |= (((uint32_t)cs_num & 0x03UL) << 23);
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
obj->spi->CFG = reg_val;
}
void spi_free(spi_t *obj)
{
/* Disable SPI clock gating */
SPI_CLKGATE_REG &= ~(0x01UL << 18);
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
uint32_t polarity = (mode & 0x2) ? (0x01UL) : (0x00UL);
uint32_t reg_val;
#if ENABLE_RDA_SPI_MODE
MBED_ASSERT(((bits >= 4) && (bits <= 64)) && (mode >= 0 && mode <= 3));
#else /* ENABLE_RDA_SPI_MODE */
MBED_ASSERT(((bits >= 4) && (bits <= 32)) && (mode >= 0 && mode <= 3));
#endif /* ENABLE_RDA_SPI_MODE */
/* Set number of frame bits and clock phase */
reg_val = obj->spi->CFG & ~(0x7FUL << 16) & ~(0x01UL << 1);
obj->spi->CFG = reg_val | ((uint32_t)bits << 16) | (polarity << 1);
#if ENABLE_RDA_SPI_MODE
/* Set bit offset value */
obj->bit_ofst[0] = 0;
obj->bit_ofst[1] = 0;
if (2 > (bits >> 5)) {
obj->bit_ofst[bits >> 5] = (uint8_t)(32 - (bits & 0x1F));
}
#else /* ENABLE_RDA_SPI_MODE */
obj->bit_ofst[0] = (uint8_t)(32 - bits);
#endif /* ENABLE_RDA_SPI_MODE */
}
void spi_frequency(spi_t *obj, int hz)
{
uint32_t clk_rate = ((AHBBusClock / (uint32_t)hz) >> 2) - 1U;
uint32_t reg_val;
/* Check for valid frequency */
MBED_ASSERT(clk_rate <= 0x3FUL);
/* Set clk rate field */
reg_val = obj->spi->CFG & ~(0x3FUL << 4);
obj->spi->CFG = reg_val | ((clk_rate & 0x3FUL) << 4);
}
int spi_master_write(spi_t *obj, int value)
{
spi_write(obj, value);
return spi_read(obj);
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill)
{
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
char in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
int spi_busy(spi_t *obj)
{
return (obj->spi->CFG & (0x01UL << 31)) ? (1) : (0);
}
static inline int spi_pin_cs_num(PinName ssel)
{
int idx = 0;
while (PinMap_SPI_SSEL[idx].pin != NC) {
if (PinMap_SPI_SSEL[idx].pin == ssel)
return idx;
idx++;
}
return (int)NC;
}
static inline void spi_write(spi_t *obj, int value)
{
#if ENABLE_RDA_SPI_MODE
/* Write data register */
if (obj->bit_ofst[0] != 0) {
obj->spi->D1CMD = (uint32_t)value << obj->bit_ofst[0];
} else {
obj->spi->D1CMD = (uint32_t)value;
obj->spi->D0CMD = (uint32_t)value << obj->bit_ofst[1];
}
/* Set write bit & start bit */
obj->spi->CFG = (obj->spi->CFG & ~(0x01UL << 3)) | 0x01UL;
#else /* ENABLE_RDA_SPI_MODE */
/* Write data reg */
if (obj->bit_ofst[0] != 0) {
obj->spi->D1CMD = ((uint32_t)value << obj->bit_ofst[0]) | (0xFFFFFFFFUL >> (32 - obj->bit_ofst[0]));
} else {
obj->spi->D1CMD = (uint32_t)value;
obj->spi->D0CMD = 0xFFFFFFFFUL;
}
/* Set start bit */
obj->spi->CFG |= 0x01UL;
#endif /* ENABLE_RDA_SPI_MODE */
__DSB();
while (spi_busy(obj));
}
static inline int spi_read(spi_t *obj)
{
uint32_t ret_val;
#if ENABLE_RDA_SPI_MODE
/* Set read bit & start bit */
obj->spi->CFG |= ((0x01UL << 3) | 0x01UL);
__DSB();
while (spi_busy(obj));
/* Read data register */
if (obj->bit_ofst[0] != 0) {
ret_val = obj->spi->D0CMD & ((0x01UL << (32UL - obj->bit_ofst[0])) - 1UL);
} else {
ret_val = obj->spi->D0CMD;
ret_val = obj->spi->D1CMD & ((0x01UL << (32UL - obj->bit_ofst[1])) - 1UL);
}
#else /* ENABLE_RDA_SPI_MODE */
/* Read data register */
ret_val = obj->spi->D0CMD & ((0x01UL << (32UL - obj->bit_ofst[0])) - 1UL);
#endif /* ENABLE_RDA_SPI_MODE */
return (int)ret_val;
}
#endif

119
targets/TARGET_RDA/TARGET_UNO_91H/trng_api.c Normal file
View File

@ -0,0 +1,119 @@
/*
* Hardware entropy collector for the UNO_91H, using RDA's TRNG
*
* Copyright (C) 2006-2018, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#if defined(DEVICE_TRNG)
#include "cmsis.h"
#include "trng_api.h"
#include "us_ticker_api.h"
#define rRNG_CLKGATE (RDA_SCU->CLKGATE0)
#define rRNG_CLKGEN (RDA_DMACFG->dma_func_ctrl)
#define rTRNG_CTRL (RDA_RNG->TCTRL)
#define rPRNG_DATA (RDA_RNG->PD)
static uint32_t trng_inited = 0;
/** trng_get_byte
* @brief Get one byte of entropy from the RNG, assuming it is up and running.
* @param obj TRNG obj
* @param pointer to the hardware generated random byte.
*/
static void trng_get_byte(trng_t *obj, unsigned char *byte )
{
if (0U == obj->byte_idx) {
uint32_t start_time = us_ticker_read();
/* Delay for PRNG data ready, generate 4-byte per 32us */
while ((us_ticker_read() - start_time) <= 32);
}
*byte = (unsigned char)((rPRNG_DATA >> (obj->byte_idx << 3)) & 0x00FFUL);
obj->byte_idx++;
obj->byte_idx &= 0x03U;
}
void trng_init(trng_t *obj)
{
uint32_t regval, start_time = 0;
volatile uint32_t count = 10;
if(trng_inited == 1)
return;
obj->dma_clk_flag = (uint8_t)((rRNG_CLKGATE >> 18) & 0x01U);
obj->byte_idx = 0;
if (0x00U == obj->dma_clk_flag) {
/* DMA Peripheral clock enable */
rRNG_CLKGATE |= (0x01UL << 18);
/* dealy after clk en */
while(count--);
}
/* RNG Engine clock enable */
rRNG_CLKGEN |= (0x01UL << 30);
/* Set TRNG enable bit, once mode */
regval = rTRNG_CTRL | ((0x01UL << 4) | (0xFFUL << 16));
rTRNG_CTRL = regval & ~((0x01UL << 1) | (0x01UL << 2) | (0x01UL << 3));
/*Entropy data was mixed by TRNG seed and noise, so we add one 32us delay to
ensure all 32 bits of seed is entropy when init and
another delay to update noise data when get data.
*/
/* Delay for TRNG seed ready */
start_time = us_ticker_read();
while ((us_ticker_read() - start_time) <= 32);
rTRNG_CTRL |= (0x01UL << 0);
trng_inited = 1;
}
void trng_free(trng_t *obj)
{
if(trng_inited == 0)
return;
/* Clear TRNG enable bit */
rTRNG_CTRL = 0x00UL;
/* RNG Engine clock disable */
rRNG_CLKGEN &= ~(0x01UL << 30);
if (0x00U == obj->dma_clk_flag) {
/* DMA Peripheral clock disable */
rRNG_CLKGATE &= ~(0x01UL << 18);
}
trng_inited = 0;
}
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
{
int ret = 0;
if(trng_inited != 1)
return -1;
/* Get Random byte */
for (uint32_t i = 0; i < length; i++) {
trng_get_byte(obj, output + i);
}
*output_length = length;
return ret;
}
#endif

237
targets/TARGET_RDA/TARGET_UNO_91H/us_ticker.c Normal file
View File

@ -0,0 +1,237 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "us_ticker_api.h"
#include "rda_ccfg_api.h"
#include "mbed_critical.h"
#define US_TICKER_TIMER (RDA_TIM0)
#define rTIMER0_CURVAL (RDA_TIM0->CVAL)
#define TIMER0_PRESCALE (8)
#define TIMER0_SHIFTBITS (3)
#define TIMER0_LDCNT_INIT_VAL (0xFFFFFFFF)
#define TIMER0_MAX_COUNT (0x1FFFFFFF)
#define TIMER0_CONTROL_ENABLE (0x01)
#define TIMER0_CONTROL_MODE (0x02)
#define TIMER0_CONTROL_INT_MSK (0x04)
volatile uint32_t us_ticker_clrInt = 0;
static uint32_t us_ticker_inited = 0;
uint32_t us_ticker_soft_int_flag;
static uint32_t us_ticker_timestamp;
static uint32_t us_ticker_interruptCount;
extern void rda_timer_irq_set(void);
void us_ticker_init(void)
{
if (us_ticker_inited) {
us_ticker_disable_interrupt();
return;
}
/* Enable apb timer clock */
RDA_SCU->CLKGATE1 |= (0x01UL << 3);
/* Set timer mode */
US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_MODE);
/* Set period mode */
RDA_GPIO->REVID |= (0x01UL << 25);
/* Set timer count */
US_TICKER_TIMER->LDCNT = TIMER0_LDCNT_INIT_VAL;
/* Enable timer */
US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_ENABLE);
/* mask timer, disable an overflow int */
US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_INT_MSK);
rda_timer_irq_set();
/* Set us_ticker_inited true, after all settings done */
us_ticker_inited = 1U;
us_ticker_soft_int_flag = 0;
us_ticker_timestamp = 0;
us_ticker_interruptCount = TIMER0_MAX_COUNT;
}
uint32_t us_ticker_read(void)
{
if (!us_ticker_inited) {
return 0 ;
}
uint32_t tick_readout = 0 ;
core_util_critical_section_enter();
uint32_t ticker = rTIMER0_CURVAL >> TIMER0_SHIFTBITS ;
if (us_ticker_interruptCount > ticker)
tick_readout = (us_ticker_timestamp + us_ticker_interruptCount - ticker) % TIMER0_MAX_COUNT ;
else
tick_readout = (us_ticker_timestamp + TIMER0_MAX_COUNT + us_ticker_interruptCount - ticker) % TIMER0_MAX_COUNT ;
core_util_critical_section_exit();
return tick_readout;
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
if (!us_ticker_inited) {
return ;
}
uint32_t tmp_stamp = timestamp % TIMER0_MAX_COUNT ;
core_util_critical_section_enter();
us_ticker_timestamp = us_ticker_read() ;
us_ticker_interruptCount = (tmp_stamp > us_ticker_timestamp) ? (tmp_stamp - us_ticker_timestamp):(tmp_stamp + TIMER0_MAX_COUNT - us_ticker_timestamp) ;
/* Disable timer */
US_TICKER_TIMER->TCTRL &= (~TIMER0_CONTROL_ENABLE);
US_TICKER_TIMER->LDCNT = us_ticker_interruptCount << TIMER0_SHIFTBITS ;
/* Enable timer */
US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_ENABLE);
/* Unmask timer, enable an overflow int */
US_TICKER_TIMER->TCTRL &= (~(TIMER0_CONTROL_INT_MSK));
core_util_critical_section_exit();
return ;
}
void us_ticker_fire_interrupt(void)
{
if (!us_ticker_inited) {
return ;
}
core_util_critical_section_enter();
us_ticker_soft_int_flag = 1 ;
NVIC_SetPendingIRQ(TIMER_IRQn);
core_util_critical_section_exit();
}
void us_ticker_disable_interrupt_help(void)
{
if (!us_ticker_inited) {
return ;
}
/* Mask timer, disable an overflow int */
US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_INT_MSK);
}
void us_ticker_disable_interrupt(void)
{
if (!us_ticker_inited) {
return ;
}
core_util_critical_section_enter();
/* Mask timer, disable an overflow int */
US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_INT_MSK);
us_ticker_timestamp = us_ticker_read();
us_ticker_interruptCount = TIMER0_MAX_COUNT;
/* Disable timer */
US_TICKER_TIMER->TCTRL &= (~TIMER0_CONTROL_ENABLE);
/* Set timer count */
US_TICKER_TIMER->LDCNT = TIMER0_LDCNT_INIT_VAL;
/* Enable timer */
US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_ENABLE);
/* mask timer, disable an overflow int */
US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_INT_MSK);
core_util_critical_section_exit();
}
void us_ticker_clear_interrupt(void)
{
if (!us_ticker_inited) {
return ;
}
us_ticker_clrInt = US_TICKER_TIMER->INTCLR;
}
const ticker_info_t* us_ticker_get_info()
{
static const ticker_info_t info =
{
5000000, // 5MHZ
29 // 29 bit counter
};
return &info;
}
void us_ticker_free(void)
{
if (!us_ticker_inited) {
return ;
}
core_util_critical_section_enter();
us_ticker_disable_interrupt_help();
us_ticker_clear_interrupt();
/* Disable timer */
US_TICKER_TIMER->TCTRL &= (~TIMER0_CONTROL_ENABLE);
us_ticker_inited = 0;
us_ticker_timestamp = 0 ;
us_ticker_interruptCount = 0 ;
core_util_critical_section_exit();
return;
}
void us_ticker_irq_callback()
{
us_ticker_clear_interrupt () ;
if (us_ticker_soft_int_flag == 1) {
us_ticker_soft_int_flag = 0 ;
return ;
}
core_util_critical_section_enter();
/* Check the flag firstly, because following hanlder can change it */
us_ticker_disable_interrupt_help();
/* Disable timer */
US_TICKER_TIMER->TCTRL &= (~TIMER0_CONTROL_ENABLE);
US_TICKER_TIMER->LDCNT = TIMER0_LDCNT_INIT_VAL ;
/* Enable timer */
US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_ENABLE);
/* mask timer, disable an overflow int */
US_TICKER_TIMER->TCTRL |= (TIMER0_CONTROL_INT_MSK);
core_util_critical_section_exit();
}

56
targets/TARGET_RDA/mbed_rtx.h Normal file
View File

@ -0,0 +1,56 @@
/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_MBED_RTX_H
#define MBED_MBED_RTX_H
#include <stdint.h>
#ifndef OS_TASKCNT
#define OS_TASKCNT 14
#endif
#ifndef OS_MAINSTKSIZE
#define OS_MAINSTKSIZE 256
#endif
#ifndef OS_CLOCK
#define OS_CLOCK 160000000
#endif
#if defined(__CC_ARM)
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[];
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[];
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[];
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Length[];
#define HEAP_START ((unsigned char*) Image$$ARM_LIB_HEAP$$ZI$$Base)
#define HEAP_SIZE ((uint32_t) Image$$ARM_LIB_HEAP$$ZI$$Length)
#define ISR_STACK_START ((unsigned char*)Image$$ARM_LIB_STACK$$ZI$$Base)
#define ISR_STACK_SIZE ((uint32_t)Image$$ARM_LIB_STACK$$ZI$$Length)
#elif defined(__GNUC__)
extern uint32_t __StackTop[];
extern uint32_t __StackLimit[];
extern uint32_t __end__[];
extern uint32_t __HeapLimit[];
#define HEAP_START ((unsigned char*)__end__)
#define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START))
#define ISR_STACK_START ((unsigned char*)__StackLimit)
#define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit))
#elif defined(__ICCARM__)
/* No region declarations needed */
#else
#error "no toolchain defined"
#endif
#endif // MBED_MBED_RTX_H

14
targets/targets.json
View File

@ -7398,5 +7398,19 @@
"device_name": "TMPM3HQFDFG",
"detect_code": ["7014"],
"release_versions": ["5"]
},
"RDA5981X": {
"inherits": ["Target"],
"core": "Cortex-M4F",
"public": true,
"extra_labels": ["RDA", "UNO_91H", "FLASH_CMSIS_ALGO"],
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"macros": ["TWO_RAM_REGIONS", "CMSIS_NVIC_VIRTUAL", "CMSIS_NVIC_VIRTUAL_HEADER_FILE=\"RDA5981_nvic_virtual.h\""],
"device_has": ["USTICKER", "PORTIN", "PORTOUT", "PORTINOUT", "INTERRUPTIN", "SERIAL", "STDIO_MESSAGES", "PWMOUT", "SPI", "SLEEP", "ANALOGIN", "FLASH", "TRNG"],
"release_versions": ["2", "5"]
},
"UNO_91H": {
"inherits": ["RDA5981X"],
"detect_code": ["8001"]
}
}