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Error resolve, bug fix and 2 new targets information add 

1. Resolve the Error: L6218E: Undefined symbol flash_get_erase_value
2. Bug fix (ADC, USART, etc.)
3. Modify the wrong name (TATGET_GigaDevice-->TARGET_GigaDevice)
4. Add new targets (GD32-F450ZI and GD32-E103VB) support to target.json
5. Add INITIAL_SP macro for GD32-F450ZI and GD32-E103VB
pull/8725/head
c_jin 2018-12-06 19:43:20 +08:00
parent 95f7a97a9b
commit 881561ac5e
25 changed files with 1842 additions and 1748 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/PeripheralNames.h → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/PeripheralNames.h
View File

@ -43,9 +43,9 @@ typedef enum {
UART_4 = (int)UART4
} UARTName;
#define STDIO_UART_TX PORTA_9
#define STDIO_UART_RX PORTA_10
#define STDIO_UART UART_0
#define STDIO_UART_TX PORTC_10
#define STDIO_UART_RX PORTC_11
#define STDIO_UART UART_2
typedef enum {
SPI_0 = (int)SPI0,

8
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/PeripheralPins.c → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/PeripheralPins.c
View File

@ -272,7 +272,7 @@ const PinMap PinMap_UART_TX[] = {
{PORTB_10, UART_2, 7},
{PORTC_10, UART_2, 7 | (5 << 3)}, /* GPIO_USART2_TX_PARTIAL_REMAP */
{PORTD_8, UART_2, 7 | (6 << 3)}, /* GPIO_USART2_TX_FULL_REMAP */
{PORTC_10, UART_3, 7},
{PORTC_10_MUL0, UART_3, 7},
{PORTC_12, UART_4, 7},
{NC, NC, 0}
};
@ -284,8 +284,8 @@ const PinMap PinMap_UART_RX[] = {
{PORTD_6, UART_1, 1 | (4 << 3)}, /* GPIO_USART1_RX_REMAP */
{PORTB_11, UART_2, 1},
{PORTC_11, UART_2, 1 | (5 << 3)}, /* GPIO_USART2_RX_PARTIAL_REMAP */
{PORTD_9, UART_2, 1 | (6 << 3)}, /* PGPIO_USART2_RX_PARTIAL_REMAP */
{PORTC_11, UART_3, 1},
{PORTD_9, UART_2, 1 | (6 << 3)}, /* GPIO_USART2_RX_FULL_REMAP */
{PORTC_11_MUL0, UART_3, 1},
{PORTD_2, UART_4, 1},
{NC, NC, 0}
};
@ -317,7 +317,7 @@ const PinMap PinMap_SPI_MOSI[] = {
};
const PinMap PinMap_SPI_MISO[] = {
{PORTA_6, SPI_0, 1},
{PORTA_6, SPI_0, 7},
{PORTB_4, SPI_0, 7 | (1 << 3)}, /* GPIO_SPI0_REMAP */
{PORTB_14, SPI_1, 7},
{NC, NC, 0}

69
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/PinNames.h → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/PinNames.h
View File

@ -102,7 +102,9 @@ typedef enum {
PORTC_9 = 0x29,
PORTC_9_MUL0 = PORTC_9 | MUL0,
PORTC_10 = 0x2A,
PORTC_10_MUL0 = PORTC_10 | MUL0,
PORTC_11 = 0x2B,
PORTC_11_MUL0 = PORTC_11 | MUL0,
PORTC_12 = 0x2C,
PORTC_13 = 0x2D,
PORTC_14 = 0x2E,
@ -152,21 +154,19 @@ typedef enum {
A1 = PORTC_1,
A2 = PORTC_2,
A3 = PORTC_3,
A4 = PORTC_4,
A4_I2C_SDA = PORTC_11,
A4_I2C_SCL = PORTC_10,
A5 = PORTC_5,
A4 = PORTA_0,
A5 = PORTB_1,
D0 = PORTA_3,
D1 = PORTA_2,
D2 = PORTA_4,
D3 = PORTC_6,
D2 = PORTE_4,
D3 = PORTD_12,
D4 = PORTB_3,
D5 = PORTC_7,
D6 = PORTC_8,
D6 = PORTB_0,
D7 = PORTB_4,
D8 = PORTB_5,
D9 = PORTC_9,
D10 = PORTA_1,
D8 = PORTD_11,
D9 = PORTE_5,
D10 = PORTA_8,
D11 = PORTB_15,
D12 = PORTB_14,
D13 = PORTB_13,
@ -177,29 +177,44 @@ typedef enum {
LED2 = PORTE_1,
LED3 = PORTE_6,
KEY2 = PORTA_0,
KEY3 = PORTB_1,
KEY1 = PORTE_2,
KEY2 = PORTE_7,
BUTTON1 = KEY2,
BUTTON2 = KEY3,
BUTTON1 = KEY1,
BUTTON2 = KEY2,
SERIAL_TX = PORTA_9,
SERIAL_RX = PORTA_10,
USBTX = PORTA_9,
USBRX = PORTA_10,
SERIAL_TX = PORTC_10,
SERIAL_RX = PORTC_11,
USBTX = SERIAL_TX,
USBRX = SERIAL_RX,
I2C_SCL = PORTB_6,
I2C_SDA = PORTB_7,
SPI_MOSI = PORTA_7,
SPI_MISO = PORTA_6,
SPI_SCK = PORTA_5,
SPI_CS = PORTE_3,
PWM_OUT = PORTA_7,
I2C_SCL = D15,
I2C_SDA = D14,
SPI_MOSI = D11,
SPI_MISO = D12,
SPI_SCK = D13,
SPI_CS = D10,
PWM_OUT = D9,
USBFS_VBUS = PORTA_9,
USBFS_DM = PORTA_11,
USBFS_DP = PORTA_12,
RMII_TX_EN = PORTB_11,
RMII_TXD0 = PORTB_12,
RMII_TXD1 = PORTB_13,
RMII_RXD0 = PORTC_4,
RMII_RXD1 = PORTC_5,
RMII_CRS_DV = PORTA_7,
RMII_MDC = PORTC_1,
RMII_MDIO = PORTA_2,
RMII_INT = PORTB_0,
RMII_REF_CLK = PORTA_1,
NC = (int)0xFFFFFFFF
} PinName;
/* BIT[7:4] port number (0=PORTA, 1=PORTB, 2=PORTC, 3=PORTD, 4=PORTE, 5=PORTF)
/* BIT[7:4] port number (0=PORTA, 1=PORTB, 2=PORTC, 3=PORTD, 4=PORTE)
BIT[3:0] pin number */
#define GD_PORT_GET(X) (((uint32_t)(X) >> 4) & 0xF)
#define GD_PIN_GET(X) (((uint32_t)(X) & 0xF))
@ -208,7 +223,7 @@ typedef enum {
#define GD_PIN_MODE_GET(X) (X & 0x07)
#define GD_PIN_SPEED_GET(X) ((X >> 9) & 0x03)
#define GD_PIN_REMAP_GET(X) ((X >> 3) & 0x3F)
#define GD_PIN_CHANNEL_GET(X) ((X >> 11) & 0x0F)
#define GD_PIN_CHANNEL_GET(X) ((X >> 11) & 0x1F)
/* Defines GPIO pin direction */
typedef enum {

54
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/gd32f307vg.sct → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/gd32f307vg.sct
View File

@ -1,27 +1,27 @@
#! armcc -E
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *****
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x08000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x100000
#endif
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K)
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150)
RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data
.ANY (+RW +ZI)
}
}
#! armcc -E
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *****
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x08000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x100000
#endif
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K)
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150)
RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data
.ANY (+RW +ZI)
}
}

0
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.S → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_MICRO/startup_gd32f30x_cl.S
View File

54
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/gd32f307vg.sct → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/gd32f307vg.sct
View File

@ -1,27 +1,27 @@
#! armcc -E
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *****
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x08000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x100000
#endif
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K)
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150)
RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data
.ANY (+RW +ZI)
}
}
#! armcc -E
; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *****
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x08000000
#endif
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x100000
#endif
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region (1024K)
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 84 vectors (16 core + 68 peripheral) * 4 bytes = 336 bytes to reserve (0x150)
RW_IRAM1 (0x20000000+0x150) (0x18000-0x150) { ; RW data
.ANY (+RW +ZI)
}
}

0
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.S → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_ARM_STD/startup_gd32f30x_cl.S
View File

246
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/GD32F307xG.ld → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/GD32F307xG.ld
View File

@ -1,123 +1,123 @@
/* specify memory regions */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
RAM (rwx) : ORIGIN = 0x20000150, LENGTH = 96K - 0x150
}
/* define output sections */
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
_sidata = .;
.data : AT (__etext)
{
__data_start__ = .;
_sdata = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
_edata = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
_ebss = .;
} > RAM
.heap (COPY):
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* initializes stack on the end of block */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
_estack = __StackTop;
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
/* specify memory regions */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
RAM (rwx) : ORIGIN = 0x20000150, LENGTH = 96K - 0x150
}
/* define output sections */
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
_sidata = .;
.data : AT (__etext)
{
__data_start__ = .;
_sdata = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
_edata = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
_ebss = .;
} > RAM
.heap (COPY):
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* initializes stack on the end of block */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
_estack = __StackTop;
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

0
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.S → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_GCC_ARM/startup_gd32f30x_cl.S
View File

70
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_IAR/gd32f307vg.icf → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_IAR/gd32f307vg.icf
View File

@ -1,36 +1,36 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000;
define symbol __ICFEDIT_region_NVIC_end__ = 0x2000014F;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000150;
define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
/*-Sizes-*/
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x3000;
define symbol __ICFEDIT_size_heap__ = 0x6000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
define symbol __ICFEDIT_region_NVIC_start__ = 0x20000000;
define symbol __ICFEDIT_region_NVIC_end__ = 0x2000014F;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000150;
define symbol __ICFEDIT_region_RAM_end__ = 0x20017FFF;
/*-Sizes-*/
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x3000;
define symbol __ICFEDIT_size_heap__ = 0x6000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block HEAP, block CSTACK };

0
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/TOOLCHAIN_IAR/startup_gd32f30x_cl.S → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/TOOLCHAIN_IAR/startup_gd32f30x_cl.S
View File

0
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/cmsis.h → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/cmsis.h
View File

0
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/cmsis_nvic.h → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/cmsis_nvic.h
View File

772
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/gd32f30x.h → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/gd32f30x.h
View File

@ -1,386 +1,386 @@
/*!
\file gd32f30x.h
\brief general definitions for GD32F30x
\version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32F30X_H
#define GD32F30X_H
#ifdef __cplusplus
extern "C" {
#endif
/* define GD32F30x */
#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL)
/* #define GD32F30X_HD */
/* #define GD32F30X_XD */
/* #define GD32F30X_CL */
#endif /* define GD32F30x */
#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL)
#error "Please select the target GD32F30x device in gd32f30x.h file"
#endif /* undefine GD32F30x tip */
/* define value of high speed crystal oscillator (HXTAL) in Hz */
#if !defined HXTAL_VALUE
#ifdef GD32F30X_CL
#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */
#else
#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/
#endif /* HXTAL_VALUE */
#endif /* high speed crystal oscillator value */
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
#if !defined (HXTAL_STARTUP_TIMEOUT)
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800)
#endif /* high speed crystal oscillator startup timeout */
/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
#if !defined (IRC48M_VALUE)
#define IRC48M_VALUE ((uint32_t)48000000)
#endif /* internal 48MHz RC oscillator value */
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
#if !defined (IRC8M_VALUE)
#define IRC8M_VALUE ((uint32_t)8000000)
#endif /* internal 8MHz RC oscillator value */
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
#if !defined (IRC8M_STARTUP_TIMEOUT)
#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* internal 8MHz RC oscillator startup timeout */
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
#if !defined (IRC40K_VALUE)
#define IRC40K_VALUE ((uint32_t)40000)
#endif /* internal 40KHz RC oscillator value */
/* define value of low speed crystal oscillator (LXTAL)in Hz */
#if !defined (LXTAL_VALUE)
#define LXTAL_VALUE ((uint32_t)32768)
#endif /* low speed crystal oscillator value */
/* GD32F30x firmware library version number V1.0 */
#define __GD32F30x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __GD32F30x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __GD32F30x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __GD32F30x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __GD32F30x_STDPERIPH_VERSION ((__GD32F30x_STDPERIPH_VERSION_MAIN << 24)\
|(__GD32F30x_STDPERIPH_VERSION_SUB1 << 16)\
|(__GD32F30x_STDPERIPH_VERSION_SUB2 << 8)\
|(__GD32F30x_STDPERIPH_VERSION_RC))
/* configuration of the Cortex-M4 processor and core peripherals */
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< GD32F30x do not provide MPU */
#define __NVIC_PRIO_BITS 4 /*!< GD32F30x uses 4 bits for the priority levels */
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
/* define interrupt number */
typedef enum IRQn
{
/* Cortex-M4 processor exceptions numbers */
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */
/* interruput numbers */
WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */
RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */
FMC_IRQn = 4, /*!< FMC interrupt */
RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */
#ifdef GD32F30X_HD
USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */
TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */
TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */
TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
SPI0_IRQn = 35, /*!< SPI0 interrupt */
SPI1_IRQn = 36, /*!< SPI1 interrupt */
USART0_IRQn = 37, /*!< USART0 interrupt */
USART1_IRQn = 38, /*!< USART1 interrupt */
USART2_IRQn = 39, /*!< USART2 interrupt */
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */
TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */
TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */
TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
EXMC_IRQn = 48, /*!< EXMC global interrupt */
SDIO_IRQn = 49, /*!< SDIO global interrupt */
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
UART3_IRQn = 52, /*!< UART3 global interrupt */
UART4_IRQn = 53, /*!< UART4 global interrupt */
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */
#endif /* GD32F30X_HD */
#ifdef GD32F30X_XD
USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare interrupts */
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
SPI0_IRQn = 35, /*!< SPI0 interrupt */
SPI1_IRQn = 36, /*!< SPI1 interrupt */
USART0_IRQn = 37, /*!< USART0 interrupt */
USART1_IRQn = 38, /*!< USART1 interrupt */
USART2_IRQn = 39, /*!< USART2 interrupt */
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
EXMC_IRQn = 48, /*!< EXMC global interrupt */
SDIO_IRQn = 49, /*!< SDIO global interrupt */
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
UART3_IRQn = 52, /*!< UART3 global interrupt */
UART4_IRQn = 53, /*!< UART4 global interrupt */
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */
#endif /* GD32F30X_XD */
#ifdef GD32F30X_CL
CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
SPI0_IRQn = 35, /*!< SPI0 interrupt */
SPI1_IRQn = 36, /*!< SPI1 interrupt */
USART0_IRQn = 37, /*!< USART0 interrupt */
USART1_IRQn = 38, /*!< USART1 interrupt */
USART2_IRQn = 39, /*!< USART2 interrupt */
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */
USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
EXMC_IRQn = 48, /*!< EXMC global interrupt */
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
UART3_IRQn = 52, /*!< UART3 global interrupt */
UART4_IRQn = 53, /*!< UART4 global interrupt */
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */
ENET_IRQn = 61, /*!< ENET global interrupt */
ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
USBFS_IRQn = 67, /*!< USBFS global interrupt */
#endif /* GD32F30X_CL */
} IRQn_Type;
/* includes */
#include "core_cm4.h"
#include "system_gd32f30x.h"
#include <stdint.h>
#define GD_MBED_USED
#ifdef GD_MBED_USED
typedef enum
{
GD_OK = 0x00U,
GD_ERROR = 0x01U,
GD_BUSY = 0x02U,
GD_TIMEOUT = 0x03U
}gd_status_enum;
typedef enum
{
OP_STATE_RESET = 0x00U,
OP_STATE_READY = 0x01U,
OP_STATE_BUSY = 0x02U,
OP_STATE_TIMEOUT = 0x03U,
OP_STATE_ERROR = 0x04U,
OP_STATE_ABORT = 0x05U,
OP_STATE_LISTEN = 0x06U,
OP_STATE_BUSY_TX = 0x21U, /* (OP_STATE_BUSY << 4) + 1 */
OP_STATE_BUSY_RX = 0x22U, /* (OP_STATE_BUSY << 4) + 2 */
OP_STATE_BUSY_TX_LISTEN = 0x61U, /* (OP_STATE_LISTEN << 4) + 1 */
OP_STATE_BUSY_RX_LISTEN = 0x62U, /* (OP_STATE_LISTEN << 4) + 2 */
OP_STATE_BUTT
}operation_state_enum;
#endif
/* enum definitions */
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
/* bit operations */
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
/* main flash and SRAM memory map */
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
/* peripheral memory map */
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
/* advanced peripheral bus 1 memory map */
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */
/* advanced peripheral bus 2 memory map */
#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
/* advanced high performance bus 1 memory map */
#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */
#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
/* define marco USE_STDPERIPH_DRIVER */
#if !defined USE_STDPERIPH_DRIVER
#define USE_STDPERIPH_DRIVER
#endif
#ifdef USE_STDPERIPH_DRIVER
#include "gd32f30x_libopt.h"
#endif /* USE_STDPERIPH_DRIVER */
#ifdef __cplusplus
}
#endif
#endif
/*!
\file gd32f30x.h
\brief general definitions for GD32F30x
\version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32F30X_H
#define GD32F30X_H
#ifdef __cplusplus
extern "C" {
#endif
/* define GD32F30x */
#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL)
/* #define GD32F30X_HD */
/* #define GD32F30X_XD */
/* #define GD32F30X_CL */
#endif /* define GD32F30x */
#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL)
#error "Please select the target GD32F30x device in gd32f30x.h file"
#endif /* undefine GD32F30x tip */
/* define value of high speed crystal oscillator (HXTAL) in Hz */
#if !defined HXTAL_VALUE
#ifdef GD32F30X_CL
#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */
#else
#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 16M *!< value of the external oscillator in Hz*/
#endif /* HXTAL_VALUE */
#endif /* high speed crystal oscillator value */
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
#if !defined (HXTAL_STARTUP_TIMEOUT)
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800)
#endif /* high speed crystal oscillator startup timeout */
/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
#if !defined (IRC48M_VALUE)
#define IRC48M_VALUE ((uint32_t)48000000)
#endif /* internal 48MHz RC oscillator value */
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
#if !defined (IRC8M_VALUE)
#define IRC8M_VALUE ((uint32_t)8000000)
#endif /* internal 8MHz RC oscillator value */
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
#if !defined (IRC8M_STARTUP_TIMEOUT)
#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* internal 8MHz RC oscillator startup timeout */
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
#if !defined (IRC40K_VALUE)
#define IRC40K_VALUE ((uint32_t)40000)
#endif /* internal 40KHz RC oscillator value */
/* define value of low speed crystal oscillator (LXTAL)in Hz */
#if !defined (LXTAL_VALUE)
#define LXTAL_VALUE ((uint32_t)32768)
#endif /* low speed crystal oscillator value */
/* GD32F30x firmware library version number V1.0 */
#define __GD32F30x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __GD32F30x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __GD32F30x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __GD32F30x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __GD32F30x_STDPERIPH_VERSION ((__GD32F30x_STDPERIPH_VERSION_MAIN << 24)\
|(__GD32F30x_STDPERIPH_VERSION_SUB1 << 16)\
|(__GD32F30x_STDPERIPH_VERSION_SUB2 << 8)\
|(__GD32F30x_STDPERIPH_VERSION_RC))
/* configuration of the Cortex-M4 processor and core peripherals */
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< GD32F30x do not provide MPU */
#define __NVIC_PRIO_BITS 4 /*!< GD32F30x uses 4 bits for the priority levels */
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
/* define interrupt number */
typedef enum IRQn
{
/* Cortex-M4 processor exceptions numbers */
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */
/* interruput numbers */
WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */
RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */
FMC_IRQn = 4, /*!< FMC interrupt */
RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */
#ifdef GD32F30X_HD
USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupts */
TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupts */
TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupts */
TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
SPI0_IRQn = 35, /*!< SPI0 interrupt */
SPI1_IRQn = 36, /*!< SPI1 interrupt */
USART0_IRQn = 37, /*!< USART0 interrupt */
USART1_IRQn = 38, /*!< USART1 interrupt */
USART2_IRQn = 39, /*!< USART2 interrupt */
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */
TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupts */
TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupts */
TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupts */
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
EXMC_IRQn = 48, /*!< EXMC global interrupt */
SDIO_IRQn = 49, /*!< SDIO global interrupt */
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
UART3_IRQn = 52, /*!< UART3 global interrupt */
UART4_IRQn = 53, /*!< UART4 global interrupt */
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */
#endif /* GD32F30X_HD */
#ifdef GD32F30X_XD
USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare interrupts */
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
SPI0_IRQn = 35, /*!< SPI0 interrupt */
SPI1_IRQn = 36, /*!< SPI1 interrupt */
USART0_IRQn = 37, /*!< USART0 interrupt */
USART1_IRQn = 38, /*!< USART1 interrupt */
USART2_IRQn = 39, /*!< USART2 interrupt */
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
EXMC_IRQn = 48, /*!< EXMC global interrupt */
SDIO_IRQn = 49, /*!< SDIO global interrupt */
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
UART3_IRQn = 52, /*!< UART3 global interrupt */
UART4_IRQn = 53, /*!< UART4 global interrupt */
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */
#endif /* GD32F30X_XD */
#ifdef GD32F30X_CL
CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
TIMER0_CC_IRQn = 27, /*!< TIMER0 capture compare interrupts */
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
SPI0_IRQn = 35, /*!< SPI0 interrupt */
SPI1_IRQn = 36, /*!< SPI1 interrupt */
USART0_IRQn = 37, /*!< USART0 interrupt */
USART1_IRQn = 38, /*!< USART1 interrupt */
USART2_IRQn = 39, /*!< USART2 interrupt */
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
RTC_ALARM_IRQn = 41, /*!< RTC alarm interrupt */
USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
TIMER7_CC_IRQn = 46, /*!< TIMER7 capture compare interrupts */
EXMC_IRQn = 48, /*!< EXMC global interrupt */
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
UART3_IRQn = 52, /*!< UART3 global interrupt */
UART4_IRQn = 53, /*!< UART4 global interrupt */
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */
ENET_IRQn = 61, /*!< ENET global interrupt */
ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
USBFS_IRQn = 67, /*!< USBFS global interrupt */
#endif /* GD32F30X_CL */
} IRQn_Type;
/* includes */
#include "core_cm4.h"
#include "system_gd32f30x.h"
#include <stdint.h>
#define GD_MBED_USED
#ifdef GD_MBED_USED
typedef enum
{
GD_OK = 0x00U,
GD_ERROR = 0x01U,
GD_BUSY = 0x02U,
GD_TIMEOUT = 0x03U
}gd_status_enum;
typedef enum
{
OP_STATE_RESET = 0x00U,
OP_STATE_READY = 0x01U,
OP_STATE_BUSY = 0x02U,
OP_STATE_TIMEOUT = 0x03U,
OP_STATE_ERROR = 0x04U,
OP_STATE_ABORT = 0x05U,
OP_STATE_LISTEN = 0x06U,
OP_STATE_BUSY_TX = 0x21U, /* (OP_STATE_BUSY << 4) + 1 */
OP_STATE_BUSY_RX = 0x22U, /* (OP_STATE_BUSY << 4) + 2 */
OP_STATE_BUSY_TX_LISTEN = 0x61U, /* (OP_STATE_LISTEN << 4) + 1 */
OP_STATE_BUSY_RX_LISTEN = 0x62U, /* (OP_STATE_LISTEN << 4) + 2 */
OP_STATE_BUTT
}operation_state_enum;
#endif
/* enum definitions */
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
/* bit operations */
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
/* main flash and SRAM memory map */
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
/* peripheral memory map */
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
/* advanced peripheral bus 1 memory map */
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */
/* advanced peripheral bus 2 memory map */
#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
/* advanced high performance bus 1 memory map */
#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */
#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
/* define marco USE_STDPERIPH_DRIVER */
#if !defined USE_STDPERIPH_DRIVER
#define USE_STDPERIPH_DRIVER
#endif
#ifdef USE_STDPERIPH_DRIVER
#include "gd32f30x_libopt.h"
#endif /* USE_STDPERIPH_DRIVER */
#ifdef __cplusplus
}
#endif
#endif

130
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/gd32f30x_libopt.h → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/gd32f30x_libopt.h
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@ -1,65 +1,65 @@
/*!
\file gd32f30x_libopt.h
\brief library optional for gd32f30x
\version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32F30X_LIBOPT_H
#define GD32F30X_LIBOPT_H
#include "gd32f30x_rcu.h"
#include "gd32f30x_adc.h"
#include "gd32f30x_can.h"
#include "gd32f30x_crc.h"
#include "gd32f30x_ctc.h"
#include "gd32f30x_dac.h"
#include "gd32f30x_dbg.h"
#include "gd32f30x_dma.h"
#include "gd32f30x_exti.h"
#include "gd32f30x_fmc.h"
#include "gd32f30x_fwdgt.h"
#include "gd32f30x_gpio.h"
#include "gd32f30x_i2c.h"
#include "gd32f30x_pmu.h"
#include "gd32f30x_bkp.h"
#include "gd32f30x_rtc.h"
#include "gd32f30x_sdio.h"
#include "gd32f30x_spi.h"
#include "gd32f30x_timer.h"
#include "gd32f30x_usart.h"
#include "gd32f30x_wwdgt.h"
#include "gd32f30x_misc.h"
#include "gd32f30x_enet.h"
#include "gd32f30x_exmc.h"
#endif /* GD32F30X_LIBOPT_H */
/*!
\file gd32f30x_libopt.h
\brief library optional for gd32f30x
\version 2018-10-10, V1.1.0, firmware for GD32F30x(The version is for mbed)
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32F30X_LIBOPT_H
#define GD32F30X_LIBOPT_H
#include "gd32f30x_rcu.h"
#include "gd32f30x_adc.h"
#include "gd32f30x_can.h"
#include "gd32f30x_crc.h"
#include "gd32f30x_ctc.h"
#include "gd32f30x_dac.h"
#include "gd32f30x_dbg.h"
#include "gd32f30x_dma.h"
#include "gd32f30x_exti.h"
#include "gd32f30x_fmc.h"
#include "gd32f30x_fwdgt.h"
#include "gd32f30x_gpio.h"
#include "gd32f30x_i2c.h"
#include "gd32f30x_pmu.h"
#include "gd32f30x_bkp.h"
#include "gd32f30x_rtc.h"
#include "gd32f30x_sdio.h"
#include "gd32f30x_spi.h"
#include "gd32f30x_timer.h"
#include "gd32f30x_usart.h"
#include "gd32f30x_wwdgt.h"
#include "gd32f30x_misc.h"
#include "gd32f30x_enet.h"
#include "gd32f30x_exmc.h"
#endif /* GD32F30X_LIBOPT_H */

0
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/hal_tick.h → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/hal_tick.h
View File

1974
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/system_gd32f30x.c → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/system_gd32f30x.c
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File diff suppressed because it is too large Load Diff

116
targets/TARGET_GigaDevice/TARGET_GD32F30X/TATGET_GD32F307VG/device/system_gd32f30x.h → targets/TARGET_GigaDevice/TARGET_GD32F30X/TARGET_GD32F307VG/device/system_gd32f30x.h
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@ -1,58 +1,58 @@
/*!
\file system_gd32f30x.h
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
GD32F30x Device Series
*/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
#ifndef SYSTEM_GD32F30X_H
#define SYSTEM_GD32F30X_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/* system clock frequency (core clock) */
extern uint32_t SystemCoreClock;
/* function declarations */
/* initialize the system and update the SystemCoreClock variable */
extern void SystemInit (void);
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_GD32F30X_H */
/*!
\file system_gd32f30x.h
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
GD32F30x Device Series
*/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
#ifndef SYSTEM_GD32F30X_H
#define SYSTEM_GD32F30X_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/* system clock frequency (core clock) */
extern uint32_t SystemCoreClock;
/* function declarations */
/* initialize the system and update the SystemCoreClock variable */
extern void SystemInit (void);
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_GD32F30X_H */

2
targets/TARGET_GigaDevice/TARGET_GD32F30X/analogin_api.c
View File

@ -89,7 +89,7 @@ void analogin_init(analogin_t *obj, PinName pin)
adc_channel_length_config(obj->adc, ADC_REGULAR_CHANNEL, 1);
adc_special_function_config(obj->adc, ADC_SCAN_MODE, DISABLE);
adc_special_function_config(obj->adc, ADC_CONTINUOUS_MODE, DISABLE);
adc_external_trigger_config(ADC0, ADC_REGULAR_CHANNEL, ENABLE);
adc_external_trigger_config(obj->adc, ADC_REGULAR_CHANNEL, ENABLE);
adc_external_trigger_source_config(obj->adc, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_REGULAR_NONE);
/* ADC enable */

10
targets/TARGET_GigaDevice/TARGET_GD32F30X/flash_api.c
View File

@ -192,4 +192,14 @@ uint32_t flash_get_size(const flash_t *obj)
return FLASH_SIZE;
}
/** Get the flash erase value
*
* @param obj The flash object
* @return The flash erase value
*/
uint8_t flash_get_erase_value(const flash_t *obj)
{
return 0xFF;
}
#endif /* DEVICE_FLASH */

4
targets/TARGET_GigaDevice/TARGET_GD32F30X/mbed_overrides.c
View File

@ -22,7 +22,7 @@
int mbed_sdk_inited = 0;
/*!
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
\brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
\param[in] none
\param[out] none
\retval none
@ -34,7 +34,7 @@ extern void ticker_32bits_timer_init(void);
#endif
/*!
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
\brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
\param[in] none
\param[out] none
\retval none

2
targets/TARGET_GigaDevice/TARGET_GD32F30X/serial_api.c
View File

@ -177,7 +177,7 @@ void serial_baud(serial_t *obj, int baudrate)
struct serial_s *p_obj = GET_SERIAL_S(obj);
/* store the UEN flag */
uen_flag = USART_CTL0(USART0) & USART_CTL0_UEN;
uen_flag = USART_CTL0(p_obj->uart) & USART_CTL0_UEN;
/* disable the USART clock first */
usart_disable(p_obj->uart);

2
targets/TARGET_GigaDevice/TARGET_GD32F30X/sleep.c
View File

@ -27,7 +27,7 @@ extern void ticker_timer_data_restore(void);
extern int serial_busy_state_check(void);
/*!
\brief configure the system clock to 120M by PLL which selects HXTAL(8M) as its clock source
\brief configure the system clock to 120M by PLL which selects HXTAL(25M) as its clock source
\param[in] none
\param[out] none
\retval none

16
targets/TARGET_GigaDevice/mbed_rtx.h
View File

@ -29,6 +29,22 @@
#endif
#if defined(TARGET_GD32E103VB)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20008000UL)
#endif
#endif
#if defined(TARGET_GD32F450ZI)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20070000UL)
#endif
#endif
#if (defined(__GNUC__) && !defined(__CC_ARM) && !defined(__ARMCC_VERSION) && defined(TWO_RAM_REGIONS))
extern uint32_t __StackLimit[];
extern uint32_t __StackTop[];

55
targets/targets.json
View File

@ -7438,7 +7438,8 @@
"USTICKER",
"ANALOGIN",
"INTERRUPTIN",
"PORTIN", "PORTINOUT",
"PORTIN",
"PORTINOUT",
"PORTOUT",
"PWMOUT",
"SERIAL"
@ -7470,5 +7471,57 @@
"overrides": {
"network-default-interface-type": "ETHERNET"
}
},
"GD32_F450ZI": {
"inherits": ["GD32_Target"],
"supported_form_factors": ["ARDUINO"],
"core": "Cortex-M4",
"extra_labels_add": ["GD32F4XX", "GD32F450ZI", "GD_EMAC"],
"device_has_add": [
"RTC",
"I2C",
"CAN",
"I2CSLAVE",
"ANALOGOUT",
"SPI",
"SPISLAVE",
"SERIAL_ASYNCH",
"SERIAL_FC",
"EMAC",
"FLASH",
"SLEEP",
"MPU",
"TRNG",
"LPTICKER"
],
"device_name": "GD32F450ZI",
"detect_code": ["1702"],
"macros_add": ["GD32F450"],
"release_versions": ["5"],
"overrides": {
"network-default-interface-type": "ETHERNET"
}
},
"GD32_E103VB": {
"inherits": ["GD32_Target"],
"supported_form_factors": ["ARDUINO"],
"core": "Cortex-M23",
"extra_labels_add": ["GD32E10X", "GD32E103VB"],
"device_has_add": [
"RTC",
"I2C",
"CAN",
"I2CSLAVE",
"ANALOGOUT",
"SPI",
"SPISLAVE",
"SERIAL_ASYNCH",
"SERIAL_FC",
"FLASH",
"SLEEP"
],
"detect_code": ["1703"],
"macros_add": ["GD32E10X"],
"release_versions": ["5"]
}
}