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Added Support for TOSHIBA TMPM3HQ

pull/8324/head
Ganesh Ramachandran 2018-10-04 15:51:46 +05:30
parent 0e6eac5faa
commit 7d93fb4c15
36 changed files with 14829 additions and 0 deletions
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130
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PeripheralNames.h Normal file
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
SERIAL_0 = 0,
SERIAL_1,
SERIAL_2,
SERIAL_3,
SERIAL_4,
SERIAL_5,
INVALID_SERIAL = (int)NC
} UARTName;
typedef enum {
ADC_AINA00 = 0,
ADC_AINA01,
ADC_AINA02,
ADC_AINA03,
ADC_AINA04,
ADC_AINA05,
ADC_AINA06,
ADC_AINA07,
ADC_AINA08,
ADC_AINA09,
ADC_AINA10,
ADC_AINA11,
ADC_AINA12,
ADC_AINA13,
ADC_AINA14,
ADC_AINA15,
ADC_AINA16,
ADC_AINA17,
ADC_AINA18,
ADC_AINA19,
ADC_AINA20,
INVALID_ADC = (int)NC
} ADCName;
typedef enum {
DAC_A0 = 0,
DAC_A1,
INVALID_DAC = (int)NC
} DACName;
typedef enum {
SPI_0 = 0,
SPI_1,
SPI_2,
SPI_3,
SPI_4,
INVALID_SPI = (int)NC
} SPIName;
typedef enum {
I2C_0 = 0,
I2C_1,
I2C_2,
I2C_3,
INVALID_I2C = (int)NC
} I2CName;
typedef enum {
PWM_0 = 0,
PWM_1,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7,
INVALID_PWM = (int)NC
} PWMName;
typedef enum {
GPIO_IRQ_00 = 0,
GPIO_IRQ_01,
GPIO_IRQ_02,
GPIO_IRQ_03,
GPIO_IRQ_04,
GPIO_IRQ_05,
GPIO_IRQ_06,
GPIO_IRQ_07,
GPIO_IRQ_08,
GPIO_IRQ_09,
GPIO_IRQ_10,
GPIO_IRQ_11,
GPIO_IRQ_12,
GPIO_IRQ_13,
GPIO_IRQ_14,
GPIO_IRQ_15,
GPIO_IRQ_16,
GPIO_IRQ_17_18,
GPIO_IRQ_19_22,
GPIO_IRQ_23_26,
GPIO_IRQ_27_28,
GPIO_IRQ_29,
GPIO_IRQ_30_31,
INVALID_GPIO_IRQ = (int)NC
} gpio_irqname;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART SERIAL_1
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PinNames.h Normal file
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INOUT
} PinDirection;
typedef enum {
// TMPM3HQ Pin Names
PA0 = 0 << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
PB0 = 1 << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
PC0 = 2 << 3, PC1, PC2, PC3, PC4, PC5, PC6,
PD0 = 3 << 3, PD1, PD2, PD3, PD4, PD5,
PE0 = 4 << 3, PE1, PE2, PE3, PE4, PE5, PE6,
PF0 = 5 << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
PG0 = 6 << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7,
PH0 = 7 << 3, PH1, PH2, PH3, PH4, PH5, PH6, PH7,
PJ0 = 8 << 3, PJ1, PJ2, PJ3, PJ4, PJ5,
PK0 = 9 << 3, PK1, PK2, PK3, PK4, PK5, PK6, PK7,
PL0 = 10 << 3, PL1, PL2, PL3, PL4, PL5, PL6, PL7,
PM0 = 11 << 3, PM1, PM2, PM3, PM4, PM5, PM6, PM7,
PN0 = 12 << 3, PN1, PN2, PN3, PN4, PN5,
PP0 = 13 << 3, PP1, PP2, PP3, PP4, PP5, PP6, PP7,
PR0 = 14 << 3, PR1, PR2, PR3, PR4, PR5, PR6, PR7,
PT0 = 15 << 3, PT1, PT2, PT3, PT4, PT5, PT6, PT7,
PU0 = 16 << 3, PU1, PU2, PU3, PU4, PU5,
PV0 = 17 << 3, PV1, PV2, PV3, PV4, PV5, PV6, PV7,
// Other mbed Pin Names
LED1 = PK4,
LED2 = PK5,
LED3 = PK6,
LED4 = PK7,
// External data bus Pin Names
D0 = PV7,
D1 = PV6,
D2 = PC4,
D3 = PK2,
D4 = PC3,
D5 = PJ0,
D6 = PN0,
D7 = PM6,
D8 = PT0,
D9 = PG2,
D10 = PT1,
D11 = PT3,
D12 = PT4,
D13 = PT2,
D14 = PC1,
D15 = PC0,
// Analogue out pins
A0 = PF2,
A1 = PF3,
A2 = PF4,
A3 = PF5,
A4 = PF6,
A5 = PF7,
DAC0 = PG0,
DAC1 = PG1,
// DAP_UART
USBTX = PJ1,
USBRX = PJ2,
MBEDIF_TXD = USBTX,
MBEDIF_RXD = USBRX,
// Switches
SW1 = PV0,
SW2 = PV1,
SW3 = PV2,
SW4 = PV3,
// I2C pins
SDA = D14,
SCL = D15,
I2C_SDA = SDA,
I2C_SCL = SCL,
// Not connected
NC = (int)0xFFFFFFFF,
} PinName;
typedef enum {
PullUp = 0,
PullDown,
PullNone,
OpenDrain,
PullDefault
} PinMode;
typedef enum {
DISABLE = 0,
ENABLE
} FunctionalState;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/PortNames.h Normal file
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB,
PortC,
PortD,
PortE,
PortF,
PortG,
PortH,
PortJ,
PortK,
PortL,
PortM,
PortN,
PortP,
PortR,
PortT,
PortU,
PortV
} PortName;
#define IS_GPIO_PORT(param) ((param) <= PortV) // parameter checking for port number
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/analogin_api.c Normal file
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogin_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_wait_api.h"
#include "gpio_include.h"
static const PinMap PinMap_ADC[] = {
{PD0, ADC_AINA00, PIN_DATA(0, 0)},
{PD1, ADC_AINA01, PIN_DATA(0, 0)},
{PD2, ADC_AINA02, PIN_DATA(0, 0)},
{PD3, ADC_AINA03, PIN_DATA(0, 0)},
{PE0, ADC_AINA04, PIN_DATA(0, 0)},
{PE1, ADC_AINA05, PIN_DATA(0, 0)},
{PE2, ADC_AINA06, PIN_DATA(0, 0)},
{PE3, ADC_AINA07, PIN_DATA(0, 0)},
{PE4, ADC_AINA08, PIN_DATA(0, 0)},
{PE5, ADC_AINA09, PIN_DATA(0, 0)},
{PE6, ADC_AINA10, PIN_DATA(0, 0)},
{PF0, ADC_AINA11, PIN_DATA(0, 0)},
{PF1, ADC_AINA12, PIN_DATA(0, 0)},
{PF2, ADC_AINA13, PIN_DATA(0, 0)},
{PF3, ADC_AINA14, PIN_DATA(0, 0)},
{PF4, ADC_AINA15, PIN_DATA(0, 0)},
{PF5, ADC_AINA16, PIN_DATA(0, 0)},
{PF6, ADC_AINA17, PIN_DATA(0, 0)},
{PF7, ADC_AINA18, PIN_DATA(0, 0)},
{PD4, ADC_AINA19, PIN_DATA(0, 0)},
{PD5, ADC_AINA20, PIN_DATA(0, 0)},
{NC, NC, 0}
};
void analogin_init(analogin_t *obj, PinName pin)
{
// Check that pin belong to ADC module
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
obj->obj = TSB_ADA;
TSB_CG_FSYSENB_IPENB15 = ENABLE; // ADC CG Fsys Enable
TSB_CG_SPCLKEN_ADCKEN = ENABLE; // ADC Clock Enable
pinmap_pinout(pin, PinMap_ADC); // Set pin function as ADC
obj->obj->CLK = (ADC_SCLK_1 | ADC_SAMPLING_PERIOD_3V); // Set sample hold time and pre-scale clock
obj->obj->MOD0 = (ADxMOD0_RCUT_NORMAL | ADxMOD0_DACON_ON);
obj->obj->MOD1 = ADC_MOD1_AVDD5_3V;
obj->obj->MOD2 = ADC_MOD2_TMPM3Hx;
}
uint16_t analogin_read_u16(analogin_t *obj)
{
uint16_t ADCResultValue = 0;
uint32_t ADCResultStored = 0;
wait_us(300); // Wait at least 300us to ensure the voltage is stable
obj->obj->CR0 = (ADxCR0_ADEN_DISABLE | ADxCR0_CNT_DISABLE); // Disable Conversion
obj->obj->TSET0 = (ADxTSETn_ENINT_DISABLE | ADxTSETn_TRGS_SGL | obj->adc); // Enable Conversion
obj->obj->CR1 = (ADxCR1_CNTDMEN_DISABLE | ADxCR1_SGLDMEN_DISABLE |
ADxCR1_TRGDMEN_DISABLE | ADxCR1_TRGEN_DISABLE);
obj->obj->CR0 = (ADxCR0_ADEN_ENABLE | ADxCR0_SGL_ENABLE | ADxCR0_CNT_DISABLE);
while ((obj->obj->ST & ADxST_SNGF_RUN) != ADxST_SNGF_IDLE) {
// Wait until AD conversion complete
}
wait_us(30); // Wait for register to update with convert value.
ADCResultStored = (obj->obj->REG0 | obj->adc); // Convert result
if ((ADCResultStored & ADxREGn_ADRFn_MASK) == ADxREGn_ADRFn_ON) {
ADCResultValue = (uint16_t)((ADCResultStored & ADxREGn_ADRn_MASK) >> 4);
}
return ADCResultValue;
}
float analogin_read(analogin_t *obj)
{
float result = 0.0;
uint16_t value = 0;
value = analogin_read_u16(obj);
result = ((float)value * (1.0f / (float)ADC_12BIT_RANGE));
return result;
}

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targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/analogout_api.c Normal file
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "analogout_api.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "mbed_wait_api.h"
#include "gpio_include.h"
static const PinMap PinMap_DAC[] = {
{DAC0, DAC_A0, PIN_DATA(0, 3)},
{DAC1, DAC_A1, PIN_DATA(0, 3)},
{NC, NC, 0}
};
void analogout_init(dac_t *obj, PinName pin)
{
obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); // Check that pin belong to DAC module
MBED_ASSERT(obj->dac != (DACName)NC);
pinmap_pinout(pin, PinMap_DAC); // Set pin function as DAC
TSB_CG_FSYSENA_IPENA06 = ENABLE;
if (obj->dac == DAC_A0) { // Compute handler
obj->handler = TSB_DA0;
TSB_CG_FSYSENB_IPENB17 = ENABLE;
} else {
if (obj->dac == DAC_A1) {
obj->handler = TSB_DA1;
TSB_CG_FSYSENB_IPENB18 = ENABLE;
} else {
obj->handler = NULL;
}
}
obj->handler->CTL = DAC_STOP;
}
void analogout_free(dac_t *obj)
{
obj->handler->CTL = DAC_STOP;
}
void analogout_write(dac_t *obj, float value)
{
uint8_t outputcode = 0;
// Enable DAC
obj->handler->CTL = DAC_START;
if (value < 0.0f) {
value = 0.0f;
} else {
if (value >= 1.0f) {
value = 1.0f;
}
}
outputcode = (uint8_t)(value * 255.0f);
obj->handler->REG = outputcode;
wait_ms(3);
}
void analogout_write_u16(dac_t *obj, uint16_t value)
{
// Enable DAC
obj->handler->CTL = DAC_START;
obj->handler->REG = (uint8_t)(value & 0xFF);
wait_ms(3);
}
float analogout_read(dac_t *obj)
{
float result = 0.0;
uint32_t value = 0;
value = ((obj->handler->REG) & (0xFF));
result = ((float)value / 255.0f);
return result;
}
uint16_t analogout_read_u16(dac_t *obj)
{
uint16_t value = 0;
value = (uint16_t)((obj->handler->REG) & (0xFF));
return value;
}

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targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device.h Normal file
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#include "objects.h"
#endif

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targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TMPM3HQ.h Normal file
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targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_ARM_STD/startup_TMPM3HQ.S Normal file
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;/**
; *******************************************************************************
; * @file startup_TMPM3HQ.s
; * @brief CMSIS Cortex-M3 Core Device Startup File for the
; * TOSHIBA 'TMPM3HQ' Device Series
; * @version V1.0.0.0
; * $Date:: 2017-12-08 #$
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
; *
; * (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
; *******************************************************************************
; */
__initial_sp EQU 0x20010000
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD INT00_IRQHandler ; 0: Interrupt Pin 00
DCD INT01_IRQHandler ; 1: Interrupt Pin 01
DCD INT02_IRQHandler ; 2: Interrupt Pin 02
DCD INT03_IRQHandler ; 3: Interrupt Pin 03
DCD INT04_IRQHandler ; 4: Interrupt Pin 04
DCD INT05_IRQHandler ; 5: Interrupt Pin 05
DCD INT06_IRQHandler ; 6: Interrupt Pin 06
DCD INT07_IRQHandler ; 7: Interrupt Pin 07
DCD INT08_IRQHandler ; 8: Interrupt Pin 08
DCD INT09_IRQHandler ; 9: Interrupt Pin 09
DCD INT10_IRQHandler ; 10: Interrupt Pin 10
DCD INT11_IRQHandler ; 11: Interrupt Pin 11
DCD INT12_IRQHandler ; 12: Interrupt Pin 12
DCD INT13_IRQHandler ; 13: Interrupt Pin 13
DCD INT14_IRQHandler ; 14: Interrupt Pin 14
DCD INT15_IRQHandler ; 15: Interrupt Pin 15
DCD INT16_IRQHandler ; 16: Interrupt Pin 16
DCD INT17_18_IRQHandler ; 17: Interrupt Pin 17_18
DCD INT19_22_IRQHandler ; 18: Interrupt Pin 19_22
DCD INT23_26_IRQHandler ; 19: Interrupt Pin 23_26
DCD INT27_28_IRQHandler ; 20: Interrupt Pin 27_28
DCD INT29_IRQHandler ; 21: Interrupt Pin 29
DCD INT30_31_IRQHandler ; 22: Interrupt Pin 30_31
DCD INTEMG0_IRQHandler ; 23: PMD0 EMG interrupt
DCD INTOVV0_IRQHandler ; 24: PMD0 OVV interrupt
DCD INTPMD0_IRQHandler ; 25: PMD0 interrupt
DCD INTENC00_IRQHandler ; 26: Encoder 0 interrupt 0
DCD INTENC01_IRQHandler ; 27: Encoder 0 interrupt 1
DCD INTADAPDA_IRQHandler ; 28: ADC conversion triggered by PMD is finished A
DCD INTADAPDB_IRQHandler ; 29: ADC conversion triggered by PMD is finished B
DCD INTADACP0_IRQHandler ; 30: ADC conversion monitoring function interrupt 0
DCD INTADACP1_IRQHandler ; 31: ADC conversion monitoring function interrupt 1
DCD INTADATRG_IRQHandler ; 32: ADC conversion triggered by General purpose is finished
DCD INTADASGL_IRQHandler ; 33: ADC conversion triggered by Single program is finished
DCD INTADACNT_IRQHandler ; 34: ADC conversion triggered by Continuity program is finished
DCD INTT0RX_IRQHandler ; 35: TSPI/SIO reception (channel 0)
DCD INTT0TX_IRQHandler ; 36: TSPI/SIO transmit (channel 0)
DCD INTT0ERR_IRQHandler ; 37: TSPI/SIO error (channel 0)
DCD INTT1RX_IRQHandler ; 38: TSPI/SIO reception (channel 1)
DCD INTT1TX_IRQHandler ; 39: TSPI/SIO transmit (channel 1)
DCD INTT1ERR_IRQHandler ; 40: TSPI/SIO error (channel 1)
DCD INTT2RX_IRQHandler ; 41: TSPI/SIO reception (channel 2)
DCD INTT2TX_IRQHandler ; 42: TSPI/SIO transmit (channel 2)
DCD INTT2ERR_IRQHandler ; 43: TSPI/SIO error (channel 2)
DCD INTT3RX_IRQHandler ; 44: TSPI/SIO reception (channel 3)
DCD INTT3TX_IRQHandler ; 45: TSPI/SIO transmit (channel 3)
DCD INTT3ERR_IRQHandler ; 46: TSPI/SIO error (channel 3)
DCD INTT4RX_IRQHandler ; 47: TSPI/SIO reception (channel 4)
DCD INTT4TX_IRQHandler ; 48: TSPI/SIO transmit (channel 4)
DCD INTT4ERR_IRQHandler ; 49: TSPI/SIO error (channel 4)
DCD INTI2CWUP_IRQHandler ; 50: Serial bus interface (WakeUp) interrupt (channel 0)
DCD INTI2C0_IRQHandler ; 51: I2C0 transmission and reception interrupt
DCD INTI2C0AL_IRQHandler ; 52: I2C0 arbitration lost interrupt
DCD INTI2C0BF_IRQHandler ; 53: I2C0 bus free interrupt
DCD INTI2C0NA_IRQHandler ; 54: I2C0 no ack interrupt
DCD INTI2C1_IRQHandler ; 55: I2C1 transmission and reception interrupt
DCD INTI2C1AL_IRQHandler ; 56: I2C1 arbitration lost interrupt
DCD INTI2C1BF_IRQHandler ; 57: I2C1 bus free interrupt
DCD INTI2C1NA_IRQHandler ; 58: I2C1 no ack interrupt
DCD INTI2C2_IRQHandler ; 59: I2C2 transmission and reception interrupt
DCD INTI2C2AL_IRQHandler ; 60: I2C2 arbitration lost interrupt
DCD INTI2C2BF_IRQHandler ; 61: I2C2 bus free interrupt
DCD INTI2C2NA_IRQHandler ; 62: I2C2 no ack interrupt
DCD INTI2C3_IRQHandler ; 63: I2C3 transmission and reception interrupt
DCD INTI2C3AL_IRQHandler ; 64: I2C3 arbitration lost interrupt
DCD INTI2C3BF_IRQHandler ; 65: I2C3 bus free interrupt
DCD INTI2C3NA_IRQHandler ; 66: I2C3 no ack interrupt
DCD INTUART0RX_IRQHandler ; 67: UART reception (channel 0)
DCD INTUART0TX_IRQHandler ; 68: UART transmit (channel 0)
DCD INTUART0ERR_IRQHandler ; 69: UART error (channel 0)
DCD INTUART1RX_IRQHandler ; 70: UART reception (channel 1)
DCD INTUART1TX_IRQHandler ; 71: UART transmit (channel 1)
DCD INTUART1ERR_IRQHandler ; 72: UART error (channel 1)
DCD INTUART2RX_IRQHandler ; 73: UART reception (channel 2)
DCD INTUART2TX_IRQHandler ; 74: UART transmit (channel 2)
DCD INTUART2ERR_IRQHandler ; 75: UART error (channel 2)
DCD INTUART3RX_IRQHandler ; 76: UART reception (channel 3)
DCD INTUART3TX_IRQHandler ; 77: UART transmit (channel 3)
DCD INTUART3ERR_IRQHandler ; 78: UART error (channel 3)
DCD INTUART4RX_IRQHandler ; 79: UART reception (channel 4)
DCD INTUART4TX_IRQHandler ; 80: UART transmit (channel 4)
DCD INTUART4ERR_IRQHandler ; 81: UART error (channel 4)
DCD INTUART5RX_IRQHandler ; 82: UART reception (channel 5)
DCD INTUART5TX_IRQHandler ; 83: UART transmit (channel 5)
DCD INTUART5ERR_IRQHandler ; 84: UART error (channel 5)
DCD INTT32A00A_IRQHandler ; 85: 32bit T32A00A compare match detection 0 / Over flow / under flow
DCD INTT32A00ACAP0_IRQHandler ; 86: 32bit T32A00A input capture 0
DCD INTT32A00ACAP1_IRQHandler ; 87: 32bit T32A00A input capture 1
DCD INTT32A00B_IRQHandler ; 88: 32bit T32A00B compare match detection 0 / Over flow / under flow
DCD INTT32A00BCAP0_IRQHandler ; 89: 32bit T32A00B input capture 0
DCD INTT32A00BCAP1_IRQHandler ; 90: 32bit T32A00B input capture 1
DCD INTT32A00C_IRQHandler ; 91: 32bit T32A00C compare match detection 0 / Over flow / under flow
DCD INTT32A00CCAP0_IRQHandler ; 92: 32bit T32A00C input capture 0
DCD INTT32A00CCAP1_IRQHandler ; 93: 32bit T32A00C input capture 1
DCD INTT32A01A_IRQHandler ; 94: 32bit T32A01A compare match detection 0 / Over flow / under flow
DCD INTT32A01ACAP0_IRQHandler ; 95: 32bit T32A01A input capture 0
DCD INTT32A01ACAP1_IRQHandler ; 96: 32bit T32A01A input capture 1
DCD INTT32A01B_IRQHandler ; 97: 32bit T32A01B compare match detection 0 / Over flow / under flow
DCD INTT32A01BCAP0_IRQHandler ; 98: 32bit T32A01B input capture 0
DCD INTT32A01BCAP1_IRQHandler ; 99: 32bit T32A01B input capture 1
DCD INTT32A01C_IRQHandler ; 100: 32bit T32A01C compare match detection 0 / Over flow / under flow
DCD INTT32A01CCAP0_IRQHandler ; 101: 32bit T32A01C input capture 0
DCD INTT32A01CCAP1_IRQHandler ; 102: 32bit T32A01C input capture 1
DCD INTT32A02A_IRQHandler ; 103: 32bit T32A02A compare match detection 0 / Over flow / under flow
DCD INTT32A02ACAP0_IRQHandler ; 104: 32bit T32A02A input capture 0
DCD INTT32A02ACAP1_IRQHandler ; 105: 32bit T32A02A input capture 1
DCD INTT32A02B_IRQHandler ; 106: 32bit T32A02B compare match detection 0 / Over flow / under flow
DCD INTT32A02BCAP0_IRQHandler ; 107: 32bit T32A02B input capture 0
DCD INTT32A02BCAP1_IRQHandler ; 108: 32bit T32A02B input capture 1
DCD INTT32A02C_IRQHandler ; 109: 32bit T32A02C compare match detection 0 / Over flow / under flow
DCD INTT32A02CCAP0_IRQHandler ; 110: 32bit T32A02C input capture 0
DCD INTT32A02CCAP1_IRQHandler ; 111: 32bit T32A02C input capture 1
DCD INTT32A03A_IRQHandler ; 112: 32bit T32A03A compare match detection 0 / Over flow / under flow
DCD INTT32A03ACAP0_IRQHandler ; 113: 32bit T32A03A input capture 0
DCD INTT32A03ACAP1_IRQHandler ; 114: 32bit T32A03A input capture 1
DCD INTT32A03B_IRQHandler ; 115: 32bit T32A03B compare match detection 0 / Over flow / under flow
DCD INTT32A03BCAP0_IRQHandler ; 116: 32bit T32A03B input capture 0
DCD INTT32A03BCAP1_IRQHandler ; 117: 32bit T32A03B input capture 1
DCD INTT32A03C_IRQHandler ; 118: 32bit T32A03C compare match detection 0 / Over flow / under flow
DCD INTT32A03CCAP0_IRQHandler ; 119: 32bit T32A03C input capture 0
DCD INTT32A03CCAP1_IRQHandler ; 120: 32bit T32A03C input capture 1
DCD INTT32A04A_IRQHandler ; 121: 32bit T32A04A compare match detection 0 / Over flow / under flow
DCD INTT32A04ACAP0_IRQHandler ; 122: 32bit T32A04A input capture 0
DCD INTT32A04ACAP1_IRQHandler ; 123: 32bit T32A04A input capture 1
DCD INTT32A04B_IRQHandler ; 124: 32bit T32A04B compare match detection 0 / Over flow / under flow
DCD INTT32A04BCAP0_IRQHandler ; 125: 32bit T32A04B input capture 0
DCD INTT32A04BCAP1_IRQHandler ; 126: 32bit T32A04B input capture 1
DCD INTT32A04C_IRQHandler ; 127: 32bit T32A04C compare match detection 0 / Over flow / under flow
DCD INTT32A04CCAP0_IRQHandler ; 128: 32bit T32A04C input capture 0
DCD INTT32A04CCAP1_IRQHandler ; 129: 32bit T32A04C input capture 1
DCD INTT32A05A_IRQHandler ; 130: 32bit T32A05A compare match detection 0 / Over flow / under flow
DCD INTT32A05ACAP0_IRQHandler ; 131: 32bit T32A05A input capture 0
DCD INTT32A05ACAP1_IRQHandler ; 132: 32bit T32A05A input capture 1
DCD INTT32A05B_IRQHandler ; 133: 32bit T32A05B compare match detection 0 / Over flow / under flow
DCD INTT32A05BCAP0_IRQHandler ; 134: 32bit T32A05B input capture 0
DCD INTT32A05BCAP1_IRQHandler ; 135: 32bit T32A05B input capture 1
DCD INTT32A05C_IRQHandler ; 136: 32bit T32A05C compare match detection 0 / Over flow / under flow
DCD INTT32A05CCAP0_IRQHandler ; 137: 32bit T32A05C input capture 0
DCD INTT32A05CCAP1_IRQHandler ; 138: 32bit T32A05C input capture 1
DCD INTT32A06A_IRQHandler ; 139: 32bit T32A06A compare match detection 0 / Over flow / under flow
DCD INTT32A06ACAP0_IRQHandler ; 140: 32bit T32A06A input capture 0
DCD INTT32A06ACAP1_IRQHandler ; 141: 32bit T32A06A input capture 1
DCD INTT32A06B_IRQHandler ; 142: 32bit T32A06B compare match detection 0 / Over flow / under flow
DCD INTT32A06BCAP0_IRQHandler ; 143: 32bit T32A06B input capture 0
DCD INTT32A06BCAP1_IRQHandler ; 144: 32bit T32A06B input capture 1
DCD INTT32A06C_IRQHandler ; 145: 32bit T32A06C compare match detection 0 / Over flow / under flow
DCD INTT32A06CCAP0_IRQHandler ; 146: 32bit T32A06C input capture 0
DCD INTT32A06CCAP1_IRQHandler ; 147: 32bit T32A06C input capture 1
DCD INTT32A07A_IRQHandler ; 148: 32bit T32A07A compare match detection 0 / Over flow / under flow
DCD INTT32A07ACAP0_IRQHandler ; 149: 32bit T32A07A input capture 0
DCD INTT32A07ACAP1_IRQHandler ; 150: 32bit T32A07A input capture 1
DCD INTT32A07B_IRQHandler ; 151: 32bit T32A07B compare match detection 0 / Over flow / under flow
DCD INTT32A07BCAP0_IRQHandler ; 152: 32bit T32A07B input capture 0
DCD INTT32A07BCAP1_IRQHandler ; 153: 32bit T32A07B input capture 1
DCD INTT32A07C_IRQHandler ; 154: 32bit T32A07C compare match detection 0 / Over flow / under flow
DCD INTT32A07CCAP0_IRQHandler ; 155: 32bit T32A07C input capture 0
DCD INTT32A07CCAP1_IRQHandler ; 156: 32bit T32A07C input capture 1
DCD INTPARI_IRQHandler ; 157: RAM parity interrupt
DCD INTDMAATC_IRQHandler ; 158: DMAA end of transfer
DCD INTDMAAERR_IRQHandler ; 159: DMAA transfer error
DCD INTDMABTC_IRQHandler ; 160: DMAB end of transfer
DCD INTDMABERR_IRQHandler ; 161: DMAB transfer error
DCD INTRTC_IRQHandler ; 162: Real time clock interrupt
DCD INTRMC0_IRQHandler ; 163: Remote control reception interrupt
DCD INTFLCRDY_IRQHandler ; 164: Code FLASH Ready interrupt
DCD INTFLDRDY_IRQHandler ; 165: Data FLASH Ready interrupt
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT INT00_IRQHandler [WEAK]
EXPORT INT01_IRQHandler [WEAK]
EXPORT INT02_IRQHandler [WEAK]
EXPORT INT03_IRQHandler [WEAK]
EXPORT INT04_IRQHandler [WEAK]
EXPORT INT05_IRQHandler [WEAK]
EXPORT INT06_IRQHandler [WEAK]
EXPORT INT07_IRQHandler [WEAK]
EXPORT INT08_IRQHandler [WEAK]
EXPORT INT09_IRQHandler [WEAK]
EXPORT INT10_IRQHandler [WEAK]
EXPORT INT11_IRQHandler [WEAK]
EXPORT INT12_IRQHandler [WEAK]
EXPORT INT13_IRQHandler [WEAK]
EXPORT INT14_IRQHandler [WEAK]
EXPORT INT15_IRQHandler [WEAK]
EXPORT INT16_IRQHandler [WEAK]
EXPORT INT17_18_IRQHandler [WEAK]
EXPORT INT19_22_IRQHandler [WEAK]
EXPORT INT23_26_IRQHandler [WEAK]
EXPORT INT27_28_IRQHandler [WEAK]
EXPORT INT29_IRQHandler [WEAK]
EXPORT INT30_31_IRQHandler [WEAK]
EXPORT INTEMG0_IRQHandler [WEAK]
EXPORT INTOVV0_IRQHandler [WEAK]
EXPORT INTPMD0_IRQHandler [WEAK]
EXPORT INTENC00_IRQHandler [WEAK]
EXPORT INTENC01_IRQHandler [WEAK]
EXPORT INTADAPDA_IRQHandler [WEAK]
EXPORT INTADAPDB_IRQHandler [WEAK]
EXPORT INTADACP0_IRQHandler [WEAK]
EXPORT INTADACP1_IRQHandler [WEAK]
EXPORT INTADATRG_IRQHandler [WEAK]
EXPORT INTADASGL_IRQHandler [WEAK]
EXPORT INTADACNT_IRQHandler [WEAK]
EXPORT INTT0RX_IRQHandler [WEAK]
EXPORT INTT0TX_IRQHandler [WEAK]
EXPORT INTT0ERR_IRQHandler [WEAK]
EXPORT INTT1RX_IRQHandler [WEAK]
EXPORT INTT1TX_IRQHandler [WEAK]
EXPORT INTT1ERR_IRQHandler [WEAK]
EXPORT INTT2RX_IRQHandler [WEAK]
EXPORT INTT2TX_IRQHandler [WEAK]
EXPORT INTT2ERR_IRQHandler [WEAK]
EXPORT INTT3RX_IRQHandler [WEAK]
EXPORT INTT3TX_IRQHandler [WEAK]
EXPORT INTT3ERR_IRQHandler [WEAK]
EXPORT INTT4RX_IRQHandler [WEAK]
EXPORT INTT4TX_IRQHandler [WEAK]
EXPORT INTT4ERR_IRQHandler [WEAK]
EXPORT INTI2CWUP_IRQHandler [WEAK]
EXPORT INTI2C0_IRQHandler [WEAK]
EXPORT INTI2C0AL_IRQHandler [WEAK]
EXPORT INTI2C0BF_IRQHandler [WEAK]
EXPORT INTI2C0NA_IRQHandler [WEAK]
EXPORT INTI2C1_IRQHandler [WEAK]
EXPORT INTI2C1AL_IRQHandler [WEAK]
EXPORT INTI2C1BF_IRQHandler [WEAK]
EXPORT INTI2C1NA_IRQHandler [WEAK]
EXPORT INTI2C2_IRQHandler [WEAK]
EXPORT INTI2C2AL_IRQHandler [WEAK]
EXPORT INTI2C2BF_IRQHandler [WEAK]
EXPORT INTI2C2NA_IRQHandler [WEAK]
EXPORT INTI2C3_IRQHandler [WEAK]
EXPORT INTI2C3AL_IRQHandler [WEAK]
EXPORT INTI2C3BF_IRQHandler [WEAK]
EXPORT INTI2C3NA_IRQHandler [WEAK]
EXPORT INTUART0RX_IRQHandler [WEAK]
EXPORT INTUART0TX_IRQHandler [WEAK]
EXPORT INTUART0ERR_IRQHandler [WEAK]
EXPORT INTUART1RX_IRQHandler [WEAK]
EXPORT INTUART1TX_IRQHandler [WEAK]
EXPORT INTUART1ERR_IRQHandler [WEAK]
EXPORT INTUART2RX_IRQHandler [WEAK]
EXPORT INTUART2TX_IRQHandler [WEAK]
EXPORT INTUART2ERR_IRQHandler [WEAK]
EXPORT INTUART3RX_IRQHandler [WEAK]
EXPORT INTUART3TX_IRQHandler [WEAK]
EXPORT INTUART3ERR_IRQHandler [WEAK]
EXPORT INTUART4RX_IRQHandler [WEAK]
EXPORT INTUART4TX_IRQHandler [WEAK]
EXPORT INTUART4ERR_IRQHandler [WEAK]
EXPORT INTUART5RX_IRQHandler [WEAK]
EXPORT INTUART5TX_IRQHandler [WEAK]
EXPORT INTUART5ERR_IRQHandler [WEAK]
EXPORT INTT32A00A_IRQHandler [WEAK]
EXPORT INTT32A00ACAP0_IRQHandler [WEAK]
EXPORT INTT32A00ACAP1_IRQHandler [WEAK]
EXPORT INTT32A00B_IRQHandler [WEAK]
EXPORT INTT32A00BCAP0_IRQHandler [WEAK]
EXPORT INTT32A00BCAP1_IRQHandler [WEAK]
EXPORT INTT32A00C_IRQHandler [WEAK]
EXPORT INTT32A00CCAP0_IRQHandler [WEAK]
EXPORT INTT32A00CCAP1_IRQHandler [WEAK]
EXPORT INTT32A01A_IRQHandler [WEAK]
EXPORT INTT32A01ACAP0_IRQHandler [WEAK]
EXPORT INTT32A01ACAP1_IRQHandler [WEAK]
EXPORT INTT32A01B_IRQHandler [WEAK]
EXPORT INTT32A01BCAP0_IRQHandler [WEAK]
EXPORT INTT32A01BCAP1_IRQHandler [WEAK]
EXPORT INTT32A01C_IRQHandler [WEAK]
EXPORT INTT32A01CCAP0_IRQHandler [WEAK]
EXPORT INTT32A01CCAP1_IRQHandler [WEAK]
EXPORT INTT32A02A_IRQHandler [WEAK]
EXPORT INTT32A02ACAP0_IRQHandler [WEAK]
EXPORT INTT32A02ACAP1_IRQHandler [WEAK]
EXPORT INTT32A02B_IRQHandler [WEAK]
EXPORT INTT32A02BCAP0_IRQHandler [WEAK]
EXPORT INTT32A02BCAP1_IRQHandler [WEAK]
EXPORT INTT32A02C_IRQHandler [WEAK]
EXPORT INTT32A02CCAP0_IRQHandler [WEAK]
EXPORT INTT32A02CCAP1_IRQHandler [WEAK]
EXPORT INTT32A03A_IRQHandler [WEAK]
EXPORT INTT32A03ACAP0_IRQHandler [WEAK]
EXPORT INTT32A03ACAP1_IRQHandler [WEAK]
EXPORT INTT32A03B_IRQHandler [WEAK]
EXPORT INTT32A03BCAP0_IRQHandler [WEAK]
EXPORT INTT32A03BCAP1_IRQHandler [WEAK]
EXPORT INTT32A03C_IRQHandler [WEAK]
EXPORT INTT32A03CCAP0_IRQHandler [WEAK]
EXPORT INTT32A03CCAP1_IRQHandler [WEAK]
EXPORT INTT32A04A_IRQHandler [WEAK]
EXPORT INTT32A04ACAP0_IRQHandler [WEAK]
EXPORT INTT32A04ACAP1_IRQHandler [WEAK]
EXPORT INTT32A04B_IRQHandler [WEAK]
EXPORT INTT32A04BCAP0_IRQHandler [WEAK]
EXPORT INTT32A04BCAP1_IRQHandler [WEAK]
EXPORT INTT32A04C_IRQHandler [WEAK]
EXPORT INTT32A04CCAP0_IRQHandler [WEAK]
EXPORT INTT32A04CCAP1_IRQHandler [WEAK]
EXPORT INTT32A05A_IRQHandler [WEAK]
EXPORT INTT32A05ACAP0_IRQHandler [WEAK]
EXPORT INTT32A05ACAP1_IRQHandler [WEAK]
EXPORT INTT32A05B_IRQHandler [WEAK]
EXPORT INTT32A05BCAP0_IRQHandler [WEAK]
EXPORT INTT32A05BCAP1_IRQHandler [WEAK]
EXPORT INTT32A05C_IRQHandler [WEAK]
EXPORT INTT32A05CCAP0_IRQHandler [WEAK]
EXPORT INTT32A05CCAP1_IRQHandler [WEAK]
EXPORT INTT32A06A_IRQHandler [WEAK]
EXPORT INTT32A06ACAP0_IRQHandler [WEAK]
EXPORT INTT32A06ACAP1_IRQHandler [WEAK]
EXPORT INTT32A06B_IRQHandler [WEAK]
EXPORT INTT32A06BCAP0_IRQHandler [WEAK]
EXPORT INTT32A06BCAP1_IRQHandler [WEAK]
EXPORT INTT32A06C_IRQHandler [WEAK]
EXPORT INTT32A06CCAP0_IRQHandler [WEAK]
EXPORT INTT32A06CCAP1_IRQHandler [WEAK]
EXPORT INTT32A07A_IRQHandler [WEAK]
EXPORT INTT32A07ACAP0_IRQHandler [WEAK]
EXPORT INTT32A07ACAP1_IRQHandler [WEAK]
EXPORT INTT32A07B_IRQHandler [WEAK]
EXPORT INTT32A07BCAP0_IRQHandler [WEAK]
EXPORT INTT32A07BCAP1_IRQHandler [WEAK]
EXPORT INTT32A07C_IRQHandler [WEAK]
EXPORT INTT32A07CCAP0_IRQHandler [WEAK]
EXPORT INTT32A07CCAP1_IRQHandler [WEAK]
EXPORT INTPARI_IRQHandler [WEAK]
EXPORT INTDMAATC_IRQHandler [WEAK]
EXPORT INTDMAAERR_IRQHandler [WEAK]
EXPORT INTDMABTC_IRQHandler [WEAK]
EXPORT INTDMABERR_IRQHandler [WEAK]
EXPORT INTRTC_IRQHandler [WEAK]
EXPORT INTRMC0_IRQHandler [WEAK]
EXPORT INTFLCRDY_IRQHandler [WEAK]
EXPORT INTFLDRDY_IRQHandler [WEAK]
INT00_IRQHandler
INT01_IRQHandler
INT02_IRQHandler
INT03_IRQHandler
INT04_IRQHandler
INT05_IRQHandler
INT06_IRQHandler
INT07_IRQHandler
INT08_IRQHandler
INT09_IRQHandler
INT10_IRQHandler
INT11_IRQHandler
INT12_IRQHandler
INT13_IRQHandler
INT14_IRQHandler
INT15_IRQHandler
INT16_IRQHandler
INT17_18_IRQHandler
INT19_22_IRQHandler
INT23_26_IRQHandler
INT27_28_IRQHandler
INT29_IRQHandler
INT30_31_IRQHandler
INTEMG0_IRQHandler
INTOVV0_IRQHandler
INTPMD0_IRQHandler
INTENC00_IRQHandler
INTENC01_IRQHandler
INTADAPDA_IRQHandler
INTADAPDB_IRQHandler
INTADACP0_IRQHandler
INTADACP1_IRQHandler
INTADATRG_IRQHandler
INTADASGL_IRQHandler
INTADACNT_IRQHandler
INTT0RX_IRQHandler
INTT0TX_IRQHandler
INTT0ERR_IRQHandler
INTT1RX_IRQHandler
INTT1TX_IRQHandler
INTT1ERR_IRQHandler
INTT2RX_IRQHandler
INTT2TX_IRQHandler
INTT2ERR_IRQHandler
INTT3RX_IRQHandler
INTT3TX_IRQHandler
INTT3ERR_IRQHandler
INTT4RX_IRQHandler
INTT4TX_IRQHandler
INTT4ERR_IRQHandler
INTI2CWUP_IRQHandler
INTI2C0_IRQHandler
INTI2C0AL_IRQHandler
INTI2C0BF_IRQHandler
INTI2C0NA_IRQHandler
INTI2C1_IRQHandler
INTI2C1AL_IRQHandler
INTI2C1BF_IRQHandler
INTI2C1NA_IRQHandler
INTI2C2_IRQHandler
INTI2C2AL_IRQHandler
INTI2C2BF_IRQHandler
INTI2C2NA_IRQHandler
INTI2C3_IRQHandler
INTI2C3AL_IRQHandler
INTI2C3BF_IRQHandler
INTI2C3NA_IRQHandler
INTUART0RX_IRQHandler
INTUART0TX_IRQHandler
INTUART0ERR_IRQHandler
INTUART1RX_IRQHandler
INTUART1TX_IRQHandler
INTUART1ERR_IRQHandler
INTUART2RX_IRQHandler
INTUART2TX_IRQHandler
INTUART2ERR_IRQHandler
INTUART3RX_IRQHandler
INTUART3TX_IRQHandler
INTUART3ERR_IRQHandler
INTUART4RX_IRQHandler
INTUART4TX_IRQHandler
INTUART4ERR_IRQHandler
INTUART5RX_IRQHandler
INTUART5TX_IRQHandler
INTUART5ERR_IRQHandler
INTT32A00A_IRQHandler
INTT32A00ACAP0_IRQHandler
INTT32A00ACAP1_IRQHandler
INTT32A00B_IRQHandler
INTT32A00BCAP0_IRQHandler
INTT32A00BCAP1_IRQHandler
INTT32A00C_IRQHandler
INTT32A00CCAP0_IRQHandler
INTT32A00CCAP1_IRQHandler
INTT32A01A_IRQHandler
INTT32A01ACAP0_IRQHandler
INTT32A01ACAP1_IRQHandler
INTT32A01B_IRQHandler
INTT32A01BCAP0_IRQHandler
INTT32A01BCAP1_IRQHandler
INTT32A01C_IRQHandler
INTT32A01CCAP0_IRQHandler
INTT32A01CCAP1_IRQHandler
INTT32A02A_IRQHandler
INTT32A02ACAP0_IRQHandler
INTT32A02ACAP1_IRQHandler
INTT32A02B_IRQHandler
INTT32A02BCAP0_IRQHandler
INTT32A02BCAP1_IRQHandler
INTT32A02C_IRQHandler
INTT32A02CCAP0_IRQHandler
INTT32A02CCAP1_IRQHandler
INTT32A03A_IRQHandler
INTT32A03ACAP0_IRQHandler
INTT32A03ACAP1_IRQHandler
INTT32A03B_IRQHandler
INTT32A03BCAP0_IRQHandler
INTT32A03BCAP1_IRQHandler
INTT32A03C_IRQHandler
INTT32A03CCAP0_IRQHandler
INTT32A03CCAP1_IRQHandler
INTT32A04A_IRQHandler
INTT32A04ACAP0_IRQHandler
INTT32A04ACAP1_IRQHandler
INTT32A04B_IRQHandler
INTT32A04BCAP0_IRQHandler
INTT32A04BCAP1_IRQHandler
INTT32A04C_IRQHandler
INTT32A04CCAP0_IRQHandler
INTT32A04CCAP1_IRQHandler
INTT32A05A_IRQHandler
INTT32A05ACAP0_IRQHandler
INTT32A05ACAP1_IRQHandler
INTT32A05B_IRQHandler
INTT32A05BCAP0_IRQHandler
INTT32A05BCAP1_IRQHandler
INTT32A05C_IRQHandler
INTT32A05CCAP0_IRQHandler
INTT32A05CCAP1_IRQHandler
INTT32A06A_IRQHandler
INTT32A06ACAP0_IRQHandler
INTT32A06ACAP1_IRQHandler
INTT32A06B_IRQHandler
INTT32A06BCAP0_IRQHandler
INTT32A06BCAP1_IRQHandler
INTT32A06C_IRQHandler
INTT32A06CCAP0_IRQHandler
INTT32A06CCAP1_IRQHandler
INTT32A07A_IRQHandler
INTT32A07ACAP0_IRQHandler
INTT32A07ACAP1_IRQHandler
INTT32A07B_IRQHandler
INTT32A07BCAP0_IRQHandler
INTT32A07BCAP1_IRQHandler
INTT32A07C_IRQHandler
INTT32A07CCAP0_IRQHandler
INTT32A07CCAP1_IRQHandler
INTPARI_IRQHandler
INTDMAATC_IRQHandler
INTDMAAERR_IRQHandler
INTDMABTC_IRQHandler
INTDMABERR_IRQHandler
INTRTC_IRQHandler
INTRMC0_IRQHandler
INTFLCRDY_IRQHandler
INTFLDRDY_IRQHandler
B .
ENDP
END

29
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct Normal file
View File

@ -0,0 +1,29 @@
;; TMPM3HQFDFG scatter file
;; Vector table starts at 0
;; Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model)
;; or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model)
;; Initial PC == &__main (with LSB set to indicate Thumb)
;; These two values are provided by the library
;; Other vectors must be provided by the user
;; Code starts after the last possible vector
;; Data starts at 0x20000000
;; Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries)
;; Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above)
;; Compatible with ISSM model
LR_IROM1 0x00000000 0x80000
{
ER_IROM1 0x00000000 0x80000
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x200002D8 (0x10000 - 0x2D8)
{
.ANY (+RW, +ZI)
}
}

582
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_GCC_ARM/startup_TMPM3HQ.S Normal file
View File

@ -0,0 +1,582 @@
/**
*******************************************************************************
* @file startup_TMPM3HQ.s
* @brief CMSIS Cortex-M3 Core Device Startup File for the
* TOSHIBA 'TMPM3HQ' Device Series
* @version V5.00
* @date 2016/03/02
*------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*
* (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
*******************************************************************************
*/
.syntax unified
.arch armv7-m
.section .stack
.align 3
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
// <h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop // Top of Stack
.long Reset_Handler // Reset Handler
.long NMI_Handler // NMI Handler
.long HardFault_Handler // Hard Fault Handler
.long MemManage_Handler // MPU Fault Handler
.long BusFault_Handler // Bus Fault Handler
.long UsageFault_Handler // Usage Fault Handler
.long 0 // Reserved
.long 0 // Reserved
.long 0 // Reserved
.long 0 // Reserved
.long SVC_Handler // SVCall Handler
.long DebugMon_Handler // Debug Monitor Handler
.long 0 // Reserved
.long PendSV_Handler // PendSV Handler
.long SysTick_Handler // SysTick Handler
// External interrupts
.long INT00_IRQHandler // 0: Interrupt Pin0
.long INT01_IRQHandler // 1: Interrupt Pin1
.long INT02_IRQHandler // 2: Interrupt Pin2
.long INT03_IRQHandler // 3: Interrupt Pin3
.long INT04_IRQHandler // 4: Interrupt Pin4
.long INT05_IRQHandler // 5: Interrupt Pin5
.long INT06_IRQHandler // 6: Interrupt Pin6
.long INT07_IRQHandler // 7: Interrupt Pin7
.long INT08_IRQHandler // 8: Interrupt Pin8
.long INT09_IRQHandler // 9: Interrupt Pin9
.long INT10_IRQHandler // 10: Interrupt Pin10
.long INT11_IRQHandler // 11: Interrupt Pin11
.long INT12_IRQHandler // 12: Interrupt Pin12
.long INT13_IRQHandler // 13: Interrupt Pin13
.long INT14_IRQHandler // 14: Interrupt Pin14
.long INT15_IRQHandler // 15: Interrupt Pin15
.long INT16_IRQHandler // 16: Interrupt Pin 16
.long INT17_18_IRQHandler // 17: Interrupt Pin 17_18
.long INT19_22_IRQHandler // 18: Interrupt Pin 19_22
.long INT23_26_IRQHandler // 19: Interrupt Pin 23_26
.long INT27_28_IRQHandler // 20: Interrupt Pin 27_28
.long INT29_IRQHandler // 21: Interrupt Pin 29
.long INT30_31_IRQHandler // 22: Interrupt Pin 30_31
.long INTEMG0_IRQHandler // 23: PMD0 EMG interrupt
.long INTOVV0_IRQHandler // 24: PMD0 OVV interrupt
.long INTPMD0_IRQHandler // 25: PMD0 interrupt
.long INTENC00_IRQHandler // 26: Encoder 0 interrupt 0
.long INTENC01_IRQHandler // 27: Encoder 0 interrupt 1
.long INTADAPDA_IRQHandler // 28: ADC conversion triggered by PMD is finished A
.long INTADAPDB_IRQHandler // 29: ADC conversion triggered by PMD is finished B
.long INTADACP0_IRQHandler // 30: ADC conversion monitoring function interrupt 0
.long INTADACP1_IRQHandler // 31: ADC conversion monitoring function interrupt 1
.long INTADATRG_IRQHandler // 32: ADC conversion triggered by General purpose is finished
.long INTADASGL_IRQHandler // 33: ADC conversion triggered by Single program is finished
.long INTADACNT_IRQHandler // 34: ADC conversion triggered by Continuity program is finished
.long INTT0RX_IRQHandler // 35: TSPI/SIO reception (channel 0)
.long INTT0TX_IRQHandler // 36: TSPI/SIO transmit (channel 0)
.long INTT0ERR_IRQHandler // 37: TSPI/SIO error (channel 0)
.long INTT1RX_IRQHandler // 38: TSPI/SIO reception (channel 1)
.long INTT1TX_IRQHandler // 39: TSPI/SIO transmit (channel 1)
.long INTT1ERR_IRQHandler // 40: TSPI/SIO error (channel 1)
.long INTT2RX_IRQHandler // 41: TSPI/SIO reception (channel 2)
.long INTT2TX_IRQHandler // 42: TSPI/SIO transmit (channel 2)
.long INTT2ERR_IRQHandler // 43: TSPI/SIO error (channel 2)
.long INTT3RX_IRQHandler // 44: TSPI/SIO reception (channel 3)
.long INTT3TX_IRQHandler // 45: TSPI/SIO transmit (channel 3)
.long INTT3ERR_IRQHandler // 46: TSPI/SIO error (channel 3)
.long INTT4RX_IRQHandler // 47: TSPI/SIO reception (channel 4)
.long INTT4TX_IRQHandler // 48: TSPI/SIO transmit (channel 4)
.long INTT4ERR_IRQHandler // 49: TSPI/SIO error (channel 4)
.long INTI2CWUP_IRQHandler // 50: Serial bus interface (WakeUp) interrupt (channel 0)
.long INTI2C0_IRQHandler // 51: I2C0 transmission and reception interrupt
.long INTI2C0AL_IRQHandler // 52: I2C0 arbitration lost interrupt
.long INTI2C0BF_IRQHandler // 53: I2C0 bus free interrupt
.long INTI2C0NA_IRQHandler // 54: I2C0 no ack interrupt
.long INTI2C1_IRQHandler // 55: I2C1 transmission and reception interrupt
.long INTI2C1AL_IRQHandler // 56: I2C1 arbitration lost interrupt
.long INTI2C1BF_IRQHandler // 57: I2C1 bus free interrupt
.long INTI2C1NA_IRQHandler // 58: I2C1 no ack interrupt
.long INTI2C2_IRQHandler // 59: I2C2 transmission and reception interrupt
.long INTI2C2AL_IRQHandler // 60: I2C2 arbitration lost interrupt
.long INTI2C2BF_IRQHandler // 61: I2C2 bus free interrupt
.long INTI2C2NA_IRQHandler // 62: I2C2 no ack interrupt
.long INTI2C3_IRQHandler // 63: I2C3 transmission and reception interrupt
.long INTI2C3AL_IRQHandler // 64: I2C3 arbitration lost interrupt
.long INTI2C3BF_IRQHandler // 65: I2C3 bus free interrupt
.long INTI2C3NA_IRQHandler // 66: I2C3 no ack interrupt
.long INTUART0RX_IRQHandler // 67: UART reception (channel 0)
.long INTUART0TX_IRQHandler // 68: UART transmit (channel 0)
.long INTUART0ERR_IRQHandler // 69: UART error (channel 0)
.long INTUART1RX_IRQHandler // 70: UART reception (channel 1)
.long INTUART1TX_IRQHandler // 71: UART transmit (channel 1)
.long INTUART1ERR_IRQHandler // 72: UART error (channel 1)
.long INTUART2RX_IRQHandler // 73: UART reception (channel 2)
.long INTUART2TX_IRQHandler // 74: UART transmit (channel 2)
.long INTUART2ERR_IRQHandler // 75: UART error (channel 2)
.long INTUART3RX_IRQHandler // 76: UART reception (channel 3)
.long INTUART3TX_IRQHandler // 77: UART transmit (channel 3)
.long INTUART3ERR_IRQHandler // 78: UART error (channel 3)
.long INTUART4RX_IRQHandler // 79: UART reception (channel 4)
.long INTUART4TX_IRQHandler // 80: UART transmit (channel 4)
.long INTUART4ERR_IRQHandler // 81: UART error (channel 4)
.long INTUART5RX_IRQHandler // 82: UART reception (channel 5)
.long INTUART5TX_IRQHandler // 83: UART transmit (channel 5)
.long INTUART5ERR_IRQHandler // 84: UART error (channel 5)
.long INTT32A00A_IRQHandler // 85: 32bit T32A00A compare match detection 0 / Over flow / under flow
.long INTT32A00ACAP0_IRQHandler // 86: 32bit T32A00A input capture 0
.long INTT32A00ACAP1_IRQHandler // 87: 32bit T32A00A input capture 1
.long INTT32A00B_IRQHandler // 88: 32bit T32A00B compare match detection 0 / Over flow / under flow
.long INTT32A00BCAP0_IRQHandler // 89: 32bit T32A00B input capture 0
.long INTT32A00BCAP1_IRQHandler // 90: 32bit T32A00B input capture 1
.long INTT32A00C_IRQHandler // 91: 32bit T32A00C compare match detection 0 / Over flow / under flow
.long INTT32A00CCAP0_IRQHandler // 92: 32bit T32A00C input capture 0
.long INTT32A00CCAP1_IRQHandler // 93: 32bit T32A00C input capture 1
.long INTT32A01A_IRQHandler // 94: 32bit T32A01A compare match detection 0 / Over flow / under flow
.long INTT32A01ACAP0_IRQHandler // 95: 32bit T32A01A input capture 0
.long INTT32A01ACAP1_IRQHandler // 96: 32bit T32A01A input capture 1
.long INTT32A01B_IRQHandler // 97: 32bit T32A01B compare match detection 0 / Over flow / under flow
.long INTT32A01BCAP0_IRQHandler // 98: 32bit T32A01B input capture 0
.long INTT32A01BCAP1_IRQHandler // 99: 32bit T32A01B input capture 1
.long INTT32A01C_IRQHandler // 100: 32bit T32A01C compare match detection 0 / Over flow / under flow
.long INTT32A01CCAP0_IRQHandler // 101: 32bit T32A01C input capture 0
.long INTT32A01CCAP1_IRQHandler // 102: 32bit T32A01C input capture 1
.long INTT32A02A_IRQHandler // 103: 32bit T32A02A compare match detection 0 / Over flow / under flow
.long INTT32A02ACAP0_IRQHandler // 104: 32bit T32A02A input capture 0
.long INTT32A02ACAP1_IRQHandler // 105: 32bit T32A02A input capture 1
.long INTT32A02B_IRQHandler // 106: 32bit T32A02B compare match detection 0 / Over flow / under flow
.long INTT32A02BCAP0_IRQHandler // 107: 32bit T32A02B input capture 0
.long INTT32A02BCAP1_IRQHandler // 108: 32bit T32A02B input capture 1
.long INTT32A02C_IRQHandler // 109: 32bit T32A02C compare match detection 0 / Over flow / under flow
.long INTT32A02CCAP0_IRQHandler // 110: 32bit T32A02C input capture 0
.long INTT32A02CCAP1_IRQHandler // 111: 32bit T32A02C input capture 1
.long INTT32A03A_IRQHandler // 112: 32bit T32A03A compare match detection 0 / Over flow / under flow
.long INTT32A03ACAP0_IRQHandler // 113: 32bit T32A03A input capture 0
.long INTT32A03ACAP1_IRQHandler // 114: 32bit T32A03A input capture 1
.long INTT32A03B_IRQHandler // 115: 32bit T32A03B compare match detection 0 / Over flow / under flow
.long INTT32A03BCAP0_IRQHandler // 116: 32bit T32A03B input capture 0
.long INTT32A03BCAP1_IRQHandler // 117: 32bit T32A03B input capture 1
.long INTT32A03C_IRQHandler // 118: 32bit T32A03C compare match detection 0 / Over flow / under flow
.long INTT32A03CCAP0_IRQHandler // 119: 32bit T32A03C input capture 0
.long INTT32A03CCAP1_IRQHandler // 120: 32bit T32A03C input capture 1
.long INTT32A04A_IRQHandler // 121: 32bit T32A04A compare match detection 0 / Over flow / under flow
.long INTT32A04ACAP0_IRQHandler // 122: 32bit T32A04A input capture 0
.long INTT32A04ACAP1_IRQHandler // 123: 32bit T32A04A input capture 1
.long INTT32A04B_IRQHandler // 124: 32bit T32A04B compare match detection 0 / Over flow / under flow
.long INTT32A04BCAP0_IRQHandler // 125: 32bit T32A04B input capture 0
.long INTT32A04BCAP1_IRQHandler // 126: 32bit T32A04B input capture 1
.long INTT32A04C_IRQHandler // 127: 32bit T32A04C compare match detection 0 / Over flow / under flow
.long INTT32A04CCAP0_IRQHandler // 128: 32bit T32A04C input capture 0
.long INTT32A04CCAP1_IRQHandler // 129: 32bit T32A04C input capture 1
.long INTT32A05A_IRQHandler // 130: 32bit T32A05A compare match detection 0 / Over flow / under flow
.long INTT32A05ACAP0_IRQHandler // 131: 32bit T32A05A input capture 0
.long INTT32A05ACAP1_IRQHandler // 132: 32bit T32A05A input capture 1
.long INTT32A05B_IRQHandler // 133: 32bit T32A05B compare match detection 0 / Over flow / under flow
.long INTT32A05BCAP0_IRQHandler // 134: 32bit T32A05B input capture 0
.long INTT32A05BCAP1_IRQHandler // 135: 32bit T32A05B input capture 1
.long INTT32A05C_IRQHandler // 136: 32bit T32A05C compare match detection 0 / Over flow / under flow
.long INTT32A05CCAP0_IRQHandler // 137: 32bit T32A05C input capture 0
.long INTT32A05CCAP1_IRQHandler // 138: 32bit T32A05C input capture 1
.long INTT32A06A_IRQHandler // 139: 32bit T32A06A compare match detection 0 / Over flow / under flow
.long INTT32A06ACAP0_IRQHandler // 140: 32bit T32A06A input capture 0
.long INTT32A06ACAP1_IRQHandler // 141: 32bit T32A06A input capture 1
.long INTT32A06B_IRQHandler // 142: 32bit T32A06B compare match detection 0 / Over flow / under flow
.long INTT32A06BCAP0_IRQHandler // 143: 32bit T32A06B input capture 0
.long INTT32A06BCAP1_IRQHandler // 144: 32bit T32A06B input capture 1
.long INTT32A06C_IRQHandler // 145: 32bit T32A06C compare match detection 0 / Over flow / under flow
.long INTT32A06CCAP0_IRQHandler // 146: 32bit T32A06C input capture 0
.long INTT32A06CCAP1_IRQHandler // 147: 32bit T32A06C input capture 1
.long INTT32A07A_IRQHandler // 148: 32bit T32A07A compare match detection 0 / Over flow / under flow
.long INTT32A07ACAP0_IRQHandler // 149: 32bit T32A07A input capture 0
.long INTT32A07ACAP1_IRQHandler // 150: 32bit T32A07A input capture 1
.long INTT32A07B_IRQHandler // 151: 32bit T32A07B compare match detection 0 / Over flow / under flow
.long INTT32A07BCAP0_IRQHandler // 152: 32bit T32A07B input capture 0
.long INTT32A07BCAP1_IRQHandler // 153: 32bit T32A07B input capture 1
.long INTT32A07C_IRQHandler // 154: 32bit T32A07C compare match detection 0 / Over flow / under flow
.long INTT32A07CCAP0_IRQHandler // 155: 32bit T32A07C input capture 0
.long INTT32A07CCAP1_IRQHandler // 156: 32bit T32A07C input capture 1
.long INTPARI_IRQHandler // 157: RAM parity interrupt
.long INTDMAATC_IRQHandler // 158: DMAA end of transfer
.long INTDMAAERR_IRQHandler // 159: DMAA transfer error
.long INTDMABTC_IRQHandler // 160: DMAB end of transfer
.long INTDMABERR_IRQHandler // 161: DMAB transfer error
.long INTRTC_IRQHandler // 162: Real time clock interrupt
.long INTRMC0_IRQHandler // 163: Remote control reception interrupt
.long INTFLCRDY_IRQHandler // 164: Code FLASH Ready interrupt
.long INTFLDRDY_IRQHandler // 165: Data FLASH Ready interrupt
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
.align 1
.thumb_func
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
b .
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler INT00_IRQHandler
def_irq_handler INT01_IRQHandler
def_irq_handler INT02_IRQHandler
def_irq_handler INT03_IRQHandler
def_irq_handler INT04_IRQHandler
def_irq_handler INT05_IRQHandler
def_irq_handler INT06_IRQHandler
def_irq_handler INT07_IRQHandler
def_irq_handler INT08_IRQHandler
def_irq_handler INT09_IRQHandler
def_irq_handler INT10_IRQHandler
def_irq_handler INT11_IRQHandler
def_irq_handler INT12_IRQHandler
def_irq_handler INT13_IRQHandler
def_irq_handler INT14_IRQHandler
def_irq_handler INT15_IRQHandler
def_irq_handler INT16_IRQHandler
def_irq_handler INT17_18_IRQHandler
def_irq_handler INT19_22_IRQHandler
def_irq_handler INT23_26_IRQHandler
def_irq_handler INT27_28_IRQHandler
def_irq_handler INT29_IRQHandler
def_irq_handler INT30_31_IRQHandler
def_irq_handler INTEMG0_IRQHandler
def_irq_handler INTOVV0_IRQHandler
def_irq_handler INTPMD0_IRQHandler
def_irq_handler INTENC00_IRQHandler
def_irq_handler INTENC01_IRQHandler
def_irq_handler INTADAPDA_IRQHandler
def_irq_handler INTADAPDB_IRQHandler
def_irq_handler INTADACP0_IRQHandler
def_irq_handler INTADACP1_IRQHandler
def_irq_handler INTADATRG_IRQHandler
def_irq_handler INTADASGL_IRQHandler
def_irq_handler INTADACNT_IRQHandler
def_irq_handler INTT0RX_IRQHandler
def_irq_handler INTT0TX_IRQHandler
def_irq_handler INTT0ERR_IRQHandler
def_irq_handler INTT1RX_IRQHandler
def_irq_handler INTT1TX_IRQHandler
def_irq_handler INTT1ERR_IRQHandler
def_irq_handler INTT2RX_IRQHandler
def_irq_handler INTT2TX_IRQHandler
def_irq_handler INTT2ERR_IRQHandler
def_irq_handler INTT3RX_IRQHandler
def_irq_handler INTT3TX_IRQHandler
def_irq_handler INTT3ERR_IRQHandler
def_irq_handler INTT4RX_IRQHandler
def_irq_handler INTT4TX_IRQHandler
def_irq_handler INTT4ERR_IRQHandler
def_irq_handler INTI2CWUP_IRQHandler
def_irq_handler INTI2C0_IRQHandler
def_irq_handler INTI2C0AL_IRQHandler
def_irq_handler INTI2C0BF_IRQHandler
def_irq_handler INTI2C0NA_IRQHandler
def_irq_handler INTI2C1_IRQHandler
def_irq_handler INTI2C1AL_IRQHandler
def_irq_handler INTI2C1BF_IRQHandler
def_irq_handler INTI2C1NA_IRQHandler
def_irq_handler INTI2C2_IRQHandler
def_irq_handler INTI2C2AL_IRQHandler
def_irq_handler INTI2C2BF_IRQHandler
def_irq_handler INTI2C2NA_IRQHandler
def_irq_handler INTI2C3_IRQHandler
def_irq_handler INTI2C3AL_IRQHandler
def_irq_handler INTI2C3BF_IRQHandler
def_irq_handler INTI2C3NA_IRQHandler
def_irq_handler INTUART0RX_IRQHandler
def_irq_handler INTUART0TX_IRQHandler
def_irq_handler INTUART0ERR_IRQHandler
def_irq_handler INTUART1RX_IRQHandler
def_irq_handler INTUART1TX_IRQHandler
def_irq_handler INTUART1ERR_IRQHandler
def_irq_handler INTUART2RX_IRQHandler
def_irq_handler INTUART2TX_IRQHandler
def_irq_handler INTUART2ERR_IRQHandler
def_irq_handler INTUART3RX_IRQHandler
def_irq_handler INTUART3TX_IRQHandler
def_irq_handler INTUART3ERR_IRQHandler
def_irq_handler INTUART4RX_IRQHandler
def_irq_handler INTUART4TX_IRQHandler
def_irq_handler INTUART4ERR_IRQHandler
def_irq_handler INTUART5RX_IRQHandler
def_irq_handler INTUART5TX_IRQHandler
def_irq_handler INTUART5ERR_IRQHandler
def_irq_handler INTT32A00A_IRQHandler
def_irq_handler INTT32A00ACAP0_IRQHandler
def_irq_handler INTT32A00ACAP1_IRQHandler
def_irq_handler INTT32A00B_IRQHandler
def_irq_handler INTT32A00BCAP0_IRQHandler
def_irq_handler INTT32A00BCAP1_IRQHandler
def_irq_handler INTT32A00C_IRQHandler
def_irq_handler INTT32A00CCAP0_IRQHandler
def_irq_handler INTT32A00CCAP1_IRQHandler
def_irq_handler INTT32A01A_IRQHandler
def_irq_handler INTT32A01ACAP0_IRQHandler
def_irq_handler INTT32A01ACAP1_IRQHandler
def_irq_handler INTT32A01B_IRQHandler
def_irq_handler INTT32A01BCAP0_IRQHandler
def_irq_handler INTT32A01BCAP1_IRQHandler
def_irq_handler INTT32A01C_IRQHandler
def_irq_handler INTT32A01CCAP0_IRQHandler
def_irq_handler INTT32A01CCAP1_IRQHandler
def_irq_handler INTT32A02A_IRQHandler
def_irq_handler INTT32A02ACAP0_IRQHandler
def_irq_handler INTT32A02ACAP1_IRQHandler
def_irq_handler INTT32A02B_IRQHandler
def_irq_handler INTT32A02BCAP0_IRQHandler
def_irq_handler INTT32A02BCAP1_IRQHandler
def_irq_handler INTT32A02C_IRQHandler
def_irq_handler INTT32A02CCAP0_IRQHandler
def_irq_handler INTT32A02CCAP1_IRQHandler
def_irq_handler INTT32A03A_IRQHandler
def_irq_handler INTT32A03ACAP0_IRQHandler
def_irq_handler INTT32A03ACAP1_IRQHandler
def_irq_handler INTT32A03B_IRQHandler
def_irq_handler INTT32A03BCAP0_IRQHandler
def_irq_handler INTT32A03BCAP1_IRQHandler
def_irq_handler INTT32A03C_IRQHandler
def_irq_handler INTT32A03CCAP0_IRQHandler
def_irq_handler INTT32A03CCAP1_IRQHandler
def_irq_handler INTT32A04A_IRQHandler
def_irq_handler INTT32A04ACAP0_IRQHandler
def_irq_handler INTT32A04ACAP1_IRQHandler
def_irq_handler INTT32A04B_IRQHandler
def_irq_handler INTT32A04BCAP0_IRQHandler
def_irq_handler INTT32A04BCAP1_IRQHandler
def_irq_handler INTT32A04C_IRQHandler
def_irq_handler INTT32A04CCAP0_IRQHandler
def_irq_handler INTT32A04CCAP1_IRQHandler
def_irq_handler INTT32A05A_IRQHandler
def_irq_handler INTT32A05ACAP0_IRQHandler
def_irq_handler INTT32A05ACAP1_IRQHandler
def_irq_handler INTT32A05B_IRQHandler
def_irq_handler INTT32A05BCAP0_IRQHandler
def_irq_handler INTT32A05BCAP1_IRQHandler
def_irq_handler INTT32A05C_IRQHandler
def_irq_handler INTT32A05CCAP0_IRQHandler
def_irq_handler INTT32A05CCAP1_IRQHandler
def_irq_handler INTT32A06A_IRQHandler
def_irq_handler INTT32A06ACAP0_IRQHandler
def_irq_handler INTT32A06ACAP1_IRQHandler
def_irq_handler INTT32A06B_IRQHandler
def_irq_handler INTT32A06BCAP0_IRQHandler
def_irq_handler INTT32A06BCAP1_IRQHandler
def_irq_handler INTT32A06C_IRQHandler
def_irq_handler INTT32A06CCAP0_IRQHandler
def_irq_handler INTT32A06CCAP1_IRQHandler
def_irq_handler INTT32A07A_IRQHandler
def_irq_handler INTT32A07ACAP0_IRQHandler
def_irq_handler INTT32A07ACAP1_IRQHandler
def_irq_handler INTT32A07B_IRQHandler
def_irq_handler INTT32A07BCAP0_IRQHandler
def_irq_handler INTT32A07BCAP1_IRQHandler
def_irq_handler INTT32A07C_IRQHandler
def_irq_handler INTT32A07CCAP0_IRQHandler
def_irq_handler INTT32A07CCAP1_IRQHandler
def_irq_handler INTPARI_IRQHandler
def_irq_handler INTDMAATC_IRQHandler
def_irq_handler INTDMAAERR_IRQHandler
def_irq_handler INTDMABTC_IRQHandler
def_irq_handler INTDMABERR_IRQHandler
def_irq_handler INTRTC_IRQHandler
def_irq_handler INTRMC0_IRQHandler
def_irq_handler INTFLCRDY_IRQHandler
def_irq_handler INTFLDRDY_IRQHandler
.end

162
targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld Normal file
View File

@ -0,0 +1,162 @@
/* Linker script for Toshiba TMPM3HQ */
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
/* 8_byte_aligned((166 + 16) vect * 4 bytes) = 8_byte_aligned(0x2D8) = 0x2D8 */
RAM (rwx) : ORIGIN = (0x20000000 + 0x2D8), LENGTH = (64K - 0x2D8)
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __copy_table_start__
* __copy_table_end__
* __zero_table_start__
* __zero_table_end__
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* __Vectors_End
* __Vectors_Size
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
KEEP(*(.stack*))
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

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targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_IAR/startup_TMPM3HQ.S Normal file
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targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x200002D8;
define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF;
/*Heap 1/4 of ram and stack 1/8*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define symbol __BRAM_start__ = 0x20010000;
define symbol __BRAM_end__ = 0x200107FF;
define symbol __DFLASH_start__ = 0x30000000;
define symbol __DFLASH_end__ = 0x30007FFF;
define region BRAM_region = mem:[from __BRAM_start__ to __BRAM_end__ ];
define region DFLASH_region = mem:[from __DFLASH_start__ to __DFLASH_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
place in BRAM_region { section .backup_ram };
place in DFLASH_region { section .data_flash };

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/* mbed Microcontroller Library - CMSIS for TMPM3HQ
* Copyright (C) 2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in TMPM3HQ specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "TMPM3HQ.h"
#include "cmsis_nvic.h"
#endif

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/* mbed Microcontroller Library - cmsis_nvic for TMPM3HQ
* Copyright (c) 2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_FLASH_VECTOR_ADDRESS 0x00000000
#define NVIC_USER_IRQ_NUMBER 166
#define NVIC_NUM_VECTORS (16 + 166) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
#endif

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/**
*******************************************************************************
* @file system_TMPM3Hy.c
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File for the
* TOSHIBA 'TMPM3Hy' Device Series
* @version 0.0.5.0
* $Date:: 2017-07-01 #$
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
*
* (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
*******************************************************************************
*/
#include "TMPM3HQ.h"
/*-------- <<< Start of configuration section >>> ----------------------------*/
/* Semi-Independent Watchdog Timer (SIWDT) Configuration */
#define SIWD_SETUP (1U) /* 1:Disable SIWD, 0:Enable SIWD */
#define SIWDEN_Val (0x00000000UL) /* SIWD Disable */
#define SIWDCR_Val (0x000000B1UL) /* SIWD Disable code */
/* Clock Generator (CG) Configuration */
#define CLOCK_SETUP (1U) /* 1:External HOSC, 0: Internal HOSC */
#define SYSCR_Val (0x00000000UL)
#define STBYCR_Val (0x00000000UL)
#define CG_6M_MUL_13_328_FPLL (0x001C6535UL<<8U) /* fPLL = 6MHz * 13.328 */
#define CG_8M_MUL_10_FPLL (0x00246028UL<<8U) /* fPLL = 8MHz * 10 */
#define CG_10M_MUL_8_FPLL (0x002E6020UL<<8U) /* fPLL = 10MHz * 8 */
#define CG_12M_MUL_6_656_FPLL (0x0036EA1AUL<<8U) /* fPLL = 12MHz * 6.656 */
#define CG_6M_MUL_6_664_FPLL (0x001C7535UL<<8U) /* fPLL = 6MHz * 6.664 */
#define CG_8M_MUL_5_FPLL (0x00247028UL<<8U) /* fPLL = 8MHz * 5 */
#define CG_10M_MUL_4_FPLL (0x002E7020UL<<8U) /* fPLL = 10MHz * 4 */
#define CG_12M_MUL_3_328_FPLL (0x0036FA1AUL<<8U) /* fPLL = 12MHz * 3.328 */
#define CG_PLL0SEL_PLL0ON_SET ((uint32_t)0x00000001)
#define CG_PLL0SEL_PLL0ON_CLEAR ((uint32_t)0xFFFFFFFE)
#define CG_PLL0SEL_PLL0SEL_SET ((uint32_t)0x00000002)
#define CG_PLL0SEL_PLL0SEL_CLEAR ((uint32_t)0xFFFFFFFD)
#define CG_OSCCR_IHOSC1EN_CLEAR ((uint32_t)0xFFFFFFFE)
#define CG_OSCCR_EOSCEN_SET ((uint32_t)0x00000002)
#define CG_OSCCR_OSCSEL_SET ((uint32_t)0x00000100)
#define CG_WUPHCR_WUON_START_SET ((uint32_t)0x00000001)
#if (CLOCK_SETUP)
#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000100)
#define PLL0SEL_Ready CG_12M_MUL_3_328_FPLL
#else
#define CG_WUPHCR_WUCLK_SET ((uint32_t)0x00000000)
#define PLL0SEL_Ready CG_10M_MUL_8_FPLL
#endif
#define PLL0SEL_Val (PLL0SEL_Ready|0x00000003UL)
#define PLL0SEL_MASK (0xFFFFFF00UL)
/*-------- <<< End of configuration section >>> ------------------------------*/
/*-------- DEFINES -----------------------------------------------------------*/
/* Define clocks */
#define EOSC_6M (6000000UL)
#define EOSC_8M (8000000UL)
#define EOSC_10M (10000000UL)
#define EOSC_12M (12000000UL)
#define IOSC_10M (10000000UL)
#define EXTALH EOSC_12M /* External high-speed oscillator freq */
#define IXTALH IOSC_10M /* Internal high-speed oscillator freq */
#define EOSC_6M_DIV4_PLLON (79970000UL) /* 6.00MHz * 53.3125 / 4 */
#define EOSC_8M_DIV4_PLLON (80000000UL) /* 8.00MHz * 40.0000 / 4 */
#define EOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */
#define EOSC_12M_DIV4_PLLON (79880000UL) /* 12.00MHz * 26.6250 / 4 */
#define IOSC_10M_DIV4_PLLON (80000000UL) /* 10.00MHz * 32.0000 / 4 */
#define EOSC_6M_DIV8_PLLON (39980000UL) /* 6.00MHz * 53.3125 / 8 */
#define EOSC_8M_DIV8_PLLON (40000000UL) /* 8.00MHz * 40.0000 / 8 */
#define EOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */
#define EOSC_12M_DIV8_PLLON (39940000UL) /* 12.00MHz * 26.6250 / 8 */
#define IOSC_10M_DIV8_PLLON (40000000UL) /* 10.00MHz * 32.0000 / 8 */
/* Configure Warm-up time */
#define HZ_1M (1000000UL)
#define WU_TIME_EXT (5000UL) /* warm-up time for EXT is 5ms */
#define INIT_TIME_PLL (100UL) /* Initial time for PLL is 100us */
#define LOCKUP_TIME_PLL (400UL) /* Lockup time for PLL is 400us */
#define WUPHCR_WUPT_EXT ((uint32_t)(((((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M) - 16UL) /16UL) << 20U)) /* OSCCR<WUPT11:0> = warm-up time(us) * EXTALH / 16 */
#if (CLOCK_SETUP)
#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * EXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#else
#define WUPHCR_INIT_PLL ((uint32_t)(((((uint64_t)INIT_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#define WUPHCR_LUPT_PLL ((uint32_t)(((((uint64_t)LOCKUP_TIME_PLL * IXTALH / HZ_1M) - 16UL) /16UL) << 20U))
#endif
/* Determine core clock frequency according to settings */
/* System clock is high-speed clock*/
#if (CLOCK_SETUP)
#define CORE_TALH (EXTALH)
#else
#define CORE_TALH (IXTALH)
#endif
#if ((PLL0SEL_Val & (1U<<1U)) && (PLL0SEL_Val & (1U<<0U))) /* If PLL selected and enabled */
#if (CORE_TALH == EOSC_6M) /* If input is 6MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_13_328_FPLL))
#define __CORE_CLK EOSC_6M_DIV4_PLLON /* output clock is 79.97MHz */
#elif ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_6M_MUL_6_664_FPLL))
#define __CORE_CLK EOSC_6M_DIV8_PLLON /* output clock is 39.98MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 6MHz */
#elif (CORE_TALH == EOSC_8M) /* If input is 8MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_10_FPLL))
#define __CORE_CLK EOSC_8M_DIV4_PLLON /* output clock is 80MHz */
#elif ((PLL0SEL_Val & PLL0SEL_MASK) == (CG_8M_MUL_5_FPLL))
#define __CORE_CLK EOSC_8M_DIV8_PLLON /* output clock is 40MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 8MHz */
#elif (CORE_TALH == EOSC_10M) /* If input is 10MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL)
#define __CORE_CLK EOSC_10M_DIV4_PLLON /* output clock is 80MHz */
#elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL)
#define __CORE_CLK EOSC_10M_DIV8_PLLON /* output clock is 40MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 10MHz */
#elif (CORE_TALH == EOSC_12M) /* If input is 12MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_6_656_FPLL)
#define __CORE_CLK EOSC_12M_DIV4_PLLON /* output clock is 79.88MHz */
#elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL)
#define __CORE_CLK EOSC_12M_DIV8_PLLON /* output clock is 39.94MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 12MHz */
#elif (CORE_TALH == IOSC_10M) /* If input is 10MHz */
#if ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL)
#define __CORE_CLK IOSC_10M_DIV4_PLLON /* output clock is 80MHz */
#elif ((PLL0SEL_Val & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL)
#define __CORE_CLK IOSC_10M_DIV8_PLLON /* output clock is 40MHz */
#else /* fc -> reserved */
#define __CORE_CLK (0U)
#endif /* End input is 10MHz */
#else /* input clock not known */
#define __CORE_CLK (0U)
#error "Core Oscillator Frequency invalid!"
#endif /* End switch input clock */
#else
#define __CORE_CLK (CORE_TALH)
#endif
#if ((SYSCR_Val & 7U) == 0U) /* Gear -> fc */
#define __CORE_SYS (__CORE_CLK)
#elif ((SYSCR_Val & 7U) == 1U) /* Gear -> fc/2 */
#define __CORE_SYS (__CORE_CLK / 2U)
#elif ((SYSCR_Val & 7U) == 2U) /* Gear -> fc/4 */
#define __CORE_SYS (__CORE_CLK / 4U )
#elif ((SYSCR_Val & 7U) == 3U) /* Gear -> fc/8 */
#define __CORE_SYS (__CORE_CLK / 8U)
#elif ((SYSCR_Val & 7U) == 4U) /* Gear -> fc/16 */
#define __CORE_SYS (__CORE_CLK / 16U)
#else /* Gear -> reserved */
#define __CORE_SYS (0U)
#endif
/* Clock Variable definitions */
uint32_t SystemCoreClock = __CORE_SYS; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Update SystemCoreClock according register values.
*/
void SystemCoreClockUpdate(void)
{ /* Get Core Clock Frequency */
uint32_t CoreClock = 0U;
uint32_t CoreClockInput = 0U;
uint32_t regval = 0U;
uint32_t oscsel = 0U;
uint32_t pll0sel = 0U;
uint32_t pll0on = 0U;
/* Determine clock frequency according to clock register values */
/* System clock is high-speed clock */
regval = TSB_CG->OSCCR;
oscsel = regval & CG_OSCCR_OSCSEL_SET;
if (oscsel) { /* If system clock is External high-speed oscillator freq */
CoreClock = EXTALH;
} else { /* If system clock is Internal high-speed oscillator freq */
CoreClock = IXTALH;
}
regval = TSB_CG->PLL0SEL;
pll0sel = regval & CG_PLL0SEL_PLL0SEL_SET;
pll0on = regval & CG_PLL0SEL_PLL0ON_SET;
if (pll0sel && pll0on) { /* If PLL enabled */
if (CoreClock == EOSC_6M) { /* If input is 6MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_13_328_FPLL) {
CoreClockInput = EOSC_6M_DIV4_PLLON; /* output clock is 79.97MHz */
} else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_6M_MUL_6_664_FPLL) {
CoreClockInput = EOSC_6M_DIV8_PLLON; /* output clock is 39.98MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_8M) { /* If input is 8MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_10_FPLL) {
CoreClockInput = EOSC_8M_DIV4_PLLON; /* output clock is 80MHz */
} else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_8M_MUL_5_FPLL) {
CoreClockInput = EOSC_8M_DIV8_PLLON; /* output clock is 40MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_10M) { /* If input is 10MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) {
CoreClockInput = EOSC_10M_DIV4_PLLON; /* output clock is 80MHz */
} else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) {
CoreClockInput = EOSC_10M_DIV8_PLLON; /* output clock is 40MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == EOSC_12M) { /* If input is 12MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_6_656_FPLL) {
CoreClockInput = EOSC_12M_DIV4_PLLON; /* output clock is 79.88MHz */
} else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_12M_MUL_3_328_FPLL) {
CoreClockInput = EOSC_12M_DIV8_PLLON; /* output clock is 39.94MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else if (CoreClock == IOSC_10M) { /* If input is 10MHz */
if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_8_FPLL) {
CoreClockInput = IOSC_10M_DIV4_PLLON; /* output clock is 80MHz */
} else if ((TSB_CG->PLL0SEL & PLL0SEL_MASK) == CG_10M_MUL_4_FPLL) {
CoreClockInput = IOSC_10M_DIV8_PLLON; /* output clock is 40MHz */
} else {
CoreClockInput = 0U; /* fc -> reserved */
}
} else {
CoreClockInput = 0U;
}
} else { /* If PLL not used */
CoreClockInput = CoreClock;
}
switch (TSB_CG->SYSCR & 7U) {
case 0U: /* Gear -> fc */
SystemCoreClock = CoreClockInput;
break;
case 1U: /* Gear -> fc/2 */
SystemCoreClock = CoreClockInput / 2U;
break;
case 2U: /* Gear -> fc/4 */
SystemCoreClock = CoreClockInput / 4U;
break;
case 3U: /* Gear -> fc/8 */
if (CoreClockInput >= EOSC_8M) {
SystemCoreClock = CoreClockInput / 8U;
} else {
SystemCoreClock = 0U;
}
break;
case 4U: /* Gear -> fc/16 */
if (CoreClockInput > EOSC_12M) {
SystemCoreClock = CoreClockInput / 16U;
} else {
SystemCoreClock = 0U;
}
break;
case 5U:
case 6U:
case 7U:
SystemCoreClock = 0U;
break;
default:
SystemCoreClock = 0U;
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit(void)
{
#if (SIWD_SETUP) /* Watchdog Setup */
/* SIWD Disable */
TSB_SIWD0->EN = SIWDEN_Val;
TSB_SIWD0->CR = SIWDCR_Val;
#else
/* SIWD Enable (Setting after a Reset) */
#endif
#if (CLOCK_SETUP) /* Clock(external) Setup */
TSB_CG->SYSCR = SYSCR_Val;
TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET);
TSB_CG->OSCCR |= CG_OSCCR_EOSCEN_SET;
TSB_CG->WUPHCR = (WUPHCR_WUPT_EXT | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Warm-up */
TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
while (!TSB_CG_OSCCR_OSCF) {
;
} /* Confirm CGOSCCR<OSCF>="1" */
TSB_CG->OSCCR &= CG_OSCCR_IHOSC1EN_CLEAR ;
#else
/* Internal HOSC Enable (Setting after a Reset) */
#endif
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET);
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0SEL_CLEAR; /* PLL-->fOsc */
TSB_CG->PLL0SEL &= CG_PLL0SEL_PLL0ON_CLEAR;
TSB_CG->PLL0SEL = PLL0SEL_Ready;
TSB_CG->WUPHCR = (WUPHCR_INIT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Warm-up */
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET);
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0ON_SET; /* PLL enabled */
TSB_CG->STBYCR = STBYCR_Val;
TSB_CG->WUPHCR = (WUPHCR_LUPT_PLL | CG_WUPHCR_WUCLK_SET | CG_WUPHCR_WUON_START_SET);
while (TSB_CG_WUPHCR_WUEF) {
;
} /* Lockup */
TSB_CG->PLL0SEL |= CG_PLL0SEL_PLL0SEL_SET;
while (!TSB_CG_PLL0SEL_PLL0ST) {
;
} /*Confirm CGPLL0SEL<PLL0ST> = "1" */
}

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/**
*****************************************************************************
* @file system_TMPM3Hy.h
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for the
* TOSHIBA 'TMPM3Hy' Device Series
* @version V1.0.1.0
* $Date:: 2017-07-01 #$
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
*
* (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
*****************************************************************************
*/
#include <stdint.h>
#ifndef __SYSTEM_TMPM3HQ_H
#define __SYSTEM_TMPM3HQ_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "gpio_include.h"
extern const PinMap PinMap_GPIO_IRQ[];
void gpio_init(gpio_t *obj, PinName pin)
{
// Store above pin mask, pin name into GPIO object
obj->pin = pin;
obj->mask = gpio_set(pin);
obj->port = (PortName)(pin >> 3);
TSB_CG->FSYSENA |= (1 << (obj->port));
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
pin_mode(obj->pin, mode);
}
uint32_t gpio_set(PinName pin)
{
// Check that pin is valid
MBED_ASSERT(pin != (PinName)NC);
// Set pin function as GPIO pin
pin_function(pin, GPIO_DATA);
// Return pin mask
return (1 << (pin & 0x07));
}
// Set gpio object pin direction
void gpio_dir(gpio_t *obj, PinDirection direction)
{
// Set direction
switch (direction) {
case PIN_INPUT:
pin_function(obj->pin, PIN_INPUT);
break;
case PIN_OUTPUT:
pin_function(obj->pin, PIN_OUTPUT);
break;
case PIN_INOUT:
pin_function(obj->pin, PIN_INOUT);
break;
default:
error("Invalid direction\n");
break;
}
}
// Write gpio object pin data
void gpio_write(gpio_t *obj, int value)
{
int port = 0;
uint8_t bit = 0;
uint32_t base = 0;
// Calculate port and pin position
port = PIN_PORT(obj->pin);
bit = PIN_POS(obj->pin);
base = BITBAND_PORT_BASE(port);
base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA);
if (value == GPIO_PIN_SET) {
BITBAND_PORT_SET(base, bit);
} else if (value == GPIO_PIN_RESET) {
BITBAND_PORT_CLR(base, bit);
} else {
error("Invalid value\n");
}
}
// Read gpio object pin data
int gpio_read(gpio_t *obj)
{
int port = 0;
uint8_t bit = 0;
uint32_t base = 0;
uint32_t val = 0;
int BitValue = 0;
// Calculate port and pin position
port = PIN_PORT(obj->pin);
bit = PIN_POS(obj->pin);
base = BITBAND_PORT_BASE(port);
base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA);
BITBAND_PORT_READ(val, base, bit);
if (val == GPIO_PIN_RESET) {
BitValue = GPIO_PIN_RESET;
} else {
BitValue = GPIO_PIN_SET;
}
return (BitValue);
}

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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __GPIO_INCLUDE_H
#define __GPIO_INCLUDE_H
#include <stdint.h>
#include <stdbool.h>
#include "TMPM3HQ.h"
#include "objects.h"
#include "serial_api.h"
#include "txz_driver_def.h"
enum BitMode {
GPIO_PIN_RESET = 0,
GPIO_PIN_SET,
};
enum PortFunction {
GPIO_Mode_DATA = 0x0, // 0x0: PxDATA
GPIO_Mode_CR = 0x04, // 0x4: PxCR
GPIO_Mode_FR1 = 0x08, // 0x8: PxFR1
GPIO_Mode_FR2 = 0x0C, // 0xC: PxFR2
GPIO_Mode_FR3 = 0x10, // 0x10: PxFR3
GPIO_Mode_FR4 = 0x14, // 0x14: PxFR4
GPIO_Mode_FR5 = 0x18, // 0x18: PxFR5
GPIO_Mode_FR6 = 0x1C, // 0x1C: PxFR6
GPIO_Mode_FR7 = 0x20, // 0x20: PxFR7
GPIO_Mode_OD = 0x28, // 0x28: PxOD
GPIO_Mode_PUP = 0x2C, // 0x2C: PxPUP
GPIO_Mode_PDN = 0x30, // 0x30: PxPDN
GPIO_Mode_IE = 0x38 // 0x38: PxIE
};
// GPIO
#define PORT_BASE (0x400C0000UL) // Port Register Base Adress
#define BITBAND_PORT_OFFSET (0x0000100UL) // Port Register Offset Value
#define BITBAND_PORT_BASE(gr) (PORT_BASE + (uint32_t)((BITBAND_PORT_OFFSET) * (gr)) ) // Operational target Port Adress
#define BITBAND_PORT_MODE_BASE(base, pinmode) ((uint32_t)(base) + (uint32_t)(pinmode) ) // Operational target Control Register Adress
#define BITBAND_PORT_SET(base, bitnum) (*((__IO uint32_t *)base) |= (uint32_t)(0x0000001UL<< bitnum)) // Target Pin Bit set
#define BITBAND_PORT_CLR(base, bitnum) (*((__IO uint32_t *)base) &= ~((uint32_t)(0x0000001UL<< bitnum))) // Target Pin Bit clear
#define BITBAND_PORT_READ(val, base, bitnum) val = ((*((__IO uint32_t *)base) & (uint32_t)(0x0000001UL<< bitnum)) >> bitnum) // Target Pin Bit read
#define GPIO_DATA PIN_DATA(0, 2)
#define CHANNEL_NUM 32
#define PORT_PIN_NUM 8
#define PIN_PORT(X) (((uint32_t)(X) >> 3) & 0x1F)
#define PIN_POS(X) ((uint32_t)(X) & 0x7)
// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction
#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16)| ((DIR) << 0))
#define PIN_FUNC(X) (((X) & 0xFFFF0000) >> 16)
#define PIN_DIR(X) ((X) & 0xFFFF)
// SPI
#define TIMEOUT 1000
#define INITIAL_SPI_FREQ 1000000
// I2C
#define I2CxCR2_I2CM_ENABLE ((uint32_t)0x00000080)
#define I2CxCR2_SWRES_10 ((uint32_t)0x00000002)
#define I2CxCR2_SWRES_01 ((uint32_t)0x00000001)
#define I2CxCR2_START_CONDITION ((uint32_t)0x000000F8)
#define I2CxCR2_STOP_CONDITION ((uint32_t)0x000000D8)
#define I2CxCR2_INIT ((uint32_t)0x00000008)
#define I2CxCR2_PIN_CLEAR ((uint32_t)0x00000010)
#define I2CxCR2_TRX ((uint32_t)0x00000040)
#define I2CxST_I2C ((uint32_t)0x00000001)
#define I2CxST_CLEAR ((uint32_t)0x0000000F)
#define I2CxCR1_ACK ((uint32_t)0x00000010)
#define I2CxSR_BB ((uint32_t)0x00000020)
#define I2CxSR_LRB ((uint32_t)0x00000001)
#define I2CxOP_RSTA ((uint32_t)0x00000008)
#define I2CxOP_SREN ((uint32_t)0x00000002)
#define I2CxOP_MFACK ((uint32_t)0x00000001)
#define I2CxOP_INIT ((uint32_t)0x00000084)
#define I2CxIE_CLEAR ((uint32_t)0x00000000)
#define I2CxPRS_PRCK ((uint32_t)0x0000000F)
#define I2CxDBR_DB_MASK ((uint32_t)0x000000FF)
#define I2CxOP_SLAVE_INIT ((uint32_t)0x00000084)
#define I2CAR_SA_MASK ((uint32_t)0x000000FE)
#define I2CxSR_TRX ((uint32_t)0x00000040)
#define I2CxOP_SAST ((uint32_t)0x00000020)
#define I2CxIE_INTI2C ((uint32_t)0x00000001)
#define I2C_NO_DATA (0)
#define I2C_READ_ADDRESSED (1)
#define I2C_WRITE_ADDRESSED (3)
#define I2C_ACK (1)
#define I2C_TIMEOUT (100000)
// DAC
#define DAC_START ((uint32_t)0x00000001)
#define DAC_STOP ((uint32_t)0x00000000)
// ADC
#define ADC_12BIT_RANGE 0xFFF
#define ADC_SCLK_1 ((uint32_t)0x00000000)
#define ADxMOD0_RCUT_NORMAL ((uint32_t)0x00000000)
#define ADxMOD0_DACON_ON ((uint32_t)0x00000001)
#define ADxTSETn_ENINT_DISABLE ((uint32_t)0x00000000)
#define ADxTSETn_TRGS_SGL ((uint32_t)0x00000040)
#define ADxCR1_CNTDMEN_DISABLE ((uint32_t)0x00000000)
#define ADxCR1_SGLDMEN_DISABLE ((uint32_t)0x00000000)
#define ADxCR1_TRGDMEN_DISABLE ((uint32_t)0x00000000)
#define ADxCR1_TRGEN_DISABLE ((uint32_t)0x00000000)
#define ADxCR0_ADEN_DISABLE ((uint32_t)0x00000000)
#define ADxCR0_ADEN_ENABLE ((uint32_t)0x00000080)
#define ADxCR0_SGL_ENABLE ((uint32_t)0x00000002)
#define ADxCR0_CNT_DISABLE ((uint32_t)0x00000000)
#define ADxST_SNGF_IDLE ((uint32_t)0x00000000)
#define ADxST_SNGF_RUN ((uint32_t)0x00000004)
#define ADxREGn_ADRFn_MASK ((uint32_t)0x00000001)
#define ADxREGn_ADRFn_ON ((uint32_t)0x00000001)
#define ADxREGn_ADRn_MASK ((uint32_t)0x0000FFF0)
#define ADC_SAMPLING_PERIOD_3V ((uint32_t)0x00000008)
#define ADC_MOD2_TMPM3Hx ((uint32_t)0x00000300)
#define ADC_MOD1_AVDD5_3V ((uint32_t)0x0000B001)
// Timer & PWM
#define T32A_INT_MASK ((uint32_t)0x0000000F)
#define T32A_MODE_32 ((uint32_t)0x00000001)
#define T32A_PRSCLx_32 ((uint32_t)0x30000000)
#define T32A_IMUFx_MASK_REQ ((uint32_t)0x00000008)
#define T32A_IMOFx_MASK_REQ ((uint32_t)0x00000004)
#define T32A_COUNT_STOP ((uint32_t)0x00000004)
#define T32A_COUNT_START ((uint32_t)0x00000002)
#define T32A_RUN_ENABLE ((uint32_t)0x00000001)
#define T32A_DBG_HALT_STOP ((uint32_t)0x00000002)
#define T32A_COUNT_DONT_START ((uint32_t)0x00000000)
#define T32A_RUN_DISABLE ((uint32_t)0x00000000)
#define T32A_WBF_ENABLE ((uint32_t)0x00100000)
#define T32A_RELOAD_TREGx ((uint32_t)0x00000700)
#define T32A_OCRCMPx0_SET ((uint32_t)0x00000001)
#define T32A_OCRCMPx1_CLR ((uint32_t)0x00000008)
#define T32A_OCR_DISABLE ((uint32_t)0x00000000)
#define DEFAULT_PERIOD 0.02f // 20ms
#define DEFAULT_CLOCK_DIVISION 32
#define MAX_COUNTER_16B 0xFFFF
// UART
#define UART_ENABLE_RX ((uint32_t)0x00000001)
#define UART_ENABLE_TX ((uint32_t)0x00000002)
#define UARTxSWRST_SWRSTF_MASK ((uint32_t)0x00000080)
#define UARTxSWRST_SWRSTF_RUN ((uint32_t)0x00000080)
#define UARTxSWRST_SWRST_10 ((uint32_t)0x00000002)
#define UARTxSWRST_SWRST_01 ((uint32_t)0x00000001)
#define UARTxFIFOCLR_TFCLR_CLEAR ((uint32_t)0x00000002)
#define UARTxFIFOCLR_RFCLR_CLEAR ((uint32_t)0x00000001)
#define UART_PLESCALER_1 ((uint32_t)0x00000000)
#define UART_DIVISION_ENABLE ((uint32_t)0x00800000)
#define UART_TX_INT_ENABLE ((uint32_t)0x00000040)
#define UART_RX_INT_ENABLE ((uint32_t)0x00000010)
#define UART_RX_FIFO_FILL_LEVEL ((uint32_t)0x00000100)
#define UART_RANGE_K_MIN ((uint32_t)0x00000000)
#define UART_RANGE_K_MAX ((uint32_t)0x0000003F)
#define UART_RANGE_N_MIN ((uint32_t)0x00000001)
#define UART_RANGE_N_MAX ((uint32_t)0x0000FFFF)
#define UART_NUM 6
typedef struct {
uint32_t ken; // Enable/Disable Division Definition
uint32_t brk; // Division Value K
uint32_t brn; // Division Value N
} uart_boudrate_t;
// Sleep
#define CG_STBY_MODE_IDLE 0x0
#define CG_STBY_MODE_STOP1 0x1
#define EXTERNEL_OSC_MASK 0xFFFFFFF9
#define IHOSC_CFG_WARM_UP_TIME ((uint64_t)(5000))
#define IHOSC_CFG_CLOCK ((uint64_t)(10000000))
#define CGWUPHCR_WUPT_HIGH_MASK ((uint32_t)0xFFF00000)
#endif // __GPIO_INCLUDE_H

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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_irq_api.h"
#include "mbed_error.h"
#include "PeripheralNames.h"
#include "pinmap.h"
#include "gpio_include.h"
#include "mbed_critical.h"
const PinMap PinMap_GPIO_IRQ[] = {
{PC0, GPIO_IRQ_00, PIN_DATA(0, 0)},
{PC1, GPIO_IRQ_01, PIN_DATA(0, 0)},
{PC2, GPIO_IRQ_02, PIN_DATA(0, 0)},
{PB1, GPIO_IRQ_03, PIN_DATA(0, 0)},
{PJ4, GPIO_IRQ_04, PIN_DATA(0, 0)},
{PK1, GPIO_IRQ_05, PIN_DATA(0, 0)},
{PH3, GPIO_IRQ_06, PIN_DATA(0, 0)},
{PA6, GPIO_IRQ_07, PIN_DATA(0, 0)},
{PL3, GPIO_IRQ_08, PIN_DATA(0, 0)},
{PM2, GPIO_IRQ_09, PIN_DATA(0, 0)},
{PN3, GPIO_IRQ_10, PIN_DATA(0, 0)},
{PA7, GPIO_IRQ_11, PIN_DATA(0, 0)},
{PL4, GPIO_IRQ_12, PIN_DATA(0, 0)},
{PK7, GPIO_IRQ_13, PIN_DATA(0, 0)},
{PP3, GPIO_IRQ_14, PIN_DATA(0, 0)},
{PM6, GPIO_IRQ_15, PIN_DATA(0, 0)},
{PB7, GPIO_IRQ_16, PIN_DATA(0, 0)},
{PV2, GPIO_IRQ_17_18, PIN_DATA(0, 0)},
{PH4, GPIO_IRQ_19_22, PIN_DATA(0, 0)},
{PT0, GPIO_IRQ_23_26, PIN_DATA(0, 0)},
{PG2, GPIO_IRQ_27_28, PIN_DATA(0, 0)},
{PT7, GPIO_IRQ_29, PIN_DATA(0, 0)},
{PU0, GPIO_IRQ_30_31, PIN_DATA(0, 0)},
{NC, NC, 0}
};
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL};
static void SetSTBYReleaseINTSrc(cg_intsrc, cg_intactivestate, FunctionalState);
static cg_intactivestate CurrentState;
static void INT_IRQHandler(PinName pin, uint32_t index);
// Initialize gpio IRQ pin
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
{
uint8_t bit = 0;
uint32_t port_base = 0;
// Get gpio interrupt ID
obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ);
// Disable interrupt by CPU
core_util_critical_section_enter();
// Calculate port and pin position
obj->port = (PortName)PIN_PORT(pin);
obj->pin = pin;
bit = PIN_POS(pin);
port_base = BITBAND_PORT_BASE(obj->port);
port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA);
BITBAND_PORT_CLR(port_base, bit);
// Enable gpio interrupt function
pinmap_pinout(pin, PinMap_GPIO_IRQ);
// Get GPIO irq source
switch (obj->irq_id) {
case GPIO_IRQ_00:
obj->irq_src = cg_int_src_01;
break;
case GPIO_IRQ_01:
obj->irq_src = cg_int_src_02;
break;
case GPIO_IRQ_02:
obj->irq_src = cg_int_src_03;
break;
case GPIO_IRQ_03:
obj->irq_src = cg_int_src_04;
break;
case GPIO_IRQ_04:
obj->irq_src = cg_int_src_05;
break;
case GPIO_IRQ_05:
obj->irq_src = cg_int_src_06;
break;
case GPIO_IRQ_06:
obj->irq_src = cg_int_src_07;
break;
case GPIO_IRQ_07:
obj->irq_src = cg_int_src_08;
break;
case GPIO_IRQ_08:
obj->irq_src = cg_int_src_09;
break;
case GPIO_IRQ_09:
obj->irq_src = cg_int_src_0a;
break;
case GPIO_IRQ_10:
obj->irq_src = cg_int_src_0b;
break;
case GPIO_IRQ_11:
obj->irq_src = cg_int_src_0c;
break;
case GPIO_IRQ_12:
obj->irq_src = cg_int_src_0d;
break;
case GPIO_IRQ_13:
obj->irq_src = cg_int_src_0e;
break;
case GPIO_IRQ_14:
obj->irq_src = cg_int_src_0f;
break;
case GPIO_IRQ_15:
obj->irq_src = cg_int_src_10;
break;
case GPIO_IRQ_16:
obj->irq_src = cg_int_src_11;
break;
case GPIO_IRQ_17_18:
obj->irq_src = cg_int_src_12;
break;
case GPIO_IRQ_19_22:
obj->irq_src = cg_int_src_14;
break;
case GPIO_IRQ_23_26:
obj->irq_src = cg_int_src_18;
break;
case GPIO_IRQ_27_28:
obj->irq_src = cg_int_src_1c;
break;
case GPIO_IRQ_29:
obj->irq_src = cg_int_src_1e;
break;
case GPIO_IRQ_30_31:
obj->irq_src = cg_int_src_1f;
break;
default:
break;
}
// Save irq handler
hal_irq_handler[obj->irq_src] = handler;
// Save irq id
channel_ids[obj->irq_src] = id;
// Initialize interrupt event as both edges detection
obj->event = cg_int_active_state_both_edges;
CurrentState = cg_int_active_state_both_edges;
// Set interrupt event and enable INTx clear
SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate)obj->event, ENABLE);
// Clear gpio pending interrupt
NVIC_ClearPendingIRQ((IRQn_Type) obj->irq_id);
core_util_critical_section_exit();
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
// Clear gpio_irq
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
// Reset interrupt handler
hal_irq_handler[obj->irq_src] = NULL;
// Reset interrupt id
channel_ids[obj->irq_src] = 0;
}
// Set interrupt event of gpio_irq object
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
uint8_t bit = 0;
uint32_t port_base = 0;
//Disable GPIO interrupt on obj
gpio_irq_disable(obj);
if (enable) {
// Get gpio interrupt event
if (event == IRQ_RISE) {
if ((obj->event == cg_int_active_state_falling) || (obj->event == cg_int_active_state_both_edges)) {
obj->event = cg_int_active_state_both_edges;
} else {
obj->event = cg_int_active_state_rising;
}
} else if (event == IRQ_FALL) {
if ((obj->event == cg_int_active_state_rising) || (obj->event == cg_int_active_state_both_edges)) {
obj->event = cg_int_active_state_both_edges;
} else {
obj->event = cg_int_active_state_falling;
}
} else {
error("Not supported event\n");
}
} else {
// Get gpio interrupt event
if (event == IRQ_RISE) {
if ((obj->event == cg_int_active_state_rising) || (obj->event == cg_int_active_state_invalid)) {
obj->event = cg_int_active_state_invalid;
} else {
obj->event = cg_int_active_state_falling;
}
} else if (event == IRQ_FALL) {
if ((obj->event == cg_int_active_state_falling) || (obj->event == cg_int_active_state_invalid)) {
obj->event = cg_int_active_state_invalid;
} else {
obj->event = cg_int_active_state_rising;
}
} else {
error("Not supported event\n");
}
}
CurrentState = obj->event;
// Calculate port and pin position
bit = PIN_POS(obj->pin);
port_base = BITBAND_PORT_BASE(obj->port);
port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA);
if (obj->event != cg_int_active_state_invalid ) {
// Set interrupt event and enable INTx clear
SetSTBYReleaseINTSrc(obj->irq_src, (cg_intactivestate) obj->event, ENABLE);
BITBAND_PORT_CLR(port_base, bit);
} else {
BITBAND_PORT_SET(port_base, bit);
}
//Enable GPIO interrupt on obj
gpio_irq_enable(obj);
}
// Enable gpio_irq object
void gpio_irq_enable(gpio_irq_t *obj)
{
// Clear and Enable gpio_irq object
NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
NVIC_EnableIRQ((IRQn_Type)obj->irq_id);
}
// Disable gpio_irq object
void gpio_irq_disable(gpio_irq_t *obj)
{
// Disable gpio_irq object
NVIC_DisableIRQ((IRQn_Type)obj->irq_id);
}
static void INT_IRQHandler(PinName pin, uint32_t index)
{
int port = 0;
uint8_t bit = 0;
uint32_t data = 0;
uint32_t port_base = 0;
// Calculate port and pin position
port = PIN_PORT(pin);
bit = PIN_POS(pin);
// Clear interrupt request
SetSTBYReleaseINTSrc((cg_intsrc)(cg_int_src_01 + index), CurrentState, DISABLE);
port_base = BITBAND_PORT_BASE(port);
port_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_DATA);
BITBAND_PORT_READ(data, port_base, bit);
switch (data) {
// Falling edge detection
case 0:
hal_irq_handler[index](channel_ids[index], IRQ_FALL);
break;
// Rising edge detection
case 1:
hal_irq_handler[index](channel_ids[index], IRQ_RISE);
break;
default:
break;
}
// Clear gpio pending interrupt
NVIC_ClearPendingIRQ((IRQn_Type)(cg_int_src_01 + index));
// Enable interrupt request
SetSTBYReleaseINTSrc((cg_intsrc)(cg_int_src_01 + index), CurrentState, ENABLE);
}
void INT00_IRQHandler(void)
{
INT_IRQHandler(PC0, 0);
}
void INT01_IRQHandler(void)
{
INT_IRQHandler(PC1, 1);
}
void INT02_IRQHandler(void)
{
INT_IRQHandler(PC2, 2);
}
void INT03_IRQHandler(void)
{
INT_IRQHandler(PB1, 3);
}
void INT04_IRQHandler(void)
{
INT_IRQHandler(PJ4, 4);
}
void INT05_IRQHandler(void)
{
INT_IRQHandler(PK1, 5);
}
void INT06_IRQHandler(void)
{
INT_IRQHandler(PH3, 6);
}
void INT07_IRQHandler(void)
{
INT_IRQHandler(PA6, 7);
}
void INT08_IRQHandler(void)
{
INT_IRQHandler(PL3, 8);
}
void INT09_IRQHandler(void)
{
INT_IRQHandler(PM2, 9);
}
void INT10_IRQHandler(void)
{
INT_IRQHandler(PN3, 10);
}
void INT11_IRQHandler(void)
{
INT_IRQHandler(PA7, 11);
}
void INT12_IRQHandler(void)
{
INT_IRQHandler(PL4, 12);
}
void INT13_IRQHandler(void)
{
INT_IRQHandler(PK7, 13);
}
void INT14_IRQHandler(void)
{
INT_IRQHandler(PP3, 14);
}
void INT15_IRQHandler(void)
{
INT_IRQHandler(PM6, 15);
}
void INT16_IRQHandler(void)
{
INT_IRQHandler(PB7, 16);
}
void INT17_18_IRQHandler(void)
{
INT_IRQHandler(PV2, 17);
}
void INT19_22_IRQHandler(void)
{
INT_IRQHandler(PH4, 19);
}
void INT23_26_IRQHandler(void)
{
INT_IRQHandler(PT0, 23);
}
void INT27_28_IRQHandler(void)
{
INT_IRQHandler(PG2, 27);
}
void INT29_IRQHandler(void)
{
INT_IRQHandler(PT7, 29);
}
void INT30_31_IRQHandler(void)
{
INT_IRQHandler(PU0, 30);
}
static void SetSTBYReleaseINTSrc(cg_intsrc intsource, cg_intactivestate ActiveState, FunctionalState NewState)
{
__IO uint8_t *p_imc;
if (intsource < 3U || intsource == 13U) {
if (intsource == 13U) {
intsource = (cg_intsrc)3U;
}
p_imc = (__IO uint8_t *)(&TSB_IA->IMC00 + (intsource));
*p_imc = (uint8_t)(0xC0 | ActiveState | NewState);
} else {
if (intsource > 13U) {
intsource -= 4;
} else {
intsource -= 3;
}
p_imc = (__IO uint8_t *)(&TSB_IB->IMC066 + (intsource));
*p_imc = (uint8_t)(0xC0 | ActiveState | NewState);
}
// Dummy read is need
{
__IO uint8_t imc = *p_imc;
}
}

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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_BIT_VALUE_1 ((uint8_t)0x01)
#define GPIO_BIT_VALUE_0 ((uint8_t)0x00)
#define GPIO_BIT_ALL ((uint8_t)0xFF)
typedef enum {
cg_int_src_01 = 0U,
cg_int_src_02,
cg_int_src_03,
cg_int_src_04,
cg_int_src_05,
cg_int_src_06,
cg_int_src_07,
cg_int_src_08,
cg_int_src_09,
cg_int_src_0a,
cg_int_src_0b,
cg_int_src_0c,
cg_int_src_0d,
cg_int_src_0e,
cg_int_src_0f,
cg_int_src_10,
cg_int_src_11,
cg_int_src_12,
cg_int_src_13,
cg_int_src_14,
cg_int_src_15,
cg_int_src_16,
cg_int_src_17,
cg_int_src_18,
cg_int_src_19,
cg_int_src_1a,
cg_int_src_1b,
cg_int_src_1c,
cg_int_src_1d,
cg_int_src_1e,
cg_int_src_1f,
cg_int_src_20
} cg_intsrc;
typedef enum {
cg_int_active_state_l = 0x00U,
cg_int_active_state_h = 0x02U,
cg_int_active_state_falling = 0x04U,
cg_int_active_state_rising = 0x06U,
cg_int_active_state_both_edges = 0x08U,
cg_int_active_state_invalid = 0x0AU
} cg_intactivestate;
typedef struct {
PinName pin;
uint32_t mask;
PortName port;
} gpio_t;
struct gpio_irq_s {
uint32_t mask;
PortName port;
PinName pin;
uint32_t irq_id;
cg_intactivestate event;
cg_intsrc irq_src;
};
static inline int gpio_is_connected(const gpio_t *obj)
{
return (obj->pin != (PinName)NC);
}
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "i2c_api.h"
#include "mbed_error.h"
#include "pinmap.h"
#include "gpio_include.h"
static const PinMap PinMap_I2C_SDA[] = {
{PC1, I2C_0, PIN_DATA(1, 2)},
{PA5, I2C_1, PIN_DATA(1, 2)},
{PL1, I2C_2, PIN_DATA(3, 2)},
{PT0, I2C_3, PIN_DATA(1, 2)},
{NC, NC, 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{PC0, I2C_0, PIN_DATA(1, 2)},
{PA4, I2C_1, PIN_DATA(1, 2)},
{PL0, I2C_2, PIN_DATA(3, 2)},
{PT1, I2C_3, PIN_DATA(1, 2)},
{NC, NC, 0}
};
// Clock setting structure definition
typedef struct {
uint32_t sck;
uint32_t prsck;
} I2C_clock_setting_t;
// SCK Divider value table
static const uint32_t I2C_SCK_DIVIDER_TBL[8] = {
20, 24, 32, 48, 80, 144, 272, 528
};
I2C_clock_setting_t clk;
static uint32_t start_flag = 0;
static int32_t wait_status(i2c_t *p_obj);
static void i2c_start_bit(i2c_t *obj);
// Initialize the I2C peripheral. It sets the default parameters for I2C
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
MBED_ASSERT(obj != NULL);
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
MBED_ASSERT((int)i2c_name != NC);
switch (i2c_name) {
case I2C_0:
TSB_CG_FSYSENB_IPENB11 = ENABLE;
TSB_CG_FSYSENA_IPENA02 = ENABLE;
obj->i2c = TSB_I2C0;
break;
case I2C_1:
TSB_CG_FSYSENB_IPENB12 = ENABLE;
TSB_CG_FSYSENA_IPENA00 = ENABLE;
obj->i2c = TSB_I2C1;
break;
case I2C_2:
TSB_CG_FSYSENB_IPENB13 = ENABLE;
TSB_CG_FSYSENA_IPENA10 = ENABLE;
obj->i2c = TSB_I2C2;
break;
case I2C_3:
TSB_CG_FSYSENB_IPENB14 = ENABLE;
TSB_CG_FSYSENA_IPENA15 = ENABLE;
obj->i2c = TSB_I2C3;
break;
default:
error("I2C is not available");
break;
}
pinmap_pinout(sda, PinMap_I2C_SDA);
pin_mode(sda, OpenDrain);
pin_mode(sda, PullUp);
pinmap_pinout(scl, PinMap_I2C_SCL);
pin_mode(scl, OpenDrain);
pin_mode(scl, PullUp);
i2c_reset(obj);
i2c_frequency(obj, 100000);
obj->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR |
I2CxCR2_INIT);
obj->i2c->OP = I2CxOP_INIT;
obj->i2c->IE = I2CxIE_CLEAR;
}
// Configure the I2C frequency
void i2c_frequency(i2c_t *obj, int hz)
{
uint64_t sck;
uint64_t tmp_sck;
uint64_t prsck;
uint64_t tmp_prsck;
uint64_t fscl;
uint64_t tmp_fscl;
uint64_t fx;
SystemCoreClockUpdate();
if (hz <= 1000000) {
sck = tmp_sck = 0;
prsck = tmp_prsck = 1;
fscl = tmp_fscl = 0;
for (prsck = 1; prsck <= 32; prsck++) {
fx = ((uint64_t)SystemCoreClock / prsck);
if ((fx < 20000000U) && (fx > 6666666U)) {
for (sck = 0; sck <= 7; sck++) {
fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]);
if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) {
tmp_fscl = fscl;
tmp_sck = sck;
tmp_prsck = (prsck < 32) ? prsck : 0;
}
}
}
}
clk.sck = (uint32_t)tmp_sck;
clk.prsck = (tmp_prsck < 32) ? (uint32_t)(tmp_prsck - 1) : 0;
}
obj->i2c->CR1 = (I2CxCR1_ACK | clk.sck);
obj->i2c->PRS = (I2CxPRS_PRCK & clk.prsck);
}
int i2c_start(i2c_t *obj)
{
start_flag = 1; // Start Condition
return 0;
}
int i2c_stop(i2c_t *obj)
{
uint32_t timeout = I2C_TIMEOUT;
obj->i2c->CR2 = I2CxCR2_STOP_CONDITION;
while ((obj->i2c->SR & I2CxSR_BB) == I2CxSR_BB) {
if (timeout == 0) {
break;
}
timeout--;
}
return 0;
}
void i2c_reset(i2c_t *obj)
{
obj->i2c->CR2 = I2CxCR2_SWRES_10;
obj->i2c->CR2 = I2CxCR2_SWRES_01;
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
int32_t result = 0;
int32_t count = 0;
int32_t pdata = 0;
if (length > 0) {
start_flag = 1; // Start Condition
if (i2c_byte_write(obj, (int32_t)((uint32_t)address | 1U)) == I2C_ACK) {
while (count < length) {
pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1));
if (pdata < 0) {
break;
}
data[count++] = (uint8_t)pdata;
}
result = count;
} else {
stop = 1;
result = I2C_ERROR_NO_SLAVE;
}
if (stop) { // Stop Condition
i2c_stop(obj);
}
}
return result;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
int32_t result = 0;
int32_t count = 0;
start_flag = 1; // Start Condition
if (i2c_byte_write(obj, address) == I2C_ACK) {
while (count < length) {
if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) {
break;
}
}
result = count;
} else {
stop = 1;
result = I2C_ERROR_NO_SLAVE;
}
if (stop) { // Stop Condition
i2c_stop(obj);
}
return result;
}
int i2c_byte_read(i2c_t *obj, int last)
{
int32_t result = 0;
obj->i2c->ST = I2CxST_CLEAR;
if (last) {
obj->i2c->OP |= I2CxOP_MFACK;
} else {
obj->i2c->OP &= ~I2CxOP_MFACK;
}
obj->i2c->DBR = (0 & I2CxDBR_DB_MASK);
if (wait_status(obj) < 0) {
result = -1;
} else {
result = (int32_t)(obj->i2c->DBR & I2CxDBR_DB_MASK);
}
return result;
}
int i2c_byte_write(i2c_t *obj, int data)
{
int32_t result = 0;
obj->i2c->ST = I2CxST_CLEAR;
if (start_flag == 1) {
obj->i2c->DBR = (data & I2CxDBR_DB_MASK);
i2c_start_bit(obj);
start_flag = 0;
} else {
obj->i2c->DBR = (data & I2CxDBR_DB_MASK);
}
if (wait_status(obj) < 0) {
return -1;
}
if (!((obj->i2c->SR & I2CxSR_LRB) == I2CxSR_LRB)) {
result = 1;
} else {
result = 0;
}
return result;
}
static void i2c_start_bit(i2c_t *obj) // Send START command
{
uint32_t opreg = 0;
opreg = obj->i2c->OP;
opreg &= ~(I2CxOP_RSTA | I2CxOP_SREN);
if ((obj->i2c->SR & I2CxSR_BB)) {
opreg |= I2CxOP_SREN;
}
obj->i2c->OP = opreg;
obj->i2c->CR2 |= I2CxCR2_START_CONDITION;
}
static int32_t wait_status(i2c_t *p_obj)
{
volatile int32_t timeout;
timeout = I2C_TIMEOUT;
while (!((p_obj->i2c->ST & I2CxST_I2C) == I2CxST_I2C)) {
if ((timeout--) == 0) {
return (-1);
}
}
return 0;
}
void i2c_slave_mode(i2c_t *obj, int enable_slave)
{
if (enable_slave) {
obj->i2c->OP = I2CxOP_SLAVE_INIT;
obj->i2c->CR1 = (I2CxCR1_ACK | clk.sck);
obj->i2c->CR2 = (I2CxCR2_INIT | I2CxCR2_PIN_CLEAR);
obj->i2c->PRS = (I2CxPRS_PRCK & clk.prsck);
obj->i2c->AR = (obj->address & I2CAR_SA_MASK);
obj->i2c->IE = I2CxIE_INTI2C;
} else {
i2c_reset(obj);
obj->i2c->CR2 = (I2CxCR2_I2CM_ENABLE | I2CxCR2_TRX | I2CxCR2_PIN_CLEAR |
I2CxCR2_INIT);
obj->i2c->OP = I2CxOP_INIT;
obj->i2c->CR1 = (I2CxCR1_ACK | clk.sck);
obj->i2c->PRS = (I2CxPRS_PRCK & clk.prsck);
NVIC_DisableIRQ(obj->IRQn);
NVIC_ClearPendingIRQ(obj->IRQn);
obj->i2c->ST = I2CxST_CLEAR;
}
}
int i2c_slave_receive(i2c_t *obj)
{
int32_t result = I2C_NO_DATA;
if ((obj->i2c->ST & I2CxST_I2C) && (obj->i2c->OP & I2CxOP_SAST)) {
if ((obj->i2c->SR & I2CxSR_TRX) == I2CxSR_TRX) {
result = I2C_READ_ADDRESSED;
} else {
result = I2C_WRITE_ADDRESSED;
}
}
return (result);
}
int i2c_slave_read(i2c_t *obj, char *data, int length)
{
int32_t count = 0;
while (count < length) {
int32_t pdata = i2c_byte_read(obj, ((count < (length - 1)) ? 0 : 1));
if ((obj->i2c->SR & I2CxSR_TRX)) {
return (count);
} else {
if (pdata < 0) {
break;
}
data[count++] = (uint8_t)pdata;
}
}
i2c_slave_mode(obj,1);
return (count);
}
int i2c_slave_write(i2c_t *obj, const char *data, int length)
{
int32_t count = 0;
while (count < length) {
if (i2c_byte_write(obj, (int32_t)data[count++]) < I2C_ACK) {
break;
}
}
i2c_slave_mode(obj,1);
return (count);
}
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
{
obj->address = address & I2CAR_SA_MASK;
i2c_slave_mode(obj,1);
}

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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include <stddef.h>
#include "PortNames.h"
#include "PeripheralNames.h"
#include "txz_tspi.h"
#include "PinNames.h"
#include "TMPM3HQ.h"
#include "gpio_include.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
uint32_t BaudRate;
uint32_t DataBits;
uint32_t StopBits;
uint32_t Parity;
uint32_t Mode;
uint32_t FlowCtrl;
} uart_inittypedef_t;
struct port_s {
PortName port;
uint32_t mask;
};
typedef struct {
uint8_t PinDATA;
uint8_t PinCR;
uint8_t PinFR[7];
uint8_t PinOD;
uint8_t PinPUP;
uint8_t PinPDN;
uint8_t PinIE;
} gpio_regtypedef_t;
typedef struct {
__IO uint32_t DATA;
__IO uint32_t CR;
__IO uint32_t FR[7];
uint32_t RESERVED0[1];
__IO uint32_t OD;
__IO uint32_t PUP;
__IO uint32_t PDN;
uint32_t RESERVED1;
__IO uint32_t IE;
} TSB_Port_TypeDef;
struct serial_s {
PinName pin;
uint32_t index;
TSB_UART_TypeDef *UARTx;
uart_inittypedef_t uart_config;
};
struct analogin_s {
PinName pin;
ADCName adc;
TSB_AD_TypeDef *obj;
};
struct dac_s {
DACName dac;
TSB_DA_TypeDef *handler;
};
struct pwmout_s {
PinName pin;
TSB_T32A_TypeDef *channel;
uint16_t trailing_timing;
uint16_t leading_timing;
uint16_t divisor;
float period;
};
struct i2c_s {
uint32_t address;
IRQn_Type IRQn;
TSB_I2C_TypeDef *i2c;
};
struct spi_s {
tspi_t p_obj;
SPIName module;
uint8_t bits;
};
extern const gpio_regtypedef_t GPIO_SFRs[];
extern const uint32_t GPIO_Base[];
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

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/**
*******************************************************************************
* @file txz_driver_def.h
* @brief All common macro and definition for TXZ peripheral drivers
* @version V1.0.0.0
* $Date:: 2018-01-22 15:14:05 #$
*
* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
*
* (C)Copyright TOSHIBA MICROELECTRONICS CORPORATION 2017 All rights reserved
*******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __TXZ_DRIVER_DEF_H
#define __TXZ_DRIVER_DEF_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Periph_Driver Peripheral Driver
* @{
*/
/** @defgroup TXZ_DRIVER_DEF TXZ DRIVER DEF
* @brief All common macro and definition for TXZ peripheral drivers
* @{
*/
/** @defgroup Device_Header_Included Device Header Included
* @brief Include the Device header file of a Target.
* @{
*/
#include "TMPM3HQ.h" /*!< TMPM3HQ Group Header file. */
/**
* @}
*/ /* End of group Device_Header */
/** @defgroup TXZ_Exported_typedef TXZ Exported typedef
* @{
*/
typedef enum {
TXZ_SUCCESS = 0U,
TXZ_ERROR = 1U
} TXZ_Result;
typedef enum {
TXZ_BUSY = 0U,
TXZ_DONE = 1U
} TXZ_WorkState;
typedef enum {
TXZ_DISABLE = 0U,
TXZ_ENABLE = 1U
} TXZ_FunctionalState;
/**
* @}
*/ /* End of group TXZ_Exported_typedef */
/** @defgroup TXZ_Exported_macro TXZ Exported macro
* @{
*/
#define IS_TXZ_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define IS_POINTER_NOT_NULL(param) ((void*)(param)!=(void*)0)
/**
* @brief To report the name of the source file and source line number where the
* assert_param error has occurred, "DEBUG" must be defined. And detailed
* definition of assert_failed() is needed to be implemented, which can be
* done, for example, in the main.c file.
*/
#ifdef DEBUG
void assert_failed(char *file, int32_t line);
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__))
#else
#define assert_param(expr)
#endif /* DEBUG */
/**
* @}
*/ /* End of group TXZ_Exported_macro */
/**
* @}
*/ /* End of group Periph_Driver */
/**
* @}
*/ /* End of group TXZ_DRIVER_DEF */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __TXZ_DRIVER_DEF_H */

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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "gpio_include.h"
void pin_function(PinName pin, int function)
{
int port = 0;
uint8_t bit = 0;
uint8_t func = 0;
uint8_t dir = 0;
uint32_t port_base = 0;
uint32_t mode_base = 0;
// Assert that pin is valid
MBED_ASSERT(pin != NC);
// Calculate pin function and pin direction
func = PIN_FUNC(function);
dir = PIN_DIR(function);
// Calculate port and pin position
port = PIN_PORT(pin);
bit = PIN_POS(pin);
port_base = BITBAND_PORT_BASE(port);
// Initialization PxFR OFF
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7);
BITBAND_PORT_CLR(mode_base, bit);
// Initialize Input
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
BITBAND_PORT_SET(mode_base, bit);
switch (func) {
case 0:
break;
case 1:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR1);
break;
case 2:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR2);
break;
case 3:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR3);
break;
case 4:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR4);
break;
case 5:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR5);
break;
case 6:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR6);
break;
case 7:
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_FR7);
break;
default:
break;
}
if (func != 0) {
BITBAND_PORT_SET(mode_base, bit);
}
if (dir == PIN_OUTPUT) {
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
BITBAND_PORT_CLR(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
BITBAND_PORT_SET(mode_base, bit);
} else if (dir == PIN_INOUT) {
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_IE);
BITBAND_PORT_SET(mode_base, bit);
mode_base = BITBAND_PORT_MODE_BASE(port_base, GPIO_Mode_CR);
BITBAND_PORT_SET(mode_base, bit);
}
}
void pin_mode(PinName pin, PinMode mode)
{
int port = 0;
uint8_t bit = 0;
uint8_t val = 0;
// Assert that pin is valid
MBED_ASSERT(pin != NC);
// Check if function is in range
if (mode > OpenDrain) {
return;
}
// Calculate port and pin position
port = PIN_PORT(pin);
bit = PIN_POS(pin);
val = (1 << bit);
switch (port) {
case PortA:
if (mode == OpenDrain) TSB_PA->OD |= val;
else if (mode == PullUp) TSB_PA->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PA->PDN |= val;
break;
case PortB:
if (mode == OpenDrain) TSB_PB->OD |= val;
else if (mode == PullUp) TSB_PB->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PB->PDN |= val;
break;
case PortC:
if (mode == OpenDrain) TSB_PC->OD |= val;
else if (mode == PullUp) TSB_PC->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PC->PDN |= val;
break;
case PortD:
if (mode == OpenDrain) TSB_PD->OD |= val;
else if (mode == PullUp) TSB_PD->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PD->PDN |= val;
break;
case PortE:
if (mode == OpenDrain) TSB_PE->OD |= val;
else if (mode == PullUp) TSB_PE->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PE->PDN |= val;
break;
case PortF:
if (mode == OpenDrain) TSB_PF->OD |= val;
else if (mode == PullUp) TSB_PF->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PF->PDN |= val;
break;
case PortG:
if (mode == OpenDrain) TSB_PG->OD |= val;
else if (mode == PullUp) TSB_PG->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PG->PDN |= val;
break;
case PortH:
if (mode == PullDown) TSB_PH->PDN |= val;
break;
case PortJ:
if (mode == OpenDrain) TSB_PJ->OD |= val;
else if (mode == PullUp) TSB_PJ->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PJ->PDN |= val;
break;
case PortK:
if (mode == OpenDrain) TSB_PK->OD |= val;
else if (mode == PullUp) TSB_PK->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PK->PDN |= val;
break;
case PortL:
if (mode == OpenDrain) TSB_PL->OD |= val;
else if (mode == PullUp) TSB_PL->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PL->PDN |= val;
break;
case PortM:
if (mode == OpenDrain) TSB_PM->OD |= val;
else if (mode == PullUp) TSB_PM->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PM->PDN |= val;
break;
case PortN:
if (mode == OpenDrain) TSB_PN->OD |= val;
else if (mode == PullUp) TSB_PN->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PN->PDN |= val;
break;
case PortP:
if (mode == OpenDrain) TSB_PP->OD |= val;
else if (mode == PullUp) TSB_PP->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PP->PDN |= val;
break;
case PortR:
if (mode == OpenDrain) TSB_PR->OD |= val;
else if (mode == PullUp) TSB_PR->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PR->PDN |= val;
break;
case PortT:
if (mode == OpenDrain) TSB_PT->OD |= val;
else if (mode == PullUp) TSB_PT->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PT->PDN |= val;
break;
case PortU:
if (mode == OpenDrain) TSB_PU->OD |= val;
else if (mode == PullUp) TSB_PU->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PU->PDN |= val;
break;
case PortV:
if (mode == OpenDrain) TSB_PV->OD |= val;
else if (mode == PullUp) TSB_PV->PUP |= val;
else if (mode == PullDown || mode == PullDefault) TSB_PV->PDN |= val;
break;
default:
break;
}
}

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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_include.h"
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
uint8_t i = 0;
// Assert that port is valid
MBED_ASSERT(port <= PortV);
// Store port and port mask for future use
obj->port = port;
obj->mask = mask;
// Enabling Port Clock Supply
TSB_CG->FSYSENA |= (1 << (obj->port));
// Set port function and port direction
for (i = 0; i < PORT_PIN_NUM; i++) {
if (obj->mask & (1 << i)) { // If the pin is used
pin_function(port_pin(obj->port, i), dir);
}
}
}
void port_mode(port_t *obj, PinMode mode)
{
uint8_t i = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortV);
// Set mode for masked pins
for (i = 0; i < PORT_PIN_NUM; i++) {
if (obj->mask & (1 << i)) { // If the pin is used
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir)
{
uint8_t bit = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortV);
// Set direction for masked pins
switch (dir) {
case PIN_INPUT:
for (bit = 0; bit < PORT_PIN_NUM; bit++) {
if (((obj->mask >> bit) & 0x01) == 0x01) {
pin_function((PinName)bit, PIN_INPUT);
}
}
break;
case PIN_OUTPUT:
for (bit = 0; bit < PORT_PIN_NUM; bit++) {
if (((obj->mask >> bit) & 0x01) == 0x01) {
pin_function((PinName)bit, PIN_OUTPUT);
}
}
break;
case PIN_INOUT:
for (bit = 0; bit < PORT_PIN_NUM; bit++) {
if (((obj->mask >> bit) & 0x01) == 0x01) {
pin_function((PinName)bit, PIN_INOUT);
}
}
break;
default:
break;
}
}
void port_write(port_t *obj, int value)
{
uint8_t port_data = 0;
uint8_t data = 0;
int bit = 0;
uint8_t val = 0;
uint32_t base = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortV);
base = BITBAND_PORT_BASE(obj->port);
base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA);
// Get current data of port
for (bit = 7; bit >= 0; bit--) {
BITBAND_PORT_READ(val, base, bit);
port_data <<= 1;
port_data |= val;
}
// Calculate data to write to masked pins
data = (port_data & ~obj->mask) | (value & obj->mask);
for (bit = 0; bit < PORT_PIN_NUM; bit++) {
if (((obj->mask >> bit) & 0x01) == 0x01) {
if (((data >> bit) & 0x01) == GPIO_PIN_SET) {
BITBAND_PORT_SET(base, bit);
} else {
BITBAND_PORT_CLR(base, bit);
}
}
}
}
int port_read(port_t *obj)
{
uint8_t port_data = 0;
uint8_t data = 0;
int bit = 0;
uint8_t val = 0;
uint32_t base = 0;
// Assert that port is valid
MBED_ASSERT(obj->port <= PortV);
base = BITBAND_PORT_BASE(obj->port);
base = BITBAND_PORT_MODE_BASE(base, GPIO_Mode_DATA);
// Get current data of port
for (bit = 7; bit >= 0; bit--) {
BITBAND_PORT_READ(val, base, bit);
port_data <<= 1;
port_data |= val;
}
// Calculate data of masked pins
data = port_data & obj->mask;
return data;
}
PinName port_pin(PortName port, int pin_n)
{
PinName pin = NC;
pin = (PinName)((port << 3 ) | pin_n);
return pin;
}

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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pwmout_api.h"
#include "pinmap.h"
#include "gpio_include.h"
static const PinMap PinMap_PWM[] = {
{PB0, PWM_0, PIN_DATA(5, 1)},
{PC0, PWM_1, PIN_DATA(4, 1)},
{PJ0, PWM_2, PIN_DATA(4, 1)},
{PK2, PWM_3, PIN_DATA(4, 1)},
{PN0, PWM_4, PIN_DATA(4, 1)},
{PL5, PWM_5, PIN_DATA(4, 1)},
{PG2, PWM_6, PIN_DATA(4, 1)},
{NC, NC, 0}
};
static const uint32_t prescale_tbl[] = {
2, 8, 32, 128, 256, 512, 1024
};
void pwmout_init(pwmout_t* obj, PinName pin)
{
uint16_t counter = 0;
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); // Determine the pwm channel
MBED_ASSERT(pwm != (PWMName)NC);
switch (pwm) {
case PWM_0:
obj->channel = TSB_T32A1;
TSB_CG_FSYSENA_IPENA25 = ENABLE;
TSB_CG_FSYSENA_IPENA01 = ENABLE;
break;
case PWM_1:
obj->channel = TSB_T32A2;
TSB_CG_FSYSENA_IPENA26 = ENABLE;
TSB_CG_FSYSENA_IPENA02 = ENABLE;
break;
case PWM_2:
obj->channel = TSB_T32A3;
TSB_CG_FSYSENA_IPENA27 = ENABLE;
TSB_CG_FSYSENA_IPENA08 = ENABLE;
break;
case PWM_3:
obj->channel = TSB_T32A4;
TSB_CG_FSYSENA_IPENA28 = ENABLE;
TSB_CG_FSYSENA_IPENA09 = ENABLE;
break;
case PWM_4:
obj->channel = TSB_T32A5;
TSB_CG_FSYSENA_IPENA29 = ENABLE;
TSB_CG_FSYSENA_IPENA12 = ENABLE;
break;
case PWM_5:
obj->channel = TSB_T32A6;
TSB_CG_FSYSENA_IPENA30 = ENABLE;
TSB_CG_FSYSENA_IPENA10 = ENABLE;
break;
case PWM_6:
obj->channel = TSB_T32A7;
TSB_CG_FSYSENA_IPENA31 = ENABLE;
TSB_CG_FSYSENA_IPENA06 = ENABLE;
break;
default:
obj->channel = NULL;
break;
}
pinmap_pinout(pin, PinMap_PWM); // Set pin function as PWM
obj->pin = pin;
obj->period = DEFAULT_PERIOD;
obj->divisor = DEFAULT_CLOCK_DIVISION;
obj->channel->MOD = (T32A_MODE_32 | T32A_DBG_HALT_STOP);
obj->channel->RUNC = (T32A_COUNT_STOP | T32A_COUNT_DONT_START | T32A_RUN_DISABLE);
obj->channel->CRC = (T32A_PRSCLx_32 | T32A_WBF_ENABLE | T32A_RELOAD_TREGx);
obj->channel->OUTCRC0 = T32A_OCR_DISABLE;
obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR);
counter = ((DEFAULT_PERIOD * (SystemCoreClock)) / obj->divisor);
obj->channel->RGC0 = counter;
obj->channel->RGC1 = counter;
obj->trailing_timing = counter;
obj->leading_timing = counter;
}
void pwmout_free(pwmout_t* obj)
{
// Stops and clear count operation
obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP);
pwmout_write(obj, 0);
obj->pin = NC;
obj->channel = NULL;
obj->trailing_timing = 0;
obj->leading_timing = 0;
obj->divisor = 0;
}
void pwmout_write(pwmout_t* obj, float value)
{
obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP); // Stop timer for setting clock again
obj->leading_timing = (obj->trailing_timing -
(obj->trailing_timing * value)); // leading_timing value
obj->channel->RGC0 = obj->leading_timing; // Setting TBxRG0 register
obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation
}
float pwmout_read(pwmout_t* obj)
{
float duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing)
/ obj->trailing_timing);
return duty_cycle;
}
void pwmout_period(pwmout_t* obj, float seconds)
{
pwmout_period_us(obj, (int)(seconds * 1000000.0f));
}
void pwmout_period_ms(pwmout_t* obj, int ms)
{
pwmout_period_us(obj, ms * 1000);
}
void pwmout_period_us(pwmout_t* obj, int us)
{
float seconds = 0;
int cycles = 0;
uint32_t clkdiv = 0;
int i = 0;
float duty_cycle = 0;
seconds = (float)(us / 1000000.0f);
// Select highest timer resolution
for (i = 0; i < 7; ++i) {
cycles = (int)(((SystemCoreClock) / prescale_tbl[i]) * seconds);
if (cycles <= MAX_COUNTER_16B) {
clkdiv = i + 1; // range 1:7
clkdiv <<= 28;
break;
} else {
cycles = MAX_COUNTER_16B;
clkdiv = 7;
clkdiv <<= 28;
}
}
// Stop timer for setting clock again
obj->channel->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP);
// Restore the duty-cycle
duty_cycle = ((float)(obj->trailing_timing - obj->leading_timing)
/ obj->trailing_timing);
obj->trailing_timing = cycles;
obj->leading_timing = (cycles - (cycles * duty_cycle));
// Change the source clock division and period
obj->channel->MOD = T32A_MODE_32;
obj->channel->CRC = (clkdiv | T32A_WBF_ENABLE | T32A_RELOAD_TREGx);
obj->channel->OUTCRC0 = T32A_OCR_DISABLE;
obj->channel->OUTCRC1 = (T32A_OCRCMPx0_SET | T32A_OCRCMPx1_CLR);
obj->channel->RGC0 = obj->leading_timing;
obj->channel->RGC1 = obj->trailing_timing;
obj->channel->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START); // Start count operation
}
void pwmout_pulsewidth(pwmout_t* obj, float seconds)
{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
{
pwmout_pulsewidth_us(obj, ms * 1000);
}
void pwmout_pulsewidth_us(pwmout_t* obj, int us)
{
float seconds = 0;
float value = 0;
seconds = (float)(us / 1000000.0f);
value = (((seconds / obj->period) * 100.0f) / 100.0f);
pwmout_write(obj, value);
}

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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "serial_api.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "gpio_include.h"
#include "objects.h"
static const PinMap PinMap_UART_TX[] = {
{PA1, SERIAL_0, PIN_DATA(1, 1)},
{PJ1, SERIAL_1, PIN_DATA(1, 1)},
{PB2, SERIAL_2, PIN_DATA(5, 1)},
{PA6, SERIAL_3, PIN_DATA(2, 1)},
{PV6, SERIAL_4, PIN_DATA(1, 1)},
{PN2, SERIAL_5, PIN_DATA(2, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_UART_RX[] = {
{PA2, SERIAL_0, PIN_DATA(1, 0)},
{PJ2, SERIAL_1, PIN_DATA(1, 0)},
{PB3, SERIAL_2, PIN_DATA(5, 0)},
{PA7, SERIAL_3, PIN_DATA(2, 0)},
{PV7, SERIAL_4, PIN_DATA(1, 0)},
{PN3, SERIAL_5, PIN_DATA(2, 0)},
{NC, NC, 0}
};
static uint32_t serial_irq_ids[UART_NUM] = {0};
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
static void uart_init(TSB_UART_TypeDef *UARTx, uart_inittypedef_t *InitStruct);
static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate);
static void uart_swreset(TSB_UART_TypeDef *UARTx);
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
int is_stdio_uart = 0;
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart_name != NC);
obj->index = uart_name;
switch (uart_name) {
case SERIAL_0:
obj->UARTx = TSB_UART0;
TSB_CG_FSYSENB_IPENB05 = ENABLE;
TSB_CG_FSYSENA_IPENA00 = ENABLE;
break;
case SERIAL_1:
obj->UARTx = TSB_UART1;
TSB_CG_FSYSENB_IPENB06 = ENABLE;
TSB_CG_FSYSENA_IPENA08 = ENABLE;
break;
case SERIAL_2:
obj->UARTx = TSB_UART2;
TSB_CG_FSYSENB_IPENB07 = ENABLE;
TSB_CG_FSYSENA_IPENA01 = ENABLE;
break;
case SERIAL_3:
obj->UARTx = TSB_UART3;
TSB_CG_FSYSENB_IPENB08 = ENABLE;
TSB_CG_FSYSENA_IPENA00 = ENABLE;
break;
case SERIAL_4:
obj->UARTx = TSB_UART4;
TSB_CG_FSYSENB_IPENB09 = ENABLE;
TSB_CG_FSYSENA_IPENA17 = ENABLE;
break;
case SERIAL_5:
obj->UARTx = TSB_UART5;
TSB_CG_FSYSENB_IPENB10 = ENABLE;
TSB_CG_FSYSENA_IPENA12 = ENABLE;
break;
default:
error("UART is not available");
break;
}
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
if (tx != NC && rx != NC) {
obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX;
} else {
if (tx != NC) {
obj->uart_config.Mode = UART_ENABLE_TX;
} else {
if (rx != NC) {
obj->uart_config.Mode = UART_ENABLE_RX;
}
}
}
obj->uart_config.BaudRate = 9600;
obj->uart_config.DataBits = 8;
obj->uart_config.StopBits = 0;
obj->uart_config.Parity = ParityNone;
obj->uart_config.FlowCtrl = FlowControlNone;
uart_init(obj->UARTx, &obj->uart_config);
is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0);
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj)
{
obj->UARTx->TRANS = 0;
obj->UARTx->CR0 = 0;
obj->UARTx->CR1 = 0;
uart_swreset(obj->UARTx);
obj->uart_config.BaudRate = 0;
obj->uart_config.DataBits = 0;
obj->uart_config.StopBits = 0;
obj->uart_config.Parity = 0;
obj->uart_config.Mode = 0;
obj->uart_config.FlowCtrl = 0;
}
void serial_baud(serial_t *obj, int baudrate)
{
obj->uart_config.BaudRate = baudrate;
uart_init(obj->UARTx, &obj->uart_config);
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven));
MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
obj->uart_config.DataBits = data_bits;
obj->uart_config.StopBits = stop_bits;
obj->uart_config.Parity = parity;
uart_init(obj->UARTx, &obj->uart_config);
}
void INTUART0TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_0], TxIrq);
}
void INTUART0RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_0], RxIrq);
}
void INTUART1TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_1], TxIrq);
}
void INTUART1RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_1], RxIrq);
}
void INTUART2TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_2], TxIrq);
}
void INTUART2RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_2], RxIrq);
}
void INTUART3TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_3], TxIrq);
}
void INTUART3RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_3], RxIrq);
}
void INTUART4TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_4], TxIrq);
}
void INTUART4RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_4], RxIrq);
}
void INTUART5TX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_5], TxIrq);
}
void INTUART5RX_IRQHandler(void)
{
irq_handler(serial_irq_ids[SERIAL_5], RxIrq);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
IRQn_Type irq_n = (IRQn_Type)0;
switch (obj->index) {
case SERIAL_0:
if (irq == RxIrq) {
irq_n = INTUART0RX_IRQn;
} else {
irq_n = INTUART0TX_IRQn;
}
break;
case SERIAL_1:
if (irq == RxIrq) {
irq_n = INTUART1RX_IRQn;
} else {
irq_n = INTUART1TX_IRQn;
}
break;
case SERIAL_2:
if (irq == RxIrq) {
irq_n = INTUART2RX_IRQn;
} else {
irq_n = INTUART2TX_IRQn;
}
break;
case SERIAL_3:
if (irq == RxIrq) {
irq_n = INTUART3RX_IRQn;
} else {
irq_n = INTUART3TX_IRQn;
}
break;
case SERIAL_4:
if (irq == RxIrq) {
irq_n = INTUART4RX_IRQn;
} else {
irq_n = INTUART4TX_IRQn;
}
break;
case SERIAL_5:
if (irq == RxIrq) {
irq_n = INTUART5RX_IRQn;
} else {
irq_n = INTUART5TX_IRQn;
}
break;
default:
break;
}
NVIC_ClearPendingIRQ(irq_n);
if (enable) {
NVIC_EnableIRQ(irq_n);
} else {
NVIC_DisableIRQ(irq_n);
}
}
int serial_getc(serial_t *obj)
{
int data = 0;
while (!serial_readable(obj)) { // Wait until Rx buffer is full
// Do nothing
}
if (obj->uart_config.Mode & UART_ENABLE_TX) {
obj->UARTx->TRANS &= 0x0D;
}
data = data | (obj->UARTx->DR & 0xFFU);
if (obj->uart_config.Mode & UART_ENABLE_TX) {
obj->UARTx->TRANS |= UART_ENABLE_TX;
}
return data;
}
void serial_putc(serial_t *obj, int c)
{
while (!serial_writable(obj)) {
// Do nothing
}
if (obj->uart_config.Mode & UART_ENABLE_RX) {
obj->UARTx->TRANS &= 0x0E;
}
obj->UARTx->DR = c & 0xFFU;
if (obj->uart_config.Mode & UART_ENABLE_RX) {
obj->UARTx->TRANS |= UART_ENABLE_RX;
}
}
int serial_readable(serial_t *obj)
{
int ret = 0;
if ((obj->UARTx->SR & 0x0000000F) != 0) {
ret = 1;
}
return ret;
}
int serial_writable(serial_t *obj)
{
int ret = 0;
if ((obj->UARTx->SR & 0x8000) == 0) {
ret = 1;
}
return ret;
}
void serial_clear(serial_t *obj)
{
obj->UARTx->FIFOCLR = 0x03;
}
void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj)
{
obj->UARTx->TRANS |= 0x08;
}
void serial_break_clear(serial_t *obj)
{
obj->UARTx->TRANS &= ~(0x08);
}
static void uart_swreset(TSB_UART_TypeDef *UARTx)
{
while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) {
// No process
}
UARTx->SWRST = UARTxSWRST_SWRST_10;
UARTx->SWRST = UARTxSWRST_SWRST_01;
while (((UARTx->SWRST) & UARTxSWRST_SWRSTF_MASK) == UARTxSWRST_SWRSTF_RUN) {
// No process
}
}
static void uart_get_boudrate_setting(uart_boudrate_t *brddiviser, uint32_t boudrate)
{
uint32_t clock = 0;
uint32_t k = 0;
uint64_t tx = 0;
uint64_t work = 1;
uint64_t p_range64 = 0;
uint64_t boud64 = 0;
uint64_t tx64 = 0;
uint64_t work64 = 1;
SystemCoreClockUpdate(); // Get the peripheral I/O clock frequency
clock = SystemCoreClock;
tx = (uint64_t)((uint64_t)clock << 6);
tx /= work;
tx64 = (uint64_t)((uint64_t)clock << 8);
tx64 /= work64;
work = ((uint64_t)boudrate);
tx /= work;
tx >>= 4;
boud64 = (64U * boudrate);
p_range64 = ((boud64 / 100) * 3);
for (k = UART_RANGE_K_MIN; (k <= UART_RANGE_K_MAX); k++) {
work = tx + k;
if (work >= (uint64_t)((uint64_t)1 << 6)) {
work -= (uint64_t)((uint64_t)1 << 6);
work >>= 6;
if ((UART_RANGE_N_MIN <= (uint32_t)work) && ((uint32_t)work <= UART_RANGE_N_MAX)) {
work64 = work <<6;
work64 = (uint64_t)(work64 + (64 - (uint64_t)k));
work64 = (tx64 / work64);
if (((boud64 - p_range64) <= work64) && (work64 <= (boud64 + p_range64))) {
brddiviser->brn = work;
brddiviser->brk = k;
break;
}
}
}
}
}
static void uart_init(TSB_UART_TypeDef *UARTx, uart_inittypedef_t *InitStruct)
{
uart_boudrate_t UTx_brd = {0};
uint32_t brk = 0;
uint32_t tmp = 0;
uint32_t parity_check = 0;
uint32_t data_length = 0;
UARTx->CLK = UART_PLESCALER_1; // Register Setting
uart_get_boudrate_setting(&UTx_brd, InitStruct->BaudRate);
UTx_brd.ken = UART_DIVISION_ENABLE;
brk = (UTx_brd.brk << 16);
UARTx->BRD = (UTx_brd.ken | brk | UTx_brd.brn);
parity_check = (InitStruct->Parity == ParityOdd) ? 1 : ((InitStruct->Parity == ParityEven) ? 3 : 0);
data_length = (InitStruct->DataBits) == 8 ? 1 : (((InitStruct->DataBits) == 7) ? 0 : 2);
tmp = (((InitStruct->FlowCtrl) << 9) | ((InitStruct->StopBits) << 4) | (parity_check << 2) | data_length);
UARTx->CR0 = tmp;
UARTx->CR1 = (UART_RX_FIFO_FILL_LEVEL | UART_TX_INT_ENABLE | UART_RX_INT_ENABLE);
UARTx->FIFOCLR = (UARTxFIFOCLR_TFCLR_CLEAR | UARTxFIFOCLR_RFCLR_CLEAR);
UARTx->TRANS = InitStruct->Mode;
}

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targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/sleep.c Normal file
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "sleep_api.h"
#include "gpio_include.h"
static void warming_up_time(void);
void hal_sleep(void)
{
// Set low power consumption mode IDLE
TSB_CG->STBYCR = CG_STBY_MODE_IDLE;
__DSB(); // Enter idle mode
__WFI();
}
void hal_deepsleep(void)
{
uint32_t tmp = 0;
TSB_CG_FSYSENB_IPENB31 = ENABLE;
while ((TSB_FC->SR0 & 0x01) != 0x01) {
// Flash wait
}
while (TSB_CG_WUPHCR_WUEF) {
// Wait for end of Warming-up for IHOSC1
}
TSB_CG_WUPHCR_WUCLK = DISABLE;
warming_up_time();
TSB_CG->STBYCR = CG_STBY_MODE_STOP1;
TSB_CG_PLL0SEL_PLL0SEL = DISABLE;
while (TSB_CG_PLL0SEL_PLL0ST) {
// Wait for PLL status of fsys until off state(fosc=0)
}
TSB_CG_PLL0SEL_PLL0ON = DISABLE; // Stop PLL of fsys
TSB_CG_OSCCR_IHOSC1EN = ENABLE;
TSB_CG_OSCCR_OSCSEL = DISABLE;
while (TSB_CG_OSCCR_OSCF) {
// Wait for fosc status until IHOSC1 = 0
}
tmp = TSB_CG->OSCCR;
tmp &= EXTERNEL_OSC_MASK;
TSB_CG->OSCCR = tmp;
TSB_CG_OSCCR_IHOSC2EN = DISABLE;
while (TSB_CG_OSCCR_IHOSC2F) {
// Wait for status of OFD until off "0"
}
__DSB();
__WFI();
}
static void warming_up_time(void)
{
uint32_t work = 0;
uint64_t x = 0;
x = (uint64_t)(IHOSC_CFG_WARM_UP_TIME * IHOSC_CFG_CLOCK);
x = (uint64_t)(x / (uint64_t)(1000000));
work = (uint32_t)x;
work &= (uint32_t)(0xFFFFFFF0);
work <<= 16;
work |= (uint32_t)(TSB_CG->WUPHCR & ~CGWUPHCR_WUPT_HIGH_MASK);
TSB_CG->WUPHCR = work;
}

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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "spi_api.h"
#include "mbed_error.h"
#include "pinmap.h"
#include "gpio_include.h"
#include "txz_tspi.h"
static const PinMap PinMap_SPI_SCLK[] = {
{PM0, SPI_0, PIN_DATA(3, 1)},
{PB2, SPI_1, PIN_DATA(3, 1)},
{PT2, SPI_2, PIN_DATA(1, 1)},
{PP5, SPI_3, PIN_DATA(1, 1)},
{PH4, SPI_4, PIN_DATA(1, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{PM1, SPI_0, PIN_DATA(3, 1)},
{PB3, SPI_1, PIN_DATA(3, 1)},
{PT3, SPI_2, PIN_DATA(1, 1)},
{PP4, SPI_3, PIN_DATA(1, 1)},
{PH5, SPI_4, PIN_DATA(1, 1)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{PM2, SPI_0, PIN_DATA(3, 0)},
{PB4, SPI_1, PIN_DATA(3, 0)},
{PT4, SPI_2, PIN_DATA(1, 0)},
{PP3, SPI_3, PIN_DATA(1, 0)},
{PH6, SPI_4, PIN_DATA(1, 0)},
{NC, NC, 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{PM3, SPI_0, PIN_DATA(3, 1)},
{PB5, SPI_1, PIN_DATA(3, 1)},
{PT1, SPI_2, PIN_DATA(2, 1)},
{PP6, SPI_3, PIN_DATA(1, 1)},
{NC, NC, 0}
};
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
// Check pin parameters
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->module = (SPIName)pinmap_merge(spi_data, spi_sclk);
obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)obj->module!= NC);
// Identify SPI module to use
switch ((int)obj->module) {
case SPI_0:
obj->p_obj.p_instance = TSB_TSPI0;
TSB_CG_FSYSENA_IPENA11 = ENABLE;
TSB_CG_FSYSENB_IPENB00 = ENABLE;
break;
case SPI_1:
obj->p_obj.p_instance = TSB_TSPI1;
TSB_CG_FSYSENA_IPENA01 = ENABLE;
TSB_CG_FSYSENB_IPENB01 = ENABLE;
break;
case SPI_2:
obj->p_obj.p_instance = TSB_TSPI2;
TSB_CG_FSYSENA_IPENA15 = ENABLE;
TSB_CG_FSYSENB_IPENB02 = ENABLE;
break;
case SPI_3:
obj->p_obj.p_instance = TSB_TSPI3;
TSB_CG_FSYSENA_IPENA13 = ENABLE;
TSB_CG_FSYSENB_IPENB03 = ENABLE;
break;
case SPI_4:
obj->p_obj.p_instance = TSB_TSPI4;
TSB_CG_FSYSENA_IPENA07 = ENABLE;
TSB_CG_FSYSENB_IPENB04 = ENABLE;
break;
default:
error("Cannot found SPI module corresponding with input pins.");
break;
}
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
//Control 1 configurations
obj->p_obj.init.id = (uint32_t)obj->module;
obj->p_obj.init.cnt1.trgen = TSPI_TRGEN_DISABLE; // Trigger disabled
obj->p_obj.init.cnt1.trxe = TSPI_DISABLE; // Enable Communication
obj->p_obj.init.cnt1.tspims = TSPI_SPI_MODE; // SPI mode
obj->p_obj.init.cnt1.mstr = TSPI_MASTER_OPEARTION; // master mode operation
obj->p_obj.init.cnt1.tmmd = TSPI_TWO_WAY; // Full-duplex mode (Transmit/receive)
obj->p_obj.init.cnt1.cssel = TSPI_TSPIxCS0_ENABLE; // Chip select of pin CS0 is valid
obj->p_obj.init.cnt1.fc = TSPI_TRANS_RANGE_SINGLE; // transfer single frame at a time continuously
//Control 2 configurations
obj->p_obj.init.cnt2.tidle = TSPI_TIDLE_HI;
obj->p_obj.init.cnt2.txdemp = TSPI_TXDEMP_HI; // when slave underruns TxD fixed to low
obj->p_obj.init.cnt2.rxdly = TSPI_RXDLY_40MHz_OVER;
obj->p_obj.init.cnt2.til = TSPI_TX_FILL_LEVEL_0; // transmit FIFO Level
obj->p_obj.init.cnt2.ril = TSPI_RX_FILL_LEVEL_1; // receive FIFO Level
obj->p_obj.init.cnt2.inttxwe = TSPI_TX_INT_DISABLE;
obj->p_obj.init.cnt2.intrxwe = TSPI_RX_INT_DISABLE;
obj->p_obj.init.cnt2.inttxfe = TSPI_TX_FIFO_INT_DISABLE;
obj->p_obj.init.cnt2.intrxfe = TSPI_RX_FIFO_INT_DISABLE;
obj->p_obj.init.cnt2.interr = TSPI_ERR_INT_DISABLE;
obj->p_obj.init.cnt2.dmate = TSPI_TX_DMA_INT_DISABLE;
obj->p_obj.init.cnt2.dmare = TSPI_RX_DMA_INT_DISABLE;
//Control 3 configurations
obj->p_obj.init.cnt3.tfempclr = TSPI_TX_BUFF_CLR_DONE; // transmit buffer clear
obj->p_obj.init.cnt3.rffllclr = TSPI_RX_BUFF_CLR_DONE; // receive buffer clear
//baudrate settings
spi_frequency(obj, (int)INITIAL_SPI_FREQ);
//Format Control 0 settings
obj->p_obj.init.fmr0.dir = TSPI_DATA_DIRECTION_MSB; // MSB bit first
obj->p_obj.init.fmr0.fl = TSPI_DATA_LENGTH_8;
obj->p_obj.init.fmr0.fint = TSPI_INTERVAL_TIME_0;
//Special control on polarity of signal and generation timing
obj->p_obj.init.fmr0.cs3pol = TSPI_TSPIxCS3_NEGATIVE;
obj->p_obj.init.fmr0.cs2pol = TSPI_TSPIxCS2_NEGATIVE;
obj->p_obj.init.fmr0.cs1pol = TSPI_TSPIxCS1_NEGATIVE;
obj->p_obj.init.fmr0.cs0pol = TSPI_TSPIxCS0_NEGATIVE;
obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW;
obj->p_obj.init.fmr0.csint = TSPI_MIN_IDLE_TIME_1;
obj->p_obj.init.fmr0.cssckdl = TSPI_SERIAL_CK_DELAY_1;
obj->p_obj.init.fmr0.sckcsdl = TSPI_NEGATE_1;
//Format Control 1 settings tspi_fmtr1_t
obj->p_obj.init.fmr1.vpe = TSPI_PARITY_DISABLE;
obj->p_obj.init.fmr1.vpm = TSPI_PARITY_BIT_ODD;
obj->bits = (uint8_t)TSPI_DATA_LENGTH_8;
//initialize SPI
tspi_init(&obj->p_obj);
}
void spi_free(spi_t *obj)
{
tspi_deinit(&obj->p_obj);
obj->module = (SPIName)NC;
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
MBED_ASSERT((slave == 0U) || (slave == 1U)); // 0: master mode, 1: slave mode
MBED_ASSERT((bits >= 8) && (bits <= 32));
obj->bits = bits;
obj->p_obj.init.fmr0.fl = (bits << 24);
if ((mode >> 1) & 0x1) {
obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_HI;
} else {
obj->p_obj.init.fmr0.ckpol = TSPI_SERIAL_CK_IDLE_LOW;
}
if (mode & 0x1) {
obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_2ND_EDGE;
} else {
obj->p_obj.init.fmr0.ckpha = TSPI_SERIAL_CK_1ST_EDGE;
}
tspi_init(&obj->p_obj);
}
void spi_frequency(spi_t *obj, int hz)
{
uint8_t brs = 0;
uint8_t brck = 0;
uint16_t prsck = 1;
uint64_t fscl = 0;
uint64_t tmp_fscl = 0;
uint64_t fx = 0;
uint64_t tmpvar = SystemCoreClock;
SystemCoreClockUpdate();
tmpvar = tmpvar / 2;
for (prsck = 1; prsck <= 512; prsck *= 2) {
fx = ((uint64_t)tmpvar / prsck);
for (brs = 1; brs <= 16; brs++) {
fscl = fx /brs;
if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) {
tmp_fscl = fscl;
obj->p_obj.init.brd.brck = (brck << 4);
if (brs == 16) {
obj->p_obj.init.brd.brs = 0;
} else {
obj->p_obj.init.brd.brs = brs;
}
}
}
brck ++;
}
tspi_init(&obj->p_obj);
}
int spi_master_write(spi_t *obj, int value)
{
uint8_t ret_value = 0;
tspi_transmit_t send_obj;
tspi_receive_t rec_obj;
// Transmit data
send_obj.tx8.p_data = (uint8_t *)&value;
send_obj.tx8.num = 1;
tspi_master_write(&obj->p_obj, &send_obj, TIMEOUT);
// Read received data
rec_obj.rx8.p_data = &ret_value;
rec_obj.rx8.num = 1;
tspi_master_read(&obj->p_obj, &rec_obj, TIMEOUT);
return ret_value;
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill)
{
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
char in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
int spi_busy(spi_t *obj)
{
int ret = 1;
uint32_t status = 0;
tspi_get_status(&obj->p_obj, &status);
if ((status & (TSPI_TX_FLAG_ACTIVE | TSPI_RX_FLAG_ACTIVE)) == 0) {
ret = 0;
}
return ret;
}
uint8_t spi_get_module(spi_t *obj)
{
return (uint8_t)(obj->module);
}

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targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/us_ticker.c Normal file
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/* mbed Microcontroller Library
* (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdbool.h>
#include "us_ticker_api.h"
#include "gpio_include.h"
static bool us_ticker_inited = false; // Is ticker initialized yet?
const ticker_info_t* us_ticker_get_info(void)
{
static const ticker_info_t info = {
1249200, // PLL output freq is ~40 MHz(39.974 MHz).
32 // 32 bit counter
};
return &info;
}
void us_ticker_init(void)
{
if (us_ticker_inited) {
us_ticker_disable_interrupt();
return;
}
us_ticker_inited = true;
TSB_CG_FSYSENA_IPENA24 = TXZ_ENABLE;
TSB_T32A0->MOD = T32A_MODE_32;
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
TSB_T32A0->CRC = T32A_PRSCLx_32;
TSB_T32A0->IMC = (T32A_IMUFx_MASK_REQ | T32A_IMOFx_MASK_REQ);
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
NVIC_SetVector(INTT32A00C_IRQn, (uint32_t)us_ticker_irq_handler);
NVIC_EnableIRQ(INTT32A00C_IRQn);
}
uint32_t us_ticker_read(void)
{
if (!us_ticker_inited) {
us_ticker_init();
}
return (TSB_T32A0->TMRC);
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
NVIC_DisableIRQ(INTT32A00C_IRQn);
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_STOP);
TSB_T32A0->RGC1 = timestamp;
NVIC_EnableIRQ(INTT32A00C_IRQn);
TSB_T32A0->RUNC = (T32A_RUN_ENABLE | T32A_COUNT_START);
}
void us_ticker_fire_interrupt(void)
{
NVIC_SetPendingIRQ(INTT32A00C_IRQn);
NVIC_EnableIRQ(INTT32A00C_IRQn);
}
void us_ticker_disable_interrupt(void)
{
// Disable interrupts by NVIC
TSB_T32A0->STC = T32A_INT_MASK;
NVIC_ClearPendingIRQ(INTT32A00C_IRQn);
NVIC_DisableIRQ(INTT32A00C_IRQn);
}
void us_ticker_clear_interrupt(void)
{
TSB_T32A0->STC = T32A_INT_MASK;
NVIC_ClearPendingIRQ(INTT32A00C_IRQn);
}
void us_ticker_free(void)
{
TSB_T32A0->RUNC = (T32A_RUN_DISABLE | T32A_COUNT_STOP);
us_ticker_inited = false;
TSB_T32A0->STC = 0x0F;
// Clear Pending interrupt in NVIC
NVIC_ClearPendingIRQ(INTT32A00C_IRQn);
// Disable interrupt in NVIC
NVIC_DisableIRQ(INTT32A00C_IRQn);
// Disable Clock.
TSB_CG_FSYSENA_IPENA24 = 0;
}

8
targets/TARGET_TOSHIBA/mbed_rtx.h
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@ -57,4 +57,12 @@
#endif
#if defined(TARGET_TMPM3HQ)
#ifndef INITIAL_SP
#define INITIAL_SP (0x20010000UL)
#endif
#endif
#endif // MBED_MBED_RTX_H

12
targets/targets.json
View File

@ -4611,5 +4611,17 @@
"macro_name": "CY_CLK_SLOWCLK_FREQ_HZ"
}
}
},
"TMPM3HQ": {
"inherits": ["Target"],
"core": "Cortex-M3",
"is_disk_virtual": true,
"extra_labels": ["TOSHIBA"],
"macros": ["__TMPM3HQ__"],
"supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
"device_has": ["USTICKER", "ANALOGIN", "ANALOGOUT", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "I2C", "I2CSLAVE", "STDIO_MESSAGES"],
"device_name": "TMPM3HQFDFG",
"detect_code": ["7014"],
"release_versions": ["5"]
}
}

5
tools/export/iar/iar_definitions.json
View File

@ -335,5 +335,10 @@
"GBECoreSlave": 39,
"FPU2": 6,
"GFPUCoreSlave2": 39
},
"TMPM3HQFDFG":{
"OGChipSelectEditMenu": "TMPM3HQFDFG\tToshiba TMPM3HQFDFG",
"GFPUCoreSlave": 25,
"GBECoreSlave": 25
}
}