Implement the following:
KVStore base class
TDBStore class
FileSystemStore class
SecureStore class
Global APIs
Configuration framework
Design documentation
RAM/ROM sizes in tools were updated to report entire device size, and in M2351
they were used earlier to report secure/non-secure partition size.
M2351 files are updated to take full RAM/ROM device size and derive secure
and non-secure partition size based on that.
When initializing serial disable all interrupts as some of these may
have been enabled by a bootloader. This ensures that the NRF52
serial driver remains compatible with any bootloader version.
Make the following enhancement:
-Support serial port use without flow control
-Prevent dropped bytes by updating flow control handling
-Remove dead code
Serial port use without flow control:
In the prior implementation there was a window of time between
reloading DMA buffers after a timeout where bytes could be dropped.
This is because the uart needed to be turned off in order to flush the
bytes in the DMA buffer.
This change configures the DMA buffer to only receive one byte at a
time so there is no need to disable the uart to flush it. After each
byte is received the DMA transfer will be over so the transfer will
never be partially complete and need flushing. Since the uart is
always on it is safe to use it even without flow control.
Prevent dropped bytes by updating flow control handling:
To prevent dropped bytes due to high latency the flow control handling
of the RTS line was configured to be asserted automatically by
hardware after each byte. Once the CPU has read the byte and setup
the next receive buffer the RTS line is deasserted to the transfer can
continue. This ensure that when flow control is enabled data won't be
lost due to interrupt latency.
Remove dead code:
With the above changes there is a lot of dead code, such as the timer
handling code. This patch removes the code that is no longer used.
### Description
The Mbed 2 release was broken for FF_LPC546XX as it would include
the entire mbed 2 build of the LPC546XX. This PR seperates these 2
builds completely by:
* Removing non-shared extra labels from the MCU_LPC546XX target
* Moving the target implementation to a shared target directory
### Pull request type
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Breaking change
Busy-wait before sending a charecter instead of after. If
serial_writeable has been called first, the busy-wait loop will
be skipped.
Added initialization code to ensure NRF_UARTE_EVENT_TXDRDY is
armed correctly.
In nordic_nrf5_uart_event_handler if the events NRF_UARTE_EVENT_ENDRX
and NRF_UARTE_EVENT_RXSTARTED become pending after the check for
NRF_UARTE_EVENT_ENDRX but before the check for
NRF_UARTE_EVENT_RXSTARTED the RX DMA buffers will be setup incorrectly
by nordic_nrf5_uart_event_handler_rxstarted because active_bank hasn't
been updated. This cause dropped and incorrect data.
This patch fixes that problem by adding a second check for
NRF_UARTE_EVENT_ENDRX after checking for NRF_UARTE_EVENT_RXSTARTED
and skipping processing if NRF_UARTE_EVENT_ENDRX is set. The
subsequent interrupt will process both in the correct order. This
ensures that these events cannot be handled out of order and thus fixes
the corruption.
This commit represents the second stage of the low power implementations
that are required from Mbed 5.10 onwards. Besides the default hal
implementations (rtc_api.c and sleep.c), the PL031 RTC's native driver
needed to be added. Due to HW limitations in SSE-050 and the CM3DS,
Deep Sleep couldn't be implemented, therefore it is functionally
identical to Sleep (WFI).
Change-Id: Ibed2bdb452f48c98024dc7ef07fb51a4425e0a80
Signed-off-by: Bence Kaposzta <bence.kaposzta@arm.com>
This commit represents the first stage of the low power implementations
that are required from Mbed 5.10 onwards. The LP ticker has been
implemented using a CMSDK Dual Timer's both timers (HW prescaler needed
to operate in the specified frequency domain), whereas the us ticker
uses one CMSDK Timer. Besides the default hal implementations (lp_ticker.c
and us_ticker.c), the CMSDK Dual Timer's native driver needed to be added.
Change-Id: I0b16b93dfac7753bebf430a2ce77761cb9c43ee5
Signed-off-by: Bence Kaposzta <bence.kaposzta@arm.com>
`flash_get_erase_value` is added in hal/TARGET_FLASH_CMSIS_ALGO/flash_common_algo.c
duplicate copy of same function in targets/TARGET_NUVOTON/TARGET_M2351/flash_api.c
resulted in build issues with secure build
hex files subfolder moved up one level to avoid license confusion.
Removed non-TLS implementation of TRNG. Removed unused crypto libraries and headers.
Replaced Cypress copyright licence per agreement.
Removed unsed eeprom emulation middleware files.
Renamed assembler files from *.s to *.S
Removed "device_name" from targets.json definitions as it is not supoprted yet.
Exporter hooks removed completely.
Cleanup and improvements to the comments, including removal of the redundant doxygen comments.
Code run through astyle. Additionally:
- changes to drivers/Timer.cpp reverted
- ipcpipe_transport.* files removed as they are not used for now,
- fixed condition in stdio_init.cpp to perform serial initialization only when STDIO is enabled,
- added missing resurce manager call in PWM initialization,
- us_ticker initialization changed to use pre-reserved clock divider (to avoid resource manager call).
Changed reporting level from info to debug in PSOC6.py.
Added missing includes for function declarations in startup files.
Fixed (removed) garbadge text in psoc6_utils.c
Precompiled binaries updated for recent changes in psoc6_utils.c and moved to a separate folder; README and LICENSE files added.
1. In drivers/Timer.cpp make sure that hardware timer is initialized outside of critical section.
This is because on PSoC 6 hardware resources are shared between both cores
and we have to make sure that the other core is not already using a particular resource.
This mechanism is based on interprocessor communication taht cannot be handled iside of
critical section.
2. Added support for post-binary hook function for PSoC 6 targets, so the hex image for M0+ CPU core
can be merged with M4 core image for the final image.
3. Added possibility to use hook function from exportes, so the M0+ hex image could be included
in the generated project.
4. Included hex images in the build dependency list, so the update of image is catched by the
build process.
1. Complete set of HAL drivers for all peripherals of CY8C63xx PSoC chips.
2. Cypress PDL library updated to official 3.0.1 version.
3. Tree structure reorganized and cleaned up:
+ TARGET_Cypress
+--+ TARGET_PSOC6+ -> code & libs applicable to all PSoC 6 based devices
+--+ TARGET_CY86XX -> code & libs applicable to PSoC 63 based devices
| +--- TARGET_MCU_PSOC6_M0 -> code & libs applicable to PSoC6 Corted M0+ core
| +--- TARGET_MCU_PSOC6_M4 -> code & libs applicable to PSoC6 Corted M0F core
|
+--+ TARGET_FUTURE_SEQUANA -> code applicable to Sequana board, both cores
+--- TARGET_FUTURE_SEQUANA_M0 -> code applicable only to M0+ core on Sequana board
Ethernet controller. To ensure proper operation, some methods
needed to be updated in the SMSC9220's native driver as well.
It passes all related Greentea tests, however when supervised by
the Python environment it tends to fail because of Timeout.
The current timeout is set to 1200s that seems to be a little bit short
to finish all test cases, the timeout happens towards the end of the
last test case.
Change-Id: I914608c34828b493a80e133cd132537a297bfc84
Signed-off-by: Bence Kaposzta <bence.kaposzta@arm.com>
Due to buggy flow control logic in the UARTE, the stop signal
is not being set as it is supposed to when the the module is
not ready to receive data.
This commit signals the sender to halt transmitting when a DMA
buffer is full and only continue again when the atomic FIFO
buffer has been emptied. This allows platforms with hardware
flow control to minimize all buffers and rely on flow control
instead.
Only deep sleep when the wakeup time is more than
MBED_CONF_TARGET_DEEP_SLEEP_LATENCY ms in the future.
This ensures that RTOS events are handled at the correct time. Note -
when deep sleep is allow interrupt latency may still be as high as
10ms.
LPC devices require a checksummed vector table to boot. To ensure
this most programmers automatically compute the checksum when
programming flash. This causes problems with verification if the
original image does not have a checksummed vector table. This is because
when reading the data back the checksum location differs from the
original image.
To fix this verification failure this patch adds a post build hook to
checksum the vector table of the LPC54XXX. This fixes flash
verification failures due to the checksum not matching.
The preprocessor based macro check #if evaluates all
enums as 0 and hence the code does not get compiled.
Since move this to a runtime check where the pin variable
can be correctly evaluated.
Delete mbed_overrides.c as it has a target specific mbed_sdk_init() to
resolve linking problem.
This is a follow on patch to:
https://github.com/ARMmbed/mbed-os/pull/8046
Add 16-bit access mode when writing the transfer size to prevent
the QSPI transaction from starting
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Small space savings, the casting from int to float will bloat
the code a bit. Using wait(1.0f) for example would avoid it,
but seems a bit silly to use floats for anything unless
really needed (in embedded products).
Martin Kojtal
David Saada
bcostm
Ganesh Ramachandran
jeromecoutant
Deepika
Russ Butler
ccli8
Przemyslaw Stekiel
c_jin
Cruz Monrreal II
Bence Káposzta
Russ Butler
Jimmy Brisson
chao_king
Marcus Chang
Senthil Ramakrishnan
Ashok Rao
Mahesh Mahadevan
Qinghao Shi
zhangzhenwu
Yoshihiro TSUBOI
Anna Bridge
Bence Kaposzta
Oren Cohen
Teppo Järvelin
Steve Cartmell
shileiyu
Adam Heinrich
Leon Lindenfelser
Leszek Rusinowicz
Adrien Chardon
Ammad Rehmat
Yossi Levy
micgur01
Naveen Kaje
Jarkko Paso
Offir Kochalsky
Mac Lobdell
aqin
Janne Kiiskila