mirror of https://github.com/ARMmbed/mbed-os.git
KL82Z FRDM: Update the KL82Z Freedom board for QSPI
Add the QSPI pin defines, clock information and flash details Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>pull/8485/head
Mahesh Mahadevan
parent
858e536f1a
commit
9dc3f8c19a
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@ -95,6 +95,10 @@ typedef enum {
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DAC_0 = 0
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} DACName;
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typedef enum {
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QSPI_0 = 0
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} QSPIName;
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#ifdef __cplusplus
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}
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#endif
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@ -158,3 +158,28 @@ const PinMap PinMap_PWM[] = {
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{NC , NC , 0}
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};
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const PinMap PinMap_QSPI_DATA[] = {
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{PTE0, QSPI_0, 5},
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{PTE2, QSPI_0, 5},
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{PTE3, QSPI_0, 5},
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{PTE4, QSPI_0, 5},
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{PTE6, QSPI_0, 5},
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{PTE7, QSPI_0, 5},
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{PTE8, QSPI_0, 5},
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{PTE9, QSPI_0, 5},
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{PTE10, QSPI_0, 5},
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{NC , NC , 0}
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};
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const PinMap PinMap_QSPI_SCLK[] = {
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{PTE1, QSPI_0, 5},
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{PTE7, QSPI_0, 5},
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{NC , NC , 0}
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};
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const PinMap PinMap_QSPI_SSEL[] = {
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{PTE5, QSPI_0, 5},
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{PTE11, QSPI_0, 5},
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{NC , NC , 0}
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};
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@ -156,6 +156,14 @@ typedef enum {
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A4 = PTB1,
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A5 = PTB0,
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/**** QSPI FLASH pins ****/
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QSPI_FLASH1_IO0 = PTE2,
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QSPI_FLASH1_IO1 = PTE4,
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QSPI_FLASH1_IO2 = PTE3,
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QSPI_FLASH1_IO3 = PTE0,
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QSPI_FLASH1_SCK = PTE1,
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QSPI_FLASH1_CSN = PTE5,
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// Not connected
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NC = (int)0xFFFFFFFF
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} PinName;
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@ -45,3 +45,10 @@ void serial_clock_init(void)
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{
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CLOCK_SetLpuartClock(2U);
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}
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// Get the QSPI clock frequency
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uint32_t qspi_get_freq(void)
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{
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return CLOCK_GetFreq(kCLOCK_McgPll0Clk);
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}
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@ -0,0 +1,77 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2018, ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_MBED_QSPI_DEVICE_H_
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#define _FSL_MBED_QSPI_DEVICE_H_
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#include "fsl_qspi.h"
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#define FLASH_SIZE 0x01000000U
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#define FLASH_PAGE_SIZE 256U
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qspi_flash_config_t single_config = {
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.flashA1Size = FLASH_SIZE, /* 16MB */
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.flashA2Size = 0,
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#if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
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.flashB1Size = FLASH_SIZE,
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.flashB2Size = 0,
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#endif
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#if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
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.dataHoldTime = 0,
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#endif
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.CSHoldTime = 0,
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.CSSetupTime = 0,
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.cloumnspace = 0,
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.dataLearnValue = 0,
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.endian = kQSPI_64LittleEndian,
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.enableWordAddress = false
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};
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/* Pre-defined LUT definitions */
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uint32_t lut[FSL_FEATURE_QSPI_LUT_DEPTH] =
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{
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/* Seq0 : Read */
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/* CMD: 0x03 - Read, Single pad */
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/* ADDR: 0x18 - 24bit address, Single pad */
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/* READ: 0x80 - Read 128 bytes, Single pad */
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/* JUMP_ON_CS: 0 */
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[0] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x03, QSPI_ADDR, QSPI_PAD_1, 0x18),
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[1] = QSPI_LUT_SEQ(QSPI_READ, QSPI_PAD_1, 0x80, QSPI_JMP_ON_CS, QSPI_PAD_1, 0x0),
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/* Seq1: Page Program */
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/* CMD: 0x02 - Page Program, Single pad */
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/* ADDR: 0x18 - 24bit address, Single pad */
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/* WRITE: 0x80 - Write 128 bytes at one pass, Single pad */
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[4] = QSPI_LUT_SEQ(QSPI_CMD, QSPI_PAD_1, 0x02, QSPI_ADDR, QSPI_PAD_1, 0x18),
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[5] = QSPI_LUT_SEQ(QSPI_WRITE, QSPI_PAD_1, 0x80, 0, 0, 0),
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/* Match MISRA rule */
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[63] = 0
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};
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#endif /* _FSL_MBED_QSPI_DEVICE_H_*/
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