mirror of https://github.com/ARMmbed/mbed-os.git
MCUXpresso: Add the QSPI HAL driver
This should support QSPI on Kinetis devices Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>pull/8485/head
Mahesh Mahadevan
parent
f3fee040c5
commit
e28fb7466b
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@ -13,7 +13,7 @@
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_PERIPHERALPINS_H
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#define MBED_PERIPHERALPINS_H
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@ -47,4 +47,11 @@ extern const PinMap PinMap_SPI_SSEL[];
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/************PWM***************/
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extern const PinMap PinMap_PWM[];
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#if DEVICE_QSPI
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/************QSPI***************/
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extern const PinMap PinMap_QSPI_DATA[];
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extern const PinMap PinMap_QSPI_SCLK[];
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extern const PinMap PinMap_QSPI_SSEL[];
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#endif
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#endif
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@ -95,6 +95,12 @@ struct flash_s {
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flash_config_t flash_config;
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};
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#if DEVICE_QSPI
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struct qspi_s {
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uint32_t instance;
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};
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#endif
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#include "gpio_object.h"
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#ifdef __cplusplus
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@ -0,0 +1,403 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2018, ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#if DEVICE_QSPI
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#include "qspi_api.h"
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#include "mbed_error.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "PeripheralPins.h"
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#include "qspi_device.h"
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/* Look-up table entry indices */
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#define LUT1_SEQ_INDEX 0 // Pre-defined read sequence
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#define LUT2_SEQ_INDEX 4 // Pre-defined write sequence
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#define LUT3_SEQ_INDEX 8 // User-define sequence
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/* Minimum write size */
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#define MIN_SIZE 16 // At least four words of data must be written into the TX Buffer
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/* Array of QSPI peripheral base address. */
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static QuadSPI_Type *const qspi_addrs[] = QuadSPI_BASE_PTRS;
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extern uint32_t qspi_get_freq(void);
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qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode)
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{
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uint32_t clockSourceFreq = 0;
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qspi_config_t config = {0};
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uint32_t qspiio0name = pinmap_peripheral(io0, PinMap_QSPI_DATA);
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uint32_t qspiio1name = pinmap_peripheral(io1, PinMap_QSPI_DATA);
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uint32_t qspiio2name = pinmap_peripheral(io2, PinMap_QSPI_DATA);
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uint32_t qspiio3name = pinmap_peripheral(io3, PinMap_QSPI_DATA);
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uint32_t qspiclkname = pinmap_peripheral(sclk, PinMap_QSPI_SCLK);
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uint32_t qspisselname = pinmap_peripheral(ssel, PinMap_QSPI_SSEL);
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uint32_t qspi_data_first = pinmap_merge(qspiio0name, qspiio1name);
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uint32_t qspi_data_second = pinmap_merge(qspiio2name, qspiio3name);
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uint32_t qspi_data_third = pinmap_merge(qspiclkname, qspisselname);
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if (qspi_data_first != qspi_data_second || qspi_data_second != qspi_data_third ||
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qspi_data_first != qspi_data_third) {
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return QSPI_STATUS_INVALID_PARAMETER;
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}
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clockSourceFreq = qspi_get_freq();
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/*Get QSPI default settings and configure the qspi */
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QSPI_GetDefaultQspiConfig(&config);
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/*Set AHB buffer size for reading data through AHB bus */
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config.AHBbufferSize[3] = FLASH_PAGE_SIZE;
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// tested all combinations, take first
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obj->instance = qspi_data_first;
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QSPI_Init(qspi_addrs[obj->instance], &config, clockSourceFreq);
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/* Copy the pre-defined LUT table */
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memcpy(single_config.lookuptable, lut, sizeof(uint32_t) * FSL_FEATURE_QSPI_LUT_DEPTH);
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/*According to serial flash feature to configure flash settings */
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QSPI_SetFlashConfig(qspi_addrs[obj->instance], &single_config);
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qspi_frequency(obj, hz);
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pinmap_pinout(io0, PinMap_QSPI_DATA);
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pinmap_pinout(io1, PinMap_QSPI_DATA);
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pinmap_pinout(io2, PinMap_QSPI_DATA);
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pinmap_pinout(io3, PinMap_QSPI_DATA);
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pinmap_pinout(sclk, PinMap_QSPI_SCLK);
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pinmap_pinout(ssel, PinMap_QSPI_SSEL);
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return QSPI_STATUS_OK;
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}
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qspi_status_t qspi_free(qspi_t *obj)
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{
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QSPI_Deinit(qspi_addrs[obj->instance]);
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return QSPI_STATUS_OK;
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}
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qspi_status_t qspi_frequency(qspi_t *obj, int hz)
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{
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qspi_status_t status = QSPI_STATUS_OK;
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QuadSPI_Type *base = qspi_addrs[obj->instance];
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int div = qspi_get_freq() / hz;
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if ((qspi_get_freq() % hz) == 0) {
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/* Incase the exact requested baud rate can be derived then set right div,
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* else set baudrate to the closest lower value
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*/
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div--;
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}
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if (div > 16 || div < 1) {
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status = QSPI_STATUS_INVALID_PARAMETER;
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return status;
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}
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/* Configure QSPI */
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QSPI_Enable(base, false);
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/* Set the divider of QSPI clock */
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base->MCR &= ~QuadSPI_MCR_SCLKCFG_MASK;
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base->MCR |= QuadSPI_MCR_SCLKCFG(div);
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QSPI_Enable(base, true);
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return status;
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}
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static void qspi_prepare_command(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size)
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{
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uint32_t lut_seq[4] = {0, 0, 0, 0};
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uint8_t instr1 = QSPI_CMD, instr2 = 0;
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uint8_t pad1 = command->instruction.bus_width, pad2 = 0;
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uint8_t op1 = command->instruction.value, op2 = 0;
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bool set_jmp_instr = false;
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QuadSPI_Type *base = qspi_addrs[obj->instance];
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uint32_t addr = FSL_FEATURE_QSPI_AMBA_BASE;
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/* Check if the flash address is provided */
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if (command->address.disabled) {
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/* Check if a second instruction is needed, this is for register accesses */
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if (tx_data != NULL && tx_size) {
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instr2 = QSPI_WRITE;
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pad2 = command->data.bus_width;
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op2 = tx_size;
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/* Read and write pointers of the TX buffer are reset to 0 */
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QSPI_ClearFifo(base, kQSPI_TxFifo);
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/* Clear underrun error flag */
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QSPI_ClearErrorFlag(base, kQSPI_TxBufferUnderrun);
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}
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if (rx_data != NULL && rx_size) {
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instr2 = QSPI_READ;
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pad2 = command->data.bus_width;
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op2 = rx_size;
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/* Read and write pointers of the RX buffer are reset to 0 */
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QSPI_ClearFifo(base, kQSPI_RxFifo);
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}
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/* Setup the LUT entry */
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lut_seq[0] = QSPI_LUT_SEQ(instr1, pad1, op1, instr2, pad2, op2);
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} else {
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instr2 = QSPI_ADDR;
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pad2 = command->address.bus_width;
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/* Number of address bits */
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op2 = (8 * (command->address.size + 1));
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addr += command->address.value;
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/* Setup the first LUT entry */
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lut_seq[0] = QSPI_LUT_SEQ(instr1, pad1, op1, instr2, pad2, op2);
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/* Clear the variables */
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instr1 = instr2 = 0;
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pad1 = pad2 = 0;
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op1 = op2 = 0;
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/* Check if a second LUT entry is needed */
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if (tx_data != NULL && tx_size) {
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instr1 = QSPI_WRITE;
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pad1 = command->data.bus_width;
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op1 = 0x80;
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/* Read and write pointers of the TX buffer are reset to 0 */
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QSPI_ClearFifo(base, kQSPI_TxFifo);
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/* Clear underrun error flag */
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QSPI_ClearErrorFlag(base, kQSPI_TxBufferUnderrun);
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}
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if (rx_data != NULL && rx_size) {
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instr1 = QSPI_READ;
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pad1 = command->data.bus_width;
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op1 = 0x80;
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/* Read operations need a jump command at the end of the sequence */
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set_jmp_instr = true;
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/* Read and write pointers of the TX buffer are reset to 0 */
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QSPI_ClearFifo(base, kQSPI_RxFifo);
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}
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/* Setup more LUT entries if needed */
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if (instr1 != 0) {
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/* Check if we need to add dummy entries */
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if (command->dummy_count > 0) {
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instr2 = instr1;
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pad2 = pad1;
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op2 = op1;
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instr1 = QSPI_DUMMY;
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pad1 = command->address.bus_width;
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op1 = command->dummy_count;
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}
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/* Check if need to add jump command entry */
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if (set_jmp_instr) {
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/* Need to add a jump command in the sequence */
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if (command->dummy_count > 0) {
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/* Third LUT entry for jump command */
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lut_seq[2] = QSPI_LUT_SEQ(QSPI_JMP_ON_CS, QSPI_PAD_1, LUT3_SEQ_INDEX, 0, 0, 0);
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} else {
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/* As there is no dummy we have space in the second LUT entry to add jump command */
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instr2 = QSPI_JMP_ON_CS;
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pad2 = QSPI_PAD_1;
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op2 = 8;
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}
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}
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/* Second LUT entry for read & write operations */
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lut_seq[1] = QSPI_LUT_SEQ(instr1, pad1, op1, instr2, pad2, op2);
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}
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}
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/* Update the LUT registers from index 8, prior entries have pre-defined LUT sequences
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* which is used when the instruction is disabled
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*/
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if (!(command->instruction.disabled)) {
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QSPI_UpdateLUT(base, LUT3_SEQ_INDEX, lut_seq);
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}
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/* Setup the address */
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QSPI_SetIPCommandAddress(base, addr);
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/* Reset AHB domain and serial flash domain flops */
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QSPI_SoftwareReset(base);
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while (QSPI_GetStatusFlags(base) & kQSPI_Busy) {
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}
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}
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qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length)
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{
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uint32_t to_write = *length;
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uint8_t *data_send = (uint8_t *)data;
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QuadSPI_Type *base = qspi_addrs[obj->instance];
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/* At least four words of data must be written to the TX buffer */
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if (to_write < MIN_SIZE) {
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return QSPI_STATUS_INVALID_PARAMETER;
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}
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/* Enforce word-sized access */
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if ((to_write & 0x3) != 0) {
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return QSPI_STATUS_INVALID_PARAMETER;
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}
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/* Prepare the write command */
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qspi_prepare_command(obj, command, data, to_write, NULL, 0);
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QSPI_SetIPCommandSize(base, to_write);
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if (to_write > (FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4)) {
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/* First write some data into TXFIFO to prevent underrun */
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QSPI_WriteBlocking(base, (uint32_t *)data_send, FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
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data_send += (FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
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to_write -= (FSL_FEATURE_QSPI_TXFIFO_DEPTH * 4);
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} else {
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QSPI_WriteBlocking(base, (uint32_t *)data_send, to_write);
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to_write = 0;
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}
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/* Start the program */
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if (command->instruction.disabled) {
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/* If no instruction provided then use the pre-defined write sequence */
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QSPI_ExecuteIPCommand(base, LUT2_SEQ_INDEX);
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} else {
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/* Use the user-defined write sequence */
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QSPI_ExecuteIPCommand(base, LUT3_SEQ_INDEX);
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}
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/* Write the remaining data to TXFIFO */
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if (to_write) {
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QSPI_WriteBlocking(base, (uint32_t *)data_send, to_write);
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}
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while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_IPAccess)) {
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}
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return QSPI_STATUS_OK;
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}
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qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length)
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{
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uint32_t dest_addr = FSL_FEATURE_QSPI_AMBA_BASE + command->address.value;
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uint32_t to_read = *length;
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QuadSPI_Type *base = qspi_addrs[obj->instance];
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/* Enforce word-sized access */
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if ((to_read & 0x3) != 0) {
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return QSPI_STATUS_INVALID_PARAMETER;
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}
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/* Prepare for read command */
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qspi_prepare_command(obj, command, NULL, 0, data, to_read);
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/* Point to the read sequence in the LUT */
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if (command->instruction.disabled) {
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/* If no instruction provided then use the pre-defined read sequence */
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QSPI_ExecuteAHBCommand(base, LUT1_SEQ_INDEX);
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} else {
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/* Use the user-defined write sequence */
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QSPI_ExecuteAHBCommand(base, LUT3_SEQ_INDEX);
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}
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for (uint32_t i = 0; i < to_read / 4; i++) {
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((uint32_t*)data)[i] = *((uint32_t *)(dest_addr) + i);
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}
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while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_AHBAccess)) {
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}
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return QSPI_STATUS_OK;
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}
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qspi_status_t qspi_command_transfer(qspi_t *obj, const qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data, size_t rx_size)
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{
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QuadSPI_Type *base = qspi_addrs[obj->instance];
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if (tx_size > MIN_SIZE || rx_size > MIN_SIZE) {
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return QSPI_STATUS_INVALID_PARAMETER;
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}
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if ((tx_data == NULL || tx_size == 0) && (rx_data == NULL || rx_size == 0)) {
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/* Setup the sequence in the Look-up Table (LUT) */
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qspi_prepare_command(obj, command, tx_data, tx_size, rx_data, rx_size);
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/* Execute the sequence */
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QSPI_ExecuteIPCommand(base, LUT3_SEQ_INDEX);
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while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_IPAccess)) {
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}
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} else {
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if (tx_data != NULL && tx_size) {
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/* Transmit data to QSPI */
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/* Need to write at least 16 bytes into TX buffer */
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uint8_t val[MIN_SIZE];
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memset(val, 0, sizeof(val));
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memcpy(val, tx_data, tx_size);
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/* Setup the sequence in the Look-up Table (LUT) */
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qspi_prepare_command(obj, command, tx_data, tx_size, rx_data, rx_size);
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/* First write some data into TXFIFO to prevent from underrun */
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QSPI_WriteBlocking(base, (uint32_t *)val, MIN_SIZE);
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/* Use the user-defined write sequence */
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QSPI_ExecuteIPCommand(base, LUT3_SEQ_INDEX);
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while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_IPAccess)) {
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}
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}
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if (rx_data != NULL && rx_size) {
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/* Receive data from QSPI */
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uint32_t val[MIN_SIZE / 4];
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memset(val, 0, sizeof(val));
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/* Read data from the IP read buffers */
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QSPI_SetReadDataArea(base, kQSPI_ReadIP);
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/* Setup the sequence in the Look-up Table (LUT) */
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qspi_prepare_command(obj, command, tx_data, tx_size, rx_data, rx_size);
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/* Execute the sequence */
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QSPI_SetIPCommandSize(base, rx_size);
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QSPI_ExecuteIPCommand(base, LUT3_SEQ_INDEX);
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while (QSPI_GetStatusFlags(base) & (kQSPI_Busy | kQSPI_IPAccess)) {
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}
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for (uint32_t i = 0, j =0; i < rx_size; i += 4, j++) {
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val[j] = QSPI_ReadData(base);
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}
|
||||
|
||||
memcpy(rx_data, val, rx_size);
|
||||
}
|
||||
}
|
||||
|
||||
return QSPI_STATUS_OK;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -574,7 +574,7 @@
|
|||
"is_disk_virtual": true,
|
||||
"inherits": ["Target"],
|
||||
"detect_code": ["0218"],
|
||||
"device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
|
||||
"device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH", "QSPI"],
|
||||
"release_versions": ["2", "5"],
|
||||
"device_name": "MKL82Z128xxx7"
|
||||
},
|
||||
|
|
@ -757,7 +757,7 @@
|
|||
"macros": ["CPU_MK82FN256VDC15", "FSL_RTOS_MBED"],
|
||||
"inherits": ["Target"],
|
||||
"detect_code": ["0217"],
|
||||
"device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH"],
|
||||
"device_has": ["USTICKER", "LPTICKER", "RTC", "ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "TRNG", "FLASH", "QSPI"],
|
||||
"release_versions": ["2", "5"],
|
||||
"device_name": "MK82FN256xxx15"
|
||||
},
|
||||
|
|
|
|||
Loading…
Reference in New Issue